ADF4355-2BCPZ_技术文档

Microwave Wideband Synthesizer

with Integrated VCO

Data Sheet

ADF4355-2

FEATURES

GENERAL DESCRIPTION

RF output frequency range: 54 MHz to 4400 MHz

Fractional-N synthesizer and integer-N synthesizer

High resolution 38-bit modulus

The ADF4355-2 allows implementation of fractional-N or

integer-N phase-locked loop (PLL) frequency synthesizers

when used with an external loop filter and an external reference

frequency. A series of frequency dividers permits operation

from 54 MHz to 4400 MHz.

Low phase noise, VCO

Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output

Analog and digital power supplies: 3.3 V

Charge pump and VCO power supplies: 5 V typical

Logic compatibility: 1.8 V

Programmable dual modulus prescaler of 4/5 or 8/9

Programmable output power level

RF output mute function

The ADF4355-2 has an integrated voltage controlled oscillator

(VCO) with a fundamental output frequency ranging from

3400 MHz to 6800 MHz. In addition, the VCO frequency is

connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow

the user to generate radio frequency (RF) output frequencies as

low as 54 MHz. For applications that require isolation, the RF

output stage can be muted. The mute function is both pin and

software controllable.

3-wire serial interface

Analog and digital lock detect

APPLICATIONS

Control of all on-chip registers is through a simple 3-wire interface.

The ADF4355-2 operates with analog and digital power supplies,

ranging from 3.15 V to 3.45 V, with charge pump and VCO

supplies from 4.75 V to 5.25 V. The ADF4355-2 also contains

hardware and software power-down modes.

Wireless infrastructure (W-CDMA, TD-SCDMA,

WiMAX, GSM, PCS, DCS, DECT)

Point to point/point to multipoint microwave links

Satellites/VSATs

Test equipment/instrumentation

Clock generation

FUNCTIONAL BLOCK DIAGRAM

AV

DV

V

R

V

VCO

V

RF

AV

DD

CE

DD

P

SET

MULTIPLEXER

MUXOUT

10-BIT R

COUNTER

÷2

DIVIDER

REF

A

B

IN

×2

DOUBLER

LOCK

DETECT

C

1

2

IN

REG

C

CLK

DATA

LE

DATA REGISTER

FUNCTION

LATCH

CHARGE

PUMP

CP

OUT

PHASE

COMPARATOR

V

TUNE

REF

V

VCO

CORE

BIAS

INTEGER

REG

FRACTION

REG

MODULUS

REG

REGVCO

RF

A+

OUT

1/2/4/8

16/32/64

OUTPUT

STAGE

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

÷

A–

PDB

RF

B+

B–

OUTPUT

STAGE

OUT

N COUNTER

RF

OUT

MULTIPLEXER

SD

ADF4355-2

A

CP

A

GNDVCO

A

GND

GNDRF

Figure 1.

Rev. C

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ADF4355-2

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 4 ..................................................................................... 23

Register 5 ..................................................................................... 24

Register 6 ..................................................................................... 25

Register 7 ..................................................................................... 27

Register 8 ..................................................................................... 28

Register 9 ..................................................................................... 28

Register 10................................................................................... 29

Register 11................................................................................... 29

Register 12................................................................................... 30

Register Initialization Sequence ............................................... 30

Frequency Update Sequence..................................................... 31

RF Synthesizer—A Worked Example ...................................... 31

Reference Doubler and Reference Divider ............................. 32

Spurious Optimization and Fast Lock..................................... 32

Optimizing Jitter......................................................................... 32

Spur Mechanisms ....................................................................... 32

Lock Time.................................................................................... 32

Applications Information .............................................................. 34

Direct Conversion Modulator .................................................. 34

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 7

Transistor Count........................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Circuit Description......................................................................... 13

Reference Input Section............................................................. 13

RF N Divider............................................................................... 13

Phase Frequency Detector (PFD) and Charge Pump............ 14

MUXOUT and Lock Detect...................................................... 14

Input Shift Registers................................................................... 14

Program Modes .......................................................................... 15

VCO.............................................................................................. 15

Output Stage................................................................................ 15

Register Maps.................................................................................. 17

Register 0 ..................................................................................... 19

Register 1 ..................................................................................... 20

Register 2 ..................................................................................... 21

Register 3 ..................................................................................... 22

Printed Circuit Board (PCB) Design Guidelines for a Chip-

Scale Package .............................................................................. 35

Output Matching........................................................................ 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

Rev. C | Page 2 of 37

Data Sheet

ADF4355-2

REVISION HISTORY

8/2017—Rev. B to Rev. C

Changes to Figure 21 Caption.......................................................11

Changes to Reference Input Section and INT, FRAC, MOD, and

R Counter Relationship Section....................................................12

Changes to Figure 25 and Input Shift Registers Section............13

Changes to VCO Section and Output Stage Section..................14

Changes to Figure 28 ......................................................................16

Changes to Figure 30 and Automatic Calibration (Autocal)

Section ..............................................................................................18

Changes to Figure 32 ......................................................................20

Changes to Phase Resync Section.................................................21

Changes to Figure 34 ......................................................................22

Changes to Reference Mode Section, Counter Reset Section,

Register 5 Section, and Figure 35..................................................23

Changes to Negative Bleed Section and Feedback Select Section..24

Changes to Figure 38 Caption and Register 8 Section...............27

Changed ADC Conversion Clock (ADC_CLK) Section to ADC

Clock Divider (ADC_CLK_DIV) Section...................................28

Changes to ADC Clock Divider (ADC_CLK_DIV) Section....28

Changes to Register Initialization Sequence Section and

Changes to Frequency Update Sequence Section.......................31

Updated Outline Dimensions........................................................37

Changes to Ordering Guide...........................................................37

1/2016—Rev. A to Rev. B

Added Doubler Enabled Parameter to Table 1..............................4

Changes to Table 2 ............................................................................6

Changes to Table 3 ............................................................................7

Changes to Reference Input Section and INT, FRAC, MOD, and

R Counter Relationship Section....................................................13

Changes to Figure 25 ......................................................................14

Changes to Automatic Calibration Section .................................19

Changes to Reference Doubler Section and Figure 34...............23

Changes to Negative Bleed Section...............................................25

Changes to Loss of Lock Mode Section........................................27

Changes to ADC Clock Divider (ADC_CLK_DIV) ..................29

Changes to Register Initialization Sequence Section .................30

Changes to Frequency Update Sequence Section.......................31

Changes to Power Supplies Section and Figure 45 .....................35

Frequency Update Sequence Section............................................29

Changes to RF Synthesizer—A Worked Example Section ........30

Changes to Lock Time Section......................................................31

Added Lock Time—A Worked Example Section .......................31

Changes to Figure 45 ......................................................................33

2/2015—Rev. 0 to Rev. A

Changes to General Description Section .......................................1

Changes to Table 1 ............................................................................3

Changes to Absolute Maximum Ratings Section..........................6

Changes to Table 4 ............................................................................8

10/2014—Revision 0: Initial Version

Rev. C | Page 3 of 37

ADF4355-2

Data Sheet

SPECIFICATIONS

AV_DD= DV_DD= V_RF= 3.3 V 5%, 4.75 V ≤ V_P= V_VCO≤ 5.25 V, A_GND= CP_GND= A_GNDVCO= SD_GND= A_GNDRF= 0 V, R_SET= 5.1 kΩ, dBm

referred to 50 Ω, T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

REF_INA/REF_INB CHARACTERISTICS

Input Frequency

For f < 10 MHz, ensure slew rate > 21 V/µs

Single-Ended Mode

Differential Mode

Doubler Enabled

10

250

600

100

MHz

Doubler is set in Register 4, Bit DB26

Input Sensitivity

Single-Ended Mode

0.4

AV_DD

1.8

V p-p

REF_INA biased at AV_DD/2; ac coupling

ensures AV_DD/2 bias

LVDS and LVPECL compatible,

REF_INA/REF_INB biased at 2.1 V;

ac coupling ensures 2.1 V bias

Differential Mode

Input Capacitance

Single-Ended Mode

Differential Mode

Input Current

6.9

1.4

pF

µA

MHz

60

250

125

Single-ended reference programmed

Differential reference programmed

Phase Detector Frequency

CHARGE PUMP (CP)

Charge Pump Current, Sink/Source

High Value

Low Value

R_SETRange

Current Matching

I_CPvs. V_CP

I_CPvs. Temperature

LOGIC INPUTS

I_CP

R_SET= 5.1 kΩ

4.8

0.3

5.1

3

1.5

mA

kΩ

%

Fixed

0.5 V ≤ V_CP¹≤ V_P− 0.5 V

V_CP¹= 2.5 V

Input High Voltage

Input Low Voltage

Input Current

Input Capacitance

LOGIC OUTPUTS

Output High Voltage

V_INH

V_INL

I_INH/I_INL

C_IN

1.5

V

µA

pF

0.6

1

3.0

1.8

V_OH

DV_DD− 0.4

1.5

V

1.8 V output selected

I_OL²= 500 µA

Output High Current

Output Low Voltage

I_OH

V_OL

500

0.4

µA

V

POWER SUPPLIES

Analog Power

AV_DD

3.15

4.75

3.45

V

Digital Power and RF Supply Voltage

Charge Pump and VCO Voltage

Charge Pump Supply Power Current

DV_DD, V_RF

V_P, V_VCO

I_P

AV_DD

5.0

8

Voltages must equal AV_DD

V_Pmust equal V_VCO

5.25

9

V

Digital Power Supply Current +

Analog Power Supply Current³

DI_DD, AI_DD

62

69

mA

Output Dividers

Supply Current

6 to 36

70

mA

Each output divide by 2 consumes 6 mA

I_VCO

85

RF_OUTA /RF_OUTB Supply Current

16/20/ 20/35/ mA

42/55⁴50/70⁴

RF output stage is programmable;

RF_OUTB+/RF_OUTB− powered off

I

RF_OUTx±

Low Power Sleep Mode

500

1000

µA

Hardware power-down

Software power-down

Rev. C | Page 4 of 37

Data Sheet

ADF4355-2

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

RF OUTPUT CHARACTERISTICS

VCO Frequency Range

RF Output Frequency

VCO Sensitivity

Frequency Pushing (Open-Loop)

Frequency Pulling (Open-Loop)

Harmonic Content

3400

53.125

6800

4400

MHz

MHz/V

MHz

Fundamental VCO range

K_V

15

0.5

Voltage standing wave ratio (VSWR) = 2:1

Second

−27

−22

−20

−12

8

dBc

dBm

dB

Fundamental VCO output (RF_OUTA+)

Divided VCO output (RF_OUTA+)

Fundamental VCO output (RF_OUTA+)

Divided VCO output (RF_OUTA+)

RF_OUTA+ = 1 GHz

RF_OUTA+/RF_OUTA− = 4.4 GHz

RF_OUTA+/RF_OUTA− = 1 GHz to 4.4 GHz

Third

RF Output Power⁵

3

RF Output Power Variation

RF Output Power Variation (over

Frequency)

1

3

dB

Level of Signal with RF Output

Disabled

−60

−30

dBm

RF_OUTA+/RF_OUTA− = 1 GHz, VCO = 4 GHz

RFOUTA+/RFOUTA− = 4.4 GHz,

VCO = 4.4 GHz

NOISE CHARACTERISTICS

Fundamental VCO Phase Noise

Performance

VCO noise in open-loop conditions

−116

−136

−138

−155

−113

−133

−135

−153

−110

−130

−132

−150

dBc/Hz 100 kHz offset from 3.4 GHz carrier

dBc/Hz 800 kHz offset from 3.4 GHz carrier

dBc/Hz 1 MHz offset from 3.4 GHz carrier

dBc/Hz 10 MHz offset from 3.4 GHz carrier

dBc/Hz 100 kHz offset from 5.0 GHz carrier

dBc/Hz 800 kHz offset from 5.0 GHz carrier

dBc/Hz 1 MHz offset from 5.0 GHz carrier

dBc/Hz 10 MHz offset from 5.0 GHz carrier

dBc/Hz 100 kHz offset from 6.8 GHz carrier

dBc/Hz 800 kHz offset from 6.8 GHz carrier

dBc/Hz 1 MHz offset from 6.8 GHz carrier

dBc/Hz 10 MHz offset from 6.8 GHz carrier

Normalized In-Band Phase Noise Floor

Fractional Channel⁶

−221

−223

−116

150

dBc/Hz

Integer Channel⁷

8

Normalized 1/f Noise, PN_{1_f}

dBc/Hz 10 kHz offset; normalized to 1 GHz

fs

Integrated RMS Jitter

Spurious Signals due to Phase

−80

dBc

Frequency Detector (PFD) Frequency

¹V_CPis the voltage at the CP_OUTpin.

²I_OLis the output low current.

³T_A= 25°C; AV_DD= DV_DD= V_RF= 3.3 V; V_VCO= V_P= 5.0 V; prescaler = 4/5; f_REF= 122.88 MHz; f_PFD= 61.44 MHz; and f_RF= 1650 MHz.

IN

⁴The value measured varies between 16, 20, 42, and 55, depending on the RF output stage power programmable level per Bit DB4 and DB5 in Register 6.

⁵RF output power using the EV-ADF4355-2SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. The EV-ADF4355-2SD1Z RF

outputs are pulled up externally using a 7.4 nH inductor. Unused RF output pins are terminated in 50 Ω.

⁶Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−221 + 10log(f_PFD) + 20logN. The value given is the lowest noise mode for the fractional channel.

⁷Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−223 + 10log(f_PFD) + 20logN. The value given is the lowest noise mode for the integer channel.

⁸The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f_RF

and at a frequency offset (f) is given by PN = P_{1_f}+ 10log(10 kHz/f) + 20log(f_RF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the

ADIsimPLL design tool.

)

Rev. C | Page 5 of 37

ADF4355-2

Data Sheet

TIMING CHARACTERISTICS

AV_DD= DV_DD=V_RF= 3.3 V 5%, 4.75 V ≤ V_P= V_VCO≤ 5.25 V, A_GND= CP_GND= A_GNDVCO= SD_GND= A_GNDRF= 0 V, R_SET= 5.1 kΩ, dBm

referred to 50 Ω, T_A= T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

Limit

Unit

Description

f_CLK

t₁

t₂

t₃

t₄

t₅

t₆

t₇

50

10

5

10

5

MHz max

ns min

Serial peripheral interface CLK frequency

LE setup time

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

CLK to LE setup time

LE pulse width

20 or (2/f_PFD), whichever is longer

Timing Diagram

t₄

t₅

CLK

t₂

t₃

DB3

DB2

(CONTROL BIT C3)

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB31 (MSB)

DB30

DATA

LE

(CONTROL BIT C4)

(CONTROL BIT C2)

t₇

t₁

t₆

Figure 2. Timing Diagram

Rev. C | Page 6 of 37

Data Sheet

ADF4355-2

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 3.

Parameter

V_RF, DV_DD, AV_DDto GND¹

Rating

−0.3 V to +3.6 V

−0.3 V to +0.3 V

−0.3 V to +5.8 V

−0.3 V to V_P+ 0.3 V

−0.3 V to DV_DD+ 0.3 V

−0.3 V to AV_DD+ 0.3 V

2.1 V

AV_DDto DV_DD

V_P, V_VCOto GND¹

CP_OUTto GND¹

The ADF4355-2 is a high performance RF integrated circuit with

an ESD rating of 2500 V and is ESD sensitive. Take proper

precautions for handling and assembly.

Digital Input/Output Voltage to GND¹

Analog Input/Output Voltage to GND¹

REF_INA, REF_INB to GND¹

REF_INA to REF_INB

TRANSISTOR COUNT

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

−40°C to +85°C

−65°C to +125°C

150°C

The transistor count for the ADF4355-2 is 103,665 (CMOS) and

3214 (bipolar).

ESD CAUTION

θ_JA, Thermal Impedance Paddle

Soldered to GND¹

27.3°C/W

Reflow Soldering

Peak Temperature

260°C

40 sec

Time at Peak Temperature

Electrostatic Discharge (ESD)

Charged Device Model

Human Body Model

1000 V

2500 V

¹GND = A_GND= SD_GND= A_GNDRF= A_GNDVCO= CP_GND= 0 V.

Rev. C | Page 7 of 37

ADF4355-2

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

V

R

A

V

CLK

DATA

LE

BIAS

REF

SET

ADF4355-2

TOP VIEW

(Not to Scale)

CE

GNDVCO

AV

TUNE

DD

V

A

V

P

REGVCO

CP

GNDVCO

VCO

OUT

GND

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO A

.

GND

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1

CLK

DATA

LE

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs)

as the control bits. This input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that

is selected by the four LSBs.

2

3

4

CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A

logic high on this pin powers up the device, depending on the status of the power-down bits.

5, 16

AV_DD

V_P

Analog Power Supply. These pins range from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog

ground plane as close to these pins as possible. AV_DDmust have the same value as DV_DD.

Charge Pump Power Supply. V_Pmust have the same value as V_VCO. Connect decoupling capacitors to the ground

plane as close to this pin as possible.

Charge Pump Output. When enabled, this output provides I_CPto the external loop filter. The output of the loop

filter is connected to V_TUNEto drive the internal VCO.

6

7

CP_OUT

8

9

10

CP_GND

A_GND

V_RF

Charge Pump Ground. This output is the ground return pin for CP_OUT.

Analog Ground. Ground return pin for AV_DD.

Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin

as possible. V_RFmust have the same value as AV_DD.

11

12

RF_OUTA+

RF_OUTA−

VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is

available.

Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down

version is available.

13

14

A_GNDRF

RF_OUTB+

RF Output Stage Ground. Ground return pins for the RF output stage.

Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version

is available.

15

17

RF_OUTB−

V_VCO

Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a

divided down version is available.

Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Connect decoupling capacitors to

the analog ground plane as close to this pin as possible.

18, 21

19

A_GNDVCO

V_REGVCO

VCO Ground. Ground return path for the VCO.

VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.

Connect this pin directly to V_VCO

.

20

V_TUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP_OUT

output voltage. The capacitance at this pin (V_TUNEinput capacitance) is 9 pF.

Rev. C | Page 8 of 37

Data Sheet

ADF4355-2

Pin No. Mnemonic

Description

22

23

R_SET

V_REF

Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.

Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the ground

plane as close to this pin as possible.

24

V_BIAS

Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.

25, 32

C_REG1, C_REG

2

Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits. Nominal voltage

of 1.8 V. Decoupling capacitors of 100 nF connected to A_GNDare required for these pins.

26

27

PDB_RF

DV_DD

RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable.

Digital Power Supply. This pin must be at the same voltage as AV_DD. Place decoupling capacitors to the ground

plane as close to this pin as possible.

28

29

30

REF_INB

REF_INA

MUXOUT

Complementary Reference Input. If unused, ac-couple this pin to A_GND

Reference Input.

Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the

scaled reference frequency to be externally accessible.

.

31

SD_GND

EP

Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator.

Exposed Pad. The exposed pad must be connected to A_GND

.

Rev. C | Page 9 of 37

ADF4355-2

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

–50

–70

÷1

÷2

÷4

÷8

–70

÷16

÷32

÷64

–90

–110

–130

–150

–170

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz

Figure 7. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and Dividers,

VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz

–50

–70

÷1

÷2

÷4

÷8

÷16

÷32

÷64

–70

–90

–110

–130

–150

–170

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 8. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and Dividers,

VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz

Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz

–50

–70

–50

÷1

÷2

÷4

÷8

÷16

÷32

÷64

–70

–90

–110

–130

–150

–170

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz

Figure 9. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and Dividers,

VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 20 kHz

Rev. C | Page 10 of 37

Data Sheet

ADF4355-2

10

9

8

7

6

–50

÷1

–40°C

+25°C

+85°C

÷2

–70

5

4

3

2

1

–90

–110

–130

–150

–170

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

1k

10k

100k

1M

10M

100M

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

FREQUENCY (Hz)

FREQUENCY (GHz)

Figure 10. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and

Divide by 2, VCO = 3.4 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz

Figure 13. Output Power vs. Frequency, RF_OUTA+/RF_OUTA− (7.5 nH Inductors,

10 pF Bypass Capacitors, Board Losses De-Embedded)

0

–50

÷1

SECOND HARMONIC

THIRD HARMONIC

÷2

–5

–70

–10

–15

–20

–25

–30

–35

–40

–45

–50

–90

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

FREQUENCY (Hz)

FREQUENCY (GHz)

Figure 14. RF_OUTA+/RF_OUTA− Harmonics vs. Frequency (7.5 nH Inductors,

10 pF Bypass Capacitors, Board Losses De-Embedded)

Figure 11. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and

Divide by 2, VCO = 5.0 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz

10

8

–50

÷1

÷2

–70

6

4

–90

–110

–130

–150

–170

2

0

–2

–4

–6

–8

–10

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

1k

10k

100k

1M

10M

100M

FREQUENCY (GHz)

FREQUENCY (Hz)

Figure 15. RF_OUTA+/RF_OUTA− Power vs. Frequency (100 nH Inductors,

100 pF Bypass Capacitors, Board Measurement)

Figure 12. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and

Divide by 2, VCO = 6.8 GHz, PFD = 61.44 MHz, Loop Bandwidth = 2 kHz

Rev. C | Page 11 of 37

ADF4355-2

Data Sheet

0.50

–80

–90

RMS JITTER (ps) 1kHz TO 20MHz

RMS JITTER (ps) 12kHz TO 20MHz

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

–100

–110

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

0.8

1.3

1.8

2.3

2.8

3.3

3.8

4.3

FREQUENCY (Hz)

OUTPUT FREQUENCY (GHz)

Figure 19. Fractional-N Spur Performance, W-CDMA Band, RF_OUTA+ =

2113.5 MHz, REF_IN= 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2 Selected,

Loop Filter Bandwidth = 2 kHz, Channel Spacing = 20 kHz

Figure 16. RMS Jitter vs. Output Frequency, PFD Frequency = 61.44 MHz,

Loop Filter = 20 kHz

–80

–90

–50

PFD = 15.36MHz

PFD = 30.72MHz

PFD = 61.44MHz

–60

–100

–110

–120

–130

–140

–150

–160

–70

–80

–90

–100

–110

1k

10k

100k

1M

10M

100M

0

0.5

RF

1.0

1.5

2.0

A– OUTPUT FREQUENCY (GHz)

OUT

2.5

3.0

3.5

4.0

4.5

FREQUENCY (Hz)

A+/RF

OUT

Figure 20. Fractional-N Spur Performance, RF_OUTA+ = 2.591 GHz,

REF_IN= 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2 Selected,

Loop Filter Bandwidth = 2 kHz, Channel Spacing = 20 kHz

Figure 17. PFD Spur Amplitude vs. RF_OUTA+/RF_OUTA− Output Frequency,

PFD = 15.36 MHz, PFD = 30.72 MHz, PFD = 61.44 MHz, Loop Filter = 20 kHz

4.65

4.60

–80

–90

4.55

4.50

4.45

–100

–110

–120

–130

–140

–150

–160

1

4.40

4.35

4.30

4.25

4.20

4.15

1k

10k

100k

1M

10M

100M

–1

0

1

2

3

4

TIME (ms)

FREQUENCY (Hz)

Figure 21. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz, Loop

Bandwidth = 20 kHz

Figure 18. Fractional-N Spur Performance, GSM1800 Band, RF_OUTA+ =

1550.2 MHz, REF_IN= 122.88 MHz, PFD = 61.44 MHz, Output Divide by 4 Selected,

Loop Filter Bandwidth = 2 kHz, Channel Spacing = 20 kHz

Rev. C | Page 12 of 37

Data Sheet

ADF4355-2

CIRCUIT DESCRIPTION

INT, FRAC, MOD, and R Counter Relationship

REFERENCE INPUT SECTION

The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in

conjunction with the R counter, make it possible to generate output

frequencies that are spaced by fractions of the PFD frequency

(f_PFD). For more information, see the RF Synthesizer—A Worked

Example section.

Figure 22 shows the reference input stage. The reference input

can accept both single-ended and differential signals. Use the

reference mode bit (Register 4, Bit DB9) to select the signal. To

use a differential signal on the reference input, program this bit

high. In this case, SW1 and SW2 are open, SW3 and SW4 are

closed, and the current source that drives the differential pair of

transistors switches on. The differential signal is buffered and it is

provided to an emitter coupled logic (ECL) to CMOS converter.

When a single-ended signal is used as the reference, program

Bit DB9 in Register 4 to 0. Connect the single-ended reference

signal to REF_INA. In this case, SW1 and SW2 are closed, SW3

and SW4 are open, and the current source that drives the

differential pair of transistors switches off.

Calculate the RF VCO frequency (VCO_OUT) by

VCO_OUT= f_PFD× N

where:

(1)

VCO_OUTis the output frequency of the VCO (without using the

output divider).

f

_PFDis the frequency of the phase frequency detector.

N is the desired value of the feedback counter, N.

REFERENCE

INPUT MODE

Calculate f_PFDby

f

_PFD= REF_IN× [(1 + D)/(R × (1 + T))]

(2)

85kꢀ

where:

SW2

BUFFER

SW1

REF_INis the reference input frequency.

D is the REF_INdoubler bit.

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

SW3

TO

R COUNTER

MULTIPLEXER

AV

DD

T is the REF_INdivide by 2 bit (0 or 1).

N comprises

ECL TO CMOS

BUFFER

FRAC2

MOD2

MOD1

FRAC1

REF

A

IN

N  INT 

(3)

where:

B

IN

INT is the 16-bit integer value (23 to 32,767 for the 4/5 prescaler,

2.5kΩ

75 to 65,535 for the 8/9 prescaler).

SW4

BIAS

FRAC1 is the numerator of the primary modulus (0 to 16,777,215).

FRAC2 is the numerator of the 14-bit auxiliary modulus

(0 to 16,383).

GENERATOR

Figure 22. Reference Input Stage

MOD2 is the programmable, 14-bit auxiliary fractional

modulus (2 to 16,383).

RF N DIVIDER

The RF N divider allows a division ratio in the PLL feedback

path. Determine the division ratio by the INT, FRAC1, FRAC2,

and MOD2 values that this divider comprises.

MOD1 is a 24-bit primary modulus with a fixed value of 2²⁴=

16,777,216.

Equation 3 results in a very fine frequency resolution with no

residual frequency error. To apply this formula, take the

following steps:

FRAC2

MOD2

RF N COUNTER

N = INT +

FRAC1 +

MOD1

1. Calculate N by dividing VCO_OUT/f_PFD

.

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

TO PFD

N COUNTER

2. The integer value of this number forms INT.

3. Subtract the INT value from the full N value.

4. Multiply the remainder by 2²⁴.

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

5. The integer value of this number forms FRAC1.

6. Calculate MOD2 based on the channel spacing (f_CHSP) by

INT

REG

FRAC1

REG

FRAC2

VALUE

MOD2

VALUE

MOD2 = f_PFD/GCD(f_PFD, f_CHSP

)

(4)

where:

GCD(f_PFD, f_CHSP) is the greatest common divider of the PFD

frequency and the channel spacing frequency.

Figure 23. RF N Divider

f

_CHSPis the desired channel spacing frequency.

Rev. C | Page 13 of 37

ADF4355-2

Data Sheet

DVDD

7. Calculate FRAC2 by the following equation:

FRAC2 = [(N − INT) × 2²⁴− FRAC1)] × MOD2

(5)

(6)

THREE-STATE OUTPUT

DV

The FRAC2 and MOD2 fraction results in outputs with zero

frequency error for channel spacings when

DD

SD

GND

f

_PFD/GCD(f_PFD/f_CHSP) < 16,383

where:

_PFDis the frequency of the phase frequency detector.

GCD is a greatest common denominator function.

_CHSPis the desired channel spacing frequency.

R DIVIDER OUTPUT

N DIVIDER OUTPUT

MUX

CONTROL

MUXOUT

ANALOG LOCK DETECT

f

DIGITAL LOCK DETECT

RESERVED

f

If zero frequency error is not required, the MOD1 and MOD2

denominators operate together to create a 38-bit resolution

modulus.

SD

GND

Figure 25. MUXOUT Schematic

INPUT SHIFT REGISTERS

INT N Mode

The ADF4355-2 digital section includes a 10-bit R counter, a

16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 14-bit

auxiliary fractional counter, and a 14-bit auxiliary modulus counter.

Data clocks into the 32-bit shift register on each rising edge of

CLK. The data clocks in MSB first. Data transfers from the shift

register to one of 12 latches on the rising edge of LE. The state

of the four control bits (C4, C3, C2, and C1) in the shift register

determines the destination latch. As shown in Figure 2, the four

LSBs are DB3, DB2, DB1, and DB0. The truth table for these bits is

shown in Table 5. Figure 28 and Figure 29 summarize the

programing of the latches.

When FRAC1 and FRAC2 = 0, the synthesizer operates in

integer-N mode.

R Counter

The 10-bit R counter allows the input reference frequency (REF_IN)

to be divided down to produce the reference clock to the PFD.

Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 24 is a simplified schematic of

the phase frequency detector. The PFD includes a fixed delay

element that sets the width of the antibacklash pulse. This pulse

ensures that there is no dead zone in the PFD transfer function

and provides a consistent reference spur level. Set the phase

detector polarity to positive on this device because of the positive

tuning of the VCO.

Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits

Control Bits

C4

0

1

C3

0

1

0

1

C2

0

1

0

1

0

1

0

C1

0

1

0

1

0

1

0

1

0

1

0

1

0

Register

Register 0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

Register 7

Register 8

Register 9

Register 10

Register 11

Register 12

UP

HIGH

D1

Q1

U1

CLR1

+IN

CHARGE

PUMP

CP

U3

DELAY

DOWN

CLR2

D2 Q2

HIGH

U2

–IN

Figure 24. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4355-2 allows the user to access

various internal points on the chip. The M3, M2, and M1 bits in

Register 4 control the state of MUXOUT. Figure 25 shows the

MUXOUT section in block diagram form.

Rev. C | Page 14 of 37

Data Sheet

ADF4355-2

50

45

40

35

30

25

20

15

10

5

PROGRAM MODES

Table 5 and Figure 28 through Figure 42 show the program

modes that must be set up in the ADF4355-2.

The following settings in the ADF4355-2 are double buffered: main

fractional value (FRAC1), auxiliary modulus value (MOD2),

auxiliary fractional value (FRAC2), reference doubler, reference

divide by 2 (RDIV2), R counter value, and charge pump current

setting. Two events must occur before the ADF4355-2 uses a new

value for any of the double buffered settings. First, the new value

must latch into the device by writing to the appropriate register,

and second, a new write to Register 0 must be performed.

LINEAR

TREND LINE

AVERAGE

VCO SENSITIVITY

0

3.3

3.8

4.3

4.8

5.3

5.8

6.3

6.8

For example, to ensure that the modulus value loads correctly,

every time the modulus value updates, Register 0 must be written

to. The RF divider select in Register 6 is also double buffered,

but only when DB14 of Register 4 is high.

FREQUENCY (GHz)

Figure 26. K_Vvs. Frequency

OUTPUT STAGE

The RF_OUTA+ and RF_OUTA− pins of the ADF4355-2 connect to

the collectors of an NPN differential pair driven by buffered

outputs of the VCO, as shown in Figure 27. In this scheme, the

ADF4355-2 contains internal 50 Ω resistors connected to the

VCO

The VCO core in the ADF4355-2 consists of four separate VCOs,

each of which uses 256 overlapping bands, which allows covering

a wide frequency range without a large VCO sensitivity (K_V) and

without resultant poor phase noise and spurious performance.

V

_RFpin. To optimize the power dissipation vs. the output

power requirements, the tail current of the differential pair is

programmable using Bits[D2:D1] in Register 6. Four current

levels can be set. These levels give approximate output power

levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively,

using a 50 Ω resistor to V_RFand ac coupling into a 50 Ω load.

For accurate power levels, refer to the Typical Performance

Characteristics section. With an output power of 5 dBm, an

external shunt inductor is necessary to provide higher power

levels; however, this addition results in less wideband operation.

Terminate the unused complementary output with a similar

circuit to the used output.

The correct VCO and band are chosen automatically by the

VCO and band select logic when Register 0 is updated and

auto-calibration is enabled. The VCO V_TUNEis disconnected

from the output of the loop filter and is connected to an internal

reference voltage.

The R counter output is used as the clock for the band select logic.

After band selection, normal PLL action resumes. The nominal

value of K_Vis 15 MHz/V when the N divider is driven from the

VCO output, or the K_Vvalue is divided by D. D is the output

divider value if the N divider is driven from the RF output divider

(chosen by programming Bits[D23:D21] in Register 6).

V

RF

50Ω

A+

50Ω

RF

The VCO shows variation of K_Vas the tuning voltage, V_TUNE

,

RF

A–

OUT

varies within the band and from band to band. For wideband

applications covering a wide frequency range (and changing

output dividers), a value of 15 MHz/V provides the most accurate

K_V, because this value is closest to the average value. Figure 26

shows how K_Vvaries with fundamental VCO frequency along with

an average value for the frequency band. Users may prefer this

figure when using narrow-band designs.

BUFFER/

DIVIDE BY

1/2/4/8/

VCO

16/32/64

Figure 27. Output Stage

Another feature of the ADF4355-2 is that the supply current to

the output stages can shut down until the ADF4355-2 achieves

lock as measured by the digital lock detect circuitry. The mute till

lock detect (MTLD) bit (DB11) in Register 6 enables this.

The RF_OUTB+/RF_OUTB− pins are duplicate outputs that can be

used independently or in addition to the RF_OUTA+/RF_OUTA− pins.

Rev. C | Page 15 of 37

ADF4355-2

Data Sheet

Table 6. Total I_DD(RF_OUT

Divide By

A

Refers to RF_OUTA+/RF_OUTA−)

RF_OUTOff RF_OUT= −4 dBm

78 mA

A

RF_OUTA

= −1 dBm

RF_OUTA

= +2 dBm

RF_OUTA = +5 dBm

5 V Supply (I_VCOand I_P)

78 mA

3.3 V Supply (AI_DD, DI_DD, I_RF)

1

2

4

8

16

32

64

79.8 mA

87.8 mA

97.1 mA

104.9 mA

109.8 mA

113.6 mA

115.9 mA

101.3 mA

110.1 mA

119.3 mA

127.1 mA

131.8 mA

135.5 mA

137.8 mA

111.9 mA

120.6 mA

130.1 mA

137.8 mA

142.7 mA

146.5 mA

148.9 mA

122.7 mA

131.9 mA

141.6 mA

149.2 mA

154.1 mA

157.8 mA

160.1 mA

132.8 mA

141.9 mA

152.1 mA

159.7 mA

164.6 mA

168.4 mA

170.8 mA

Rev. C | Page 16 of 37

Data Sheet

ADF4355-2

REGISTER MAPS

REGISTER 0

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

N15 N14 N13 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1 C4(0) C3(0) C2(0) C1(0)

0

AC1

PR1

N16

REGISTER 1

CONTROL

BITS

1

RESERVED

24-BIT MAIN FRACTIONAL VALUE (FRAC1)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

0

C3(0) C2(0) C1(1)

C4(0)

0

REGISTER 2

CONTROL

BITS

1

DBR

14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2)

DBR

14-BIT AUXILIARY MODULUS VALUE (MOD2)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

M14 M13 M12 M11 M10 M9

M8

M7

M6

M5

M4

M3

M2

M1

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

C3(0) C2(1) C1(0)

C4(0)

REGISTER 3

CONTROL

BITS

1

24-BIT PHASE VALUE (PHASE)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3(0) C2(1) C1(1)

P1 C4(0)

0

SD1

PR1 PA1 P24

P23 P22

P21

P20

P19

P18

P17

P16 P15

P14 P13

P12

P11 P10

P9

P8

P7

P6

P5

P4

P3

P2

REGISTER 4

CONTROL

BITS

CURRENT

SETTING

1

DBR

1

RESERVED

MUXOUT

10-BIT R COUNTER

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3(1) C2(0) C1(0)

U1 C4(0)

0

M3

M2

M1

RD2 RD1

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4

CP3 CP2 CP1 U6

U5

U4

U3

U2

REGISTER 5

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

C4(0) C3(1) C2(0)

C1(1)

REGISTER 6

AUX RF

OUTPUT

POWER

RF

OUTPUT

POWER

RF DIVIDER

CONTROL

BITS

2

RESERVED

SELECT

CHARGE PUMP BLEED CURRENT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BL2

BL3

0

BL10 BL9

1

0

1

0

D13 D12 D11

D10

BL7

BL4

BL1

0

D8

0

D6

D5

D4

D3

D2

D1

BL8

BL6

BL5

C4(0) C3(1) C2(1) C1(0)

1

2

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.

Figure 28. Register Summary (Register 0 to Register 6)

Rev. C | Page 17 of 37

ADF4355-2

Data Sheet

REGISTER 7

LD

CYCLE

COUNT

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LD4

LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)

0

1

0

LE

0

LD5

LOL

REGISTER 8

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

1

0

C4(1) C3(0) C2(0) C1(0)

REGISTER 9

SYNTHESIZER

LOCK TIMEOUT

CONTROL

BITS

VCO BAND DIVISION

TIMEOUT

AUTOMATIC LEVEL TIMEOUT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VC8 VC7 VC6 VC5 VC4 VC3 VC2 VC1 TL10 TL9 TL8 TL7 TL6 TL5 TL4 TL3 TL2 TL1 AL5 AL4 AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)

REGISTER 10

ADC

CLOCK DIVIDER

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

AD8 AD7 AD6

AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)

REGISTER 11

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

C4(1) C3(0) C2(1) C1(1)

0

REGISTER 12

CONTROL

BITS

RESERVED

RESYNC CLOCK

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P13 P12

P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1

0

1

0

1

P16 P15

C4(1) C3(1) C2(0) C1(0)

P14

Figure 29. Register Summary (Register 7 to Register 12)

Rev. C | Page 18 of 37

Data Sheet

ADF4355-2

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22

DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

N15 N14 N13 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1 C4(0) C3(0) C2(0) C1(0)

0

AC1

PR1

N16

0

N15

0

...

N5

N4

N3

N2

N1

0

1

0

.

INTEGER VALUE (INT)

PR1 PRESCALER

0

.

0

.

0

.

0

1

.

NOT ALLOWED

0

1

4/5

8/9

0

NOT ALLOWED

0

NOT ALLOWED

.

...

0

1

.

0

1

.

1

0

.

1

0

.

0

1

0

.

NOT ALLOWED

0

23

0

24

VCO

AUTOCAL

AC1

.

...

1

0

1

0

1

65533

65534

65535

0

1

DISABLED

ENABLED

1

INT

MIN

= 75 WITH PRESCALER = 8/9

Figure 30. Register 0

Prescaler Value

REGISTER 0

The dual modulus prescaler (P/P + 1), along with the INT,

FRACx, and MODx counters, determines the overall division

ratio from the VCO output to the PFD input. The PR1 bit

(Bit DB20) in Register 0 sets the prescaler value.

Control Bits

With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 30

shows the input data format for programming this register.

Reserved

Operating at CML levels, the prescaler takes the clock from the

VCO output and divides it down for the counters. It is based on

a synchronous 4/5 core. When the prescaler is set to 4/5, the

maximum RF frequency allowed is 7 GHz. The prescaler limits

the INT value; therefore, if P is 4/5, N_MINis 23, and if P is 8/9,

Bits[DB31:DB22] are reserved and must be set to 0.

Automatic Calibration (Autocalibration)

Write to Register 0 to enact (by default) the VCO autocalibration,

and to choose the appropriate VCO and VCO subband. Write 1

to the AC1 bit (Bit DB21) to enable the autocalibration, which is

the recommended mode of operation.

N_MINis 75.

16-Bit Integer Value

Set the AC1 bit to 0 to disable the autocalibration, which leaves

the ADF4355-2 in the same band it was already in when

Register 0 is updated.

The 16 INT bits (Bits[DB19:DB4]) set the INT value, which

determines the integer part of the feedback division factor. The

INT value is used in Equation 3 (see the INT, FRAC, MOD, and

R Counter Relationship section). All integer values from 23 to

32,767 are allowed for the 4/5 prescaler. For the 8/9 prescaler, the

minimum integer value is 75, and the maximum value is 65,535.

Disable the autocalibration only for fixed frequency applications,

phase adjust applications, or very small (<10 kHz) frequency

jumps. Toggling autocalibration is also required when changing

frequency (see the Frequency Update Sequence section for

additional details).

Rev. C | Page 19 of 37

ADF4355-2

Data Sheet

CONTROL

BITS

1

RESERVED

24-BIT MAIN FRACTIONAL VALUE (FRAC1)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1

0

C3(0) C2(0) C1(1)

C4(0)

0

F24

F23

.......... F2

F1

MAIN FRACTIONAL VALUE (FRAC1)

0

.

0

.

..........

.........

0

1

.

0

1

0

1

.

0

1

2

3

.

1

0

1

0

1

0

1

16777212

16777213

16777214

16777215

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 31. Register 1

24-Bit Main Fractional Value

REGISTER 1

The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the

fraction that is input to the sigma-delta (Σ-Δ) modulator. This

fraction, along with the INT value, specifies the new frequency

channel that the synthesizer locks to, as shown in the RF

Synthesizer—A Worked Example section. FRAC1 values from 0

to (MOD1 − 1) cover channels over a frequency range equal to

the PFD reference frequency.

Control Bits

With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 31

shows the input data format for programming this register.

Reserved

Bits[DB31:DB28] are reserved and must be set to 0.

Rev. C | Page 20 of 37

Data Sheet

ADF4355-2

CONTROL

BITS

14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2) DBR¹

14-BIT AUXILIARY MODULUS VALUE (MOD2) DBR¹

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

M14 M13 M12 M11 M10 M9

M8

M7

M6

M5

M4

M3

M2

M1

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

C1(0)

C3(0) C2(1)

C4(0)

M14 M13 .......... M2

M1

0

1

0

1

.

MODULUS VALUE (MOD2)

F14

F13

.......... F2

F1

0

1

0

1

.

FRAC2 WORD

0

.

0

.

..........

.........

0

1

.

NOT ALLOWED

0

.

0

.

..........

.........

0

1

.

0

NOT ALLOWED

1

2

3

.

1

0

1

0

1

0

1

16380

16381

16382

16383

1

0

1

0

1

0

1

16381

16382

16383

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 32. Register 2

14-Bit Auxiliary Modulus Value (MOD2)

REGISTER 2

The 14-bit auxiliary modulus value (Bits[DB17:DB4]) sets the

auxiliary fractional modulus. Use MOD2 to correct any residual

error due to the main fractional modulus.

Control Bits

With Bits[C4:C1] set to 0010, Register 2 is programmed. Figure 32

shows the input data format for programming this register.

14-Bit Auxiliary Fractional Value (FRAC2)

The 14-bit auxiliary fractional value (Bits[DB31:DB18]) controls

the auxiliary fractional word. FRAC2 must be less than the

MOD2 value programmed in Register 2.

Rev. C | Page 21 of 37

ADF4355-2

Data Sheet

CONTROL

BITS

1

DBR

24-BIT PHASE VALUE (PHASE)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3(0) C2(1) C1(1)

0

SD1

PR1 PA1 P24

P23 P22

P21

P20

P19

P18

P17

P16

P15

P14 P13

P12

P11 P10

P9

P8

P7

P6

P5

P4

P3

P2

P1 C4(0)

PHASE

ADJUST

PA1

P24

P23

.......... P2

P1

PHASE VALUE (PHASE)

0

1

DISABLED

ENABLED

0

.

0

.

..........

0

1

.

0

1

0

1

.

0

..........

.........

1

2

3

PHASE

RESYNC

PR1

.

0

1

DISABLED

ENABLED

.

1

0

1

0

1

0

1

16777212

16777213

16777214

16777215

SD LOAD

RESET

SD1

0

1

ON REGISTER0 UPDATE

DISABLED

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 33. Register 3

This is achieved by programming the D13 bit (Bit DB24) in

Register 6 to 0, which ensures divided feedback to the N divider.

Phase resynchronization only operates when FRAC2 = 0.

REGISTER 3

Control Bits

With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 33

shows the input data format for programming this register.

For resync applications, enable the SD load reset in Register 3

by setting DB30 to 0.

Reserved

Phase Adjust

Bit DB31 is reserved and must be set to 0.

SD Load Reset

To adjust the relative output phase of the ADF4355-2 on each

Register 0 update, set the PA1 bit (Bit DB28) to 1. This feature

differs from the resynchronization feature in that it is useful

when adjustments to phase are made continually in an application.

For this function, disable the VCO autocalibration by setting the

AC1 bit (Bit DB21) in Register 0 to 1, and disable the SD load reset

by setting the SD1 bit (Bit DB30) in Register 3 to 1. Note that

phase resync and phase adjust cannot be used simultaneously.

When writing to Register 0, the Σ-Δ modulator resets. For

applications in which the phase is continually adjusted, this may

not be desirable; therefore, in these cases, the Σ-Δ reset can be

disabled by writing a 1 to the SD1 bit (Bit DB30).

Phase Resync

To use the phase resynchronization feature, the PR1 bit (Bit DB29)

must be set to 1. If unused, the bit can be programmed to 0. The

phase resync timer must also be used in Register 12 to ensure

that the resynchronization feature is applied after PLL has settled to

the final frequency. If the PLL has not settled to the final frequency,

phase resync may not function correctly. Resynchronization is

useful in phased array and beam forming applications. It ensures

repeatability of output phase when programming the same

frequency. In phase critical applications that use frequencies

requiring the output divider (<3400 MHz), it is necessary to

feed the N divider with the divided VCO frequency as distinct

from the fundamental VCO frequency.

24-Bit Phase Value

The phase of the RF output frequency can adjust in 24-bit steps;

from 0° (0) to 360° (2²⁴− 1). For phase adjust applications, the

phase is set by

(Phase Value/16,777,216) × 360°

When the phase value is programmed to Register 3, each

subsequent adjustment of Register 0 increments the phase by

the value in this equation.

Rev. C | Page 22 of 37

Data Sheet

ADF4355-2

CURRENT

SETTING

CONTROL

BITS

MUXOUT

10-BIT R COUNTER

DBR¹

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

0

M3

M2

M1 RD2 RD1 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4 CP3 CP2 CP1 U6

U5

U4

U3

U2

U1

C3(1) C2(0) C1(0)

C4(0)

REFERENCE

RD2

COUNTER

RESET

DOUBLE BUFFERED

REGISTER 6, BITS[DB23:DB21]

U1

DOUBLER

D1

U6

0

REFIN

SINGLE

DIFF

0

1

DISABLED

ENABLED

0

1

DISABLED

ENABLED

0

1

DISABLED

1

ENABLED

RD1 REFERENCE DIVIDE BY 2

CP

I

(mA)

CP

U2

U5

LDP

THREE-STATE

CP4

CP3

CP2

CP1

5.1kΩ

0

1

DISABLED

ENABLED

0

1

1.8V

3.3V

0

1

DISABLED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.31

0.63

0.94

1.25

1.56

1.88

2.19

2.50

2.81

3.13

3.44

3.75

4.06

4.38

4.69

5.00

ENABLED

R10

R9

..........

R2

R1

R DIVIDER (R)

U4

0

PD POLARITY

NEGATIVE

POSITIVE

U3

POWER DOWN

0

.

0

.

..........

0

1

.

1

0

.

1

0

1

DISABLED

ENABLED

2

1

.

1

0

1

0

1

0

1

1020

1021

1022

1023

M3

0

M2

0

M1

0

OUTPUT

THREE-STATE OUTPUT

0

1

DV

DD

0

1

0

SD

GND

0

1

R DIVIDER OUTPUT

N DIVIDER OUTPUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

RESERVED

1

0

1

0

1

0

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.

Figure 34. Register 4

RDIV2

REGISTER 4

Setting the RDIV2 bit (Bit DB25) to 1 inserts a divide by 2 toggle

flip-flop between the R counter and PFD, which extends the

maximum reference frequency input rate. This function

provides a 50% duty cycle signal at the PFD input.

Control Bits

With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 34

shows the input data format for programming this register.

Reserved

10-Bit R Counter

Bits[DB31:DB30] are reserved and must be set to 0.

The 10-bit R counter divides the input reference frequency

(REF_IN) to produce the reference clock to the PFD. Division

ratios range from 1 to 1023.

MUXOUT

The on-chip multiplexer (MUXOUT) is controlled by

Bits[DB29:DB27]. For additional details, see Figure 34.

Double Buffer

Reference Doubler

The D1 bit (Bit DB14) enables or disables double buffering of

the RF divider select bits (Bits[DB23:DB21]) in Register 6. The

section explains how double buffering works.

Setting the RD2 bit (Bit DB26) to 0 feeds the REF_INsignal directly

to the 10-bit R counter, disabling the doubler. Setting this bit to

1 multiplies the reference frequency by a factor of 2 before feeding

it into the 10-bit R counter. When the doubler is disabled, the

REF_INfalling edge is the active edge at the PFD input to the

fractional synthesizer. When the doubler is enabled, both the rising

and falling edges of the reference frequency become active edges

at the PFD input.

Charge Pump Current Setting

The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump

current. Set this value to the charge pump current for which the

loop filter is designed (see Figure 34). For the lowest spurs, the

0.9 mA setting is recommended.

The maximum allowable reference frequency when the doubler

is enabled is 100 MHz.

Rev. C | Page 23 of 37

ADF4355-2

Data Sheet

When power-down activates, the following events occur:

Reference Mode

The ADF4355-2 permits use of either differential or single-

ended reference sources. For differential sources, set the

reference mode bit (Bit DB9) to 1, and set it to 0 for single-

ended sources.



The synthesizer counters are forced to their load state

conditions.

The VCO powers down.

The charge pump is forced into three-state mode.

The digital lock detect circuitry resets.

The RF_OUTA+/RF_OUTA− and RF_OUTB+/RF_OUTB− output

stages are disabled.

The input registers remain active and capable of loading

and latching data.



For optimum integer boundary spur performance, use the

single-ended setting for all references up to 250 MHz (even if

using a differential reference signal). Use the differential setting for

reference frequencies above 250 MHz.



Level Select

To assist with logic compatibility, MUXOUT is programmable to

two logic levels. Set theU5 bit (Bit DB8) to 0 to select 1.8 V

logic, and set it to 1 to select 3.3 V logic.

Charge Pump Three-State

Setting the U2 bit (Bit DB5) to 1 puts the charge pump into

three-state mode. Set DB5 to 0 for normal operation.

Phase Detector Polarity

Counter Reset

The U4 bit (Bit DB7) sets the phase detector polarity. When a

passive loop filter or a noninverting active loop filter is used,

set DB7 to 1 (positive). If an active filter with an inverting

characteristic is used, set this bit to 0 (negative).

The U1 bit (Bit DB4) resets the R counter, N counter, and VCO

band select of the ADF4355-2. When DB4 is set to 1, the RF

synthesizer N counter and R counter and the VCO band select

are reset. For normal operation, set DB4 to 0. Toggling counter

reset (Bit DB4) is also required when changing frequency (see

the Frequency Update Sequence section for additional details).

Power-Down

The U3 bit (Bit DB6) sets the programmable power-down mode.

Setting DB6 to 1 performs a power-down. Setting DB6 to 0

returns the synthesizer to normal operation. In software power-

down mode, the ADF4355-2 retains all information in its registers.

The register contents are only lost if the supply voltages are

removed.

REGISTER 5

The bits in Register 5 are reserved and must be programmed as

described in Figure 35, using a hexadecimal word of 0x00800025.

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C4(0) C3(1) C2(0)

0

1

0

1

0

C1(1)

Figure 35. Register 5 (0x00800025)

Rev. C | Page 24 of 37

Data Sheet

ADF4355-2

AUX RF

OUTPUT

POWER

RF

OUTPUT

POWER

RF DIVIDER

SELECT¹

CONTROL

BITS

RESERVED

CHARGE PUMP BLEED CURRENT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BL2

BL3

0

BL10 BL9

1

0

1

0

D13 D12 D11 D10

BL7

BL4

BL1

0

D8

0

D6

D5

D4

D3

D2

D1

BL8

BL6 BL5

C4(0) C3(1) C2(1) C1(0)

FEEDBACK

SELECT

D13

D2

D1

OUTPUT POWER

–4dBm

0

1

0

1

DIVIDED

1

0

1

–1dBm

FUNDAMENTAL

+2dBm

+5dBm

BLEED CURRENT

BL9

D12

D11

D10 RF DIVIDER SELECT

D3

0

RF OUT

0

1

DISABLED

ENABLED

0

1

0

1

0

1

0

1

0

1

0

1

0

÷1

DISABLED

ENABLED

÷2

MUTE TILL

LOCK DETECT

1

D8

÷4

0

1

MUTE DISABLED

MUTE ENABLED

÷8

GATED BLEED

BL10

D5

0

D4

0

AUXILARY OUTPUT POWER

÷16

÷32

÷64

–4dBm

–1dBm

+2dBm

+5dBm

0

1

DISABLED

ENABLED

0

1

0

1

D6

0

AUXILARY OUT

DISABLED

1

ENABLED

BL8

BL7

..........

BL2

BL1 BLEED CURRENT

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

(3.75µA)

(7.5µA)

.

1

0

1

0

1

0

1

252 (945µA)

253 (948.75µA)

254 (952.5µA)

255 (956.25µA)

1

BITS[DB23:DB21] ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT IS ENABLED, BIT DB14 OF REGISTER 4.

Figure 36. Register 6

Use negative bleed only when operating in fractional-N mode,

that is, FRAC1 = FRAC2 = 0. Do not use negative bleed for f_PFD

greater than 100 MHz.

REGISTER 6

Control Bits

With Bits[C4:C1] set to 0110, Register 6 is programmed. Figure 36

shows the input data format for programming this register.

Reserved

Bits[DB28:DB25] are reserved and must be set to 1010.

Reserved

Feedback Select

Bit DB31 is reserved and must be set to 0.

Gated Bleed

D13 (Bit DB24) selects the feedback from the output of the VCO to

the N counter. When D13 is set to 1, the signal is taken directly

from the VCO. When this bit is set to 0, the signal is taken from

the output of the output dividers. The dividers enable coverage of

the wide frequency band (54 MHz to 4.4 GHz). When the divider

is enabled and the feedback signal is taken from the output, the

RF output signals of two separately configured PLLs are in phase.

Divided feedback is useful in some applications where the positive

interference of signals is required to increase the power.

Bleed currents can be used for improving phase noise and

spurs. However, due to a potential impact on lock time, the

gated bleed bit, BL10 (Bit DB30), if set to 1, ensures bleed currents

are not switched on until the digital lock detect asserts logic high.

Note that this function requires digital lock detect to be enabled.

Negative Bleed

Use of constant negative bleed is recommended for most

applications because it improves the linearity of the charge pump,

leading to lower noise and spurious than if the negative bleed is

left off. To enable negative bleed, write 1 to BL9 (Bit DB29), and

to disable negative bleed, write 0 to BL9 (Bit DB29).

Divider Select

D12 to D10 (Bits[DB23:DB21]) select the value of the RF output

divider (see Figure 36).

Rev. C | Page 25 of 37

ADF4355-2

Data Sheet

Charge Pump Bleed Current

Reserved

BL8 to BL1 (Bits[DB20:DB13]) control the level of the bleed

current added to the charge pump output. This current

optimizes the phase noise and spurious levels from the device.

Bit DB10 is reserved and must be set to 0.

Auxiliary RF Output Enable

Bit DB9 enables or disables the auxiliary frequency RF output

(RF_OUTB+/RF_OUTB−). When DB9 is set to 1, the auxiliary

frequency RF output is enabled. When DB10 is set to 0, the

auxiliary RF output is disabled.

Tests have shown that the optimal bleed set is the following:

4/N < I_BLEED/I_CP< 10/N

where:

Auxiliary RF Output Power

I_BLEEDis the value of constant negative bleed applied to the

charge pump, which is set by the contents of Bits[BL8:BL1].

I_CPis the value of charge pump current setting, Bits[DB13:DB10] of

Register 4.

Bits[DB8:DB7] set the value of the auxiliary RF output power

level (see Figure 43).

RF Output Enable

N is the value of the feedback counter from the VCO to the PFD.

Bit DB6 enables or disables the primary RF output (RF_OUTA+/

RF_OUTA−). If DB6 is set to 0, the primary RF output is disabled;

if DB6 is set to 1, the primary RF output is enabled.

Reserved

Bit DB12 is reserved and must be set to 0.

Mute Till Lock Detect

Output Power

When D8 (Bit DB11) is set to 1, the supply current to the RF

output stage is shut down until the device achieves lock, as

determined by the digital lock detect circuitry.

Bits[DB5:DB4] set the value of the primary RF output power

level (see Figure 43).

Rev. C | Page 26 of 37

Data Sheet

ADF4355-2

LD

CYCLE

COUNT

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LD4

LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)

0

1

0

LE

0

LD5

LOL

LD1 LOCK DETECT MODE

FRACTIONAL-N

0

1

INTEGER-N (2.9ns)

LD3

0

LD2

0

FRACTIONAL-N LD PRECISION

5.0ns

6.0ns

8.0ns

12.0ns

0

1

0

1

LE

LE SYNCHRONIZATION

LOL LOSS OF LOCK MODE

DISABLED

ENABLED

0

1

0

1

LE SYNCED TO REFIN

LD5

0

LD4

LOCK DETECT CYCLE COUNT

0

1

0

1

1024

2048

4096

8192

0

1

Figure 37. Register 7

Loss of Lock Mode

REGISTER 7

Set LOL (Bit DB7) to 1 when the application is a fixed frequency

application in which the reference (REF_IN) is likely to be removed,

such as a clocking application. The standard lock detect circuit

assumes that REF_INis always present; however, this may not be

the case with clocking applications. To enable this functionality,

set DB7 to 1. Loss of lock mode does not function reliably when

using a differential REF_INmode.

Control Bits

With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 37

shows the input data format for programming this register.

Reserved

Bits[DB31:DB29] are reserved and must be set to 0. Bit DB28 is

reserved and must be set to 1. Bits[DB27:DB26] are reserved

and must be set to 0.

Fractional-N Lock Detect Precision (LDP)

LE Sync

LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect

circuitry in fractional-N mode. LDP is available at 5 ns, 6 ns, 8 ns,

or 12 ns. If bleed currents are used, use 12 ns.

When set to 1, Bit DB25 ensures that the LE edge is synchronized

internally with the rising edge of reference input frequency. This

synchronization prevents the rare event of reference and RF

dividers loading at the same time as a falling edge of reference

frequency, which can lead to longer lock times.

Lock Detect Mode (LDM)

If LD1 (Bit DB4) is set to 0, each reference cycle is set by

fractional-N lock detect precision as described in the

Fractional-N Lock Detect Count (LDC) section. If DB4 is

set to 1, each reference cycle is 2.9 ns long, which is more

appropriate for integer-N applications.

Reserved

Bits[DB24:DB10] are reserved and must be set to 0.

Fractional-N Lock Detect Count (LDC)

LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive

cycles counted by the lock detect circuitry before asserting lock

detect high. See Figure 37 for details.

Rev. C | Page 27 of 37

ADF4355-2

Data Sheet

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

1

0

C4(1) C3(0) C2(0) C1(0)

Figure 38. Register 8 (0x102D0428)

SYNTHESIZER

LOCK TIMEOUT

CONTROL

BITS

VCO BAND DIVISION

TIMEOUT

AUTOMATIC LEVEL TIMEOUT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VC8 VC7 VC6

VC5 VC4 VC3 VC2 VC1 TL10 TL9

TL8

TL7

TL6

TL5

TL4

TL3

TL2

TL1 AL5 AL4

AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)

SL5

SL4

..........

SL2

SL1 SLC WAIT

0

.

0

.

..........

0

1

.

1

0

.

1

TL10

TL9

..........

TL2

TL1 TIMEOUT

2

0

.

0

.

..........

0

1

.

1

0

.

1

.

2

.

1

0

1

0

1

0

1

28

29

30

31

.

1

0

1

0

1

0

1

1020

1021

1022

1023

AL5

AL4

..........

AL2

AL1 ALC WAIT

VC8

VC7

..........

VC2

VC1 VCO BAND DIV

0

.

0

.

..........

0

1

.

1

0

.

1

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

1

0

1

0

1

0

1

28

29

30

31

1

0

1

0

1

0

1

252

253

254

255

Figure 39. Register 9

Automatic Level Calibration (ALC) Timeout

REGISTER 8

AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the

automatic level calibration of the VCO. This function combines

the PFD frequency, the timeout variable, and ALC wait variable.

Choose ALC such that the following equation is always greater

than 50 μs.

The bits in this register are reserved and must be programmed

as described in Figure 38, using a hexadecimal word of

0x102D0428.

REGISTER 9

Control Bits

(Timeout × ALC Wait/PFD Frequency) > 50 μs

With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 39

shows the input data format for programming this register.

Synthesizer Lock Timeout

SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout

value. Use this value to allow the V_TUNEforce to settle on the

VCO Band Division

VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band

division clock. Determine the value of this clock by PFD/(band

division × 16) such that the result is <150 kHz.

V_TUNEpin. The value must be 20 μs. Calculate the value using

the following equation:

(Timeout × Synthesizer Lock Timeout/PFD Frequency) > 20 μs

Timeout

TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the

VCO band select. Use this value as a variable in the other VCO

calibration settings.

Rev. C | Page 28 of 37

ADF4355-2

Data Sheet

ADC

CLOCK DIVIDER

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)

0

1

0

AE1 ADC

0

1

DISABLED

ENABLED

AE2 ADC CONVERSION

0

1

DISABLED

ENABLED

AD8

AD7

..........

AD2 AD1 ADC CLK DIV

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

1

0

1

0

1

0

1

252

253

254

255

Figure 40. Register 10

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

C4(1) C3(0) C2(1) C1(1)

0

Figure 41. Register 11 (0x0061300B)

Choose the ADC_CLK_DIV value such that

REGISTER 10

Control Bits

ADC_CLK_DIV = ceiling(((f_PFD/100,000) − 2)/4)

With Bits[C4:C1] set to 1010, Register 10 is programmed.

Figure 40 shows the input data format for programming this

register.

where ceiling() is a function to round up to the nearest integer.

For example, for f_PFD= 61.44 MHz, set ADC_CLK_DIV = 154

so that the ADC clock frequency is 99.417 kHz. If ADC_CLK_DIV

is greater than 255, set it to 255.

Reserved

Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to

11, but all other bits in this range must be set to 0.

ADC Conversion Enable

AE2 (Bit DB5) ensures that the ADC performs a conversion

when a write to Register 10 is performed. It is recommended to

enable this mode.

ADC Clock Divider (ADC_CLK_DIV)

An on-board analog-to-digital converter (ADC) determines

the V_TUNEsetpoint relative to the ambient temperature of the

ADF4355-2 environment. The ADC ensures that the initial

tuning voltage in any application is chosen correctly to avoid

any temperature drift issues.

ADC Enable

When set to 1, AE1 (Bit DB4) powers up the ADC for the

temperature dependent V_TUNEcalibration. It is recommended to

always use this function.

The ADC uses a clock that is equal to the output of the R counter

(or the PFD frequency) divided by ADC_CLK_DIV.

REGISTER 11

The bits in this register are reserved and must be programmed

as described in Figure 41 using a hexadecimal word of

0x0061300B.

AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On

power-up, the R counter is not programmed; however, in these

power-up cases, it defaults to R = 1.

Rev. C | Page 29 of 37

ADF4355-2

Data Sheet

CONTROL

BITS

RESERVED

RESYNC CLOCK

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P13

P12

P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1

C4(1) C3(1) C2(0) C1(0)

0

1

0

1

P16

P15

P14

P16

P15

...

P5

P4

P3

P2

P1

RESYNC CLOCK

0

.

0

.

0

.

0

.

0

.

0

1

.

0

1

0

.

NOT ALLOWED

1

2

...

0

.

0

.

1

.

0

1

.

1

0

.

1

0

.

0

1

0

.

22

23

24

...

1

0

1

0

1

65533

65534

65535

Figure 42. Register 12

For f_PFD> 75 MHz (initially lock with half f_PFD), use the

following sequence:

REGISTER 12

Control Bits

1. Register 12.

2. Register 11.

3. Register 10.

4. Register 9.

With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 42

shows the input data format for programming this register.

Phase Resync Clock Divider Value

P16 to P1 (Bits[DB31:DB16]) set the timeout counter for activation

of phase resync. This value must be set such that the resync

happens immediately after (and not before) the PLL has

achieved lock after reprogramming.

5. Register 8.

6. Register 7.

7. Register 6.

8. Register 5.

9. Register 4 (with the R divider doubled to output half f_PFD).

10. Register 3.

Calculate the timeout value using the following:

Time Out Value = Phase Resync Clock/PFD Frequency

Reserved

11. Register 2 (for halved f_PFD).

12. Register 1 (for halved f_PFD).

13. Wait >16 ADC_CLK cycles. For example, if

ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.

See the Register 10 section for more information.

14. Register 0 (for halved f_PFD; autocalibration enabled).

15. Register 4 (with the R divider set for desired f_PFD).

16. Register 2 (for desired f_PFD).

17. Register 1 (for desired f_PFD).

18. Register 0 (for desired f_PFD; autocalibration disabled).

Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set

to 1, but all other bits in this range must be set to 0.

REGISTER INITIALIZATION SEQUENCE

At initial power-up, after the correct application of voltages to

the supply pins, registers must be programmed in sequence. For

f ≤ 75 MHz, use the following sequence:

1. Register 12

2. Register 11

3. Register 10

4. Register 9

5. Register 8

6. Register 7

7. Register 6

8. Register 5

9. Register 4

10. Register 3

11. Register 2

12. Register 1

13. Wait >16 ADC_CLK cycles. For example, if

ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs.

See the Register 10 section for more information.

14. Register 0

Rev. C | Page 30 of 37

Data Sheet

ADF4355-2

f_PFD= REF_IN× ((1 + D)/(R × (1 + T)))

(8)

FREQUENCY UPDATE SEQUENCE

where:

Frequency updates require updating the auxiliary modulator

(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,

and the integer value (INT) in Register 0. It is recommended to

perform a temperature dependent V_TUNEcalibration by updating

Register 10 first. A counter reset (Bit DB4) is also required in

the frequency update sequence Therefore, for f_PFD≤ 75 MHz,

the sequence must be as follows:

REF_INis the reference frequency input.

D is the RF REF_INdoubler bit.

R is the RF reference division factor.

T is the reference divide by 2 bit (0 or 1).

For example, in a universal mobile telecommunication system

(UMTS) where 2112.8 MHz RF frequency output (RF_OUT) is

required, a 122.88 MHz reference frequency input (REF_IN) is

available. Note that the ADF4355-2 VCO operates in the frequency

range of 3.4 GHz to 6.8 GHz. Therefore, an RF divider of 2 must be

used (VCO frequency = 4225.6 MHz, RF_OUT= VCO frequency/RF

divider = 4225.6 MHz/2 = 2112.8 MHz).

1. Register 10.

2. Register 4 (counter reset enabled [DB4 = 1])

3. Register 2

4. Register 1

5. Register 0 (autocalibration disabled [DB21 = 0])

6. Register 4 (counter reset disabled [DB4 = 0])

7. Wait > 16 ADC_CLK_DIV cycles. For example, if

ADC_CLK_DIV = 99.417 kHz, wait 16/99417 sec =

161 µs. See the Register 10 section.

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 43).

In this example, divide the 122.88 MHz signal by 2 to generate a

f_PFDof 61.44 MHz. The desired channel spacing is 200 kHz.

8. Register 0 (autocalibration enabled [DB21 = 1])

f_PFD

RF

OUT

For f_PFD> 75 MHz (initially lock with half f_PFD), the sequence

must be as follows:

PFD

VCO

÷2

1. Register 10.

2. Register 4 (counter reset enabled [DB4 = 1])

3. Register 2 (for halved f_PFD).

N

DIVIDER

Figure 43. Loop Closed Before Output Divider

4. Register 1 (for halved f_PFD).

5. Register 0 (for halved f_PFD; autocalibration disabled).

6. Register 4 (counter reset disabled [DB4 = 0]), with the

The worked example is as follows:

•

N = VCO_OUT/f_PFD= 4225.6 MHz/61.44 MHz =

68.7760416666666667

R divider doubled to output half f_PFD

.

•

INT = int(VCO frequency/f_PFD) = 68

FRAC = 0.7760416666666667

MOD1 = 16,777,216

FRAC1 = int(MOD1 × FRAC) = 13019817

Remainder = 0.6666666667 or 2/3

MOD2 = f_PFD/GCD(f_PFD/f_CHSP) =

61.44 MHz/GCD(61.44 MHz/200 kHz) = 1536

FRAC2 = remainder × 1536 = 1024

7. Wait >16 ADC_CLK cycles. For example, if

ADC_CLK = 99.417 kHz, wait 16/99417 sec = 161 μs.

See the Register 10 section for more information.

8. Register 0 (for halved f_PFD; autocalibration enabled).

9. Register 4 (with the R divider set for desired f_PFD).

10. Register 2 (for desired f_PFD).

11. Register 1 (for desired f_PFD).

12. Register 0 (for desired f_PFD; autocalibration disabled).

•

The frequency change only occurs when writing to Register 0.

From Equation 8, where the RF Divider = 2,

_PFD= (122.88 MHz × (1 + 0)/2) = 61.44 MHz

RF SYNTHESIZER—A WORKED EXAMPLE

f

(9)

Use the following equations to program the ADF4355-2

synthesizer:

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/2²⁴))/2

(10)

FRAC2

MOD2

MOD1

where:

INT = 68

FRAC1 = 13,019,817

MOD2 = 1536

FRAC2 = 1024

FRAC1+

RF_OUT

=

INT +

× (f_PFD)/RF Divider (7)

where:

RF_OUTis the RF frequency output.

INT is the integer division factor.

FRAC1 is the fractionality.

FRAC2 is the auxiliary fractionality.

MOD2 is the auxiliary modulus.

MOD1 is the fixed 24-bit modulus.

RF Divider is the output divider that divides down the

VCO frequency.

Rev. C | Page 31 of 37

ADF4355-2

Data Sheet

Lock Time—A Worked Example

REFERENCE DOUBLER AND REFERENCE DIVIDER

Assuming f_PFD= 61.44 MHz,

The on-chip reference doubler allows the input reference signal

to be doubled. The doubler is useful for increasing the PFD

comparison frequency. To improve the noise performance of

the system increase the PFD frequency. Doubling the PFD

frequency usually improves noise performance by 3 dB.

VCO Band Div = Ceiling(f_PFD/2,400,000) = 26

where Ceiling() rounds up to the nearest integer.

By combining the following two equations:

ALC Wait > (50 µs × f_PFD)/Timeout

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

Synthesizer Lock Timeout > (20 µs × f_PFD)/Timeout

The following is found:

SPURIOUS OPTIMIZATION AND FAST LOCK

Narrow loop bandwidths can filter unwanted spurious signals,

but these bandwidths usually have a long lock time. A wider

loop bandwidth achieves faster lock times but may lead to

increased spurious signals inside the loop bandwidth.

ALC Wait = 2.5 × Synthesizer Lock Timeout

Maximize ALC Wait (to reduce Timeout to minimize time) so

that ALC Wait = 30 and Synthesizer Lock Timeout = 12.

Finally, ALC Wait > (50 µs × f_PFD)/Timeout, is rearranged as

Timeout = Ceiling((f_PFD× 50 µs)/ALC Wait)

Timeout = Ceiling((61.44 MHz × 50 µs)/30) = 103

Synthesizer Lock Timeout

OPTIMIZING JITTER

For lowest jitter applications, use the highest possible PFD

frequency to minimize the contribution of in-band noise from

the PLL. Set the PLL filter bandwidth such that the in-band noise

of the PLL intersects with the open-loop noise of the VCO,

minimizing the contribution of both to the overall noise.

The synthesizer lock timeout ensures that the VCO calibration

DAC, which forces V_TUNE, has settled to a steady value for the

band select circuitry.

Use the ADIsimPLL design tool for this task.

The timeout and synthesizer lock timeout variables programmed

in Register 9 select the length of time the DAC is allowed to

settle to the final voltage, before the VCO calibration process

continues to the next phase, which is VCO band selection. The

PFD frequency is used as the clock for this logic, and the

duration is set by

SPUR MECHANISMS

This section describes the two different spur mechanisms that

arise with a fractional-N synthesizer and how to minimize them

in the ADF4355-2.

Integer Boundary Spurs

One mechanism for fractional spur creation is the interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (the purpose of a

fractional-N synthesizer), spur sidebands appear on the VCO

output spectrum at an offset frequency that corresponds to the

beat note or the difference in frequency between an integer

multiple of the reference and the VCO frequency. These spurs

are attenuated by the loop filter and are more noticeable on

channels close to integer multiples of the reference where the

difference frequency can be inside the loop bandwidth (thus

the name, integer boundary spurs).

Timeout ×Synthesizer Lock Timeout

PFD Frequency

The calculated time must be equal to or greater than 20 µs.

VCO Band Selection

Use the PFD frequency again as the clock for the band selection

process. Calculate this value by

PFD/(VCO Band Selection × 16) < 150 kHz

The band selection takes 11 cycles of the previously calculated

value. Calculate the duration by

Reference Spurs

11 × (VCO Band Selection × 16)/PFD Frequency

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop may cause a problem. Feedthrough of

low levels of on-chip reference switching noise, through the

prescaler back to the VCO, can result in reference spur levels

as high as −80 dBc.

Automatic Level Calibration Timeout

Use the automatic level calibration (ALC) function to choose

the correct bias current in the ADF4355-2 VCO core. Calculate

the time taken by

5 × 11 × ALC Timeout × Timeout/PFD Frequency

LOCK TIME

The PLL lock time divides into a number of settings. All of

these are modeled in the ADIsimPLL design tool. Faster lock

times than those detailed in this data sheet are possible. Contact

your local Analog Devices, Inc., sales representative for more

information.

Rev. C | Page 32 of 37

Data Sheet

ADF4355-2

PLL Low-Pass Filter Settling Time

The total lock time for changing frequencies is the sum of the

four separate times (synthesizer lock, VCO band selection, ALC

timeout, and PLL settling time) and is all modeled in the

ADIsimPLL design tool.

The time taken for the loop to settle is inversely proportional to

the low-pass filter bandwidth. The settling time is also modeled

in the ADIsimPLL design tool.

Rev. C | Page 33 of 37

ADF4355-2

Data Sheet

APPLICATIONS INFORMATION

The LO ports of the ADL5375 can be driven differentially from

the complementary RF_OUTA+/RF_OUTA− outputs of the ADF4355-2.

Differential drive gives better second-order distortion performance

than a single-ended LO driver and eliminates the use of a balun

to convert from a single-ended LO input to the more desirable

differential LO input for the ADL5375.

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly used to implement

base station transmitters. Figure 44 shows how to use Analog

Devices, Inc., devices to implement such a system.

The circuit block diagram shows the AD9761 TxDAC® used

with the ADL5375. The use of a dual integrated DAC, such as

the AD9761, ensures minimum error contribution (over

temperature) from this portion of the signal chain.

The ADL5375 accepts LO drive levels from −6 dBm to +6 dBm.

The optimum LO power can be software programmed on the

ADF4355-2, which allows levels from −4 dBm to +5 dBm from

each output.

The local oscillator (LO) is implemented using the ADF4355-2.

The low-pass filter was designed using the ADIsimPLL design

tool for a PFD of 61.44 MHz and a closed-loop bandwidth of

20 kHz.

The RF output is designed to drive a 50 Ω load; however, it must be

ac-coupled, as shown in Figure 44. If the I and Q inputs are driven

in quadrature by 2 V p-p signals, the resulting output power

from the ADL5375 modulator is approximately 2 dBm.

51Ω

REFIO

IOUTA

IOUTB

LOW-PASS

FILTER

MODULATED

DIGITAL

DATA

AD9761

TxDAC

QOUTA

QOUTB

LOW-PASS

FILTER

FSADJ

51Ω

2kΩ

V_VCO

LOCK

DETECT

V_DD

16

100nF

32

100nF

2

25

17

26

10

5

27

4

6

30

C_REG

1

C_REG

V_VCO

PDB_RFV_RF

MUXOUT

V_PAV_DDDV_DDAV_DDCE

1nF 1nF

ADL5375

IBBP

FREF_IN

29

REF_INA

RF_OUTB+ 14

IBBN

V_OUT

RF_OUTB–

FREF_IN

15

28

REF_INB

7.5nH

1

2

3

CLK

DATA

LE

1nF

LOIP

LOIN

11

12

RF_OUTA+

RF_OUTA–

QUADRATURE

PHASE

SPLITTER

LPF

ADF4355-2

RFOUT

DSOP

V_TUNE20

CP_OUT

3.3kΩ

QBBP

QBBN

22 R_SET

7

4.7kΩ

33nF

1500pF

390pF

1kΩ

V_REGVCO

19

V_BIAS

24

CP_GNDSD_GNDA_GNDA_GNDVCO

31 13 18 21

V_REF

23

8

9

10pF

0.1µF 10pF

10pF

0.1µF

Figure 44. Direct Conversion Modulator

Rev. C | Page 34 of 37

Data Sheet

ADF4355-2

Power Supplies

The bottom of the chip-scale package has a central exposed

thermal pad. The thermal pad on the PCB must be at least as

large as the exposed pad. On the PCB, there must be a minimum

clearance of 0.25 mm between the thermal pad and the inner

edges of the pad pattern. This clearance ensures the avoidance

of shorting.

The ADF4355-2 contains four multiband VCOs that together cover

an octave range of frequencies. To ensure best performance, it is

vital to connect a low noise regulator, such as the ADM7170, to

the V_VCOpin. Connect the same regulator to V_VCO, V_REGVCO, and V_P.

For the 3.3 V supply pins, use two ADM7170 regulators, one for

the DV_DDand AV_DDsupplies and one for V_RF. Figure 45 shows

the recommended connections.

To improve the thermal performance of the package, use thermal

vias on the PCB thermal pad. If vias are used, incorporate them

into the thermal pad at the 1.2 mm pitch grid. The via diameter

must measure between 0.3 mm and 0.33 mm and the via barrel

must be plated with 1 oz. of copper to plug the via.

PRINTED CIRCUIT BOARD (PCB) DESIGN

GUIDELINES FOR A CHIP-SCALE PACKAGE

The lands on the 32-lead lead frame chip-scale package are

rectangular. The PCB pad for these lands must be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. Center each land on the pad to

maximize the solder joint size.

For a microwave PLL and VCO synthesizer, such as the ADF4355-2,

take care with the board stack up and layout. Do not consider

using FR4 material because it is too lossy above 3 GHz. Instead,

Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is

suitable.

Take care with the RF output traces to minimize discontinuities

and ensure the best signal integrity. Via placement and grounding

are critical.

V

= 3.3V

OUT

V

= 6.0V

IN

VIN

EN

VOUT

C

10µF

IN

C

10µF

OUT

ON

SENSE

OFF

ADM7170

SS

C

SS

1nF

LOCK

DETECT

GND

100nF

17

V_VCOV_PDV_DDAV_DDCE PDB_RFV_RF

25

C_REG

26

10

6

27

16

4

32

C_REG

30

2

1

MUXOUT

1nF 1nF

V

= 3.3V

C

OUT

FREF_IN

29

REF_INA

V

= 6.0V

RF_OUTB+ 14

IN

VIN

EN

VOUT

V_OUT

C

RF_OUTB–

IN

15

28 REF_INB

OUT

10µF

ON

10µF

7.5nH

SENSE

1

2

3

CLK

DATA

LE

OFF

1nF

ADM7170

11

12

RF_OUTA+

RF_OUTA–

SS

C

ADF4355-2

SS

1nF

GND

V_TUNE

20

7

3.3kΩ

CP_OUT

22 R_SET

4.7kΩ

33nF

V

= 5.0V

C

V

= 6.0V

OUT

IN

1500pF

390pF

AV_DD

5

VIN

EN

VOUT

1kΩ

C

CP_GNDSD_GNDA_GNDA_GNDRFA_GNDVCOV_REGVCO

31 13 18 21 19

V_REFV_BIAS

IN

OUT

10µF

ON

10µF

8

9

23

24

SENSE

OFF

ADM7170

SS

C

SS

1nF

10pF

0.1µF 10pF

0.1µF

GND

Figure 45. ADF4355-2 Power Supplies

Rev. C | Page 35 of 37

ADF4355-2

Data Sheet

When differential outputs are not needed, terminate the unused

output or combine it with both outputs using a balun.

OUTPUT MATCHING

The low frequency output can simply be ac-coupled to the next

circuit, if desired; however, if higher output power is required,

use a pull-up inductor to increase the output power level.

For lower frequencies below 2 GHz, it is recommended to use a

100 nH inductor on the RF_OUTA+/RF_OUTA− pins.

V

The RF_OUTA+/RF_OUTA− pins are a differential circuit. Provide

each output with the same (or similar) components where

possible, such as the same shunt inductor value, bypass

capacitor, and termination.

RF

7.5nH

100pF

RF

A+

OUT

50Ω

The auxiliary frequency output, RF_OUTB+/RF_OUTB−, can be

treated the same as the RF_OUTA+/RF_OUTA− output. If unused,

leave both RF_OUTB+/RF_OUTB− pins open.

Figure 46. Optimum Output Stage

Rev. C | Page 36 of 37

Data Sheet

ADF4355-2

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

25

32

24

1

0.50

BSC

3.75

3.60 SQ

3.55

EXPOSED

PAD

17

8

16

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.

Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height

(CP-32-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADF4355-2BCPZ

ADF4355-2BCPZ-RL7

EV-ADF4355-2SD1Z

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-32-12

32-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D12452-0-8/17(C)

Rev. C | Page 37 of 37


型号：	ADF4355-2BCPZ
厂家：	ADI
描述：	Microwave Wideband Synthesizer with Integrated VCO 信息通信管理
文件：	总37页 (文件大小：991K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF4355-2BCPZ [ADI]

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