ADF4372BCCZ-RL7 [ADI]
Microwave Wideband Synthesizer with Integrated VCO;
| 型号： | ADF4372BCCZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Microwave Wideband Synthesizer with Integrated VCO |
| 文件： | 总47页 (文件大小：849K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microwave Wideband Synthesizer
with Integrated VCO
Data Sheet
ADF4372
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 62.5 MHz to 16,000 MHz
Fractional-N synthesizer and integer-N synthesizer
High resolution 39-bit fractional modulus
Typical spurious fPFD: −90 dBc
Integrated rms jitter: 38 fs (1 kHz to 100 MHz)
Normalized phase noise floor: −234 dBc/Hz
The ADF4372 allows implementation of fractional-N or integer-N
phase-locked loop (PLL) frequency synthesizers when used with
an external loop filter and an external reference frequency. The
wideband microwave voltage controlled oscillator (VCO) design
allows frequencies from 62.5 MHz to 16 GHz to be generated.
The ADF4372 has an integrated VCO with a fundamental output
frequency ranging from 4000 MHz to 8000 MHz. In addition, the
VCO frequency is connected to a divide by 1, 2, 4, 8, 16, 32, or 64
circuit that allows the user to generate radio frequency (RF)
output frequencies as low as 62.5 MHz at RF8x. A frequency
multiplier at RF16x generates from 8 GHz to 16 GHz. RFAUX8x
duplicates the frequency range of RF8x or permits direct access to
the VCO output. To suppress the unwanted products of frequency
multiplication, a harmonic filter exists between the multiplier and
the output stage of RF16x.
f
PFD operation to 250 MHz
Reference input frequency operation to 600 MHz
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x
8,000 MHz to 16,000 MHz output at RF16x
Lock time approximately 3 ms with automatic calibration
Lock time <30 μs with autocalibration bypassed, typical
Analog and digital power supplies: 3.3 V typical
VCO supply voltage: 3.3 V and 5 V
RF output mute function
Control of all on-chip registers is through a 3-wire interface.
The ADF4372 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, and 5 V for the VCO power
supply. The ADF4372 also contains hardware and software
power-down modes.
7mm × 7mm, 48-terminal LGA package
APPLICATIONS
Wireless infrastructure (multicarrier global system for
mobile communication (MC-GSM), 5G)
Test equipment and instrumentation
Clock generation
Aerospace and defense
FUNCTIONAL BLOCK DIAGRAM
VCC_CAL VCC_VCO VCC_LDO VCC_X1 VCC_X2
VCC_MUX VCC_3V VDD_NDIV VDD_LS VCC_LDO_3V VCC_REF VDD_PFD VDD_VP
MUX
MUXOUT
5-BIT R
COUNTER
÷2
DIVIDER
REFP
×2
DOUBLER
RS_SW
REFN
LOCK
DETECT
VCC_REG_OUT
ADF4372
SCLK
SDIO
CS
CHARGE
PUMP
CPOUT
VTUNE
DATA REGISTER
FUNCTION
LATCH
PHASE
COMPARATOR
TRACKING
FILTER
8GHz
TO 16GHz
VCO
RF16P
RF16N
OUTPUT
STAGE
LOW
NOISE
LDO
×2
CORE
INTEGER
FRACTION
MODULUS
REGISTER
62.5MHz TO 8000MHz
REGISTER REGISTER
RF8P
RF8N
1, 2, 4, 8,
16, 32, 64
OUTPUT
STAGE
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MUX
62.5MHz TO 8000MHz
N COUNTER
RFAUX8P
RFAUX8N
OUTPUT
STAGE
MUX
GND
Figure 1.
Rev. 0
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ADF4372
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
RF N Divider............................................................................... 18
PFD and Charge Pump.............................................................. 19
MUXOUT and Lock Detect...................................................... 19
Double Buffers............................................................................ 19
VCO ............................................................................................. 20
Output Stage................................................................................ 20
Doubler........................................................................................ 21
Output Stage Mute ..................................................................... 21
SPI................................................................................................. 21
Device Setup.................................................................................... 22
Step 1: Set Up the SPI Interface................................................ 22
Step 2: Initialization Sequence.................................................. 22
Step 3: Frequency Update Sequence........................................ 22
Applications Information.............................................................. 23
Power Supplies............................................................................ 23
PCB Design Guidelines for an LGA Package ......................... 23
Output Matching........................................................................ 23
Register Summary .......................................................................... 24
Register Details ............................................................................... 26
Outline Dimensions....................................................................... 47
Ordering Guide .......................................................................... 47
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 15
RF Synthesizer, a Worked Example.......................................... 15
Reference Input Sensitivity........................................................ 15
Reference Doubler and Reference Divider ............................. 16
Spurious Optimization and Fast Lock..................................... 16
Optimizing Jitter......................................................................... 16
Spur Mechanisms ....................................................................... 16
Lock Time.................................................................................... 16
Circuit Description......................................................................... 18
Reference Input........................................................................... 18
REVISION HISTORY
8/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 47
Data Sheet
ADF4372
SPECIFICATIONS
4.75 V ≤ VCC_VCO ≤ 5.25 V, all other supply pins (AVDD) = 3.3 V 5ꢀ, ꢁND = 0 V, dBm referred to 50 Ω, TA = whole operating
temperature range, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
REFP AND REFN CHARACTERISTICS
Input Frequency
Single-Ended Mode
Differential Mode
Single-Ended or Differential Mode
Input Sensitivity
10
10
10
500
600
125
MHz
MHz
MHz
Doubler disabled
Doubler disabled
Doubler enabled
Single-Ended Mode
0.4
0.4
AVDD
1.8
V p-p
V p-p
REFP biased at AVDD/2, ac coupling
ensures AVDD/2 bias
Differential Mode
Low voltage differential signal (LVDS) and
low voltage positive emitter coupled
logic (LVPECL) compatible, REFP and REFN
biased at 2.1 V, ac coupling ensures 2.1 V
bias
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
6.9
1.4
pF
pF
μA
μA
MHz
150
300
160
Single-ended reference programmed
Differential reference programmed
Fractional mode
Phase Frequency Detector Frequency
(fPFD
)
250
MHz
Integer mode
CHARGE PUMP
Charge Pump Current, Sink and Source
High Value
Low Value
ICP
5.6
0.35
3
mA
mA
%
Current Matching
0.5 V ≤ voltage at the CPOUT pin (VCP) ≤
VDD_VP − 0.5 V
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
3
1.5
%
%
0.5 V ≤ VCP ≤ VDD_VP − 0.5 V
VCP = 2.5 V
CS, SDIO, SCLK, and CE are 3 V logic
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
VINH
VINL
IINH/IINL
CIN
1.17
V
V
μA
pF
0.63
1
3.0
VOH
AVDD
− 0.4
V
3.3 V output selected
1.8 V output selected
1.5
1.875
V
Output High Current
Output Low Voltage
IOH
VOL
500
0.4
μA
V
Output low current (IOL) = 500 μA
POWER SUPPLIES
Supply Voltage (Except VCO)
AVDD
3.15
3.45
V
VCC_CAL, VCC_X1, VDD_X1, VCC_X2,
VCC_MUX, VCC_3V, VDD_NDIV, VDD_LS,
VCC_LDO_3V, VCC_REF, VDD_PFD,
VDD_VP are grouped as AVDD and are at
the same voltage
Supply Current (Except VCO)1
AIDD
190
260
mA
All outputs are disabled
Rev. 0 | Page 3 of 47
ADF4372
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Output Dividers
Divider = 2
14
50
20
65
mA
mA
Each divide by 2 consumes additional
typical 7 mA current
Divider = 64
VCO Supply Voltage
VCC_VCO
IVCO
3.15
4.75
3.3
5
80
135
3.45
5.25
120
180
V
V
mA
mA
3.3 V condition
5 V condition
3.3 V condition
5 V condition
VCO Supply Current
RF8x Supply Current
RF8P and RF8N output stage is
programmable, extra current is drawn in
VCC_X1
25
39
52
65
42
56
70
84
90
5.1
8
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
−4 dBm setting
−1 dBm setting
2 dBm setting
5 dBm setting
−4 dBm setting
−1 dBm setting
2 dBm setting
5 dBm setting
RFAUX8x Supply Current
RF16x Supply Current
Low Power Sleep Mode
120
6.2
9.5
25
Hardware power-down 3.3 V VCO case
Hardware power-down 5 V VCO case
Software power-down 3.3 V VCO case
Software power-down 5 V VCO case
21.5
23.7
28
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF8P and RF8N Output Frequency
RFAUX8P and RFAUX8N Output
Frequency
4000
62.5
62.5
8000
8000
8000
MHz
MHz
MHz
Fundamental VCO range
RF16P and RF16N Output Frequency
VCO Sensitivity
8000
16000
MHz
2 × VCO output
KV
For 5 V
80
60
MHz/V VCO frequency = 6 GHz, see Figure 33 for
KV plot
MHz/V VCO frequency = 6 GHz, see Figure 34 for
KV plot
For 3.3 V
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
8
0.5
MHz/V
MHz
Voltage standing wave ratio (VSWR) = 2:1
RF8P and RF8N
30
MHz
°C
VSWR = 2:1 RF16x
Maintains lock without reprogramming
device
Maintain Lock Temperature Range2
125
Harmonic Content
Second Harmonic RF8P and RF8N
−25
−25
−12
−15
−30
−30
−62
−30
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Fundamental VCO output (RF8x)
Divided VCO output (RF8x)
Fundamental VCO output RF8x)
Divided VCO output (RF8x)
Measured at 20 GHz
Third Harmonic RF8P and RF8N
Second Harmonic RF16P and RF16N
Third Harmonic RF16P and RF16N
Fundamental VCO Feedthrough
Measured at 30 GHz
RF16x = 10 GHz, VCO frequency = 5 GHz
RF8P and RF8N = 1 GHz,
VCO frequency = 4 GHz
RF8P = 4 GHz, 7.5 nH inductor to VCC_X1
RF8P = 8 GHz, 7.5 nH inductor to VCC_X1
RF16x = 8 GHz
RF Output Power Maximum Setting3
7
5
0
dBm
dBm
dBm
Rev. 0 | Page 4 of 47
Data Sheet
ADF4372
Parameter
Symbol
Min
Typ
4
±1
±1
±±
Max
Unit
dBm
dB
dB
dB
Test Conditions/Comments
RF16x = 16 GHz
RF8P and RF8N = 5 GHz
RF16x = 10 GHz
RF Output Power Variation
RF Output Power Variation (Over
Frequency)
RF8x and RFAUX8x = 4 GHz to 8 GHz
±±.5
−50
−44
−41
−75
−55
dB
RF16x = 8 GHz to 16 GHz
RF8P and RF8N = 1 GHz
RF8P and RF8N = 8 GHz
RF8P and RF8N = 8 GHz, 5 V VCO case
RF16P = 8 GHz
Level of Signal with RF Output Disabled
dBm
dBm
dBm
dBm
dBm
RF16P = 16 GHz
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance where VCC VCO = 5 V
VCO noise in open-loop conditions,
VCC_VCO = 5 V
−117
−139
−156
−11±
−136
−153
−109
−133
−15±
dBc/Hz 100 kHz offset from 4.0 GHz carrier
dBc/Hz 1 MHz offset from 4.0 GHz carrier
dBc/Hz 10 MHz offset from 4.0 GHz carrier
dBc/Hz 100 kHz offset from 5.7 GHz carrier
dBc/Hz 1 MHz offset from 5.7 GHz carrier
dBc/Hz 10 MHz offset from 5.7 GHz carrier
dBc/Hz 100 kHz offset from 8.0 GHz carrier
dBc/Hz 1 MHz offset from 8.0 GHz carrier
dBc/Hz 10 MHz offset from 8.0 GHz carrier
VCC_VCO = 5 V
RF16x Output Phase Noise Performance
where VCC_VCO = 5 V
−106
−130
−146
−103
−1±7
−145
dBc/Hz 100 kHz offset from 11.4 GHz carrier
dBc/Hz 1 MHz offset from 11.4 GHz carrier
dBc/Hz 10 MHz offset from 11.4 GHz carrier
dBc/Hz 100 kHz offset from 16 GHz carrier
dBc/Hz 1 MHz offset from 16 GHz carrier
dBc/Hz 10 MHz offset from 16 GHz carrier
Fundamental VCO Phase Noise
Performance where VCC_VCO = 3.3 V
VCO noise in open-loop conditions,
VCC_VCO = 3.3 V
−116
−137
−156
−111
−133
−153
−109
−13±
−153
dBc/Hz 100 kHz offset from 4.0 GHz carrier
dBc/Hz 1 MHz offset from 4.0 GHz carrier
dBc/Hz 10 MHz offset from 4.0 GHz carrier
dBc/Hz 100 kHz offset from 5.7 GHz carrier
dBc/Hz 1 MHz offset from 5.7 GHz carrier
dBc/Hz 10 MHz offset from 5.7 GHz carrier
dBc/Hz 100 kHz offset from 8.0 GHz carrier
dBc/Hz 1 MHz offset from 8.0 GHz carrier
dBc/Hz 10 MHz offset from 8.0 GHz carrier
Normalized Inband Phase Noise Floor
Fractional Channel4
−±33
−±34
−1±7
38
dBc/Hz
dBc/Hz
Integer Channel5
Normalized 1/f Noise6
Integrated RMS Jitter
PN1_f
dBc/Hz 10 kHz offset, normalized to 1 GHz
fs
Wenzel oven controlled crystal oscillators
(OCXO) as the reference frequency input
(REFIN), integer-N mode, fPFD = ±45.76 MHz,
300 kHz loop filter bandwidth, 1 kHz to
100 MHz
Integer Boundary Spurs (Filtered)
Inband Integer Boundary Spur
(Unfiltered)
−90
−55
dBc
dBc
960 kHz offset from integer channel
Measured at 5 kHz offset from integer
channel
Spurious Signals Due to fPFD
−90
dBc
Rev. 0 | Page 5 of 47
ADF4372
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
FREQUENCY LOCK TIME7
Lock Time with Automatic Calibration
Lock Time with Automatic Calibration
Bypassed
3
30
ms
µs
1 TA = ±5°C, AVDD = 3.3 V, VCC_VCO = 5.0 V, prescaler = 4/5, reference frequency (fREFP) = 50 MHz, fPFD = 50 MHz, and RF frequency (fRF) = 5001 MHz. RF8x enabled. All RF
outputs are disabled.
± Guaranteed by design and characterization.
3 RF output power using the EV-ADF437±SD±Z differential outputs combined using a Marki BAL-0036 balun, and measured by a spectrum analyzer with the evaluation
board and cable losses de-embedded. Highest power output selected for RF8P, RF8N, RFAUX8P, and RFAUX8N.
4 Use this value to calculate the phase noise for any application. To calculate inband phase noise performance as seen at the VCO output, use the following formula: −±33 +
10log(fPFD) + ±0logN. The result is the lowest noise mode for the fractional channel.
5 Use this value to calculate the phase noise for any application. To calculate inband phase noise performance as seen at the VCO output, use the following formula: −±34 +
10log(fPFD) + ±0logN. The result is the lowest noise mode for the integer channel.
6 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at a radio frequency
(fRF) and at a frequency offset (fOFFSET) is given by PN1_f + 10log(10 kHz/fOFFSET) + ±0log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
the ADIsimPLL design tool.
7 Lock time is measured for 100 MHz jump with standard evaluation board configuration.
TIMING SPECIFICATIONS
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
Serial Port Interface (SPI) Timing
SCLK Frequency
SCLK Period
SCLK Pulse Width High
SCLK Pulse Width Low
SDIO Setup Time
See Figure ±, Figure 3, and Figure 4
fSCLK
tSCLK
tHIGH
tLOW
tDS
50
MHz
ns
ns
ns
ns
±0
10
10
±
SDIO Hold Time
tDH
±
ns
SCLK Falling Edge to SDIO Valid Propagation
Delay
tACCESS
10
ns
CS Rising Edge to SDIO High-Z
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
tZ
tS
tH
10
±
ns
ns
ns
±
Rev. 0 | Page 6 of 47
Data Sheet
ADF4372
Timing Diagrams
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
R/W A14 A13
A1 A0 D7 D6
D1 D0
N
SDIO
1
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
D0 D1
SDIO
A0 A1 A2
A14 R/W
D6 D7
1
N
Figure 2. SPI Timing, MSB First (Upper) and LSB First (Lower)
tS
tSCLK
tH
CS
tLOW
tHIGH
SCLK
tDS
tDH
A14
A13
A0
D7
D6 D1
D0
SDIO
R/W
Figure 3. SPI Write Operation Timing
tS tSCLK
CS
tLOW
tHIGH
SCLK
tACCESS
tDS
tDH
tZ
SDIO
A1
A0
A14
D7
D6 D1 D0
A2
R/W
Figure 4. SPI Read Operation Timing
CS
DON’T
SCLK
DON’T
CARE
CARE
DON’T
CARE
DON’T
CARE
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – ...) DATA
SDIO
Figure 5. 3-Wire, MSB First, Descending Data, Streaming
Rev. 0 | Page 7 of 47
ADF4372
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Table 3.
Parameter
Rating
AVDD Rails to GND1
AVDD Rails to Each Other
VCC_VCO to GND1
VCC_VCO to AVDD
CPOUT to GND1
VTUNE to GND
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.5 V
−0.3 V to AVDD + ±.8 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
θJA is the natural convection, junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure. θJC is the junction to
case thermal resistance.
Table 4. Thermal Resistance
Package Type
CC-48-41
θJA
θJC
Unit
Digital Input and Output Voltage to
GND1
±5
14.4
°C/W
Analog Input and Output Voltage to
−0.3 V to AVDD + 0.3 V
1 Test Condition 1: thermal impedance simulated values are based on JESD51
standard.
GND1
REFP and REFN to GND1
REFP to REFN
−0.3 V to AVDD + 0.3 V
±±.1 V
ESD CAUTION
Temperature
Operating Range
Storage Range
Maximum Junction
Reflow Soldering
Peak
−40°C to +105°C
−65°C to +1±5°C
1±5 °C
±60°C
30 sec
Time at Peak
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
Transistor Count
1.0 kV
4.0 kV
Complementary Metal-Oxide
Semiconductor (CMOS)
Bipolar
131,439
4063
1 GND = 0 V.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress rating
only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
Rev. 0 | Page 8 of 47
Data Sheet
ADF4372
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
GND
CPOUT
RS_SW
VCC_CAL
GND
SCLK
SDIO
CS
VDD_LS
VDD_NDIV
VCC_3V
VCC_MUX
GND
RF16N
RF16P
GND
3
4
5
6
7
VTUNE
ADF4372
TOP VIEW
(Not to Scale)
VCC_REG_OUT
VCC_VCO
VCC_LDO
GND
8
9
10
11
12
NC
NC
GND
13 14 15 16 17 18 19 20 21 22 23 24
NOTES
1. THE LAND GRID ARRAY (LGA) HAS AN EXPOSED PAD
THAT MUST BE SOLDERED TO A METAL PLATE ON
THE PCB FOR MECHANICAL REASONS AND TO GND.
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
Ground Return.
1, 9, 1±, 13, ±0,
±4, ±5, ±8, 36,
37, 4±, 48
GND
±
CPOUT
Charge Pump (CP) Output. When enabled, this output provides ±ICP to the external loop filter. The
output of the loop filter is connected to VTUNE to drive the internal VCO.
3
4
RS_SW
VCC_CAL
Loop Filter Switch. Used for switching loop filter resistors in fast lock applications.
Power Supply for Internal Calibration Monitor Circuit. The voltage on this pin ranges from 3.15 V to
3.45 V. VCC_CAL must have the same value as AVDD, nominally 3.3 V.
5
6
VTUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering
the CPOUT output voltage.
VCC_REG_OUT VCO Supply Regulator Out. The output supply voltage of the VCO regulator is available at this pin, and
must be decoupled to GND with a 10 μF capacitor and shorted to the VCC_VCO pin. Leave this pin
open if an external LDO regulator is connected to VCC_VCO.
7
8
VCC_VCO
Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.±5 V. Place decoupling
capacitors to the analog ground plane as close to this pin as possible. For optimal performance, this
supply must be clean and have low noise.
Supply Pin to the VCO Regulator. If the internal regulator is used, connect the voltage supply to
VCC_LDO. The voltage on this pin ranges from 4.75 V to 5.±5 V. If the external regulator is used, short
this pin to VCC_VCO.
VCC_LDO
10, 11
14, 16
15, 17
18
NC
No Connect.
VCC_X1
VDD_X1
RF8P
Power Supply for the Main RF Output. The voltage on this pin must have the same value as AVDD.
Digital Supply for the Main RF Circuit. The voltage on this pin must have the same value as AVDD.
Main RF Output. AC couple to the next stage. The output level is programmable. The VCO fundamental
output or a divided down version is available.
19
RF8N
Complementary Main RF Output. AC couple this pin to the next stage. The output level is
programmable. The VCO fundamental output or a divided down version is available.
±1
±±
±3
VCC_X±
RFAUX8P
RFAUX8N
Power Supply for the Doubled RF Output. The voltage on this pin must have the same value as AVDD.
Auxiliary RF Output. AC couple to the next stage. This pin can be powered off when not in use.
Complementary Auxiliary RF Output. AC couple this pin to the next stage. This pin can be powered off
when not in use.
±6
±7
RF16P
RF16N
Doubled VCO Output. AC or dc couple this pin to the next stage. This pin can be powered off when not
in use. If unused, this pin can be left open.
Complementary Doubled VCO Output. AC or dc couple this pin to the next stage. This pin can be
powered off when not in use. If unused, this pin can be left open.
Rev. 0 | Page 9 of 47
ADF4372
Data Sheet
Pin No.
±9
30
31
3±
Mnemonic
VCC_MUX
VCC_3V
VDD_NDIV
VDD_LS
CS
Description
Power Supply for the VCO Mux. The voltage on this pin must have the same value as AVDD.
Analog Power Supply. The voltage on this pin must have the same value as AVDD.
N Divider Power Supply. The voltage on this pin must have the same value as AVDD.
Level Shifter Power Supply. The voltage on this pin must have the same value as AVDD.
Chip Select, CMOS Input. When CS goes high, the data stored in the shift register is loaded into the
register that is selected by the address bits.
33
34
35
SDIO
SCLK
Serial Data Input Output. This input is a high impedance CMOS input.
Serial Clock Input. Data is clocked into the ±4-bit shift register on the clock rising (or falling) edge. This
input is a high impedance CMOS input.
38
39
40
41
VCC_LDO_3V
CE
TEST
Regulator Input for 1.8 V Digital Logic. The voltage on this pin must have the same value as AVDD.
Chip Enable. Connect to 3.3 V or AVDD.
Factory Test Pin. Connect this pin to ground.
Mux Output. The mux output allows the digital lock detect, the analog lock detect, scaled RF, or the
scaled reference frequency to be externally accessible. This pin can be programmed to output the
register settings in 4-wire SPI mode.
MUXOUT
43
44
REFP
REFN
Reference Input. If driving the device with a single-ended reference, ac couple the signal to the REFP
pin.
Complementary Reference Input. If unused, ac couple this pin to GND. REFP and REFN must be ac-
coupled if driven differentially. If driven single-ended, the reference signal must be connected to REFP,
and the REFN must be ac-coupled to GND. In differential configuration, the differential impedance is
100 Ω.
45
46
VCC_REF
VDD_PFD
Power Supply to the Reference Buffer. The voltage on this pin must have the same value as AVDD.
Power Supply to the Phase Frequency Detector (PFD). The voltage on this pin must have the same
value as AVDD.
47
VDD_VP
EP
Charge Pump Power Supply. The voltage on this pin must have the same value as AVDD. A 1 μF
decoupling capacitor to GND must be included to minimize spurious signals.
Exposed Pad. The land grid array (LGA) has an exposed pad that must be soldered to a metal plate on
the PCB for mechanical reasons and to the GND.
Rev. 0 | Page 10 of 47
Data Sheet
ADF4372
TYPICAL PERFORMANCE CHARACTERISTICS
–20
–20
–30
M1 1kHz
–60.29dBc/Hz
M1 1kHz
–49.64dBc/Hz
M2 10kHz –89.95dBc/Hz
M3 100kHz –117.9dBc/Hz
M2 10kHz –79.83dBc/Hz
M3 100kHz –106.27dBc/Hz
–30
M1
M4 1MHz
–139.1dBc/Hz
M4 1MHz
–130.23dBc/Hz
–40
–40
M5 10MHz –156.3dBc/Hz
M6 30MHz –160.95dBc/Hz
M7 95MHz –162.86dBc/Hz
M5 10MHz –147.45dBc/Hz
M6 30MHz –151.39dBc/Hz
M7 95MHz –155.61dBc/Hz
M1
–50
–50
–60
–60
M2
–70
–70
M2
–80
–80
–90
–90
M3
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
M3
M4
M4
M5
M6
M7
M5
M6
M7
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10. Open-Loop VCO Phase Noise at RF16x Output, 11.4 GHz, VCC_VCO = 5 V
Figure 7. Open-Loop VCO Phase Noise, 4.0 GHz, VCC_VCO = 5 V
–20
–20
M1 1kHz
–48.74dBc/Hz
M1 1kHz
–55.29dBc/Hz
M2 10kHz –78.16dBc/Hz
M3 100kHz –103.95dBc/Hz
M2 10kHz –85.75dBc/Hz
M3 100kHz –112.32dBc/Hz
–30
–40
–30
–40
M1
M4 1MHz
–127.04dBc/Hz
M4 1MHz
–136.05dBc/Hz
M5 10MHz –146.07dBc/Hz
M6 30MHz –151.02dBc/Hz
M7 95MHz –154.34dBc/Hz
M1
M5 10MHz –155.3dBc/Hz
M6 30MHz –161.75dBc/Hz
M7 95MHz –161.11dBc/Hz
–50
–50
–60
–60
M2
–70
–70
M2
–80
–80
–90
–90
M3
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
M3
M4
M4
M5
M6
M7
M5
M6
M7
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Open-Loop VCO Phase Noise at RF16x Output, 16.0 GHz, VCC_VCO = 5 V
Figure 8. Open-Loop VCO Phase Noise, 5.7 GHz, VCC_VCO = 5 V
–40
–20
M1 1kHz
–54.23dBc/Hz
+105°C
+25°C
–40°C
M2 10kHz –84.17dBc/Hz
M3 100kHz –110.13dBc/Hz
–30
–40
M4 1MHz
–133.29dBc/Hz
–60
M1
M5 10MHz –153.36dBc/Hz
M6 30MHz –159.75dBc/Hz
M7 95MHz –163.7dBc/Hz
–50
–60
–80
–100
–120
–140
–160
–180
–70
M2
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
M3
M4
M5
M6
M7
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
FREQUENCY (Hz)
Figure 12. Open-Loop VCO Phase Noise over Temperature, 8.0 GHz,
VCC_VCO = 5 V
Figure 9. Open-Loop VCO Phase Noise, 8.0 GHz, VCC_VCO = 5 V
Rev. 0 | Page 11 of 47
ADF4372
Data Sheet
20
15
10
5
–35
–45
DE-EMBEDDED MEASUREMENT
RAW MEASUREMENT
–55
–65
–75
–85
–95
–105
–115
–125
–135
0
153.6MHz
122.88MHz
61.44MHz
–5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
FREQUENCY (GHz)
3.5
4.5
5.5
6.5
7.5
8.5
CARRIER FREQUENCY (GHz)
Figure 13. RF8P and RF8N Output Power, De-Embedded Board and Cable
Measurement, Combined Using Balun (7.4 nH Inductors, 10 pF AC Coupling
Capacitors Limit Power at Low Frequencies)
Figure 16. Integer Boundary Spurious Sweep vs. Carrier Frequency,
f
PFD = 61.44 MHz, 122.88 MHz, and 153.6 MHz,
Loop Filter Bandwidth = 100 kHz
–70
–75
–80
–85
–90
–95
–100
6
4
2
0
–2
–4
–6
–8
PFD FREQUENCY = 153.6MHz
PFD FREQUENCY = 122.88MHz
PFD FREQUENCY = 61.44MHz
–105
DE-EMBEDDED MEASUREMENT
RAW MEASUREMENT
–110
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
7
8
9
10
11
12
13
14
15
16
17
CARRIER FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 14. PFD Spurious Sweep, fPFD = 61.44 MHz, Loop Filter Bandwidth =
100 kHz
Figure 17. RF16P and RF16N Output Power, De-Embedded Board and Cable
Measurement, Combined Using Balun
0
–35
+105°C, VCO SUPPLY = 5.30V
SECOND HARMONIC
+105°C, VCO SUPPLY = 4.80V
+25°C, VCO SUPPLY = 5.05V
THIRD HARMONIC
FOURTH HARMONIC
–10
–40
–45
–50
–55
–60
–65
–70
–75
–40°C, VCO SUPPLY = 5.30V
–40°C, VCO SUPPLY = 4.80V
FIFTH HARMONIC
SIXTH HARMONIC
–20
–30
–40
–50
–60
–70
–80
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
7
8
9
10
11
12
13
14
15
16
17
CARRIER FREQUENCY (GHz)
CARRIER FREQUENCY (GHz)
Figure 15. RF8P and RF8N Output Harmonics, De-Embedded Board and Cable
Measurement, Combined Using Balun
Figure 18. RF16P and RF16N VCO Feedthrough, De-Embedded Board and
Cable Measurement, Combined Using Balun
Rev. 0 | Page 1± of 47
Data Sheet
ADF4372
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
+105°C, VCO SUPPLY = 5.30V
+105°C, VCO SUPPLY = 4.80V
+25°C, VCO SUPPLY = 5.05V
–40°C, VCO SUPPLY = 5.30V
–40°C, VCO SUPPLY = 4.80V
1kHz TO 20MHz
12kHz TO 20MHz
7
8
9
10
11
12
13
14
15
16
17
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
CARRIER FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. RF16P and RF16N VCO × 3 Feedthrough, De-Embedded Board and
Cable Measurement, Combined Using Balun
Figure 22. RMS Jitter, Fractional-N, fPFD = 153.6 MHz, VCC_VCO = 5 V
0
0.075
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
SECOND HARMONIC (4 × VCO)
THIRD HARMONIC (6 × VCO)
TH
5/2 HARMONIC (5 × VCO)
–10
–20
–30
–40
–50
–60
–70
–80
7
8
9
10
11
12
13
14
15
16
17
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
CARRIER FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. RF16P and RF16N Output Harmonics, De-Embedded Board and
Cable Measurement, Combined Using Balun
Figure 23. RMS Jitter Integrated from 1 kHz to 100 MHz, Fractional-N,
PFD = 153.6 MHz, VCC_VCO = 3.3 V
f
0.075
1kHz TO 100MHz
12kHz TO 20MHz
0.070
0.065
0.060
0.055
0.050
0.045
0.040
0.035
0.030
0.025
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
FREQUENCY (GHz)
Figure 21. RMS Jitter, Integer-N, fPFD = 245.76 MHz, Loop Filter Bandwidth =
220 kHz, VCC_VCO = 5 V
Rev. 0 | Page 13 of 47
ADF4372
Data Sheet
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–40
–50
–60
–70
–80
–90
–100
DE-EMBEDDED MEASUREMENT
RAW MEASUREMENT
DE-EMBEDDED MEASUREMENT
RAW MEASUREMENT
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
FREQUENCY (GHz)
7
8
9
10
11
12
13
14
15
16
17
FREQUENCY (GHz)
Figure 25. RF16P and RF16N Output Power When Disabled, De-Embedded
Board and Cable Measurement, Combined Using Balun
Figure 24. RF8P and RF8N Output Power When Disabled, De-Embedded Board
and Cable Measurement, Combined Using Balun
Rev. 0 | Page 14 of 47
Data Sheet
ADF4372
THEORY OF OPERATION
where:
RF SYNTHESIZER, A WORKED EXAMPLE
FRAC is the fractional part of the N.
Use the following equations to program the ADF4372
synthesizer:
MOD1 = 33,554,432
(6)
(7)
(8)
FRAC1 = INT(MOD1 × FRAC) = 26,039,637
Remainder = 0.3333333333 or 1/3
MOD2 = fPFD/GCD(fPFD, fCHSP) =
FRAC2
MOD2
FRAC1+
fPFD
RF Divider
(1)
f
RFOUT = INT +
×
MOD1
61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536
(9)
where:
RFOUT is the RF output frequency.
where:
f
GCD is the greatest common divider operant.
FRAC2 = Remainder × 1536 = 512
From Equation 2,
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality.
MOD2 is the auxiliary modulus.
MOD1 is the fixed 25-bit modulus.
(10)
fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz
(11)
(12)
RF Divider is the output divider that divides down the VCO
frequency.
2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +
FRAC2/MOD2)/225))/2
f
PFD = REFIN × ((1 + D)/(R × (1 + T)))
(2)
where:
INT = 68.
where:
FRAC1 = 26,039,637.
FRAC2 = 512.
MOD2 = 1536.
RF Divider = 2.
REFIN is the reference frequency input.
D is the REFIN doubler bit.
R is the reference division factor.
T is the reference divide by 2 bit (0 or 1).
For example, in a universal mobile telecommunication system
(UMTS) where a 2112.8 MHz fRFOUT is required, a 122.88 MHz
REFIN is available. The ADF4372 VCO operates in the frequency
range of 4 GHz to 8 GHz. Therefore, the RF divider of 2 must be
used (VCO frequency = 4225.6 MHz, fRFOUT = VCO frequency/RF
divider = 4225.6 MHz/2 = 2112.8 MHz).
REFERENCE INPUT SENSITIVITY
The slew rate of the input reference signal significantly affects
the performance. The device is functional with signals of very
low amplitude down to 0.4 V p-p and with a slew rate of 21 V/μs.
However, the optimal performance is achieved with slew rates
as high as 1000 V/μs. Achieving this slew rate with sinusoidal
waves requires high amplitudes and may not be possible at
low frequencies. The jitter and phase noise performance of
the ADF4372 is shown in Figure 27 and Figure 28 for PFD
frequencies of 250 MHz and 100 MHz, respectively. A high
performance square wave signal with a high slew rate is
recommended as the reference input signal to achieve
the best performance.
The feedback path is also important. In this example, the VCO
output is fed back before the output divider (see Figure 26).
In this example, the 122.88 MHz reference signal is divided by
2 to generate a fPFD of 61.44 MHz. The desired channel spacing
is 200 kHz.
fPFD
RF
OUT
PFD
VCO
÷2
65
60
55
50
45
40
35
–100
–102
–104
–106
–108
–110
–112
–114
N
DIVIDER
PHASE NOISE AT 10kHz
PHASE NOISE AT 1kHz
1kHz TO 100MHz
Figure 26. Loop Closed Before Output Divider
12kHz TO 20MHz
The values used in this worked example are as follows:
N = fVCO_OUT/fPFD = 4225.6 MHz/61.44 MHz =
68.7760416666666667
(3)
where:
N is the desired value of the feedback counter, N.
VCO_OUT is the output frequency of the VCO voltage controlled
oscillator without using the output divider.
PFD is the frequency of the phase frequency detector.
INT = INT(VCO frequency/fPFD) = 68
FRAC = 0.7760416666666667
f
–6
–4
–2
0
2
4
6
8
10
12
f
REFERENCE POWER (dBm)
(4)
(5)
Figure 27. Jitter and Phase Noise, fPFD = 250 MHz
Rev. 0 | Page 15 of 47
ADF4372
Data Sheet
105
95
85
75
65
55
45
35
SPUR MECHANISMS
PHASE NOISE AT 10kHz
PHASE NOISE AT 1kHz
1kHz TO 100MHz
–96
This section describes the two different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4372.
12kHz TO 20MHz
–87
–100
–102
–104
–106
–108
–110
Integer Boundary Spurs
One mechanism for fractional spur creation is the interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (which is the
purpose of a fractional-N synthesizer), spur sidebands appear on
the VCO output spectrum at an offset frequency that corresponds
to the beat note or the difference in frequency between an integer
multiple of the reference and the VCO frequency. These spurs
are attenuated by the loop filter and are more noticeable on
channels close to integer multiples of the reference where
the difference frequency can be inside the loop bandwidth.
–6
–4
–2
0
2
4
6
8
10
12
REFERENCE POWER (dBm)
Figure 28. Jitter and Phase Noise, fPFD = 100 MHz
REFERENCE DOUBLER AND REFERENCE DIVIDER
Reference Spurs
The on-chip reference doubler allows the input reference signal
to be doubled. The doubler is useful for increasing the PFD
comparison frequency. To improve the noise performance of
the system, increase the PFD frequency. Doubling the PFD
frequency typically improves noise performance by 3 dB.
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. Feedthrough of low
levels of on-chip reference switching noise through the prescaler
back to the VCO can result in reference spur levels as high as
−100 dBc.
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency.
SPURIOUS OPTIMIZATION AND FAST LOCK
LOCK TIME
Narrow loop bandwidths can filter unwanted spurious signals.
However, these bandwidths typically have a long lock time. A
wider loop bandwidth achieves faster lock times, but can lead
to increased spurious signals inside the loop bandwidth.
The PLL lock time divides into a number of settings. The total lock
time for changing frequencies is the sum of the four separate times:
synthesizer lock, VCO band selection, automatic level calibration
(ALC), and PLL settling time.
OPTIMIZING JITTER
Synthesizer Lock
For lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of inband noise from the
PLL. Set the PLL filter bandwidth such that the inband noise of the
PLL intersects with the open-loop noise of the VCO, minimizing
the contribution of both to the overall noise.
The synthesizer lock timeout ensures that the VCO calibration
DAC, which forces the VCO tune voltage (VTUNE), has settled
to a steady value for the band select circuitry. The SYNTH_LOCK_
TIMEOUT bit and the TIMEOUT bits select the length of time
the DAC is allowed to settle to the final voltage before the VCO
calibration process continues to the next phase (VCO band
selection).
Use the ADIsimPLL design tool for this task.
Additional Optimization on Loop Filter
The PFD frequency is the clock for this logic, and the duration
is set using the following equation:
The PLL filter is designed to find an optimum bandwidth for
the reference, PFD, and VCO noise, depending on the system
requirements. In addition to this design, when the Σ-Δ modulator
(SDM) is enabled, further optimization may be necessary to filter
SDM noise.
SYNTH _ LOCK _TIMEEOUT ×1024 +TIMEOUT
(13)
fPFD
where:
Reducing Σ-Δ Modulator Noise
SYNTH_LOCK_TIMEOUT is programmed in Address 0x33.
TIMEOUT is programmed in Address 0x31 and Address 0x32.
In fractional mode, SDM noise becomes apparent and starts
to contribute to overall phase noise. This noise can be reduced
to insignificant levels by using a series resistor between the
CPOUT pin and the loop filter. Place this resistor close to the
CPOUT pin. A reasonable resistor value does not affect the loop
bandwidth and phase margin of the designed loop filter. In most
cases, 91 Ω gives the best results. This resistor is not required in
integer mode (SDM not enabled) or when a narrow-band loop
filter is used (SDM noise attenuated).
The calculated time must be greater than or equal to 20 µs.
For the SYNTH_LOCK_TIMEOUT bit, the minimum value is
2 and the maximum value is 31. For the TIMEOUT bits, the
minimum value is 2 and the maximum value is 1023.
Rev. 0 | Page 16 of 47
Data Sheet
ADF4372
VCO Band Selection
PLL Settling Time
The VCO_BAND_DIV bits (programmed in Address 0x30) and
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is accurately
modeled in the ADIsimPLL design tool.
fPFD are used to generate the VCO band selection clock
as follows:
Lock Time, a Worked Example
fPFD
fBSC
=
(14)
VCO _ BAND _ DIV
Assume that fPFD = 61.44 MHz,
The calculated time must be less than or equal to 2.4 MHz.
VCO_BAND_DIV = Ceiling(fPFD/2,400,000) = 26
where Ceiling() rounds up to the nearest integer.
(18)
16 clock cycles are required for one VCO core and band
calibration step and the total band selection process takes
11 steps, resulting in the following equation:
SYNTH_LOCK_TIMEOUT × 1024 + TIMEOUT > 1228.8 (19)
VCO_ALC_TIMEOUT × 1024 + TIMEOUT > 3072
(20)
16×VCO _ BAND _ DIV
11×
(15)
There are several suitable values that meet these criteria. By
considering the minimum specifications, the following values
are the most suitable:
fPFD
The minimum value for VCO_BAND_DIV is 1 and the
maximum value is 255.
•
•
•
SYNTH_LOCK_TIMEOUT = 2 (minimum value)
VCO_ALC_TIMEOUT = 3
TIMEOUT = 2
ALC
Use the ALC function to choose the correct bias current in the
ADF4372 VCO core. The duration required for VCO bias
voltage to settle for each step is set by the following equation:
Much faster lock times than those detailed in this data sheet are
possible by bypassing the calibration processes. Contact an
Analog Devices, Inc., sales representative for more information.
VCO _ ALC _TIMEOUT ×1024 +TIMEOUT
(16)
fPFD
where:
VCO_ALC_TIMEOUT and TIMEOUT are programmed in
Address 0x34, Address 0x32, and Address 0x31.
The calculated time must be greater than or equal to 50 µs.
The total ALC takes 63 steps. Calculate the total duration for
ALC as follows:
VCO _ ALC _TIMEOUT ×1024 +TIMEOUT
63×
(17)
fPFD
The minimum value for VCO_ALC_TIMEOUT is 2 and the
maximum value is 31.
Rev. 0 | Page 17 of 47
ADF4372
Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT
RF N DIVIDER
Figure 29 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the
reference mode bit (Bit 6 in Address 0x22) to select the signal.
To use a differential signal on the reference input, program this
bit high. In this case, SW1 and SW2 are open, SW3 and SW4
are closed, and the current source that drives the differential pair of
transistors switches on. The differential signal is buffered, and
the signal is provided as an emitter coupled logic (ECL) to the
CMOS buffer.
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
RF N COUNTER
FROM
VCO OUTPUT OR
OUTPUT DIVIDERS
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
When a single-ended signal is used as the reference, connect the
reference signal to REFP and program Bit 6 in Address 0x22
to 0. In this case, SW1 and SW2 are closed, SW3 and SW4 are
open, and the current source that drives the differential pair of
transistors switches off.
INT
FRAC1
VALUE
FRAC2
VALUE
MOD2
VALUE
VALUE
Figure 30. RF N Divider
For optimum integer boundary spur and phase noise performance,
use the single-ended setting for all references up to 500 MHz
(even if using a differential signal). Use the differential setting
for reference frequencies greater than 500 MHz.
INT, FRAC, MOD, and R Counter Relationship
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies that are spaced by fractions of fPFD. For more
information, see the RF Synthesizer, a Worked Example section.
REFERENCE
INPUT MODE
85kꢀ
Calculate fVCO_OUT using the following equation:
SW2
BUFFER
SW1
fVCO_OUT = fPFD × N
(21)
(22)
Calculate fPFD using the following equation:
SW3
TO
R COUNTER
MULTIPLEXER
1 D
fPFD REFIN
R 1T
AV
DD
where:
ECL TO CMOS
BUFFER
REFIN is the reference frequency input.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
REFP
REFN
T is the REFIN divide by 2 bit (0 or 1)
2.5kΩ
2.5kΩ
Calculate the desired value of the feedback counter N using the
following equation:
SW4
BIAS
GENERATOR
FRAC2
MOD2
MOD1
FRAC1
Figure 29. Reference Input Stage, Differential Mode
(23)
N INT
where:
INT is the 16-bit integer value. In integer mode, INT = 20 to
32,767 for the 4/5 prescaler, and 64 to 65,535 for the 8/9
prescaler. In fractional mode, INT= = 23 to 32,767 for the 4/5
prescaler, and 75 to 65,535 for the 8/9 prescaler.
FRAC1 is the numerator of the primary modulus (0 to 33,554,431).
FRAC2 is the numerator of the 14-bit auxiliary modulus
(0 to 16,383).
MOD2 is the programmable, 14-bit auxiliary fractional
modulus (2 to 16,383).
MOD1 is a 25-bit primary modulus with a fixed value of
225 = 33,554,432.
Rev. 0 | Page 18 of 47
Data Sheet
ADF4372
UP
These calculations result in a very low frequency resolution
with no residual frequency error. To apply Equation 23, perform
the following steps:
HIGH
D1
Q1
U1
CLR1
+IN
1. Calculate N by dividing VCOOUT/fPFD. The integer value of
this number forms INT.
CHARGE
PUMP
CP
U3
DELAY
2. Subtract INT from the full N value.
3. Multiply the remainder by 225. The integer value of this
number forms FRAC1.
CLR2
D2 Q2
DOWN
4. Calculate MOD2 based on the channel spacing (fCHSP
using the following equation:
)
HIGH
U2
–IN
MOD2 = fPFD/GCD(fPFD, fCHSP
)
(24)
Figure 31. PFD Simplified Schematic
where:
MUXOUT AND LOCK DETECT
GCD(fPFD, fCHSP) is the greatest common divisor of the
PFD frequency and the channel spacing frequency.
The output multiplexer on the ADF4372 allows the user to
access various internal points on the chip. Figure 32 shows the
MUXOUT section in block diagram form.
fCHSP is the desired channel spacing frequency.
5. Calculate FRAC2 using the following equation:
AV
DD
FRAC2 = ((N – INT) × 225 – FRAC1) × MOD2
(25)
The FRAC2 and MOD2 fraction result in outputs with zero
frequency error for channel spacing when
THREE-STATE OUTPUT
AV
DD
f
PFD/GCD(fPFD, fCHSP) = MOD2 < 16,383
(26)
R DIVIDER OUTPUT
N DIVIDER OUTPUT
If zero frequency error is not required, the MOD1 and
MUX
CONTROL
MUXOUT
MOD2 denominators operate together to create a 39-bit
resolution modulus.
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
Integer-N Mode
When FRAC1 and FRAC2 are equal to 0, the synthesizer
operates in integer-N mode. It is recommended that the
SD_EN_FRAC0 bit in Address 0x2B be set to 1 to disable the
SDMs, which gives an improvement in the inband phase
noise and reduces any additional Σ-Δ noise.
DIGITAL
GROUND
Figure 32. MUXOUT Schematic
DOUBLE BUFFERS
The main fractional value (FRAC1), auxiliary modulus value
(MOD2), auxiliary fractional value (FRAC2), reference doubler,
reference divide by 2 (RDIV2), R counter value, and charge pump
current setting are double buffered in the ADF4372. Two events
must occur before the ADF4372 uses a new value for any of the
double buffered settings. First, the new value must latch into the
device by writing to the appropriate register, and second, a new
write to Address 0x10 must be performed.
R Counter
The 5-bit R counter allows the input reference frequency (input
to REFP and REFN) to be divided down to produce the reference
clock to the PFD. Division ratios from 1 to 32 are allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 31 is a simplified schematic
of the PFD. The PFD includes a fixed delay element that sets the
width of the antibacklash pulse. This pulse ensures that there is no
dead zone in the PFD transfer function and provides a consistent
reference spur level. Set the phase detector polarity to positive
on this device because of the positive tuning of the VCO.
For example, to ensure that the modulus value loads correctly,
Address 0x10 must be written to every time that the modulus
value updates.
Rev. 0 | Page 19 of 47
ADF4372
Data Sheet
100
90
80
70
60
50
40
30
20
10
0
VCO
The VCO in the ADF4372 consists of four separate VCO cores,
Core A, Core B, Core C, and Core D, each of which uses 256
overlapping bands, which allows the device to cover a wide
frequency range without large VCO sensitivity (KV) and without
resultant poor phase noise and spurious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic whenever Address 0x10 is updated
and automatic calibration is enabled. The VCO tune voltage is
disconnected from the output of the loop filter and is connected
to an internal reference voltage.
The R counter output is used as the clock for the band select
logic. After band selection, normal PLL action resumes. The
nominal value of KV is 50 MHz/V when the N divider is driven
from the VCO output, or the KV value is divided by D. D is
the output divider value if the N divider is driven from the
RF output divider.
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
FREQUENCY (GHz)
Figure 34. VCO Sensitivity, KV vs. Frequency, VCC_VCO = 3.3 V
OUTPUT STAGE
The RF8P pin and the RF8N pin of the ADF4372 connect to
the collectors of a bipolar negative positive negative (NPN)
differential pair driven by buffered outputs of the VCO, as
shown in Figure 35. The ADF4372 contains internal 50 Ω
resistors connected to the VCC_X1 pin. To optimize the power
dissipation vs. the output power requirements, the tail current
of the differential pair is programmable using Bits[1:0] in
Address 0x25. Four current levels can be set. These levels give
approximate output power levels of −4 dBm, −1 dBm, 2 dBm,
and 5 dBm. Levels of −4 dBm, −1 dBm, and 2 dBm can be
achieved by ac coupling into a 50 Ω load. A 5 dBm level
requires an external shunt inductor to VCC_X1. An inductor
has a narrower operating frequency than a 50 Ω resistor.
For accurate power levels, refer to the Typical Performance
Characteristics section. Add an external shunt inductor to
provide higher power levels, which is less wideband than the
internal bias only. Terminate the unused complementary output
with a circuit similar to the used output.
The VCO shows variation of KV as the tuning voltage, VTUNE
,
varies within the band and from band to band. For wideband
applications covering a wide frequency range (and changing
output dividers), a value of 50 MHz/V provides the most accurate
KV, because this value is closest to the average value. Figure 33
and Figure 34 shows how KV varies with fundamental VCO
frequency along with an average value for the frequency band.
Users may prefer Figure 33 and Figure 34 when using narrow-
band designs.
150
140
130
120
110
100
90
80
70
60
VCC_X1
VCC_X1
50
50Ω
RF8P
50Ω
RF8N
40
30
20
10
BUFFER,
DIVIDE BY
1, 2, 4, 8,
16, 32, 64
0
4.0
VCO
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
FREQUENCY (GHz)
Figure 33. VCO Sensitivity, KV vs. Frequency, VCC_VCO = 5 V
Figure 35. Output Stage
The doubled VCO output (8 GHz to 16 GHz) is available on the
RF16P pin and the RF16N pin, which can be directly connected
to the next circuit. The RFAUX8P and the RFAUX8N provide the
same functionality as the RF8x output, but they can output the
divided RF8x frequency or the VCO frequency if desired.
Rev. 0 | Page ±0 of 47
Data Sheet
ADF4372
DOUBLER
SPI
The VCO frequency multiplied by 2 is available at the RF16P
pin and RF16N pin. This output can be powered down when
not in use, and the RF16P pin and the RF16N pin can be left open
if unused.
The SPI of the ADF4372 allows the user to configure the device
as required via a 3-wire or 4-wire SPI port. This interface provides
users with added flexibility and customization. The serial port
CS
interface consists of four control lines: SCLK, SDIO, , and
MUXOUT (not used in 3-wire SPI). The timing requirements
for the SPI port are detailed in Table 2.
RF16P
×2
The SPI protocol consists of a read and write bit and 15 register
address bits, followed by eight data bits. Both the address and data
fields are organized with the MSB first and end with the LSB
by default. The timing diagrams for write mode and read mode
are shown in Figure 3 and Figure 4, respectively. The significant
bit order can be changed via the Bit 1 (LSB_FIRST) setting at
Address 0x00. The related timing diagram is shown in Figure 2.
RF16N
Figure 36. Doubler Output Stage
An automatic tracking filter on the ADF4372 that suppresses
the VCO and other unwanted frequency products ensures the
doubled output is maximized and that the VCO and 3 × VCO
frequencies are suppressed regardless of the output frequency.
Suppression of <50 dB is typical. The optimum values are set
automatically by the automatic tracking when it is enabled
using Bit 1 in Address 0x23.
The ADF4372 input logic level for the write cycle is compatible
with 1.8 V logic level (see the logic parameters in Table 1). On a
read cycle, both the SDIO pin and MUXOUT pin are configurable
for 1.8 V (default) or 3.3 V output levels by the LEV_SEL bit
setting.
The settings for optimum output power, phase noise, and
harmonic rejection are given in Table 6.
SPI Stream Mode
Table 6. Filter and Bias Settings for Doubled Output
The ADF4372 supports stream mode, where data bits are loaded
to or read from registers serially without writing the register
address (instruction word). This mode is useful in time critical
applications, when a large amount of data must be transferred or
when some registers must be updated repeatedly.
Frequency (GHz)
Filter
Bias
<8.4
7
6
5
4
3
±
1
0
3
8.4 to 9.4
9.4 to 10
3
3
10 to 11.5
11.5 to 1±.±
1±.± to 13.7
13.7 to 14.5
>14.5
3
The slave device starts reading or writing data to this address and
3
CS
continues as long as is asserted and single-byte writes are not
3
enabled (Bit 7 in Address 0x01). The slave device automatically
increments or decrements the address depending on the setting
of the address ascension bit (Bit 2 in Address 0x00).
3
3
OUTPUT STAGE MUTE
The diagram of 3-byte streaming is shown in Figure 5. The
instruction header starts with a Logic 0 to indicate a write
sequence and addresses the register. The data for registers (N,
N − 1, and N − 2) are loaded consecutively without any assertion
Another feature of the ADF4372 is that the supply current
to the RF8P and RF8N output stage can shut down until the
ADF4372 achieves lock as measured by the digital lock detect
circuitry. The mute to lock detect bit (MUTE_LD) in Address 0x25
enables this function.
CS
in
.
The registers are organized into eight bits, and if a register
requires more than eight bits, sequential register addresses
are used. This organization enables using stream mode and
simplifies loading. For example, FRAC1WORD is stored in
Address 0x16, Address 0x15, and Address 0x14 (MSB to LSB).
These registers can be loaded by using Address 0x16 and sending
the whole 24-bit data afterward, as shown in Figure 5.
Rev. 0 | Page ±1 of 47
ADF4372
Data Sheet
DEVICE SETUP
The recommended sequence of steps to set up the ADF4372 are
as follows:
STEP 3: FREQUENCY UPDATE SEQUENCE
Frequency updates require updating MOD2, FRAC1, FRAC2,
and INT. Therefore, the update sequence must be as follows:
1. Set up the SPI interface.
2. Perform the initialization sequence.
3. Perform the frequency update sequence.
1. Address 0x1A (new MOD2WORD[13:8])
2. Address 0x19 (new MOD2WORD[7:0])
3. Address 0x18 (new FRAC2WORD[13:7])
4. Address 0x17 (new FRAC2WORD[6:0])
5. Address 0x16 (new FRAC1WORD[23:16])
6. Address 0x15 (new FRAC1WORD[15:8])
7. Address 0x14 (new FRAC1WORD[7:0])
8. Address 0x11 (new BIT_INTEGER_WORD[15:8])
9. Address 0x10 (new BIT_INTEGER_WORD[7:0])
STEP 1: SET UP THE SPI INTERFACE
First, initialize the SPI. Write the values in Table 7 to Address 0x00
and Address 0x01.
Table 7. SPI Interface Setup
Address Setting Notes
0x00
0x01
0x18
0x00
4-wire SPI
Stalling, master readback control
The frequency change occurs on the write to Address 0x10.
The unchanged registers do not need to be updated. For
example, for an integer-N PLL configuration (fractional parts are
not used), skip Step 1 to Step 7. In this case, the only required
updates are Address 0x11 and Address 0x10.
STEP 2: INITIALIZATION SEQUENCE
Write to each register in reverse order from Address 0x7C to
Address 0x10. Choosing appropriate values to generate the desired
frequency. The registers that are not given in the datasheet can
be skipped in normal SPI mode. If SPI stream mode is used, write
0x00 to the registers not listed in the Register Summary section.
The frequency update sequence follows to generate the desired
output frequency.
Rev. 0 | Page ±± of 47
Data Sheet
ADF4372
APPLICATIONS INFORMATION
POWER SUPPLIES
OUTPUT MATCHING
The ADF4372 contains four multiband VCOs that together cover
an octave range of frequencies. To achieve optimal VCO phase
noise performance, it is recommended to connect a low noise
regulator, such as the ADM7150 or LT3045, to the VCC_VCO
pin. Connect the same regulator to the VCC_VCO pin and the
VCC_LDO pin. It is recommended to connect 1 μF decoupling
capacitors to the 5 V VCO supply.
The low frequency output can be ac-coupled to the next circuit,
if desired. However, if higher output power is required, use a
pull-up inductor to increase the output power level.
VDD_X1
7.5nH
10pF
RF8P
50Ω
For all other 3.3 V supply pins, use one ADM7150 or one
LT3045 regulator. A 1 μF capacitor is also recommended for the
VDD_VP pin. Additional decoupling to other supply pins is not
required.
Figure 37. Optimum Output Stage
When differential outputs are not needed, terminate the unused
output or combine it with both outputs using a balun.
PCB DESIGN GUIDELINES FOR AN LGA PACKAGE
For lower frequencies that are less than 1 GHz, it is recommended
to use a 100 nH inductor on the RF8P pin and the RF8N pin.
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad. On the PCB, there must be a minimum
clearance of 0.25 mm between the thermal pad and the inner
edges of the pad pattern. This clearance ensures there is no
shorting
The RF8P and RF8N pins form a differential circuit. Provide
each output with the same (or similar) components where
possible, including the same shunt inductor value, bypass
capacitor, and termination.
The RFAUX8P pin and the RFAUX8N pin are effectively the
same as the RF8P pin and the RF8N pin and must be treated in
the manner as outlined for the RF8P pin and the RF8N pin.
To improve the thermal performance of the package, use thermal
vias on the PCB thermal pad. If vias are used, incorporate them
into the thermal pad at the 1.2 mm pitch grid. The via diameter
must be between 0.3 mm and 0.33 mm, and the via barrel must
be plated with 1 oz. of copper to plug the via into the barrel.
The RF16P pin and the RF16N pin can be directly connected to
the next circuit stage. These pins are internally matched to 50 Ω
and do not require additional decoupling.
For a microwave PLL and VCO synthesizer, such as the
ADF4372, take care with the board stackup and layout. Do not
consider using FR4 material because it causes an amplitude
decrease in signals greater than 3 GHz. Instead, Rogers 4350,
Rogers 4003, or Rogers 3003 dielectric material is suitable.
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and grounding
are critical.
Rev. 0 | Page ±3 of 47
ADF4372
Data Sheet
REGISTER SUMMARY
Table 8. ADF4372 Register Summary
Reg
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R/W
Addr.
0x00
0x01
[7:0]
SOFT_RESET_R
LSB_FIRST_R
ADDRESS_
ASCENSION
_R
SDO_ACTIVE_
R
SDO_ACTIVE
ADDRESS_
ASCENSION
LSB_FIRST
SOFT_RESET
0x18
R/W
[7:0]
SINGLE_
INSTRUCTION
STALLING
MASTER_
READBACK_
CONTROL
RESERVED
0x00
R/W
0x03
0x04
0x05
0x06
0x10
0x11
0x12
0x14
0x15
0x16
0x17
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
CHIP_TYPE
0x0X
0xXX
0xXX
0xXX
0x32
0x00
0x40
0x00
0x00
0x00
0x00
R
PRODUCT_ID[7:0]
R/W
R/W
R
PRODUCT_ID[15:8]
PRODUCT_GRADE
DEVICE_REVISION
BIT_INTEGER_WORD[7:0]
BIT_INTEGER_WORD[15:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESERVED
EN_AUTOCAL
PRE_SEL
RESERVED
FRAC1WORD[7:0]
FRAC1WORD[15:8]
FRAC1WORD[23:16]
FRAC2WORD[6:0]
FRAC1WORD
[24]
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x22
0x23
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
RESERVED
RESERVED
FRAC2WORD[13:7]
0x00
0xE8
0x03
0x00
0x00
0x00
0x48
0x01
0x14
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MOD2WORD[7:0]
PHASE_ADJ
MOD2WORD[13:8]
PHASE_WORD[7:0]
PHASE_WORD[15:8]
PHASE_WORD[23:16]
PD_POL
CP_CURRENT
PD
RESERVED
CNTR_RESET
RESERVED
R_WORD
LEV_SEL
MUXOUT
MUXOUT_EN
RESERVED
RESERVED
REFIN_MODE
REF_DOUB
RDIV2
RESERVED
RESERVED
CLK_DIV_MODE
RESERVED
TRACKING_FIL
TER_MUX_SEL
RESERVED
0x24
0x25
[7:0]
[7:0]
FB_SEL
DIV_SEL
RESERVED
0x80
0x07
R/W
R/W
MUTE_LD
RESERVED
RF_DIVSEL_
DB
X4_EN
X2_EN
RF_EN
RF_OUT_POWER
0x26
0x27
[7:0]
[7:0]
BLEED_ICP
0x32
0xC5
R/W
R/W
LD_BIAS
LDP
BLEED_GATE
BLEED_EN
VCOLDO_P
D
RF_PBS
LOL_EN
0x28
0x2A
0x2B
[7:0]
[7:0]
[7:0]
DOUBLE_BUFF
RESERVED
RESERVED
RESERVED
LD_COUNT
RESERVED
0x03
0x00
0x01
R/W
R/W
R/W
BLEED_POL
LSB_P1
RESERVED
LE_SEL
READ_SEL
VAR_MOD_EN
RESERVED
SD_LOAD_
ENB
RESERVED
SD_EN_FRAC0
0x2C
[7:0]
RESERVED
ALC_RECT_
SELECT_
VCO1
ALC_REF_
DAC_LO_
VCO1
ALC_REF_DAC_NOM_VCO1
VTUNE_
CALSET_EN
DISABLE_ALC
0x44
R/W
0x2D
0x2E
0x2F
[7:0]
[7:0]
[7:0]
RESERVED
ALC_RECT_
SELECT_VCO2
ALC_REF_DAC_
LO_VCO2
ALC_REF_DAC_NOM_VCO2
ALC_REF_DAC_NOM_VCO3
ALC_REF_DAC_NOM_VCO4
0x11
0x12
0x94
R/W
R/W
R/W
RESERVED
ALC_RECT_
SELECT_VCO3
ALC_REF_DAC_
LO_VCO3
SWITCH_LDO_
3P3V_5V
RESERVED
ALC_RECT_
SELECT_VCO4
ALC_REF_DAC_
LO_VCO4
0x30
0x31
0x32
[7:0]
[7:0]
[7:0]
VCO_BAND_DIV
TIMEOUT[7:0]
0x3F
0xA7
0x04
R/W
R/W
R/W
ADC_MUX_
SEL
RESERVED
RESERVED
ADC_FAST_
CONV
ADC_CTS_
CONV
ADC_
CONVERSION
ADC_
ENABLE
TIMEOUT[9:8]
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3D
0x3E
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
SYNTH_LOCK_TIMEOUT
VCO_ALC_TIMEOUT
0x0C
0x9E
0x4C
0x30
0x00
0x00
0x07
0x55
0x00
0x0C
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VCO_FSM_TEST_MODES
ADC_CLK_DIVIDER
ICP_ADJUST_OFFSET
SI_BAND_SEL
SI_VCO_SEL
SI_VCO_BIAS_CODE
SI_VTUNE_CAL_SET
RESERVED
RESERVED
VCO_FSM_TEST_MUX_SEL
ADC_OFFSET
SD_RESET
RESERVED
RESERVED
CP_TMODE
RESERVED
Rev. 0 | Page 24 of 47
Data Sheet
ADF4372
Reg
Bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R/W
Addr.
0x3F
0x40
0x41
0x47
0x5±
0x6E
0x6F
0x70
0x71
0x7±
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
CLK1_DIV[7:0]
0x80
0x50
0x±8
0xC0
0xF4
0x00
0x00
0x03
0x60
0x3±
R/W
R/W
R/W
R/W
R/W
R
RESERVED
TRM_IB_VCO_BUF
CLK1_DIV[11:8]
CLK±_DIVIDER_1[7:0]
TRM_RESD_VCO_MUX
TRM_RESD_VCO_BUF
RESERVED
TRM_RESCI_VCO_BUF
RESERVED
VCO_DATA_READBACK[7:0]
VCO_DATA_READBACK[15:8]
RESERVED
R
BAND_SEL_X±
BAND_SEL_X4
BIAS_SEL_X±
BIAS_SEL_X4
R/W
R/W
R/W
RESERVED
RESERVED
AUX_FREQ_
SEL
POUT_AUX
RESERVED
PDB_AUX
RESERVED
COUPLED_
RESERVED
VCO
0x73
0x7C
[7:0]
[7:0]
ADC_CLK_
DISABLE
PD_NDIV
LD_DIV
0x00
0x00
R/W
R
RESERVED
LOCK_DETECT
_READBACK
Rev. 0 | Page ±5 of 47
ADF4372
Data Sheet
REGISTER DETAILS
Address: 0x00, Default: 0x18, Name: REG0000
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
[7] SOFT_RESET_R (R/W)
[0] SOFT_RESET (R/W)
Copy of Bit-0.
Soft Reset.
[6] LSB_FIRST_R (R/W)
[1] LSB_FIRST (R/W)
Copy of Bit-1.
Reads LSB first when Active.
[5] ADDRESS_ASCENSION_R (R/W)
Copy of Bit-2.
[2] ADDRESS_ASCENSION (R/W)
Set Address in Ascending Order (Default
is Ascending).
[4] SDO_ACTIVE_R (R/W)
Copy of Bit-3.
[3] SDO_ACTIVE (R/W)
Choose Between 3-Pin or 4-Pin Operation.
Table 9. Bit Descriptions for REG0000
Bit(s) Bit Name
Description
Default Access
7
SOFT_RESET_R
Copy of Bit 0.
0x0
Read/Write
(R/W)
6
5
4
3
LSB_FIRST_R
Copy of Bit 1.
Copy of Bit ±.
Copy of Bit 3.
0x0
0x0
0x1
0x1
R/W
R/W
R/W
R/W
ADDRESS_ASCENSION_R
SDO_ACTIVE_R
SDO_ACTIVE
Choose Between 3-Pin or 4-Pin Operation.
0: 3-pin.
1: 4-pin. Enables SDIO pin and the SDIO pin becomes an input only.
±
ADDRESS_ASCENSION
Set Address in Ascending Order (Default Is Ascending).
0x0
R/W
0: descending.
1: ascending.
1
0
LSB_FIRST
Reads LSB First when Active.
Soft Reset.
0x0
0x0
R/W
R/W
SOFT_RESET
0: normal operation.
1: soft reset.
Address: 0x01, Default: 0x00, Name: REG0001
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] SINGLE_INSTRUCTION (R/W)
[4:0] RESERVED
Single Instruction.
[5] MASTER_READBACK_CONTROL (R/W)
[6] STALLING (R/W)
Master Readback Control.
Stalling.
Table 10. Bit Descriptions for REG0001
Bit(s)
7
Bit Name
SINGLE_INSTRUCTION
STALLING
MASTER_READBACK_CONTROL
RESERVED
Description
Default
Access
R/W
Single Instruction. SPI stream mode is disabled if this bit is set to 1.
Stalling. For internal use.
Master Readback Control. For internal use.
Reserved.
0x0
0x0
0x0
0x0
6
5
R/W
R/W
[4:0]
Read
Only (R)
Rev. 0 | Page ±6 of 47
Data Sheet
ADF4372
Address: 0x03, Default: 0x0X, Name: REG0003
7
6
5
4
3
2
1
0
0
0
0
0
X
X
X
X
[7:4] RESERVED
[3:0] CHIP_TYPE (RP)
Chip Type.
Table 11. Bit Descriptions for REG0003
Bit(s)
[7:4]
[3:0]
Bit Name
RESERVED
CHIP_TYPE
Description
Reserved.
Default
0x0
0x0
Access
R
Chip Type.
Read Programmable
(RP)
Address: 0x04, Default: 0xXX, Name: REG0004
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
[7:0] PRODUCT_ID[7:0] (R/WP)
Product ID.
Table 12. Bit Descriptions for REG0004
Bit(s)
Bit Name
Description
Default
Access
[7:0]
PRODUCT_ID[7:0]
Product ID.
0x0
Read/Write
Programmable
(R/WP)
Address: 0x05, Default: 0xXX, Name: REG0005
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
[7:0] PRODUCT_ID[15:8] (R/WP)
Product ID.
Table 13. Bit Descriptions for REG0005
Bit(s) Bit Name
Description
Default Access
[7:0] PRODUCT_ID[15:8]
Product ID.
0x0
R/WP
Address: 0x06, Default: 0xXX, Name: REG0006
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
[7:4] PRODUCT_GRADE (RP)
Product Grade.
[3:0] DEVICE_REVISION (RP)
Device Revision.
Table 14. Bit Descriptions for REG0006
Bit(s)
[7:4]
[3:0]
Bit Name
PRODUCT_GRADE
DEVICE_REVISION
Description
Product Grade.
Device Revision.
Default
0x0
0x0
Access
RP
RP
Address: 0x10, Default: 0x32, Name: REG0010
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
[7:0] BIT_INTEGER_WORD[7:0] (R/W)
16-Bit Integer Word.
Table 15. Bit Descriptions for REG0010
Bit(s) Bit Name Description
[7:0]
Default Access
0x3± R/W
BIT_INTEGER_WORD[7:0] 16-Bit Integer Word. Sets the integer value of N. Updates to the PLL N counter,
including FRAC1, FRAC±, and MOD±, are double buffered by this bitfield.
Rev. 0 | Page ±7 of 47
ADF4372
Data Sheet
Address: 0x11, Default: 0x00, Name: REG0011
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] BIT_INTEGER_WORD[15:8] (R/W)
16-Bit Integer Word.
Table 16. Bit Descriptions for REG0011
Bit(s)
[7:0]
Bit Name
BIT_INTEGER_WORD[15:8]
Description
16-Bit Integer Word. Sets the integer value of N.
Default
0x0
Access
R/W
Address: 0x12, Default: 0x40, Name: REG0012
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
[7] RESERVED
[4:0] RESERVED
[6] EN_AUTOCAL (R/W)
[5] PRE_SEL (R/W)
Enables Autocalibration.
Prescaler Select.
Table 17. Bit Descriptions for REG0012
Bit(s) Bit Name
Description
Default Access
7
6
RESERVED
Reserved.
0x0
0x1
R
EN_AUTOCAL Enables Autocalibration.
0: VCO autocalibration disabled.
1: VCO autocalibration enabled.
R/W
5
PRE_SEL
Prescaler Select. The dual modulus prescaler is set by this bit. The prescaler, at the input to
0x0
0x0
R/W
the N divider, divides down the VCO signal. This action occurs so the N divider can handle the
signal. The prescaler setting affects the RF frequency and the minimum and maximum INT
value.
0: 4/5 prescaler.
1: 8/9 prescaler.
Reserved.
[4:0]
RESERVED
R
Address: 0x14, Default: 0x00, Name: REG0014
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] FRAC1WORD[7:0] (R/W)
25-Bit FRAC1 Value.
Table 18. Bit Descriptions for REG0014
Bit(s)
[7:0]
Bit Name
FRAC1WORD[7:0]
Description
±5-Bit FRAC1 Value. Sets the FRAC1 value.
Default
0x0
Access
R/W
Address: 0x15, Default: 0x00, Name: REG0015
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] FRAC1WORD[15:8] (R/W)
25-Bit FRAC1 Value.
Table 19. Bit Descriptions for REG0015
Bit(s)
Bit Name
Description
Default
Access
[7:0]
FRAC1WORD[15:8]
±5-Bit FRAC1 Value. Sets the FRAC1 value.
0x0
R/W
Rev. 0 | Page ±8 of 47
Data Sheet
ADF4372
Address: 0x16, Default: 0x00, Name: REG0016
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] FRAC1WORD[23:16] (R/W)
25-Bit FRAC1 Value.
Table 20. Bit Descriptions for REG0016
Bit(s)
Bit Name
Description
Default
Access
[7:0]
FRAC1WORD[±3:16]
±5-Bit FRAC1 Value. Sets the FRAC1 value.
0x0
R/W
Address: 0x17, Default: 0x00, Name: REG0017
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] FRAC2WORD[6:0] (R/W)
14-Bit FRAC2 Value.
[0] FRAC1WORD[24] (R/W)
25-Bit FRAC1 Value.
Table 21. Bit Descriptions for REG0017
Bit(s)
[7:1]
0
Bit Name
FRAC±WORD[6:0]
FRAC1WORD[±4:±4]
Description
14-Bit FRAC± Value. Sets the FRAC± value.
±5-Bit FRAC1 Value. Sets the FRAC1 value.
Default
0x0
0x0
Access
R/W
R/W
Address: 0x18, Default: 0x00, Name: REG0018
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESERVED
[6:0] FRAC2WORD[13:7] (R/W)
14-Bit FRAC2 Value.
Table 22. Bit Descriptions for REG0018
Bit(s) Bit Name
Description
Default Access
7
RESERVED
Reserved.
0x0
0x0
R
[6:0]
FRAC±WORD[13:7]
14-Bit FRAC± Value. Sets the FRAC± value.
R/W
Address: 0x19, Default: 0xE8, Name: REG0019
7
6
5
4
3
2
1
0
1
1
1
0
1
0
0
0
[7:0] MOD2WORD[7:0] (R/W)
14-Bit MOD2 Value.
Table 23. Bit Descriptions for REG0019
Bit(s)
[7:0]
Bit Name
MOD±WORD[7:0]
Description
14-Bit MOD± Value. Sets the MOD± value.
Default
0xE8
Access
R/W
Rev. 0 | Page ±9 of 47
ADF4372
Data Sheet
Address: 0x1A, Default: 0x03, Name: REG001A
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7] RESERVED
[5:0] MOD2WORD[13:8] (R/W)
14-Bit MOD2 Value.
[6] PHASE_ADJ (R/W)
Phase Adjust Enable.
Table 24. Bit Descriptions for REG001A
Bit(s) Bit Name Description
Reserved.
Default Access
7
6
RESERVED
0x0
0x0
R
PHASE_ADJ
Phase Adjust Enable. Set to 1 to enable phase adjust. Phase adjust increases the phase
of the output relative to the current phase.
R/W
0: phase adjust disabled.
1: phase adjust enabled.
[5:0]
MOD±WORD[13:8] 14-Bit MOD± Value. Sets the MOD± value.
0x3
R/W
Address: 0x1B, Default: 0x00, Name: REG001B
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_WORD[7:0] (R/W)
24-Bit Phase Value.
Table 25. Bit Descriptions for REG001B
Bit(s) Bit Name Description
[7:0]
Default Access
0x0 R/W
PHASE_WORD[7:0] ±4-Bit Phase Value. Sets the phase word for phase adjust. If phase adjust is not used, set
phase value to 0. The phase of the RF output frequency can be adjusted in ±4-bit steps.
Phase step = phase word ÷ 16,777,±16 × 360.
Address: 0x1C, Default: 0x00, Name: REG001C
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_WORD[15:8] (R/W)
24-Bit Phase Value.
Table 26. Bit Descriptions for REG001C
Bit(s) Bit Name Description
[7:0]
Default Access
0x0 R/W
PHASE_WORD[15:8] ±4-Bit Phase Value. Sets the phase word for phase adjust. If phase adjust is not used,
set phase value to 0. The phase of the RF output frequency can be adjusted in ±4-bit
steps. Phase step = phase word ÷ 16,777,±16 × 360°.
Address: 0x1D, Default: 0x00, Name: REG001D
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] PHASE_WORD[23:16] (R/W)
24-Bit Phase Value.
Table 27. Bit Descriptions for REG001D
Bit(s) Bit Name Description
[7:0]
Default Access
0x0 R/W
PHASE_WORD[±3:16] ±4-Bit Phase Value. Sets the phase word for phase adjust. If phase adjust is not used,
set phase value to 0. The phase of the RF output frequency can be adjusted in ±4-bit
steps. Phase step = phase word ÷ 16,777,±16 × 360°.
Rev. 0 | Page 30 of 47
Data Sheet
ADF4372
Address: 0x1E, Default: 0x48, Name: REG001E
7
6
5
4
3
2
1
0
0
1
0
0
1
0
0
0
[7:4] CP_CURRENT (R/W)
[0] CNTR_RESET (R/W)
Charge Pump Current Setting.
Counter Reset.
[3] PD_POL (R/W)
[1] RESERVED
Phase Detector Polarity.
[2] PD (R/W)
Power-Down.
Table 28. Bit Descriptions for REG001E
Bit(s) Bit Name Description
Default Access
[7:4]
CP_CURRENT Charge Pump Current Setting. Sets the charge pump current. Set these bits to the charge
pump current that the loop filter is designed for.
0x4
R/W
0: 0.35 mA.
1: 0.70 mA.
10: 1.05 mA.
11: 1.4 mA.
100: 1.75 mA.
101: ±.8 mA.
110: ±.45 mA.
111: ±.8 mA.
1000: 3.15 mA.
1001: 3.5 mA.
1010: 3.85 mA.
1011: 4.± mA.
1100: 4.55 mA.
1101: 4.9 mA.
1110: 5.±5 mA.
1111: 5.6 mA.
3
±
PD_POL
Phase Detector Polarity. If using a noninverting loop filter and a VCO with positive tuning
slope, set phase detector polarity to positive. If using an inverting loop filter and a VCO with a
negative tuning slope, set phase detector polarity to positive. If using a noninverting loop
filter and a VCO with a negative tuning slope, set phase detector polarity to negative. If using
an inverting loop filter and a VCO with a positive tuning slope, set phase detector polarity to
negative.
0x1
0x0
R/W
R/W
0: negative phase detector polarity.
1: positive phase detector polarity.
PD
Power-Down. Setting to 1 powers down all internal PLL blocks of the ADF437±. The VCO and
multipliers remain powered up. The registers do not lose their values. After bringing the
ADF437± out of power-down (setting to 0) a write to Address 0x10 is required to relock the
loop.
0: normal operation.
1: power-down.
Reserved.
1
0
RESERVED
0x0
0x0
R
CNTR_RESET
Counter Reset. Setting to 1 holds the N divider and R counter in reset. There are no signals
entering the PFD.
R/W
0: normal operation.
1: counter reset.
Rev. 0 | Page 31 of 47
ADF4372
Data Sheet
Address: 0x1F, Default: 0x01, Name: REG001F
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:5] RESERVED
[4:0] R_WORD (R/W)
5-Bit R Counter.
Table 29. Bit Descriptions for REG001F
Bit(s)
[7:5]
[4:0]
Bit Name
RESERVED
R_WORD
Description
Reserved.
Default
0x0
Access
R
5-Bit R Counter. b'00000 corresponds to 0x1
divide by 3±.
R/W
Address: 0x20, Default: 0x14, Name: REG0020
7
6
5
4
3
2
1
0
0
0
0
1
0
1
0
0
[7:4] MUXOUT (R/W)
[1:0] RESERVED
Mux Out.
[2] LEV_SEL (R/W)
[3] MUXOUT_EN (R/W)
Mux Out Level Select.
Mux Out Enable.
Table 30. Bit Descriptions for REG0020
Bit(s)
Bit Name
Description
Default
Access
[7:4]
MUXOUT
Mux Out. This bit is used to set the mux out signal when MUXOUT_EN = 1.
0x1
R/W
0: tristate, high impedance output (only works when MUXOUT_EN = 0).
1: digital lock detect.
10: charge pump up.
11: charge pump down.
100: RDIV±.
101: N divider output.
110: VCO test modes.
111: reserved.
1000: high.
1001: VCO calibration R band/±.
1010: VCO calibration N band/±.
Mux Out Enable. Set to 0 if using the SDIO pin for register readback.
0: data pin used for readback.
1: mux out pin used for readback.
Mux Out Level Select. Select the voltage level of the logic at the mux out.
0: 1.8 V logic.
3
MUXOUT_EN
LEV_SEL
0x0
0x1
0x0
R/W
R/W
R
±
1: 3.3 V logic.
[1:0]
RESERVED
Reserved.
Rev. 0 | Page 3± of 47
Data Sheet
ADF4372
Address: 0x22, Default: 0x00, Name: REG0022
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESERVED
[6] REFIN_MODE (R/W)
[3:0] RESERVED
[4] RDIV2 (R/W)
Choose Between Single-Ended or
Differential REFin.
RDIV2.
[5] REF_DOUB (R/W)
Reference Doubler.
Table 31. Bit Descriptions for REG0022
Bit(s) Bit Name
Description
Default Access
7
6
RESERVED
Reserved.
0x0
0x0
R
REFIN_MODE Choose Between Single-Ended or Differential REFIN.
0: single-ended REFIN.
R/W
1: differential REFIN.
5
4
REF_DOUB
RDIV±
Reference Doubler. Controls the reference doubler block.
0: doubler disabled.
1: doubler enabled.
0x0
0x0
R/W
R/W
RDIV±. Controls the reference divide by ± clock. This feature can be used to provide a 50%
duty cycle signal to the PFD.
0: RDIV± disabled.
1: RDIV± enabled.
Reserved.
[3:0]
RESERVED
0x0
R
Address: 0x23, Default: 0x00, Name: REG0023
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[0] RESERVED
[5:4] CLK_DIV_MODE (R/W)
[1] TRACKING_FILTER_MUX_SEL (R/W)
Clock Divide Mode.
Tracking Filter Mux Select.
[3:2] RESERVED
Table 32. Bit Descriptions for REG0023
Bit(s) Bit Name
Description
Default Access
[7:6]
[5:4]
RESERVED
CLK_DIV_MODE
Reserved.
0x0
0x0
R
R/W
Clock Divide Mode. Set to 10 to enable phase resynchronization. When not
using phase resynchronization, set to 00.
0: clock divider off (normal operation).
10: resynchronization enabled.
Reserved.
[3:±]
1
RESERVED
0x0
0x0
R
R/W
TRACKING_FILTER_MUX_SEL Tracking Filter Mux Select.
0: normal, tracking filter coefficients set automatically.
1: tracking filter coefficients set manually from SPI (Address 0x70 and
Address 0x71).
0
RESERVED
Reserved.
0x0
R
Rev. 0 | Page 33 of 47
ADF4372
Data Sheet
Address: 0x24, Default: 0x80, Name: REG0024
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7] FB_SEL (R/W)
[3:0] RESERVED
Feedback.
[6:4] DIV_SEL (R/W)
Division Selection.
Table 33. Bit Descriptions for REG0024
Bit(s)
7
Bit Name
FB_SEL
Description
Feedback.
0: divider feedback to N counter.
Default
0x1
Access
R/W
1: fundamental feedback to N counter.
Division Selection.
0: divide 1.
[6:4]
DIV_SEL
0x0
R/W
1: divide ±.
10: divide 4.
11: divide 8.
100: divide 16.
101: divide 3±.
110: divide 64.
111: reserved.
[3:0]
RESERVED
Reserved.
0x0
R
Address: 0x25, Default: 0x07, Name: REG0025
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
[7] MUTE_LD (R/W)
[1:0] RF_OUT_POWER (R/W)
Mute to Lock Detect.
Select Output Power Level.
[6] RESERVED
[2] RF_EN (R/W)
RFOUT Enable.
[5] RF_DIVSEL_DB (R/W)
Select if DIV_SEL is Double Buffered.
[3] X2_EN (R/W)
Doubler Path Enable.
[4] X4_EN (R/W)
Not Used.
Table 34. Bit Descriptions for REG0025
Bit(s) Bit Name Description
Default Access
7
MUTE_LD
Mute to Lock Detect.
0x0
R/W
0: mute to lock detect disabled.
1: mute to lock detect enabled, RF output stage gated by digital lock detect asserting
logic high.
6
5
4
3
RESERVED
RF_DIVSEL_DB
X4_EN
Reserved.
Select if DIV_SEL is Double Buffered.
Not Used.
Doubler Path Enable.
0: RF doubler off.
1: RF doubler on.
RFOUT Enable.
0: RFOUT disabled.
1: RFOUT enabled.
0x0
0x0
0x0
0x0
R
R/W
R/W
R/W
X±_EN
±
RF_EN
0x1
0x3
R/W
R/W
[1:0]
RF_OUT_POWER Select Output Power Level.
0: −4 dBm.
1: −1 dBm.
10: ± dBm.
11: 5 dBm.
Rev. 0 | Page 34 of 47
Data Sheet
ADF4372
Address: 0x26, Default: 0x32, Name: REG0026
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
[7:0] BLEED_ICP (R/W)
Bleed Current.
Table 35. Bit Descriptions for REG0026
Bit(s) Bit Name
Description
Default Access
[7:0]
BLEED_ICP Bleed Current. Sets the bleed current. The optimum bleed current is set by ((4/N) × ICP)/3.75,
where ICP is the charge pump current in μA.
0x3±
R/W
Address: 0x27, Default: 0xC5, Name: REG0027
7
6
5
4
3
2
1
0
1
1
0
0
0
1
0
1
[7:6] LD_BIAS (R/W)
[1:0] RF_PBS (R/W)
Lock Detect Bias.
Reserved.
[5] LDP (R/W)
[2] VCOLDO_PD (R/W)
Lock Detect Precision.
VCO LDO Enable.
[4] BLEED_GATE (R/W)
[3] BLEED_EN (R/W)
Gated Bleed.
Bleed Enable.
Table 36. Bit Descriptions for REG0027
Bit(s) Bit Name Description
[7:6] LD_BIAS
Default Access
Lock Detect Bias. The lock detector window size is set by adjusting the lock detector bias in
conjunction with the lock detector precision.
0x3
R/W
0: 5 ns lock detect delay if LDP = 0.
1: 6 ns.
10: 8 ns.
11: 1± ns lock detect delay (for large values of bleed)
5
LDP
Lock Detect Precision. Controls the sensitivity of the digital lock detector, depending on INT
or FRAC operation selected.
0x0
R/W
0: FRAC Mode (5 ns).
1: INT Mode (±.4 ns).
4
3
BLEED_GATE Gated Bleed.
0: gate bleed disabled.
0x0
0x0
R/W
R/W
1: gate bleed on, digital lock detect (digital lock detect must be enabled)
BLEED_EN
Bleed Enable. Bleed current applies to a current inside the charge pump to improve the
linearity of the charge pump. This current leads to lower phase noise and improved spurious
performance. Set to 1 to enable negative bleed.
0: negative bleed disabled.
1: negative bleed enabled.
±
VCOLDO_PD VCO LDO Enable. For optimal spurious and phase noise performance, disable VCO LDO.
0x1
0x1
R/W
R/W
0: VCO LDO enabled.
1: VCO LDO disabled.
[1:0]
RF_PBS
Reserved.
Rev. 0 | Page 35 of 47
ADF4372
Data Sheet
Address: 0x28, Default: 0x03, Name: REG0028
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7:3] RESERVED
[0] LOL_EN (R/W)
Loss of Lock Enable.
[2:1] LD_COUNT (R/W)
Lock Detector Count.
Table 37. Bit Descriptions for REG0028
Bits Bit Name
Description
Reset Access
[7:3] RESERVED
Reserved.
0x0
0x1
R
[±:1] LD_COUNT Lock Detector Count. Initial value of the lock detector. This field sets the number of counts of PFD
within lock window before asserting digital lock detect high.
R/W
0: 10±4 cycles.
1: ±048 cycles.
10: 4096 cycles.
11: 819± cycles.
0
LOL_EN
Loss of Lock Enable. When loss of lock is enabled, if digital lock detect is asserted, and the
reference signal is removed, digital lock detect goes low. It is recommended to set this bit to 1 to
enable loss of lock.
0x1
R/W
0: loss of lock disabled
1: loss of lock enabled.
Address: 0x2A, Default: 0x00, Name: REG002A
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:6] RESERVED
[0] READ_SEL (R/W)
Readback Select.
[5] BLEED_POL (R/W)
Bleed Polarity.
[2:1] RESERVED
[4] RESERVED
[3] LE_SEL (R/W)
CSB from Pin, Synchronized with
REFN
Table 38. Bit Descriptions for REG002A
Bit(s)
[7:6]
5
Bit Name
RESERVED
BLEED_POL
Description
Reserved.
Default
0x0
Access
R
Bleed Polarity. Controls the polarity of the bleed current. Negative is typical usage.
0: negative bleed.
0x0
R/W
1: positive bleed (not recommended).
Reserved.
CS from Pin, Synchronized with REFN.
0: CS synchronization disabled.
4
3
RESERVED
LE_SEL
0x0
0x0
R
R/W
1: CS synchronization enabled.
[±:1]
0
RESERVED
READ_SEL
Reserved.
0x0
0x0
R
R/W
Readback Select. Selects the value to be read back.
0: readback VCO, band, and bias compensation data.
1: readback device version ID.
Rev. 0 | Page 36 of 47
Data Sheet
ADF4372
Address: 0x2B, Default: 0x01, Name: REG002B
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
[7:6] RESERVED
[5] LSB_P1 (R/W)
[0] SD_EN_FRAC0 (R/W)
ΣΔ Enable.
Adds 1/2 bit to FRAC1 when auxiliary
SDM is off (VAR_MOD_EN=0) .
[1] RESERVED
[2] SD_LOAD_ENB (R/W)
Mask ΣΔ Reset when REG0010 is
updated.
[4] VAR_MOD_EN (R/W)
Enable Auxiliary SDM.
[3] RESERVED
Table 39. Bit Descriptions for REG002B
Bit(s) Bit Name Description
Reserved.
Default Access
[7:6]
5
RESERVED
LSB_P1
0x0
0x0
R
R/W
Adds a half bit to FRAC1 when auxiliary SDM is off (VAR_MOD_EN = 0). Set to 0 for normal
operation.
4
VAR_MOD_EN
Enable Auxiliary SDM. If FRAC± is different than 0, this bit is programmed to 1.
0x1
R/W
0: normal operation.
1: enable auxiliary SDM.
Reserved.
3
±
1
0
RESERVED
0x0
0x0
0x0
0x1
R
SD_LOAD_ENB Mask Σ-Δ Reset when Address 0x10 is Updated.
R/W
R
R/W
RESERVED
SD_EN_FRAC0
Reserved.
Σ-Δ Enable. Set to 1 when in integer mode (when FRAC1 = FRAC± = 0), and set to 0 when in
fractional mode.
0: Σ-Δ enabled (for fractional mode).
1: Σ-Δ disabled (for integer mode).
Address: 0x2C, Default: 0x44, Name: REG002C
7
6
5
4
3
2
1
0
0
1
0
0
0
1
0
0
[7] RESERVED
[0] DISABLE_ALC (R/W)
Automatic VCO Bias Control (ALC).
[6] ALC_RECT_SELECT_VCO1 (R/W)
Select ALC Rectifier DC Bias (Core
D).
[1] VTUNE_CALSET_EN (R/W)
Temperature Dependent VCO Calibration
Voltage.
[5] ALC_REF_DAC_LO_VCO1 (R/W)
Select ALC Threshold Voltage (Core
D).
[4:2] ALC_REF_DAC_NOM_VCO1 (R/W)
Select VCO ALC Threshold (Core
D).
Table 40. Bit Descriptions for REG002C
Bit(s)
7
6
Bit Name
RESERVED
Description
Reserved.
Default
0x0
Access
R
ALC_RECT_SELECT_VCO1
Select ALC Rectifier DC Bias (Core D).
0: 3.3 V VCO operation.
0x1
R/W
1: 5 V VCO operation.
5
ALC_REF_DAC_LO_VCO1
Select ALC Threshold Voltage (Core D).
0: 5 V VCO operation.
0x0
R/W
1: 3.3 V VCO operation.
[4:±]
1
ALC_REF_DAC_NOM_VCO1
VTUNE_CALSET_EN
Select VCO ALC Threshold (Core D).
001: 3.3 V and 5 V VCO operation.
Temperature Dependent VCO Calibration Voltage.
0: disable temperature dependent VCO calibration voltage.
1: enable temperature dependent VCO calibration voltage.
Automatic VCO Bias Control (ALC).
0: ALC enabled.
0x1
0x0
R/W
R/W
0
DISABLE_ALC
0x0
R/W
1: ALC disabled.
Rev. 0 | Page 37 of 47
ADF4372
Data Sheet
Address: 0x2D, Default: 0x11, Name: REG002D
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
1
[7:5] RESERVED
[2:0] ALC_REF_DAC_NOM_VCO2 (R/W)
Select VCO ALC Threshold (Core
C).
[4] ALC_RECT_SELECT_VCO2 (R/W)
Sets ALC Rectifier DC Bias (Core
C).
[3] ALC_REF_DAC_LO_VCO2 (R/W)
Select ALC Threshold Voltage (Core
C).
Table 41. Bit Descriptions for REG002D
Bit(s)
[7:5]
4
Bit Name
RESERVED
ALC_RECT_SELECT_VCO±
Description
Reserved.
Sets ALC Rectifier DC Bias (Core C).
0: 3.3 V VCO operation.
Default
0x0
0x1
Access
R
R/W
1: 5 V VCO operation.
3
ALC_REF_DAC_LO_VCO±
ALC_REF_DAC_NOM_VCO±
Select ALC Threshold Voltage (Core C).
0: 5 V VCO operation.
1: 3.3 V VCO operation.
Select VCO ALC Threshold (Core C).
001: 3.3 V and 5 V VCO operation.
0x0
0x1
R/W
R/W
[±:0]
Address: 0x2E, Default: 0x12, Name: REG002E
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
0
[7:5] RESERVED
[2:0] ALC_REF_DAC_NOM_VCO3 (R/W)
Select VCO ALC Threshold (Core
B).
[4] ALC_RECT_SELECT_VCO3 (R/W)
Sets ALC Rectifier DC Bias (Core
B).
[3] ALC_REF_DAC_LO_VCO3 (R/W)
Sets ALC Threshold Voltage (Core
B).
Table 42. Bit Descriptions for REG002E
Bit(s)
[7:5]
4
Bit Name
RESERVED
ALC_RECT_SELECT_VCO3
Description
Reserved.
Sets ALC Rectifier DC Bias (Core B).
0: 3.3 V VCO operation.
Default
0x0
0x1
Access
R
R/W
1: 5 V VCO operation.
3
ALC_REF_DAC_LO_VCO3
ALC_REF_DAC_NOM_VCO3
Sets ALC Threshold Voltage (Core B).
0: 5 V VCO operation.
1: 3.3 V VCO operation.
0x0
0x±
R/W
R/W
[±:0]
Select VCO ALC Threshold (Core B).
010: 3.3 V and 5 V VCO operation.
Rev. 0 | Page 38 of 47
Data Sheet
ADF4372
Address: 0x2F, Default: 0x94, Name: REG002F
7
6
5
4
3
2
1
0
1
0
0
1
0
1
0
0
[7] SWITCH_LDO_3P3V_5V (R/W)
Switch LDO Operation Between 3.3
V and 5 V.
[2:0] ALC_REF_DAC_NOM_VCO4 (R/W)
Select VCO ALC Threshold (Core
A).
[6:5] RESERVED
[3] ALC_REF_DAC_LO_VCO4 (R/W)
Select ALC Lower Threshold Voltage
Range (Core A).
[4] ALC_RECT_SELECT_VCO4 (R/W)
Sets ALC Rectifier DC Bias (Core
A).
Table 43. Bit Descriptions for REG002F
Bit(s)
Bit Name
Description
Default
Access
7
SWITCH_LDO_3P3V_5V
Switch LDO Operation Between 3.3 V and 5 V.
0: 3.3 V VCO operation.
0x1
R/W
1: 5 V VCO operation.
[6:5]
4
RESERVED
Reserved.
0x0
0x1
R
ALC_RECT_SELECT_VCO4
Sets ALC Rectifier DC Bias (Core A).
0: 3.3 V VCO operation.
R/W
1: 5 V VCO operation.
3
ALC_REF_DAC_LO_VCO4
ALC_REF_DAC_NOM_VCO4
Select ALC Lower Threshold Voltage Range (Core A).
0: 5 V VCO operation.
1: 3.3 V VCO operation.
0x0
0x4
R/W
R/W
[±:0]
Select VCO ALC Threshold (Core A).
010: 3.3 V VCO operation.
100: 5 V VCO operation.
Address: 0x30, Default: 0x3F, Name: REG0030
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
[7:0] VCO_BAND_DIV (R/W)
Sets the Autocalibration Time per
Stage.
Table 44. Bit Descriptions for REG0030
Bit(s) Bit Name
[7:0] VCO_BAND_DIV
Description
Sets the Autocalibration Time per Stage. See the Lock Time section for details.
Default
0x3F
Access
R/W
Address: 0x31, Default: 0xA7, Name: REG0031
7
6
5
4
3
2
1
0
1
0
1
0
0
1
1
1
[7:0] TIMEOUT[7:0] (R/W)
Used as Part of the ALC Wait Time
and Synthetic Lock Time.
Table 45. Bit Descriptions for REG0031
Bit(s) Bit Name
Description
Default Access
0xA7 R/W
[7:0] TIMEOUT[7:0] Used as Part of the ALC Wait Time and Synthetic Lock Time. See the Lock Time section for details.
Rev. 0 | Page 39 of 47
ADF4372
Data Sheet
Address: 0x32, Default: 0x04, Name: REG0032
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
[7] ADC_MUX_SEL (R/W)
[1:0] TIMEOUT[9:8] (R/W)
ADC Mux Select.
Used as Part of the ALC Wait Time
and Synthetic Lock Time.
[6] RESERVED
[2] ADC_ENABLE (R/W)
ADC Enable.
[5] ADC_FAST_CONV (R/W)
ADC Fast Conversion.
[3] ADC_CONVERSION (R/W)
Enables ADC Conversion.
[4] ADC_CTS_CONV (R/W)
ADC Continuous Conversion.
Table 46. Bit Descriptions for REG0032
Bit(s) Bit Name Description
Analog-to-Digital Converter (ADC) Mux Select.
Default Access
7
ADC_MUX_SEL
0x0
R/W
0: proportional to absolute temperature (PTAT) voltage muxed to ADC input.
1: scaled VTUNE voltage muxed to ADC input.
Reserved.
6
5
RESERVED
0x0
0x0
R
ADC_FAST_CONV
ADC Fast Conversion.
0: disabled.
R/W
1: enabled.
4
ADC_CTS_CONV
ADC Continuous Conversion.
0: disabled.
1: enabled.
0x0
0x0
0x1
0x0
R/W
R/W
R/W
R/W
3
ADC_CONVERSION Enables ADC Conversion.
0: no ADC conversion.
1: performs ADC conversion.
±
ADC_ENABLE
TIMEOUT[9:8]
ADC Enable.
0: disabled.
1: enabled.
[1:0]
Used as Part of the ALC Wait Time and Synthetic Lock Time. See the Lock Time section
for details.
Address: 0x33, Default: 0x0C, Name: REG0033
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
0
[7:5] RESERVED
[4:0] SYNTH_LOCK_TIMEOUT (R/W)
Part of VCO Calibration Routine.
Table 47. Bit Descriptions for REG0033
Bit(s) Bit Name
Description
Reserved.
Default
0x0
0xC
Access
R
R/W
[7:5]
[4:0]
RESERVED
SYNTH_LOCK_TIMEOUT
Part of VCO Calibration Routine. See the Lock Time section for details.
Address: 0x34, Default: 0x9E, Name: REG0034
7
6
5
4
3
2
1
0
1
0
0
1
1
1
1
0
[7:5] VCO_FSM_TEST_MODES (R/W)
[4:0] VCO_ALC_TIMEOUT (R/W)
Reserved.
Wait Time for ALC Loop to Settle.
Table 48. Bit Descriptions for REG0034
Bit(s) Bit Name
[7:5]
[4:0]
Description
VCO_FSM_TEST_MODES Reserved.
VCO_ALC_TIMEOUT Wait Time for ALC Loop to Settle. See the Lock Time section for details.
Default Access
0x4
R/W
R/W
0x1E
Rev. 0 | Page 40 of 47
Data Sheet
ADF4372
Address: 0x35, Default: 0x4C, Name: REG0035
7
6
5
4
3
2
1
0
0
1
0
0
1
1
0
0
[7:0] ADC_CLK_DIVIDER (R/W)
ADC Clock Divider.
Table 49. Bit Descriptions for REG0035
Bit(s)
Bit Name
Description
Default
Access
[7:0]
ADC_CLK_DIVIDER
ADC Clock Divider. ADC_CLK = fPFD/((ADC_CLK_DIV × 4) + ±).
0x4C
R/W
Address: 0x36, Default: 0x30, Name: REG0036
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
[7:0] ICP_ADJUST_OFFSET (R/W)
Reserved.
Table 50. Bit Descriptions for REG0036
Bit(s)
[7:0]
Bit Name
ICP_ADJUST_OFFSET
Description
Reserved.
Default
0x30
Access
R/W
Address: 0x37, Default: 0x00, Name: REG0037
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] SI_BAND_SEL (R/W)
Selects Band in Core when Test Mode
is Enabled.
Table 51. Bit Descriptions for REG0037
Bit(s)
[7:0]
Bit Name
SI_BAND_SEL
Description
Selects Band in Core when Test Mode is Enabled.
Default
0x0
Access
R/W
Address: 0x38, Default: 0x00, Name: REG0038
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:4] SI_VCO_SEL (R/W)
Selects Core when Test Mode is
Enabled.
[3:0] SI_VCO_BIAS_CODE (R/W)
Sets VCO Bias when Test Mode is
Enabled.
Table 52. Bit Descriptions for REG0038
Bit(s)
Bit Name
Description
Default
Access
[7:4]
SI_VCO_SEL
Selects Core when Test Mode is Enabled.
0: all cores off.
0x0
R/W
1: VCO Core D.
10: VCO Core C.
100: VCO Core B.
1000: VCO Core A.
[3:0]
SI_VCO_BIAS_CODE
Sets VCO Bias when Test Mode is Enabled.
0000: maximum VCO bias (approximately 3.± V).
1111: minimum VCO bias (approximately 1.8 V).
0x0
R/W
Rev. 0 | Page 41 of 47
ADF4372
Data Sheet
Address: 0x39, Default: 0x07, Name: REG0039
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
[7] RESERVED
[3:0] SI_VTUNE_CAL_SET (R/W)
Select VCO VTUNE Target Voltage
when Test Mode is Enabled.
[6:4] VCO_FSM_TEST_MUX_SEL (R/W)
VCO Test Mux Select.
Table 53. Bit Descriptions for REG0039
Bit(s) Bit Name
Description
Reserved.
Default
0x0
0x0
Access
R
7
RESERVED
[6:4]
VCO_FSM_TEST_MUX_SEL
VCO Test Mux Select.
0: busy.
R/W
1: N band.
10: R band.
11: reserved.
100: timeout clock.
101: bias minimum.
110: ADC busy.
111: logic low.
[3:0]
SI_VTUNE_CAL_SET
Select VCO VTUNE Target Voltage when Test Mode is Enabled.
0x7
R/W
0: 0.58 V.
1: 0.73 V.
10: 0.88 V.
11: 1.03 V.
100: 1.18 V.
101: 1.33 V.
110: 1.48 V.
111: 1.63 V.
1000: 1.78 V.
1001: 1.93 V.
1010: ±.08 V.
1011: ±.±3 V.
1100: ±.38 V.
1101: ±.53 V.
1110: ±.68 V.
1111: ±.83 V.
Address: 0x3A, Default: 0x55, Name: REG003A
7
6
5
4
3
2
1
0
0
1
0
1
0
1
0
1
[7:0] ADC_OFFSET (R/W)
VCO Calibration ADC Offset Correction.
Table 54. Bit Descriptions for REG003A
Bit(s)
[7:0]
Bit Name
ADC_OFFSET
Description
VCO Calibration ADC Offset Correction.
Default
0x55
Access
R/W
Rev. 0 | Page 4± of 47
Data Sheet
ADF4372
Address: 0x3D, Default: 0x00, Name: REG003D
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7] RESERVED
[5:0] RESERVED
[6] SD_RESET (R/W)
Reserved.
Table 55. Bit Descriptions for REG003D
Bit(s)
7
Bit Name
RESERVED
SD_RESET
RESERVED
Description
Reserved.
Reserved.
Reserved.
Default
Access
R
0x0
0x0
0x0
6
R/W
R
[5:0]
Address: 0x3E, Default: 0x0C, Name: REG003E
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
0
[7:4] RESERVED
[3:2] CP_TMODE (R/W)
[1:0] RESERVED
Charge Pump Test Modes.
Table 56. Bit Descriptions for REG003E
Bit(s)
[7:4]
[3:±]
Bit Name
RESERVED
CP_TMODE
Description
Reserved.
Default
0x0
0x3
Access
R
CP Test Modes
0: CP tristate
R/W
11: normal operation
Reserved.
[1:0]
RESERVED
0x0
R
Address: 0x3F, Default: 0x80, Name: REG003F
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
[7:0] CLK1_DIV[7:0] (R/W)
Reserved.
Table 57. Bit Descriptions for REG003F
Bit(s)
[7:0]
Bit Name
CLK1_DIV[7:0]
Description
Reserved.
Default
0x80
Access
R/W
Address: 0x40, Default: 0x50, Name: REG0040
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
[7] RESERVED
[3:0] CLK1_DIV[11:8] (R/W)
Reserved.
[6:4] TRM_IB_VCO_BUF (R/W)
Reserved.
Table 58. Bit Descriptions for REG0040
Bit(s)
7
Bit Name
RESERVED
Description
Reserved.
Reserved.
Reserved.
Default
Access
R
0x0
0x5
0x0
[6:4]
[3:0]
TRM_IB_VCO_BUF
CLK1_DIV[11:8]
R/W
R/W
Rev. 0 | Page 43 of 47
ADF4372
Data Sheet
Address: 0x41, Default: 0x28, Name: REG0041
7
6
5
4
3
2
1
0
0
0
1
0
1
0
0
0
[7:0] CLK2_DIVIDER_1[7:0] (R/W)
Reserved.
Table 59. Bit Descriptions for REG0041
Bit(s)
Bit Name
Description
Default
Access
[7:0]
CLK±_DIVIDER_1[7:0]
Reserved.
0x±8
R/W
Address: 0x47, Default: 0xC0, Name: REG0047
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0
[7:5] TRM_RESD_VCO_MUX (R/W)
Reserved.
[4:0] RESERVED
Table 60. Bit Descriptions for REG0047
Bit(s) Bit Name Description
TRM_RESD_VCO_MUX Reserved.
RESERVED Reserved.
Default Access
[7:5]
[4:0]
0x6
0x0
R/W
R
Address: 0x52, Default: 0xF4, Name: REG0052
7
6
5
4
3
2
1
0
1
1
1
1
0
1
0
0
[7:5] TRM_RESD_VCO_BUF (R/W)
[1:0] RESERVED
Reserved.
[4:2] TRM_RESCI_VCO_BUF (R/W)
Reserved.
Table 61. Bit Descriptions for REG0052
Bit(s)
[7:5]
[4:±]
[1:0]
Bit Name
Description
Reserved. VCO buffer trim.
Reserved.
Default
0x7
0x5
Access
TRM_RESD_VCO_BUF
TRM_RESCI_VCO_BUF
RESERVED
R/W
R/W
R
Reserved.
0x0
Address: 0x6E, Default: 0x00, Name: REG006E
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VCO_DATA_READBACK[7:0] (R)
Open-Loop VCO Counter Readback.
Table 62. Bit Descriptions for REG006E
Bit(s)
Bit Name
Description
Default
Access
[7:0]
VCO_DATA_READBACK[7:0]
Open-Loop VCO Counter Readback.
0x0
R
Address: 0x6F, Default: 0x00, Name: REG006F
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:0] VCO_DATA_READBACK[15:8] (R)
Open-Loop VCO Counter Readback.
Table 63. Bit Descriptions for REG006F
Bit(s)
Bit Name
Description
Default
Access
[7:0]
VCO_DATA_READBACK[15:8]
Open-Loop VCO Counter Readback.
0x0
R
Rev. 0 | Page 44 of 47
Data Sheet
ADF4372
Address: 0x70, Default: 0x03, Name: REG0070
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
[7:5] BAND_SEL_X2 (R/W)
Filter Select for Doubler Output Tracking
Filter.
[1:0] BIAS_SEL_X2 (R/W)
Bias Select for Doubler Output Tracking
Filter.
[4:2] RESERVED
Table 64. Bit Descriptions for REG0070
Bit(s)
Bit Name
Description
Default
Access
[7:5]
BAND_SEL_X±
Filter Select for Doubler Output
Tracking Filter.
0x0
R/W
[4:±]
[1:0]
RESERVED
Reserved.
0x0
0x3
R
BIAS_SEL_X±
Bias Select for Doubler Output
Tracking Bias.
R/W
Address: 0x71, Default: 0x60, Name: REG0071
7
6
5
4
3
2
1
0
0
1
1
0
0
0
0
0
[7:5] BAND_SEL_X4 (R/W)
[1:0] BIAS_SEL_X4 (R/W)
Not Used.
Not Used.
[4:2] RESERVED
Table 65. Bit Descriptions for REG0071
Bit(s)
[7:5]
[4:±]
[1:0]
Bit Name
BAND_SEL_X4
RESERVED
Description
Not Used.
Reserved.
Not Used.
Default
Access
R/W
R
0x3
0x0
0x0
BIAS_SEL_X4
R/W
Address: 0x72, Default: 0x32, Name: REG0072
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
0
[7] RESERVED
[0] RESERVED
[6] AUX_FREQ_SEL (R/W)
[1] COUPLED_VCO (R/W)
Auxillary RF Output Frequency Select.
Reserved.
[5:4] POUT_AUX (R/W)
[2] RESERVED
Auxiliary RF Output Power.
[3] PDB_AUX (R/W)
Power-Down Auxiliary RF Output.
Table 66. Bit Descriptions for REG0072
Bit(s) Bit Name Description
Reserved.
Default
0x0
Access
R
7
6
RESERVED
AUX_FREQ_SEL
Auxiliary RF Output Frequency Select.
0: divided output.
0x0
R/W
1: VCO output.
[5:4]
POUT_AUX
PDB_AUX
Auxiliary RF Output Power. Sets the output power at the auxiliary RF output ports.
0: −4.5 dBm single-ended ÷ −1.5 dBm differential.
1: 1 dBm single-ended ÷ 4 dBm differential.
10: 4 dBm single-ended ÷ 7 dBm differential.
11: 6 dBm single-ended ÷ 9 dBm differential.
Power-Down Auxiliary RF Output.
0: auxiliary RF off.
0x3
0x0
R/W
R/W
3
1: auxiliary RF on.
±
1
0
RESERVED
Reserved.
0x0
0x1
0x0
R
COUPLED_VCO
RESERVED
Reserved.
Reserved.
R/W
R
Rev. 0 | Page 45 of 47
ADF4372
Data Sheet
Address: 0x73, Default: 0x00, Name: REG0073
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:3] RESERVED
[0] LD_DIV (R/W)
Lock Detector Count Divider.
[2] ADC_CLK_DISABLE (R/W)
Disable ADC clock.
[1] PD_NDIV (R/W)
Power-Down N divider.
Table 67. Bit Descriptions for REG0073
Bits Bit Name
Description
Default Access
[7:3] RESERVED
Reserved.
0x0
0x0
0x0
0x0
R
±
1
0
ADC_CLK_DISABLE Disable ADC Clock. ADC_ENABLE setting overwrites this bit.
R/W
R/W
R/W
PD_NDIV
LD_DIV
Power-Down N Divider.
Lock Detector Count Divider. Divides the lock detector count cycles by 3± so that the
LD_COUNT bits in Address 0x±8 can be selected as 3±, 64, 1±8, and ±56.
Address: 0x7C, Default: 0x00, Name: REG007C
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
[7:1] RESERVED
[0] LOCK_DETECT_READBACK (R)
Readback of the Lock Detect Bit.
Table 68. Bit Descriptions for REG007C
Bit(s)
[7:1]
0
Bit Name
RESERVED
Description
Reserved.
Default
0x0
Access
R
R
LOCK_DETECT_READBACK
Readback of the Lock Detect Bit.
0x0
Rev. 0 | Page 46 of 47
Data Sheet
ADF4372
OUTLINE DIMENSIONS
7.10
7.00
6.90
0.30
0.25
0.20
PIN 1
INDICATOR
AREA
PIN 1
INDICATOR
C 0.30 × 0.45°
37
36
48
1
5.50 REF
SQ
5.00 BSC
SQ
EXPOSED
PAD
25
24
12
13
0.45
0.40
0.30
0.50
BSC
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.10
BSC
1.158
1.058
0.958
0.70 REF
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.398
0.358
0.318
SEATING
PLANE
SECTION OF THIS DATA SHEET.
Figure 38. 48-Terminal Land Grid Array Package [LGA]
(CC-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF4372BCCZ
ADF4372BCCZ-RL7
EV-ADF4372SD2Z
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
48-Terminal Land Grid Array Package [LGA]
48-Terminal Land Grid Array Package [LGA]
Evaluation Board
CC-48-4
CC-48-4
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16984-0-8/19(0)
Rev. 0 | Page 47 of 47
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