ADF4602 [ADI]
Single-Chip, Multiband 3G Femtocell Transceiver; 单芯片，多频段3G毫微微蜂窝收发器
| 型号： | ADF4602 |
| 厂家： | 
ADI |
| 描述： | Single-Chip, Multiband 3G Femtocell Transceiver |
| 文件： | 总36页 (文件大小：729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Chip, Multiband 3G Femtocell
Transceiver
ADF4602
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single-chip multiband 3G transceiver
3GPP 25.104 release 6 WCDMA/HSPA compatible
UMTS band coverage
Local area Class BS in Band 1 to Band 6 and Band 8 to
Band 10
Direct conversion transmitter and receiver
Minimal external components
ADF4602
Tx_PWR_CONTROL
TXBBIB
TXBBI
TXLBRF
Integrated multiband multimode monitoring
No Tx SAW or Rx interstage SAW filters
Integrated power management (3.1 V to 3.6 V supply)
Integrated synthesizers including PLL loop filters
Integrated PA bias control DACs/GPOs
WCDMA and GSM receive baseband filter options
Easy to use with minimal calibration
Automatic Rx DC offset control
Simple gain, frequency, mode programming
Low supply current
50 mA typical Rx current
50 mA to 100 mA Tx current (varies with output power)
6 mm × 6 mm 40-pin LFCSP package
TXBBQ
TXBBQB
Tx_PWR_
CONTROL
Tx_PWR_CONTROL
TXHBRF
Tx_PWR_
Tx PLL
CONTROL
FRAC N
SYNTHE-
SIZER
VSUP7
VSUP6
LOOP
FILTER
LO GENERATOR
Rx PLL
FRAC N
SYNTHE-
SIZER
LOOP
FILTER
LO GENERATOR
Rx_LO_LB
SELECTABLE BANDWIDTH
BASEBAND FILTERS
RXHB1RF
RXHB2RF
RXBBI
APPLICATIONS
I
RXBBIB
CHAN-
NEL
3G home basestations (femtocells)
3G repeaters
DC OFFSET
CORRECTION
RXBBQ
RXLBRF
Q
RXBBQB
CHAN-
NEL
DC OFFSET
CORRECTION
Rx_LO_LB
REFIN
26MHz 19.2MHz
SERIAL
INTER-
FACE
VSUP8
VDD
LDO1 LDO2 LDO3 LDO4 LDO5
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADF4602
TABLE OF CONTENTS
Features .............................................................................................. 1
Receiver Description.................................................................. 18
Power Management ................................................................... 21
Frequency Synthesis................................................................... 22
Serial Port Interface (SPI).............................................................. 23
Operation and Timing............................................................... 23
Registers........................................................................................... 24
Register Map ............................................................................... 24
Register Description .................................................................. 25
Software Initialization Procedure................................................. 29
Initialization Sequence .............................................................. 29
Applications Information.............................................................. 31
Interfacing the ADF4602 to the AD9863................................ 31
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 33
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics..................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 17
Transmitter Description ............................................................ 17
DACs ............................................................................................ 18
General Purpose Outputs.......................................................... 18
REVISION HISTORY
10/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADF4602
GENERAL DESCRIPTION
The ADF4602 is a 3G transceiver integrated circuit (IC)
offering unparalleled integration and feature set. The IC is
ideally suited to high performance 3G femtocells providing
cellular fixed mobile converged (FMC) services. With only a
handful of external components, a full multiband transceiver is
implemented.
coupled with the multiband LNA input structure, allows
GSM-EDGE signals to be monitored as part of a UMTS home
basestation.
The transmitter uses an innovative direct conversion modulator
that achieves high modulation accuracy with exceptionally low
noise, eliminating the need for external transmit SAW filters.
UMTS Band 1 through Band 6 and Band 8 through Band 10 are
supported in a single device.
The fully integrated phase lock loops (PLLs) provide high
performance and low power fractional-N frequency synthesis
for both receive and transmit sections. Special precautions have
been taken to provide the isolation demanded by frequency
division duplex (FDD) systems. All VCO and loop filter
components are fully integrated.
The receiver is based on a direct conversion architecture. This
architecture is the ideal choice for highly integrated wideband
CDMA (WCDMA) receivers, reducing the bill of materials by
fully integrating all interstage filtering. The front end includes
three high performance, single-ended low noise amplifiers
(LNAs), allowing the device to support tri-band applications.
The single-ended input structure eases interface and reduces
the matching components required for small footprint single-
ended duplexers. The excellent device linearity achieves good
performance with a large range of SAW and ceramic filter
duplexers.
The ADF4602 also contains on-chip low dropout voltage
regulators (LDOs) to deliver regulated supply voltages to the
functions on chip, with an input voltage of between 3.1 V
and 3.6 V.
The IC is controlled via a standard 3-wire serial interface with
advanced internal features allowing simple software programming.
Comprehensive power-down modes are included to minimize
power consumption in normal use.
The integrated receive baseband filters offer selectable
bandwidth, enabling the device to receive both WCDMA and
GSM-EDGE radio signals. The selectable bandwidth filter,
Rev. 0 | Page 3 of 36
ADF4602
SPECIFICATIONS
VDD = 3.1 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3.3 V and TA = 25°C,
26 MHz reference input level = 0.7 V p-p.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
REFERENCE SECTION
Reference Input
Reference Input Frequency
Reference Input Amplitude
REFCLK Output (26 MHz)
Output Load Capacitance
Output Swing
26
0.7
MHz
V p-p
0.1
2.0
40
Single-ended operation, dc-coupled1
10
1.5
200
2
pF
V p-p
V/μs
%
10 pF load
10 pF load
Input duty cycle = 50%
Output Slew Rate
Output Duty Cycle Variation
CHIPCLK Output (19.2 MHz)
Output Load Capacitance
Frequency Multiplication Ratio
Output Swing
Output Duty Cycle Variation
Output Jitter
Lock Time
10
40
48/65
pF
48/65
N/A
V p-p
%
ps rms
μs
1.5
2
36
50
10 pF load
Input duty cycle = 50%
TRANSMIT SECTION
I/Q Input
Input Resistance
Input Capacitance
100
2
kΩ
pF
Single-ended
Single-ended
Differential Peak Input Voltage
Input Common-Mode Voltage
Baseband Filter 3 dB Bandwidth
TX Gain Control
500
1.2
4.0
550
1.4
mV pd
V
MHz
1.05
Maximum Gain
5
dB
dB
dB
dB
dB
μs
1 V p-p differential baseband input
Gain Control Range
Gain Control Resolution
Gain Control Accuracy
60
1/32
1.0
10
1
Average of LSB steps
Any 1 dB step
Any 10 dB step
Gain Settling Time
RF Specifications (High Band)
Carrier Frequency
POUT within 0.1 dB of final value
1710
2170
MHz
Ω
Output Impedance
50
Output Power (POUT
Output Noise Spectral Density
)
−8
dBm
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
TM1 signal 64 DPCH
40 MHz offset
80 MHz offset
95 MHz offset
190 MHz offset
−155
−161
−161
−163
−35
5
Carrier Leakage
FDD EVM
POUT = −8 dBm
POUT = −8 dBm
%
FDD ACLR
55
70
dB
dB
5 MHz, POUT = −8 dBm
10 MHz, POUT = −8 dBm
Rev. 0 | Page 4 of 36
ADF4602
Parameter
Min
Typ
Max
Unit
Test Conditions
RF Specifications (Low Band)
Carrier Frequency
Output Impedance
824
960
MHz
Ω
50
Output Power (POUT
)
−6
−158
−35
5
dBm
dBc/Hz
dBc
%
TM1 signal 64 DPCH
45 MHz offset
POUT = −6 dBm
Output Noise Spectral Density
Carrier Leakage
FDD EVM
POUT = −6 dBm
FDD ACLR
55
70
dB
dB
5 MHz, POUT = −6 dBm
10 MHz, POUT = −6 dBm
RECEIVE SECTION
Baseband I/Q Output
Output Common Mode Voltage
1.15
1.35
1.2
1.4
4
1.35
1.55
V
V
Mode 1
Mode 2
Differential Output Range
Output DC Offset
V p-p d
mV
mV
dB
°rms
dB
5
WCDMA HPF mode
GSM servo loop mode
100
0.3
1
Quadrature Gain Error
Quadrature Phase Error
In-Band Gain Ripple
0.7
0.2
Low-Pass Filter Rejection
WCDMA (Seventh Order)
30
45
84
110
14
31
55
80
12
47
90
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
@2.7 MHz
@3.5 MHz
@5.9 MHz
@10 MHz
@2.7 MHz
@3.5 MHz
@5.9 MHz
@10 MHz
@200 kHz
@400 kHz
@800 kHz
WCDMA (Fifth Order)
GSM
Differential Group Delay
WCDMA
GSM
250
200
ns
ns
1.92 MHz band
100 kHz band
Receiver Gain Control
Maximum Voltage Gain
Gain Control Range
Gain Control Resolution
Gain Control Step Error
102
90
1
1
2
dB
dB
dB
dB
dB
WCDMA mode
1 dB step
10 dB step
RF Specifications (High Band)
Input Frequency
Input Impedance
Input Return Loss
Noise Figure
1710
2170
MHz
Ω
dB
dB
50
−20
4.0
TX power of −8 dBm, spur-free
measurement2
Maximum LNA gain
Maximum Input Power3
Input IP3
−20
−2
dBm
dBm
dBm
Minimum LNA gain
−7
0
53
65
8
10 MHz and 20 MHz Offset, 59 dB gain
85 MHz and 190 MHz Offset, 59 dB gain
80 MHz offset
190 MHz offset
−60 dBm input
Input IP2
dBm
dBm
%
EVM
Rev. 0 | Page 5 of 36
ADF4602
Parameter
Min
Typ
Max
Unit
Test Conditions
RF Specifications (Low Band)
Input Frequency
Input Impedance
Input Return Loss
Noise Figure
824
960
MHz
Ω
dB
50
−20
4.0
dB
80 dB gain, TX power of −8 dBm
Maximum LNA gain
Minimum LNA gain
10 MHz and 20 MHz offset, 59 dB gain
45 MHz and 90 MHz offset, 59 dB gain
45 MHz offset
Maximum Input Power3
−20
−2
dBm
dBm
dBm
dBm
dBm
%
Input IP3
2
5
40
7
Input IP2
EVM
−60 dBm input
Synthesizer Section
Channel Resolution
Lock Time3
50
kHz
μs
200
DAC/GPO CONTROL
DAC1
Resolution
5
bits
V
mV
mV
nF
Output Range
Absolute Accuracy
Output LSB Step
Output Capacitive Load
Output Current
Output Impedance
DAC2
Resolution
Output Range
DNL
2.3
−10
0
3.15
VDD > 3.15 V
Any code, VDD > 3.2 V
50
25
1
+10
mA
Ω
1
6
bits
V
LSB
LSB
nF
2.85
0.5
1.0
No load
No load
INL
Output Capacitive Load
Output Current
Output Impedance
GPO1 to GPO4
Output Current
1
+5
−5
mA
Ω
5
1
2
10
mA
mA
V
V
μs
GPO1, GPO2, GPO3
GPO4
Maximum output current
Maximum output current
5 pF load
Output High Voltage
Output Low Voltage
Switching Time
2.6
0.2
LOGIC INPUTS
Input High Voltage, VINH
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS (SDATA)
Output High Voltage, VOH
Output Low Voltage, VOL
CLKOUT Rise/Fall
1.2
1.2
2.1
3.3
0.6
1
V
V
V
μA
pF
1.8 V readback mode4
2.8 V readback mode4
10
VX − 0.45
V
V
ns
pF
°C
VX = VINT or VSUP8, IOH = 500 μA
IOL = 500 μA
0.45
5
10
85
CLKOUT Load
TEMPERATURE RANGE (TA)
0
Rev. 0 | Page 6 of 36
ADF4602
Parameter
POWER SUPPLIES
Voltage Supply
VDD
Min
Typ
Max
Unit
Test Conditions
3.1
3.3
2.6
3.6
V
V
Main supply input
Output from internal LDO1, 10 mA rating,
supply for RX VCO
VSUP1
VSUP2
2.8
V
Output from Internal LDO2, 30 mA rating,
supply for RX baseband and RX down-
converter
VSUP3
VSUP4
VSUP5
1.9
2.6
2.8
V
V
V
Output from internal LDO3, 10 mA rating,
supply for RX LNAs
Output from internal LDO4, 10 mA rating,
supply for TX VCO
Output from internal LDO5, 100 mA rating,
supply for TX modulator, TX baseband, PA
control DACs
VSUP6
VSUP7
VSUP8
VINT
1.9
1.9
2.8
1.8
V
V
V
V
Supply input for RX synthesizer,
connect to VSUP3
Supply input for TX synthesizer,
connect to VSUP3
Supply input for reference section,
connect to VSUP2
Supply input for serial interface control
logic
1.6
2.0
CURRENT CONSUMPTION
Transmit Current Consumption
−8 dBm Output Level
−28 dBm Output Level
Receive Current Consumption
VDD = 3.6 V, output is matched into 50 Ω
FRF = 2170 MHz
FRF = 2170 MHz
100
50
50
mA
mA
mA
1 The reference frequency should be dc coupled to the REFIN pin. It is ac-coupled internally.
2 The noise figure measurement does not include spurious due to harmonics of the 26 MHz reference frequency. Spurs appear at integer multiples of the reference
frequency (every 26 MHz), degrading the receive sensitivity by about 6 dB.
3 Guaranteed by design, not production tested.
4 Bit sif_vsup8 in Register 2 controls whether 1.8 V readback mode or 2.8 V readback mode is selected. See the Serial Port Interface (SPI) section for more details.
Rev. 0 | Page 7 of 36
ADF4602
TIMING CHARACTERISTICS
VDD = 3.1 V to 3.6 V, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested.
Table 2.
Parameter
Limit at TMIN to TMAX
Unit
Test Conditions/Comments
SEN high to write time
SEN to SCLK setup time
SDATA to SCLK setup time
SDATA to SCLK hold time
SCLK high duration
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
62
10
10
10
31
31
10
20
20
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
SCLK low duration
SEN to SCLK hold time
SEN to SDATA valid delay
SCLK to SDATA valid delay
SEN to SDATA disabled delay
WRITE
t5 t6
SCLK
SDATA
SEN
t3 t4
W[24]
W[25]
t2
W[1]
W[0]
t7
t1
Figure 2. Serial Interface Write Diagram
READ REQUEST
READ
SCLK
SDATA
SEN
t9
R[24]
Q[25]
Q[24]
Q[1]
Q[0]
R[25]
R[1]
R[0]
t10
t8
ADF4602
selected device
DRIVES SDATA
3 or more
3 OR MORE
SCLK PERIODS
DBB eleases
HOST RELEASES
SDATA
Figure 3. Serial Interface Read/Write Diagram
Rev. 0 | Page 8 of 36
ADF4602
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VDD to GND
VSUP1, VSUP2 to GND
VSUP4, VSUP5, VSUP6, VSUP7,
VSUP8, VSUP9 to GND
VSUP3 to GND
−0.3 V to +4 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
VINT to GND
Analog I/O Voltage to GND
Digital I/O Voltage to GND
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Maximum Junction Temperature
LFCSP θJA Thermal Impedance
Reflow Soldering
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
0°C to +85°C
−65°C to +125°C
150°C
ESD CAUTION
32°C/W
Peak Temperature
Time at Peak Temperature
240°C
40 sec
Rev. 0 | Page 9 of 36
ADF4602
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GPO3
VSUP1
1
2
3
4
5
6
7
8
9
30 DAC1
29 DAC2
VSUP3
28 VSUP5
27 TXRFGND
26 TXHBRF
25 TXRFGND
24 TXLBRF
23 TXBBQB
22 TXBBQ
21 VSUP4
RXLBRF
NC
ADF4602
TOP VIEW
(Not to Scale)
RXHB2RF
RXHB1RF
RXBBI
RXBBIB
RXBBQ 10
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PADDLE MUST BE CONNECTED TO GROUND
FOR CORRECT CHIP OPERATION. IT PROVIDES BOTHA
THERMAL AND ELECTRICAL CONNECTION TO THE PCB.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1
2
3
4
GPO3
General Purpose Output 3. Digital output. This is used for external switch or PA control.
Output from LDO 1. Supply for receive VCO. Nominal value of 2.6 V. 100 nF decoupling to ground is required.
Output from LDO 3. Supply for receive LNA. Nominal value of 1.9 V. 100 nF decoupling to ground is required.
Receive Low Band LNA Input.
VSUP11
VSUP31
RXLBRF
NC
5
No Connect. Do not connect to this pin.
6
7
8
RXHB2RF
RXHB1RF
RXBBI
Receive Second High Band LNA Input. Should be used for Band 2.
Receive First High Band LNA Input. Should be used for Band 1.
Receive Baseband I Output.
9
RXBBIB
RXBBQ
RXBBQB
VSUP21
Complementary Receive Baseband I Output.
Receive Baseband Q Output.
Complementary Receive Baseband Q Output.
Output from LDO 2. Supply for receive downconverter and baseband. Nominal value of 2.8 V. 100 nF
decoupling to ground is required.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VINT
SDATA
SCLK
SEN
NC
VSUP71
TXBBI
TXBBIB
VSUP41
TXBBQ
TXBBQB
TXLBRF
TXRFGND
TXHBRF
TXRFGND
VSUP51
Serial Port Supply Input. 1.8 V should be applied to this pin.
Serial Port Data Pin. This can be an input or output.
Serial Clock Input.
Serial Port Enable Input.
No Connect. Do not connect to this pin.
Transmit Synthesizer Supply Input. Connect to VSUP3 and decouple with 100 nF to ground.
Transmit Baseband I Input.
Complementary TX Baseband I Input.
Output from LDO4. Supply for transmit VCO. Nominal value of 2.8 V. 100 nF decoupling to GND is required.
Transmit Baseband Q Input.
ComplementaryTX Baseband Q Input.
Low Band Transmit RF Output. This can output in the range of 824 MHz to 960 MHz.
Transmit RF Ground. Connect this pin to ground.
High Band Transmit RF Output. This can output in the range of 1710 MHz to 2170 MHz.
Transmit RF Ground. Connect this pin to ground.
Output from LDO 5. Supply for transmit modulator, baseband, power detector, and DACs. Nominal value of
2.8 V. 100 nF decoupling to ground is required.
29
30
DAC2
DAC1
Output from DAC2.
Output from DAC1.
Rev. 0 | Page 10 of 36
ADF4602
Pin No. Mnemonic
Function
31
32
33
34
35
36
37
38
39
40
VDD
Main Supply Input.
Digital Output. This is used for switch or PA control.
Chip Clock Output.
Reference Clock Supply Input. Connect to VSUP2, and decouple to ground with 100 nF.
Reference Clock Output.
Reference Clock Input. The reference is ac-coupled internally.
No Connect. Do not connect to this pin.
Receive Synthesizer Supply Input. Connect to VSUP3 and decouple to ground with 100 nF.
Digital Output. This is used for switch or PA control.
Digital Output. This is used for switch or PA control.
Exposed Paddle Under Chip. This must be connected to ground for correct chip operation. It provides both a
thermal and electrical connection to the PCB.
GPO4
CHIPCLK
VSUP81
REFCLK
REFIN
NC
VSUP61
GPO1
GPO2
EPAD
1Y5V capacitors are not recommended for use with these pins. X7R, X5R, C0G or a similar type of capacitor should be used.
Rev. 0 | Page 11 of 36
ADF4602
TYPICAL PERFORMANCE CHARACTERISTICS
CF
881.5 MHz SR
15 ksps
Ref Lvl
dBm
Code Pwr Relative Chan Code
CPICH Slot Chan Slot
0
0
6
0
0
A
-7
LN
dB
–30
-21
-28
-35
-42
-49
-56
-63
-70
+5MHz
–5MHz
+10MHz
–10MHz
–35
–40
–45
–50
START: CH
Ref Lvl
0
64 CH/DIV
STOP: CH 511
881.5 MHz SR 15 ksps
CF
Result Summary
CPICH Slot
Chan Code
Chan Slot
0
0
6
dBm
0
RESULT SUMMARY
–55
–60
–65
–70
³
GLOBAL RESULTS
Total PWR
Chip Rate Err
IQ Offset
Composite EVM
CPICH Slot Number
CHANNEL RESULTS
Symb Rate
³
³
³
³
³
³
³
³
³
³
³
-4.57 dBm
1.04 ppm
Carr Freq Err
-92.42 Hz
22.62
0.36 %
B
s
Trg to Frame
IQ Imbalance
Pk Code Dom Err
LN
0.79
2.04
0
%
%
rms
-49.96 dB rms
15 ksps)
(
15 ksps
0
Timing Offset
Chan Slot Number
No. of Pilot Bits
Chan Pow abs.
Symbol EVM
0
0
0
Chips
Channel Code
Modulation Type
Chan Pow rel.
Symbol EVM
QPSK
0.00 dB
0.74 rms
–14
–12
–10
–8
–6
–4
-14.60 dBm
1.21 Pk
%
%
OUTPUT POWER (dBm/3.84MHz)
Figure 5. UMTS Band 5 Transmit EVM, Test Model 1, 64 DPCH, 2% EVM
Figure 8. TXHBRF Transmit ACLR vs. Output Power, Test Model 1 Signal,
10.54 dB PAR, 217 MHz
Code Power Relative
CF 2.1399994 GH
SR 240 ksps
Chan Code
0
CPICH Slot
0
Chan Slot 0
–30
-7
+5MHz
–5MHz
+10MHz
A
-14
-21
-28
-35
-42
-49
-56
-63
Ref
3.90
dBm
Att*
–35
–10MHz
–40
0
dB
1
VIEW
–45
–50
–55
–60
–65
–70
3DB
Start Ch
0
64 Ch/
Stop Ch 511
Result Summary
SR 240 ksps
Chan Code
Chan Slot
5
0
CF 2.1399994 GH
CPICH Slot
0
GLOBAL RESULTS FOR FRAME
Total Power
0:
-8.03 dBm
0.95 ppm
Carrier Freq Error
Trigger to Frame
IQ Imbalance
65.98 Hz
9.642977 ms
0.23
B
Chip Rate Error
IQ Offset
Ref
3.90
dBm
1.83
2.54
0
%
%
%
Composite EVM
CPICH Slot No
Pk CDE (15 ksps)
No of Active Chan
-50.12 dB
44
Att*
0
dB
RHO
0.99936
CHANNEL RESULTS
Symbol Rate
240.00 ksps
Timing Offset
Channel Slot No
Modulation Type
Channel Power Abs
Symbol EVM
0
0
Chips
Channel Code
5
0
1
No of Pilot Bits
Channel Power Rel
Symbol EVM
16QAM
-19.05 dBm
CLRWR
-0.04 dB
–25
–20
–15
–10
–5
0
3DB
2.43
%
rms
7.02 % Pk
OUTPUT POWER (dBm/3.84MHz)
Figure 6. UMTS Band 1 Transmit EVM, Test Model 5, 2.5% EVM
Figure 9. TXLBRF Transmit ACLR vs. Output Power, Test Model 1 Signal,
10.54 dB PAR, 881 MHz
*RBW 30kHz
*VBW 300kHz
20
REF –12.7dBm
*ATT 0dB
*SWT 100ms
DUT 1
DUT 4
DUT 6
DUT 8
DUT 10
DUT 2
DUT 5
DUT 7
DUT 9
DUT 3
18
16
14
12
10
8
CH PWR
–8.08dBm
POS –12.698dBm
–20
–30
ACP LOW –57.05dBm
ACP UP –57.09dBm
ALT1 LOW –70.92dBm
ALT1 UP
–71.41dBm
–40
–50
–60
–70
30dB DYNAMIC RANGE <6% EVM
6
–80
–90
4
2
–100
–110
0
–35
–30
–25
–20
–15
–10
–5
0
5
TXPWR_SET (dBm)
CENTER 2.14GHz
2.55MHz/DIV
SPAN 25.5MHz
Figure 7.Transmit EVM vs. TXPWR_SET (dBm), Measured Across 10 DUTS,
Four Calibration Points Applied
Figure 10. TXHBR Transmit ACLR, 2140 MHz
Rev. 0 | Page 12 of 36
ADF4602
*RBW 30kHz
*VBW 300kHz
REF –10.9dBm *ATT 5dB *SWT 100ms
MARKER 1 (T1)
–23.01dBm
880.877403846MHz
CH PWR –4.39dBm
ACP LOW –60.63dBm
ACP UP –58.52dBm
ALT1 LOW –72.07dBm
–54
–56
0°C 5MHz HIGH
25°C 5MHZ HIGH
85°C 5MHz HIGH
0°C 5MHz LOW
25°C 5MHz LOW
85°C 5MHz LOW
POS –10.895dBm
–20
–30
ALT1 UP
–72.13dBm
–58
–60
–62
–64
–66
–40
–50
–60
–70
–80
–90
–100
–110
865
870
875
880
885
890
895
FREQUENCY (MHz)
CENTER 881MHz
2.55MHz/DIV
SPAN 25.5MHz
Figure 11. TXLBRF Transmit ACLR, 881 MHz
Figure 14. Transmit ACLR vs. Frequency and Temperature (Band 5),
Transmit Output Power = −7 dBm
5
0
–51
–53
–55
–57
0°C 5MHz HIGH
25°C 5MHZ HIGH
85°C 5MHz HIGH
0°C 5MHz LOW
25°C 5MHz LOW
85°C 5MHz LOW
–5
–10
–15
–20
–25
–30
–35
–40
–59
–61
–63
–65
2110
0.1
1
10
FREQUENCY (MHz)
100
2120
2130
2140
2150
2160
2170
FREQUENCY (MHz)
Figure 12. Transmit ACLR vs. Frequency and Temperature (Band 1),
Transmit Output Power = −8 dBm
Figure 15. Transmit Baseband Filter Response
–70
–51
–80
–90
0°C 5MHz HIGH
25°C 5MHZ HIGH
85°C 5MHz HIGH
0°C 5MHz LOW
25°C 5MHz LOW
85°C 5MHz LOW
–53
–55
–57
–100
–110
–120
–130
–140
–150
–160
–170
–59
–61
–63
–65
1930
1k
10k
100k
1M
10M
100M
1940
1950
1960
1970
1980
1990
OFFSET FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 16. Transmit Synthesizer Phase Noise
Figure 13. Transmit ACLR vs. Frequency and Temperature (Band 2),
Transmit Output Power = −8 dBm
Rev. 0 | Page 13 of 36
ADF4602
0.14
16
MIXSTEP = 10
LNASTEP = 6
GAINCAL = 8
0.12
14
12
10
8
0.10
0.08
0.06
0.04
0.02
0
6
4
2
0
–34 –32 –30 –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4
20
30
40
50
60
70
80
90
OUTPUT POWER (dBm/3.84MHz)
RECEIVE GAIN SETTING (dB)
Figure 17. Current Consumption vs. Transmit Output Power; Frequency =
2170 MHz, VDD = 3.3 V, Test Model 5 Signal, Receiver Disabled
Figure 20. Receive EVM vs. Gain; 2.84 MHz QPSK Modulated Input Signal,
WCDMA Receive Baseband Filter
10
0
2.0
MIXSTEP = 6
LNASTEP = 10
GAINCAL = 8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.01
0.1
FREQUENCY (MHz)
1
10
20
30
40
50
60
70
80
90
100
RECEIVE GAIN SETTING (dB)
Figure 18. Receive WCDMA Baseband Filter Response
Figure 21. Receive Gain Step Error vs. Gain Setting, 1 dB Steps,
Measurement was taken by injecting known signal level and measuring the
gain through the device. The gain was then stepped through all settings in
1 dB steps, and the gain step change measured in each case.
25
10
0
MIXSTEP = 6
LNASTEP = 10
GAINCAL = 8
23
20
18
15
13
10
8
–10
–20
–30
–40
–50
–60
–70
–80
5
3
–90
0
40
–100
50
60
70
80
90
10
100
1000
RECEIVE GAIN SETTING (dB)
FREQUENCY (kHz)
Figure 22. Receiver Noise Figure vs. Gain. Rx Frequency = 1955 MHz
Figure 19. Receive GSM Baseband Filter Response
Rev. 0 | Page 14 of 36
ADF4602
20
18
16
14
12
10
8
–100
–102
–104
–106
–108
–110
–112
–114
–116
–118
–120
GAIN = 80dB
GAIN = 80dB
25°C
0°C
85°C
TS25.104 LIMIT
6
4
2
0
1920
1918
1928
1938
1948
1958
1968
1978
1930
1940
1950
1960
1970
1980
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23. HB1 Receive Noise Figure vs. Frequency
Figure 26. Receive Sensitivity vs. Frequency (See the Receive Sensitivity
Section for More Details)
16
2
GAIN = 80dB
25°C
25°C
0°C
0
14
12
10
8
0°C
85°C
85°C
–2
–4
–6
–8
–10
–12
6
4
2
0
–14
–16
–18
1850
1860
1870
1880
1890
1900
1910
0
10
20
30
40
50
60
70
80
90 100 110
FREQUENCY (MHz)
RECEIVE GAIN SETTING (dB)
Figure 24. HB2 Receive Noise Figure vs. Frequency
Figure 27. HB1 Receive IP3, 10 MHz + 19.8 MHz vs. Gain Setting
10
9
8
7
6
5
4
3
2
1
0
8
GAIN = 80dB
25°C
0°C
85°C
25°C
0°C
85°C
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
0
10
20
30
40
50
60
70
80
90 100 110
822
827
832
837
842
847
RECEIVE GAIN SETTING (dB)
FREQUENCY (MHz)
Figure 25. LB Receive Noise Figure vs. Frequency
Figure 28. HB1 Receive IP3, 85 MHz + 190 MHz vs. Gain Setting
Rev. 0 | Page 15 of 36
ADF4602
16
14
12
10
8
110
105
100
95
25°C
0°C
85°C
25°C
0°C
85°C
90
6
4
2
0
85
80
75
70
65
–2
–4
–6
60
55
50
–8
–10
–12
0
10
20
30
40
50
60
70
80
90 100 110
0
10
20
30
40
50
60
70
80
90 100 110
RECEIVE GAIN SETTING (dB)
RECEIVE GAIN SETTING (dB)
Figure 29. HB1 Receive IP2, 190 MHz vs. Gain Setting
Figure 32. LB Receive IP3, 10 MHz + 19.8 MHz vs. Gain Setting
8
6
4
2
16
25°C
0°C
85°C
25°C
0°C
85°C
14
12
10
8
0
–2
–4
–6
–8
6
4
2
0
–2
–4
–6
–10
–12
–14
–8
–10
0
10
20
30
40
50
60
70
80
90 100 110
0
10
20
30
40
50
60
70
80
90 100 110
RECEIVE GAIN SETTING (dB)
RECEIVE GAIN SETTING (dB)
Figure 30. HB2 Receive IP3, 80 MHz + 40 MHz vs. Gain Setting
Figure 33. LB Receive IP3, 45 MHz + 22.5 MHz vs. Gain Setting
100
100
25°C
0°C
85°C
25°C
0°C
85°C
90
90
80
80
70
60
50
40
70
60
50
40
30
0
10
20
30
40
50
60
70
80
90 100 110
0
10
20
30
40
50
60
70
80
90 100 110
RECEIVE GAIN SETTING (dB)
RECEIVE GAIN SETTING (dB)
Figure 31. HB2 Receive IP2, 80 MHz vs. Gain Setting
Figure 34. LB Receive IP2, 45 MHz vs. Gain Setting
Rev. 0 | Page 16 of 36
ADF4602
THEORY OF OPERATION
TRANSMITTER DESCRIPTION
TESTI, SWAP_I
TXBBI
TXBBIB
LPF
INTEGRATED
BALUN
LB ONLY
DIVIDER
÷2
÷2
PA
Σ
TX
OUTPUT
DIVIDER AND
QUAD GEN
–90 DEGREES
TXBs
TXBBQ
TXBBQB
LPF
TESTQ, SWAP_Q
GAIN CONTROL
TXPWR_SET[11:0]
Figure 35. Transmitter Block Diagram
VOLTS
The ADF4602 contains a highly innovative low noise variable
gain direct conversion transmitter architecture, that removes the
need for external transmit SAW filters. The direct conversion
architecture significantly reduces the risk of transmit harmonics
across all bands due to the simplified nature of the frequency
plan. See Figure 35 for a block diagram.
I OR Q
I/Q Baseband
The baseband interface for the I and Q channels is a differential,
dc-coupled input, supporting a wide range of input common-
mode voltages (VCM). The allowable input common-mode range is
1.05 V to 1.4 V. The maximum signal swing allowed is 550 mV
peak differential. This corresponds to a 1.1 V peak-to-peak
differential on either the I or Q channel. Figure 36 shows a
IB OR QB
PEAK V DIF
V
CM
TIME
Figure 36. Transmit Baseband Input Signals
graphical definition of peak differential voltage and VCM
.
The baseband input signals pass through a second order
Butterworth filter prior to the quadrature modulator. The cutoff
frequency is 4 MHz. This gives some rejection of the DAC
images. The filter also helps to suppress any spurious signals
that might be coupled to the baseband terminals on
the PCB.
For ease of PCB routing between the ADF4602 and the transmit
DAC, the I and Q differential inputs can be internally swapped.
For user test purposes, the I and Q inputs can also be internally
shorted together and a dc offset applied. This produces a large
carrier at the RF output, which is useful for signal path integrity
testing.
Rev. 0 | Page 17 of 36
ADF4602
I/Q Modulator
user because most power amplifiers (PAs) are singled-ended.
This situation would normally require additional external matching
components or a differential to single-ended SAW filter structure.
With the ADF4602, the SAW filter is not necessary, and the
required low loss balun is fully integrated, converting the diffe-
rential internal signals to a single-ended 50 Ω output, thus allowing
easy interfacing to the PA.
The I/Q modulator converts the transmit baseband input signals
to RF. Calibration techniques are used to maintain accurate IQ
balance and phase across frequency and environmental conditions,
thus ensuring that 3GPP carrier leakage and EVM and ACLR
requirements are met with good margin under all conditions.
The on-chip calibrations are carried out during the transmit
PLL lock time specified and are self-contained, requiring no
additional input from the user.
The high band output is available at the TXHBRF pin, and
the low band output is available at the TXLBRF pin. These are
directly connected to a 50 ꢀ load, if necessary, and do not
require ac-coupling.
The modulator has an 80 dB gain control range, programmable
in 1/32 of a decibel step. The 12-bit word txpwr_set[11:0] in
Register 28 controls the transmit output power. The setting is
referenced to a full-scale (500 mV peak differential) sine wave
signal applied to the transmit baseband inputs. To calculate the
output power when a WCDMA modulated signal with a certain
peak-to-average ratio is applied, Equation 1 should be used.
DACS
The ADF4602 integrates two DACs that are designed to interface
to an external PA to control reference or bias nodes within the
PA. If this function is not required, the DACs are used for any
general purpose or powered down if not required.
Output Power (dBm/3.84 MHz) = txpwr(dBm) − PAR(dB) (1)
DAC1 is a 5-bit voltage output DAC. The output range is from
2.3 V to 3.15 V (for VDD > 3.15 V). The DAC1 output stage is
supplied directly from VDD, with the capability to supply 10
mA of current to within 50 mV of VDD. For high accuracy, the
DAC reference is supplied from LDO5, which is internally
trimmed to 25 mV accuracy. The DAC1 output is set by the
PADAC1[4:0] word.
where txpwr(dBm) is the txpwr_set[11:0] value converted to
dBm, and PAR is the peak-to-average ratio of the WCDMA
signal. For example, if an output power of −8 dBm is required
for a WCDMA signal with a peak-to-average ratio of 10 dB
txpwr(dBm) = −8 dBm + 10 dB = +2 dBm
The current consumption of the modulator scales with output
power. When the TX power is backed off from maximum, the
transceiver benefits from lower power dissipation.
DAC2 is a 6-bit voltage output DAC with a range from 0 V to
2.8 V. LDO5 supplies both the reference voltage and full-scale
output voltage for DAC2. The output voltage is set by the
padac2_ow[5:0] word. The dacgpo_owen bit must also be set
high if control of DAC2 is required.
VCO Output
The TX VCO output is fed to a tuned buffer stage and then to
the quadrature generation circuitry. The tuned buffer ensures
that minimum current and LO related noise is generated in the
VCO transport. This action is transparent to the user. The
quadrature generator creates the highly accurate phased signals
required to drive the modulator and also acts as a divide-by-2.
In low band, an additional divide-by-2 is used in the VCO
transport path, which is bypassed in high band. This is done to
minimize the VCO tuning range required to cover all the bands.
Both DACS are powered down by writing the code, 0x0, to the
respective control register.
GENERAL PURPOSE OUTPUTS
Four general-purpose outputs (GPOs) are provided on the
ADF4602. These are used to control PA bias modes or, more
commonly, the GPOs are used to control external RF front-end
switches in the transmit/receive path. The GPOs are simple 3 V
digital output drivers. GPO1 to GPO3 are capable of supplying
a maximum current of 2 mA, whereas GPO4 can supply up to
10 mA.
The phase accuracy of the signals is important in ensuring good
modulation quality and accurate output power. An on-chip
calibration ensures that the phased signals are exactly 90° out of
phase. This calibration runs each time the frequency is changed
or if the txpwr_set[11:0] word is written to. If the temperature
of the device changes, this calibration should be updated. To run
the calibration, the user should simply write to the txpwr_set[11:0]
word for each five degree change in temperature, or update the
value regularly (every few seconds) between WCDMA frames
or timeslots. This ensures that good EVM and accurate output
power are maintained as the temperature of the device changes.
For operation of the GPOs, Bit dacgpo_owen must be set to 1.
The GPOs are then controlled via the gpo_ow[3:0] word.
RECEIVER DESCRIPTION
The ADF4602 contains a fully integrated direct conversion
receiver designed for multiband WCDMA femtocell applications.
High performance, low power consumption, and minimal external
components are the key features of the design. Figure 37 shows
a block diagram of the receiver, which consists of three LNA
blocks for multiband operation, high linearity I/Q mixers,
advanced baseband channel filtering, and a DC offset
compensation circuit.
TX Output Baluns
The baseband input, modulator, and all associated circuitry are
fully differential to maintain high signal integrity and noise
immunity. However, a differential output is not optimal for the
Rev. 0 | Page 18 of 36
ADF4602
MIXER
LNA
TRANSCONDUCTANCE
ACTIVE FILTER CHANGES
VGA
0dB TO 18dB
3 × 6dB STEPS
18dB TO 30dB (WCDMA)
27dB TO 39dB (CDMA)
2 × 6dB STEPS
0dB TO 18dB
3 × 6dB STEPS
0dB TO 18dB
3 × 6dB STEPS
–6dB TO +18dB
24 × 1dB STEPS
RxEN[1:0]
RXBBI
RXBBIB
RXHB2RF
RXHB1RF
LPF
LPF
LPF
BPF
HIGH BAND LNA 2
DAC
DAC
ADC
ADC
PROGRAMMABLE OFFSET
CONTROL
÷2 OR
÷4
BPF
HIGH BAND LNA 1
RXLBRF
RXBBQ
BPF
RXBBQB
LPF
LPF
LPF
LOW BAND LNA
VCMSEL
GAIN CONTROL
RxGAIN[6:0]
RXBW_TOGGLE
Figure 37. Receiver Block Diagram
Quadrature drive is provided to the mixers from the receiver
synthesizer section by the VCO transport system, which includes
a programmable divider, so that the same VCO is used for both
high and low bands. Excellent 90° quadrature phase and
amplitude match are achieved by careful design and layout of
the mixers and VCO transport circuits.
LNAs
The ADF4602 contains three tunable RF front ends suitable for
all major 3GPP frequency bands. Two are suitable for high band
operation in the region 1700 MHz to 2170 MHz. One is suitable
for operation from 824 MHz to 960 MHz. Thus, the three
integrated LNAs offer the designer the opportunity to create
multiband and regional specific variants with no additional
components.
Baseband Section
The ADF4602 baseband section is a distributed gain and filter
function designed to provide a maximum of 54 dB gain with
60 dB gain control range. Through careful design, pass band
ripple, group delay, signal loss, and power consumption are
kept to a minimum. Filter calibration is performed during the
manufacturing process, resulting in a high degree of accuracy
and ease of use.
LNA power control and internal band switching is fully
controlled by the serial interface.
The ADF4602 LNAs are designed for 50 Ω single-ended inputs,
thus further simplifying the front-end design and providing
easy matching with minimal components. Typically, a two-
component match is required: a series and shunt inductor.
Within the LNA, the signal is converted to a differential path
for signal processing in subsequent blocks within the receive
signal chain.
Three baseband filters are available on the ADF4602, as shown
in Table 5. Bits rxbw_toggle[2:0] are used to select the mode of
operation. The seventh order WCDMA filter with 1.92 MHz
cutoff ensures that good attenuation of the adjacent channel should
be used to meet blocking/adjacent channel selection specifications
in femtocell applications. The GSM filter has a 100 kHz cut-off
and is intended for use as a monitoring receiver in a home base
station. The fifth order WCDMA filter provides less attenuation
of the adjacent channel, so it should not be used in femtocell
applications.
Interstage RF filtering is fully integrated, ensuring that external
out-of-band blockers are suitably attenuated prior to the mixer
stages. The LNA characteristic is designed to provide additional
filtering at the transmitter frequency offset.
The LNAs are enabled by programming bits rxbs[1:0] in
Register 1. LNA input HB1 should be used for UMTS Band 1
operation, and HB2 should be used for UMTS Band 2 operation.
The I and Q channels can be internally swapped, thus allowing
optimum PCB routing between radio and analog baseband.
This is achieved using the swapi and swapq bits.
Mixers
High linearity quadrature mixer circuits are used to convert the
RF signal to baseband in-phase and quadrature components.
Although not shown in Figure 37, two mixer sections exist: one
optimized for the high band LNA outputs and one optimized
for the low band. The high band and low band mixer outputs
are combined and then driven directly into the first stage of the
baseband low-pass filter, which also acts to reduce the level of
the largest blocking signals, prior to baseband amplification.
Table 5. Receive Baseband Filter Modes
Mode
Filter Cutoff Frequency (fC)
Seventh Order WCDMA
Fifth Order WCDMA
GSM
1.92 MHz
1.92 MHz
100 kHz
Rev. 0 | Page 19 of 36
ADF4602
120
110
100
90
The receive baseband outputs have a programmable common
mode voltage of 1.2 V or 1.4 V, selectable via the vcmsel bit in
Register 15.
MIXSTEP = 10
LNASTEP = 6
GAINCAL = 8
Gain Control
80
70
60
50
Gain control is distributed throughout the receive signal chain
as shown in Figure 39. The RF front end contains 30 dB of control
range: 18 dB in the LNA and 12 dB in the mixer transconductance
stage. The two baseband active filter stages each provide 18 dB
of gain control range in 6 dB steps. Filter characteristics (ripple
and group delay) are best conserved if the active filter stages
have equal gain. This results in a total of 36 dB gain control in
4× 12 dB steps for the filter stage. The variable gain amplifier
(VGA) implements 24 dB of gain controllable in 1 dB steps. The
base gain of the mixer is 18 dB, and the base gain of the VGA is
−6 dB. This gives a total of 102 dB gain with 90 dB of gain
control range.
40
30
20
10
0
RF GAIN
BASEBAND GAIN
CHIP GAIN
–10
0
10 20 30 40 50 60 70 80 90 100 110 120
REQUESTED Rx GAIN (dB)
Figure 38. Gain Distribution Between RF and Baseband Blocks for Default
Setting
50
MIXSTEP = 10
LNASTEP = 6
GAINCAL = 8
45
40
35
30
25
20
15
10
5
LNA GAIN
The base gain of the mixer stage is 18 dB in WCDMA mode
and 27 dB in GSM mode.
MIXER GAIN
FILTER GAIN
VGA GAIN
Table 6. Receive Gain Control in WCDMA mode
Stage
Gain Control
Control Steps
3 × 6 dB steps
2 × 6 dB steps
LNA
Mixer
0 dB to +18 dB
+18 dB to +30 dB (WCDMA)
+27 dB to +39 dB (GSM)
Filter
VGA
0 dB to +36 dB
−6 dB to +18 dB
3 × 12 dB steps
24 × 1 dB steps
0
–5
–10
To simplify programming and to ensure optimum receiver
performance and dynamic range, the user simply programs the
total desired receive gain in dB via the rx_gain[6:0] bits in
Register 11. The ADF4602 then decodes the gain setting and
automatically distributes the gain between the various blocks. To
allow some flexibility, predefined user inputs control the gain
threshold points at which the LNA and mixer gain steps occur.
0
10 20 30 40 50 60 70 80 90 100 110 120
REQUESTED Rx GAIN (dB)
Figure 39. More Detailed Gain Distribution Profile
In addition, a gain calibration setting in Register 15 (gaincal[4:0]) is
used to account for losses in the RF front end.
The total gain in the ADF4602 is given by
Bit settings mixstep[3:0] and lnastep[3:0] control the mixer and
LNA gain threshold steps, respectively. An Excel spreadsheet
detailing the receive gain decode system is available from
Analog Devices, Inc., on request. Figure 38 shows an example
gain distribution profile.
ReceiveGain = rxgain[6:0] − gaincal[4:0] + X
(2)
where X = 8 in WCDMA filter mode, and X = 17 in GSM filter
mode. Rxgain[6:0] is the receive gain programmed in Register
11. Gaincal[4:0] is the gain calibration setting in Register 15,
and is calculated using the following formula:
gaincal[4:0] = 8 − front_end_losses
(3)
where front_end_losses is the loss in the receive path due to
duplexers/switches. This is useful for referencing the
programmed gain to the antenna and accounting for any losses
in the path.
For example, if the total receive front-end loss is 2 dB, the user
should program gaincal[4:0] to 6 dB. If the user then requestes
80 dB of gain by programming rxgain[6:0] to 80 dB, the
ADF4602 uses Equation 4 to give
ReceiveGain = 80 − 6 + 8 = 82 dB
(4)
82 dB is the receive gain used internally by the ADF4602.
Rev. 0 | Page 20 of 36
ADF4602
RX
TX MOD
TX BB
PWR DET
DACs
REF PATH
REF OP
BASEBAND
AND
DC Offset Compensation
SERIAL
INTERFACE
(SER INT
RX VCO
MIXERS RX LNAs
TX VCO
RX PLL
TX PLL
READ)
Due to the very high proportion of the total system gain assigned
to the analog baseband function, compensating for dc offsets is
an inherent part of any direct conversion solution. DC offsets
are characterized as falling into two categories: static or slow
varying and time varying
1.8V
2.8V
LDO
1
LDO
2
LDO
3
LDO
4
LDO
5
VINT
VBAT
VSUP1
C1
VSUP2
C2
VSUP3
VSUP4
C4
VSUP5
C5
VSUP6
VSUP7
VSUP8
DIGITAL 1.8V
SUPPLY
ANALOG BB
OR VSUP2
1.9V
C6
The ADF4602 architecture has been designed to reduce the
amount of time varying dc offsets. The device also includes a dc
offset control system. The control system consists of ADCs at
the baseband output to digitize dc offsets: a digital signal
processing block where the characteristics of the loop are
programmed for customization of the loops transfer function,
and trim DACs that are used to introduce the error term back
into the signal path. The offset control transfer function can
either be programmed to act as a servo loop that is automatically
triggered by a gain change or as a high-pass filter (HPF) with an
automatic fast settling mode that is also triggered by a gain
change. Parameters of the servo loop, high-pass filter, and fast
settling mode are set by the initial ADF4602 programming. In
operation, the dc offset control system is fully automatic and
does not require any external programming. Recommended
default programming conditions for the dc offset compensation
loop are shown in the Register Description section.
C3
C7
Figure 40. Power Management Block
VINT supplies the serial interface enabling register data
preservation with minimum current consumption during
power-down. This should be supplied with 1.8 V externally.
The five LDOs are individually powered up/down via bits
ldoen[4:0] in Register 1. Table 7 summarizes the supply strategy.
Note that the reference path (VSUP8) supply is supplied from
an external source or the internal VSUP2. The external supply
option may be convenient so that the entire reference path can
be shut down by collapsing a single supply.
VSUP8 can also be programmed to supply the voltage used for
serial interface readback. See the Serial Port Interface (SPI)
section for more information.
POWER MANAGEMENT
Table 7. Power Management Strategy
Pin
Connection
Usage
Volts
The ADF4602 contains integrated power management
requiring two external power supplies: 3.3 V VDD and 1.8 V
VINT. Figure 40 shows a block diagram.
VINT
External
Serial interface control
logic
Main device supply,
DAC1
Receive VCO
Receive baseband and
down-converter
Receive LNAs
Transmit VCO
Transmit baseband,
modulator, DAC2, and
GPOs
Receive synthesizer
Transmit synthesizer
Reference path,
1.8 V
VDD
External
3.3 V
VDD supplies the five integrated low drop-out regulators
(LDOs), VSUP1 to VSUP5, that are used to supply the vast
majority of the internal circuitry. VSUP6, VSUP7, and VSUP8
supply the receive PLL, transmit PLL, and reference block,
respectively. These nodes require external connections to
ensure good supply isolation and ensure a minimum level of
interference between the PLL/reference blocks and the rest of
the transceiver. VSUP6 and VSUP7 should be connected to
VSUP3, whereas VSUP8 should be connected to VSUP2.
VSUP1 Internal LDO1
VSUP2 Internal LDO2
2.6 V
2.8 V
VSUP3 Internal LDO3
VSUP4 Internal LDO4
VSUP5 Internal LDO5
1.9 V
2.6 V
2.8 V
VSUP6 Connect to VSUP3
VSUP7 Connect to VSUP3
VSUP8 VSUP2 or external
1.9 V
1.9 V
2.8 V
Each node, VSUP1 to VSUP8, should be externally decoupled
to ground with a 0.1 μF capacitor. Y5V capacitors are not
recommended for use here. X7R, X5R, C0G, or a similar type of
capacitor should be used.
reference buffer outputs;
Optional: serial interface
readback
Rev. 0 | Page 21 of 36
ADF4602
When the high band is enabled, the programmed frequency
is equal to the LO frequency. For low band operation, the
programmed frequency should be set to 2× the desired LO
frequency.
FREQUENCY SYNTHESIS
The ADF4602 contains two fully integrated programmable
frequency synthesizers for generation of transmit and receive
local oscillator (LO) signals. The design uses a fractional-N
architecture for low noise and fast lock-time. The fractional-N
functionality is implemented with a thirdorder Σ-Δ modulator.
Figure 41 shows a block diagram of the synthesizer architecture.
VCO
The transmit and receive synthesizers are enabled by setting
Bit txsynthen and Bit rxsynthen in Register 1, respectively.
Reference Path
The ADF4602 requires a 26 MHz reference frequency input.
A VCTCXO is used to provide this. The reference input is ac-
coupled internally, so external ac coupling is not necessary.
LOOP
FILTER
F
: 3.4GHz TO
4.4GHz RANGE
VCO
FREF
C
P
PFD
÷2
LPF
PHASE FREQUENCY
DETECTOR AND
CHARGE PUMP
The 26 MHz reference is internally buffered and distributed to
the respective blocks, such as the synthesizer PFD inputs. Figure 42
shows a block diagram.
50kHz STEP
DIVIDERS
The ADF4602 provides two buffered outputs: a buffered version
of the 26 MHz reference on Pin REFCLK and a 19.2 MHz
WCDMA chip clock on Pin CHIPCLK. The 19.2 MHz chip
clock is a multiple of the 3.84 MHz chip rate used in WCDMA.
Thus, it can be used to clock ADCs/DACs elsewhere in the
system. The chip clock is generated by an integrated PLL and
contains no user settings.
Σ-Δ
VCO FREQ CAL
AND AMPLITUDE
CONTROL
DIGITAL DECODE
RxFREQ[15:0]
Figure 41. Frequency Synthesizer Block Diagram
All necessary components are fully integrated for both transmit
and receive synthesizers, including loop filters, VCOs, and tank
components. The VCOs run at 2× the high band frequency and
4× the low band frequency. The dividers are external to the
synthesizer loop. This minimizes VCO leakage power at the
desired frequency and tuning range requirements of the VCO.
The VCOs use a multiband structure to cover the wide
frequency range required.
Both outputs are slew rate limited and produce low swing digital
outputs. The buffers contain their own 1.5 V regulator circuits
to improve isolation and minimize unwanted supply noise. The
26 MHz and 19.2 MHz buffer outputs are enabled or disabled
by programming Bit refclken and Bit chipclken (Register 1).
26MHz CLOCK
REFIN (26MHz)
DISTRIBUTION
VSUP8
The design incorporates both frequency and amplitude calibration
to ensure that the oscillator is always operating with its optimum
performance. The calibrations occur during the 200 μs PLL lock
time and are fully self contained, requiring no user inputs.
REFCLK
1.5V
REG
REFCLKEN
The charge pump and loop filter are internally trimmed to
remove variations associated with manufacture and frequency.
This process is fully automated.
PLL
CHIPCLK
1.5V
REG
VSUP8
CHIPCLKEN
VSUP8
To aid simplified programming, the ADF4602 contains a frequency
decode table for the synthesizers, meaning the programmer is
not concerned with the internal operation of the counters and
fractional-N system. Frequency step sizes of 50 kHz are possible
with both transmit and receive synthesizers. The programming
words rxfreq[15:0] and txfreq[15:0] set the frequency in
50 kHz steps from 0 MHz to 3276.75 MHz. Note that the
synthesizers do not cover this full range. The frequency range
for each synthesizer in high and low bands is given in the
Specifications section.
VSUP8
Figure 42. Reference Path Block Diagram
All reference sections are powered from VSUP8, which can
safely be removed from the chip in isolation, to enter a low
current power-down mode. Calibration data is not lost, but the
reference frequency ceases to exist. As soon as VSUP8 is re-
applied, oscillation begins. This is visible at the buffer outputs,
as long as they were previously enabled.
Rev. 0 | Page 22 of 36
ADF4602
SERIAL PORT INTERFACE (SPI)
The ADF4602 contains internal registers that are used to configure
the device. The three-wire serial port interface provides read
and write access to the internal registers. For write, read
requests, and read operations, 26-bit transfers are used. The
MSB of all words are transferred first.
The read request format has the same address structure as the
write format but does not contain a data field. Padding is used
to maintain the 26-bit word length.
The readback format is the same as the word format during a
write. Again, padding is used to maintain the 26-bit word length.
Format
Table 9. SPI Chip Select Code
Figure 43 shows the format of the register write. This consists of
a 5-bit address and 16-bit data words. The exception is register
A1 = 00000, where the lower data byte is used as an 8-bit sub-
address. In total, this creates 31 16-bit registers and 256 8-bit
registers. The 31 16 bit registers are referred to in the text as
“Register 31” for example, while the 256 8-bit sub registers are
referred to as “Register 0.144”.
CS[2]
CS[1]
CS[0]
Device
0
0
1
ADF4602
Reserved
All other permutations
OPERATION AND TIMING
SCLK, SDATA, and SEN are used to transfer data into the
ADF4602 registers. Data is clocked into the register, MSB, first
on the rising edge of each SCLK. The data is transferred to the
selected register address on the rising edge of SEN. See Figure 2
and Figure 3 for timing information.
OP is a 2-bit code specifying the type of operation being performed
(see Table 8 for more information). The chip select code, CS,
is a 3-bit field indicating which device on the bus is being
programmed. For the ADF4602, CS should be set to 001 (D2,
D1, D0).
Read
Table 8. SPI Operation Code
OP[1] OP[0] Operation Description
Figure 3 shows a read operation. First, a read request is written
by the host to the ADF4602. SEN must remain high for at least
three SCLK periods between the read request operation and the
following read operation. The host must release the SDATA line
during this period. The ADF4602 takes control of SDATA, and the
read operation commences when the host device drives SEN low.
0
0
0
1
Write
Set
Normal register write.
Register bits corresponding to 1s
in the data word are set. Other
bits are not modified.
Register bits corresponding to 1s
in the data word are cleared.
Other bits are not modified.
1
1
0
1
Clear
Read
The SDATA output voltage during readback is set to 1.8 V or
2.8 V. Bit sif_vsup8 (Register 2) controls this. A 0 in this bit
configures the device to use the 1.8 V VINT supply, whereas a 1
configures the 2.8 V VSUP8 supply. After power-up or after a
soft reset, the ADF4602 defaults to 2.8 V readback mode.
Register read request.
BIT POSITION
OPERATION
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WRITE
REGISTER 1 TO 31
W[25:0]
DATA
D[15:0]
ADDRESS
A1[4:0]
OP
[1:0]
CS
[2:0]
WRITE
REGISTER 0
W[25:0]
DATA
D[7:0]
SUBADDRESS
A2[7:0]
ADDRESS
A1 = 00000
OP
[1:0]
CS
[2:0]
READ REQUEST
REGISTER 1 TO 31
Q[25:0]
RANDOM PADDING
ADDRESS
A1[4:0]
OP
[1:0]
CS
[2:0]
P[15:0]
READ REQUEST
REGISTER 0
Q[25:0]
RANDOM PADDING
P[7:0]
SUBADDRESS
A2[7:0]
ADDRESS
A1[4:0]
OP
[1:0]
CS
[2:0]
READ
REGISTER 1 TO 31
Q[25:0]
DATA
D[15:0]
ADDRESS
A1[4:0]
CS
[2:0]
OP = 11
OP = 11
READ
REGISTER 0
Q[25:0]
DATA
D[7:0]
SUBADDRESS
A2[7:0]
ADDRESS
A1 = 00000
CS
[2:0]
Figure 43. SPI Register Write Format
Rev. 0 | Page 23 of 36
ADF4602
REGISTERS
REGISTER MAP
GENERAL USER REGISTERS
1
A1
1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT R/W
refclk chipclk
en
txsynth
en
rxsynth
en
rxen
ldoen[4:0]
txen
txbs
rxbs[1:0]
0x2FFD
0x0002
W
W
en
sif_
vsup8
reset_
soft
2
RECEIVER USER REGISTERS
D8 D7 D6
1
A1
10
11
D15
D14
D13
D12
D11
D10
D9
D5
D4
D3
D2
D1
D0
DEFAULT R/W
rxfreq[15:0]
0x9858
0x0000
W
W
rxgain[6:0]
12
13
14
rfskip[3:0]
sdmen[3:0]
nper2[3:0]
nint2[3:0]
mixstep[3:0]
nper1[3:0]
nint1[3:0]
lnastep[3:0]
nper0[3:0]
nint0[3:0]
0x0FA6
0x103E
0xEE53
W
W
W
osadc2x[3:0]
nint3[3:0]
15
vcmsel swapq
swapi
rxbw[2:0]
gaincal[4:0]
sdmosr
0x0890
W
TRANSMITTER USER REGISTERS
1
A1
21
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT R/W
gain_blanksel
[1:0]
test_I/swap_I
gpo_ow[3:0]
test_Q/swap_Q
cmmod
vcm_sat_thres[5:0]
padac1[4:0]
0x001F
W
dacgpo
_owen
22
26
28
31
padac2_ow[5:0]
0x8000
0x0000
0x0001
0x0000
W
W
W
W
txfreq[15:0]
txpwr_set[11:0]
cntrl_
mode
nvmld
SUB-ADDRESS REGISTERS
D4 D3 D2
reserved[1:0]
1
A1 A2
D7
D6
D5
D1
D0
DEFAULT R/W
0
0
144
151
0x06
0x6F
W
W
vsup2[7:0]
0
0
0
0
0
0
0
153
155
165
170
171
174
175
reserved[7:0]
reserved[7:0]
reserved[7:0]
0x85
0x78
0x20
0xF0
W
W
W
W
W
W
W
en_mix[3:0]
2
buffstate
0x04
0x5F
3
buff_value[7:0]
reserved[7:0]
0x14
NOTES
1
THESE ARE RECOMMENDED DEFAULT SETTINGS THAT SHOULD BE PROGRAMMED INTO THE REGISTERS.
DEFAULT SHOWN IS FOR BAND 1 OPERATION. SET TO 0x00 IF TRANSMIT FREQUENCY < 21100MHz.
2
3DEFAULT SHOWN IS FOR BAND 1 OPERATION. SET TO 0x50 IF TRANSMIT FREQUENCY < 21100MHz.
Figure 44. Register Map
Rev. 0 | Page 24 of 36
ADF4602
REGISTER DESCRIPTION
Table 10. General User Registers
Register Bit
Bit Name Description
1, A1
13
12
11
rxen
refclken
Set this bit high to enable the receiver. A low here disables the receiver.
Setting this bit high enables the 26 MHz reference output buffer.
chipclken Setting this bit high enables the19.2 MHz chip clock output buffer.
[10:6] ldoen
The on-chip LDOs are powered down individually. For normal operation all LDOs should be enabled
(Bits[10 : 6] = [11111])
ldoen[10:6]1
XXXX1
XXX1X
XX1XX
Mode
VSUP1 2.6 V enable
VSUP2 2.8 V enable
VSUP3 1.8 V enable
VSUP4 2.6 V enable
VSUP5 2.8 V enable
X1XXX
1XXXX
5
4
txen
txbs
Setting this bit high enables the transmitter.
This bit controls which of the transmit outputs is in use. 0 = low band (TXLBRF), 1 = high band (TXHBRF).
3
[2:1]
txsynthen Setting this bit high enables the transmit synthesizer.
rxbs These bits control the receiver band select.
rxbs[2:1]
Operation
00
01
10
11
Reserved
Low band enable (RXLB)
High Band 1 enable (RXHB1) (default)
High Band 2 enable (RXHB2)
0
1
rxsynthen Setting this bit high enables the receive synthesizer
2, A1
sif_vsup8 The serial port readback (SDATA) output voltage is changed from 1.8 V to 2.8 V with this bit. 0 = use 1.8 V
VINT supply, 1 = use 2.8 V VSUP8 supply. After power-up or after a soft reset, the ADF4602 defaults to 2.8 V
readback mode.
0
reset_soft A rising edge on this bit starts a 50 μs reset pulse for the full chip. This bit is self clearing. It is
recommended that a soft reset be performed after power-up.
1 X = don’t care.
Rev. 0 | Page 25 of 36
ADF4602
Table 11. Receiver User Registers
Register Bit
Bit
Name
Description
10, A1
[15:0]
rxfreq
These bits set the receive synthesizer frequency in 50 kHz steps from 0 MHz to 3276.75 MHz. For the high
bands this is equal to the channel frequency, and for the low bands it is 2× the channel frequency.
For example:
Bit 15 to Bit 0 (Hex) HB1, HB2 Synthesizer Frequency
LB Synthesizer Frequency
950 MHz
975 MHz
0x9470
0x9858
1900 MHz
1950 MHz
11, A1
[6:0]
rxgain
These bits set the receiver gain in conjunction with the gaincal[4:0] setting in register 15. LSB = 1 dB.
0x00 = 0dB, 0x7F = 127 dB.
Gain = rxgain − gaincal + X
where X is 8 in WCDMA mode and 17 in GSM mode. The mode is selected by the rxbw bits in
Register 15.
With mixstep = 6 and lnastep = 10, the valid range for rxgain is from 12 dB to 102 dB. Settings outside of
these are clipped at 12 dB and 102 dB. See Figure 38 for an example.
12, A1
13, A1
14, A1
15, A1
[15:12] rfskip
Skip offset control state when no RF gain step occurred for State 3 to State 0. Default = 0x0 = 0.
Σ-Δ modulator enable for State 3 to State 0. Default = 0xF = 15.
Gain decode threshold for mixer gain reduction step. LSB = 4 dB steps. Default = 0xA = 10.
Gain decode threshold for LNA gain reduction step. LSB = 4 dB steps. Default = 0x6 = 6.
[11:8]
[7:4]
[3:0]
sdmen
mixstep
lnastep
[15:12] osadc2x Offset measurement ADC range for State 3 to State 0. Default = 0x1 = 1.
[11:8]
[7:4]
[3:0]
nper2
nper1
nper0
State duration for State 2. Default = 0x0 = 0.
State duration for State 1. Default = 0x3 = 3.
State duration for State 0. Default = 0xE = 14.
[15:12] nint3
Integrator time constant for State 3. Default = 0xE = 14.
Integrator time constant for State 2. Default =0xE = 14.
Integrator time constant for State 1. Default = 0x5 = 5.
Integrator time constant for State 0. Default = 0x3 =3.
This sets the receive baseband output common-mode voltage. 0 = 1.2 V, 1 = 1.4 V.
Setting this bit high swaps the differential Q outputs, RXBBQ and RXBBQB.
Setting this bit high swaps the differential I outputs, RXBBI and RXBBIB.
This bit controls the receive baseband filter bandwidth.
[11:8]
[7:4]
[3:0]
11
10
9
nint2
nint1
nint0
vcmsel
swapq
swapi
rxbw
[8:6]
rxbw [8:6]
000
Filter Mode
Fifth order WCDMA filter (not recommended for femtocells)
010
Seventh order WCDMA filter (recommended WCDMA filter for
femtocells)
111
Else
GSM filter
Reserved
[5:1]
0
gaincal
sdmosr
These bits are used for calibration of front-end loss. LSB = 1 dB, 0x00 = 0 dB, 0x1F = 31 dB. It is used in the
calculation of the receive gain. See rxgain in Register 11. If not used for calibration, this should be set to 8
in WCDMA mode and 17 in GSM mode.
Offset loop Σ-Δ modulator over sampling ratio. 1 = 4×, 0 = 2× (default)
Rev. 0 | Page 26 of 36
ADF4602
Table 12. Transmitter User Registers
Register Bit Bit Name
21, A1 [12:11] test_I/swap_I
Description
These bits allow various options on the I inputs as detailed in the following table:
Bits
00
Function
Normal operation
01
10
Swap I differential inputs for ease of PCB routing to DAC
Zero input on I inputs
11
DC offset applied to I inputs; creates large carrier at RF
[10:9]
[8:7]
test_Q/swap_Q These bits allow various options on the Q inputs as detailed in the table below:
Bits
00
Function
Normal operation
01
10
Swap Q differential inputs for ease of PCB routing to DAC
Zero input on Q inputs
11
DC offset applied to Q inputs: creates large carrier at RF
gain_blanksel
During a transmit gain change, some spectral splatter may occur at the output of the transmitter.
These bits allow the input baseband signal at the input to the low-pass filter to be blanked for a
short period, to reduce the spectral splatter observed during the gain change.
gain_blanksel[8:7]
Operation
00
01
10
11
Default setting; no blanking
230 ns blanking
540 ns blanking
850 ns blanking
6
cmmod
This bit adjusts the internal modulator common-mode setting. It should be set to 0. Setting this bit
to 1 results in reduced power consumption but degrades transmit linearity.
[5:0]
15:
vcm_sat_thres
dacgpo_owen
This bit should be set to 0x1F for normal operation.
22, A1
Setting this bit high allows the user to have manual control over DAC2 and GPO1 to GPO4.
[14:11] gpo_ow
These bits allow manual control of GPO 1 to GPO 4. Bit dacgpo_owen must be set to 1 to allow this
mode of operation. Each bit controls one of the GPOs as per the following table. This allows all
possible permutations of GPO output combinations.
gpo_ow[14 :11]1
Mode
XXX1
XX1X
X1XX
1XXX
GPO1 high
GPO2 high
GPO3 high
GPO4 high
[10:5]
padac2_ow
These bits allow manual control of DAC2. Bit dacgpo_owen must be set to 1 to allow this mode of
operation.
[4:0]
padac1
txfreq
These bits control DAC1.
26, A1
Write
[15:0]
These bits set the transmitter synthesizer frequency in 50 kHz steps from 0 MHz to 3276.75 MHz.
For the high bands, this is equal to the channel frequency, and for the low bands it is 2× the
channel frequency.
For example:
Bit 15 to Bit 0 (Hex)
0xA730
HB Synthesizer Frequency
2140 MHz
LB synthesizer Frequency
1070 MHz
0xA988
2170 MHz
1085 MHz
Rev. 0 | Page 27 of 36
ADF4602
Register Bit
Bit Name
Description
28, A1
Write
[15:4]
txpwr_set
Requested transmit power at antenna. LSB = 1/32 dBm, 0x000 = −80 dBm, 0xFFF = 47.96875 dBm.
The output power is referenced to a full scale sine wave applied to the transmit baseband inputs.
For WCDMA modulated signals, the output power measured in a 3.84 MHz bandwidth is reduced
by the peak to average ratio of the signal. See the I/Q Modulator section for more details. The valid
range of transmit output power setting is −80 dBm to +10 dBm. Output clipping may occur sooner,
depending on the PAR of the applied signal.
The txpwr_set register should be updated periodically, or with every 5°C change in temperature to
ensure accurate output power. See the VCO Output section for more details.
0
4
Set this bit to 1 to control the output power from the txpwr_set bits.
31, A1
Write
nvmld
Setting this bit to 1 triggers a manual load of the nonvolatile memory contents. See the Software
Initialization Procedure section for more details.
1 X = don’t care.
Table 13. Sub-Address Registers
Register
Bit
Bit Name
Description
0.144, A2 Write
0.151, A2 Write
[2:1]
[7:0]
reserved[1:0]
vsup2[7:0]
These bits should be set to 11 for normal operation.
These bits control the VSUP2 regulator voltage and should be set to 0x6F for normal
operation. During the initialization sequence, the VSUP2 voltage is temporarily set to
3.1 V. See the Software Initialization Procedure section for more details.
0.153, A2 Write
0.155, A2 Write
0.165, A2 Write
0.170, A2 Write
[7:0]
[7:0]
[7:0]
[7:4]
reserved[7:0]
reserved[7:0]
reserved[7:0]
en_mix[3:0]
These bits should be set to 0x85 for normal operation.
These bits should be set to 0x78 for normal operation.
These bits should be set to 0x20 for normal operation.
These bits enable the I, IB, Q, and QB channels of the modulator separately. Set these bits
to all 1s to enable the modulator for normal operation.
0.171, A2 Write
2
buffstate
This bit controls the transmit VCO buffer state.
For transmit synthesizer frequencies > 2100 MHz (Band 1) the buffer state should be set
to 1, and the corresponding VCO buffer value in R0.174 should be set to 0x5F. This
ensures correct device operation for frequencies > 2100 MHz.
For operation below 2100 MHz (Band 2). the buffer state should be set to 0, and the
corresponding VCO buffer value in R0.174 should be set to 0x50. This ensures correct
device operation for frequencies < 2100 MHz.
0.174, A2 Write
0.175, A2 Write
[7:0]
[7:0]
buff_value[7:0] These bits should be set to 0x5F for transmit frequencies >2100 MHz, and 0x50 for
transmit frequencies <2100 MHz. See the description for Register 0.171 for more.
reserved[7:0]
These bits should be set to 0x14 for normal operation.
Rev. 0 | Page 28 of 36
ADF4602
SOFTWARE INITIALIZATION PROCEDURE
INITIALIZATION SEQUENCE
Table 14 shows the initialization sequence that should be used after power-up. Note that the 26 MHz reference clock must be applied to
the REFIN pin before programming begins. The default settings are described in the comments section, and some settings, such as output
frequency, gain, and GPO settings, may vary from those required in the end application of the user. The user can substitute his own
settings in these instances.
Table 14. Initialization Sequence
Step Register1 Data
Comment
1
02
0x0003 Performs a soft reset of the ADF4602. The reset takes 50 μs, and no registers should be written to during this
period. After 50 μs, programming can continue as normal. This bit is self clearing.
If using 1.8 V logic levels, this register should be programmed to 0x0001 instead of 0x0003.
2
3
4
5
6
0.151
31
0xE0
Set VSUP2 to 3.1 V. See the Nonvolatile Memory (NVM) Initialization section for more details.
0x0010 Transfers non-volatile memory (NVM) contents to registers. Wait 200 μs before next programming step.
0x0000 Negate bit set in last programming step.
31
0.151
01
0x6F
Set VSUP2 back to 2.8 V.
0x2FDD Enables receiver and disables transmit output. Selects TXHBRF pin as the transmit output and RXHB1 as the
receive input.
Enables all on-chip regulators.
19.2 MHz output clock is enabled, 26 MHz output clock is disabled.
If it is desired to disable the 19.2 MHz output clock, this register is programmed to 0x27DD.
7
12
0x0FA6 Default settings for mixer and LNA gain reduction steps.
8
13
0x103E
0xEE53
Default settings.
Default settings.
9
14
10
11
12
13
14
15
16
17
18
15
0x0890 Sets received gain calibration, WCDMA filter mode, and output common-mode voltage to 1.4 V.
0x001F Default settings.
0x8000 Enables DAC and GPO manual control.
21
22
0.144
0.155
0.153
0.165
0.170
0.171
0x06
0x78
0x85
0x20
0xF0
0x04
0x00
0x5F
0x50
0x14
Default settings.
Default settings.
Default settings.
Default settings.
Default settings.
If transmit synthesizer frequency is >2100 MHz
If transmit synthesizer frequency is <2100 MHz
If transmit synthesizer frequency is >2100 MHz
If transmit synthesizer frequency is <2100 MHz
Default settings.
19
0.174
20
21
22
0.175
11
0x0050 Receiver gain set to 80 dB.
10
0x9858 Receiver synthesizer frequency set to 1950 MHz. The PLL takes 200 μs to lock. Registers should not be
written to during this period.
23
26
0xA730 Transmit synthesizer frequency set to 2140 MHz. The PLL takes 200 μs to lock. Registers should not be
written to during this period.
24
25
01
28
0x2FFD Enables transmit output.
0xA001 Enables control of the output power and sets the txpwr_set field to 0 dBm. Control of output power is via
the txpwr_set bits.
1 Register numbers 0.xxx are 8-bit registers as described in the SPI Interface section of the ADF4602-x datasheet.
Rev. 0 | Page 29 of 36
ADF4602
matically turned off to prevent any unwanted transmissions as
the PLL locks. The user should wait 200 μs (time taken for PLL
to lock), and then set the output power to the desired value by
writing to Register 28.
Nonvolatile Memory (NVM) Initialization
The ADF4602 has on-chip non-volatile memory (NVM) that
contains chip factory calibration coefficients. A soft reset of the
device transfers the contents of NVM to internal registers; however,
this has been found to be unreliable if performed at temperatures
below 0°C. The software work-around outlined in Step 2 to Step 5
of Table 14 ensures that the NVM data is transferred reliably
under all operating conditions. It involves setting the VSUP2
on-chip regulator to 3.1 V, manually transferring the data by
setting the nvmld bit in Register 31, and then resetting the
VSUP2 regulator to 2.8 V. Device programming can then
continue as normal.
If the user disables the transmit synthesizer, the transmit output
power must be turned off before reenabling the transmit
synthesizer. This is achieved by two means: setting Bit D5 in
Register 1 or setting the output power in Register 28 to a
minimum.
After reenabling the synthesizer, and then locking the synthesizer
to a frequency by programming the frequency word in Register 26,
the user can reenable the output power.
Programming Transmit and Receive frequencies
To change the receive frequency, simply program the new
frequency in Register 10, and wait 200 μs before using the
device as a transceiver. The receive gain is set at any time
(apart from during the 200 μs PLL locking transient).
After initialization, the transmit/receive synthesizer frequencies
may need to be changed. To change the transmit frequency, write
the new frequency word to Register 26. When a new transmit
frequency is programmed, the transmit output power is auto-
Rev. 0 | Page 30 of 36
ADF4602
APPLICATIONS INFORMATION
is not optimum for the ADF4602. With the DAC gain set
permanently at maximum, the transmit output power is
controlled via the ADF4602 Tx power setting.
INTERFACING THE ADF4602 TO THE AD9863
The AD9863 mixed signal front-end processor is recommended
for use with the ADF4602. The AD9863 contains dual 12-bit
ADCs and dual 12-bit DACs for sampling the ADF4602 receive
signal and providing the transmit baseband signal to the ADF4602.
This section discusses the connections necessary between the
devices.
ADF4602
AD9863
IOUT+A
TXBBI
R
DC
R
DACA
L
I INPUT
R
DC
IOUT–A
TXBBIB
TXBBQ
Transmit Interface
IOUT+B
DACB
R
The AD9863 TxDAC core provides dual, differential current
output DACs generated from the 12-bit data. The full scale
output current, IOUTFSMAX, is set by means of an external resistor,
DC
R
L
Q INPUT
R
DC
IOUT–B
TXBBQB
RSET. The relationship between IOUTFSMAX and RSET is as follows:
Figure 45. AD9863 TxDAC to ADF4602 Baseband Input Interface
1.23V
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
Receive Interface
IOUTFSMAX = 67×
RSET
The AD9863 ADC input consists of a differential input resistance
of 2 kꢀ and a switched capacitor circuit with a 2 V p-p differential
full scale input level. The input is self biased to mid-supply, or,
alternatively, is programmed to accept an external dc bias. The
ADF4602 receive baseband outputs can provide this external dc
bias (1.4 V), and this is the preferred interface between the two
devices. The vcmsel bit in Register 15 should be set to 1 to give
the 1.4 V common-mode voltage from the ADF4602, and the
AD9863 input bias should be disabled. A direct connection can
then be made between the ADF4602 receive baseband outputs
and the AD9863 ADC inputs.
Setting RSET to 3.9 kꢀ gives the optimal dynamic setting for the
TxDACs and results in a full scale output current of 20 mA.
The ADF4602 transmit baseband inputs accept a 1.2 V common-
mode input signal with 1 V p-p differential swing. The configu-
ration in Figure 45 is used to provide this from the AD9863
TxDACs.
Resistor RDC set up the dc common-mode voltage, whereas load
Resistor RL sets the differential swing. The differential swing,
VDIFF, is a function of the load resistor, RL, and the DAC full
scale current, IOUTFSMAX, according to
The sampling action of the ADC sample and hold capacitor can
introduce a kick-back effect onto the input signal. This can lead
to spurs in the receive signal at integer multiples of the ADC
sampling frequency. These spurs can degrade the sensitivity of the
receiver on channels containing these spurs. To reduce these
spurs and improve the sensitivity, filtering capacitors of 100 pF
to ground should be placed on each receive baseband output.
Figure 46 shows the interface between the two devices.
2× IOUTFSMAX ×RDC ×RL
VDIFF
=
= f (IOUTFSMAX ) = g(RL )
2×RDC + RL
The common-mode voltage VCM is set by
IOUTFSMAX
VCM
=
×RDC
2
Using these equations, RDC is set to 120 ꢀ to give 1.2 V common-
mode voltage, and RL is set to 63 ꢀ to give a 1 V p-pdifferential
input swing.
Receive Sensitivity
Figure 26 shows the ADF4602 receive sensitivity vs.frequency. The
sensitivity degradation due to the 63rd and 64th harmonics of the
30.72 MHz ADC sampling frequency can be seen near 1935
MHz and 1966 MHz. The 100 pF filtering capacitors to ground
were used at the ADC inputs for this plot. Note also the
sensitivity degradation due to the 26 MHz reference frequency
harmonics at 1924 MHz, 1950 MHz, and 1976 MHz. The
degradation in sensitivity is less than 3 dB for these harmonics.
Overall, the solution exceeds the 3GPP sensitivity specifications
by 6 dB across the frequency range.
The AD9863 transmit programmable gain amplifier (TxPGA)
provides 20 dB of simultaneous gain range for both DACs and is
controlled via the SPI port. The gain is in the range of 10% to
100% IOUTFSMAX. Coarse gain controls are also available for each
DAC output. Maximum settings (255) for both TxPGA gain
and coarse gain controls (full gain) are recommended. This is
because the DAC output common-mode voltage VCM is
designed with a specific IOUTFSMAX. Varying the DAC gain results
in a different IOUTFSMAX and consequently, a different VCM, which
Rev. 0 | Page 31 of 36
ADF4602
ADF4602
AD9863
IOUT+A
RXBBI
C1
100pF
ADCA
I OUTPUT
IOUT–A
RXBBIB
RXBBQ
RXBBQB
C2
100pF
IOUT+B
ADCB
C3
100pF
QOUTPUT
IOUT–B
C4
100pF
Figure 46. ADF4602 Receive Baseband Output to AD9863 ADC Interface
Rev. 0| Page 32 of 36
ADF4602
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
40
1
30
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
4.25
4.10 SQ
3.95
5.75
BSC SQ
EXPOSED
PAD
(BOT TOM VIEW)
0.50
0.40
0.30
21
10
20
11
0.25 MIN
4.50
REF
12° MAX
0.80 MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 47. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF4602BCPZ
ADF4602BCPZ-RL
Temperature Range
0°C to +85°C
0°C to +85°C
Package Description
Package Option
CP-40-1
CP-40-1
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
1 Z = RoHS Compliant Part.
Rev. 0 | Page 33 of 36
ADF4602
NOTES
Rev. 0 | Page 34 of 36
ADF4602
NOTES
Rev. 0 | Page 35 of 36
ADF4602
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07092-0-10/09(0)
Rev. 0 | Page 36 of 36
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