ADF5901 [ADI]
24 GHz to 24.25 GHz voltage controlled oscillator;
| 型号： | ADF5901 |
| 厂家： | 
ADI |
| 描述： | 24 GHz to 24.25 GHz voltage controlled oscillator |
| 文件： | 总27页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
24 GHz VCO and PGA
with 2-Channel PA Output
ADF5901
Data Sheet
Industrial sensors
FEATURES
Precision instrumentation
Tank level sensors
Smart sensors
Door opening
Energy saving
24 GHz to 24.25 GHz voltage controlled oscillator (VCO)
2-channel 24 GHz power amplifier (PA) with 8 dBm output
Single-ended outputs
2-channel muxed outputs with mute function
Programmable output power
Commercial sensors: object detection and tracking
Cars, boats, aircraft, and UAVs (drones): collision avoidance
Intelligent transportation systems: intelligent traffic
monitoring and control
N divider output (frequency discriminator)
24 GHz local oscillator (LO) output buffer
250 MHz signal bandwidth
Power control detector
Auxiliary 8-bit ADC
Surveillance and security
5°C temperature sensor
GENERAL DESCRIPTION
4-wire serial peripheral interface (SPI)
Electrostatic discharge (ESD) performance
Human body model (HBM): 2000 V
Charged device model (CDM): 250 V
Qualified for automotive applications
The ADF5901 is a 24 GHz Tx monolithic microwave integrated
circuit (MMIC) with an on-chip, 24 GHz VCO with PGA and
dual Tx channels for radar systems. The on-chip, 24 GHz VCO
generates the 24 GHz signal for the two Tx channels and the LO
output. Each Tx channel contains a power control circuit. There
is also an on-chip temperature sensor.
APPLICATIONS
Automotive radars
Industrial radars
Microwave radar sensors
Control of all the on-chip registers is through a simple 4-wire
interface.
The ADF5901 comes in a compact 32-lead, 5 mm × 5 mm
LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
TX_AHI RF_AHI
DVDD
AHI
VCO_AHI
VREG
C1
C2
R
SET
REGULATOR
R-DIVIDER
REFERENCE
REF
IN
ADF5901
MUXOUT
ADC
VCO
CAL
TX
TX
1
OUT
2
OUT
÷2
÷2
N-DIVIDER
ADC
CLK
DATA
LE
ATEST
TEMPERATURE
SENSOR
32-BIT
DATA
REGISTER
DOUT
ADC
CE
V
AUX
AUX
GND
LO
TUNE
OUT
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADF5901* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
Reference Materials
View a parametric search of comparable parts
Technical Articles
• High Performance Integrated 24 GHz FMCW Radar
Transceiver Chipset for Auto and Industrial Sensor
Applications
Evaluation Kits
• ADF5901 Evaluation Board
• Evaluation Board for ADF5901, ADF5904, and ADF4159
Chipset for a 24 GHz FMC Radar
Design Resources
• ADF5901 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Documentation
Data Sheet
• ADF5901: 24 GHz VCO and PGA with 2-Channel PA
Output Data Sheet
Discussions
User Guides
• UG-864: Evaluating the ADF5901 24 GHz Voltage
Controlled Oscillator (VCO) and Programmable Gain
Amplifier (PGA) with a 2-Channel Power Amplifier (PA)
Output
View all ADF5901 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
• UG-866: Evaluation Board for the ADF5901, ADF5904,
and ADF4159 Chipset for a 24 GHz FMCW Radar
Technical Support
Submit a technical question or find your regional support
number
Software and Systems Requirements
• ADF5901 and ADF4159 Evaluation Board Software
• EV-RADAR-MMIC Evaluation Software
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
ADF5901
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 2 ..................................................................................... 17
Register 3 ..................................................................................... 18
Register 4 ..................................................................................... 19
Register 5 ..................................................................................... 19
Register 6 ..................................................................................... 20
Register 7 ..................................................................................... 21
Register 8 ..................................................................................... 22
Register 9 ..................................................................................... 22
Register 10................................................................................... 23
Register 11................................................................................... 23
Initialization Sequence .............................................................. 23
Recalibration Sequence ............................................................. 23
Temperature Sensor ................................................................... 24
RF Synthesis: a Worked Example............................................. 24
Applications Information .............................................................. 25
Application of the ADF5901 in FMCW Radar ...................... 25
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Automotive Products................................................................. 26
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Reference Input Section............................................................. 11
RF INT Divider........................................................................... 11
INT, FRAC, and R Relationship ............................................... 11
R Counter .................................................................................... 11
Input Shift Register..................................................................... 11
Program Modes .......................................................................... 11
Register Maps.................................................................................. 13
Register 0 ..................................................................................... 15
Register 1 ..................................................................................... 16
REVISION HISTORY
7/2016—Rev. 0 to Rev. A
Changes to Applications Section.................................................... 1
Changes to Initialization Sequence Section and Recalibration
Sequence Section ............................................................................ 23
12/2015—Revision 0: Initial Version
Rev. A | Page 2 of 26
Data Sheet
ADF5901
SPECIFICATIONS
AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = 3.3 V 5%, AGND = 0 V, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise
noted. Operating temperature range is −40°C to +105°C.
Table 1.
Parameter
Min
24
1
Typ
Max
24.25
2.8
Unit
Test Conditions/Comments
OPERATING CONDITIONS
RF Frequency Range
VCO CHARACTERISITICS
VTUNE
GHz
V
VTUNE Impedance
100
kΩ
VCO Phase Noise Performance
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
Amplitude Noise
−88
−108
−128
−150
2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz At 1 MHz offset
MHz
Static Pulling fVCO Change vs. Load
Open-loop into 2:1 voltage standing wave ratio
(VSWR) load
Open-loop
Open-loop
Open-loop
Dynamic Pulling Tx On/Off Switch Change
Dynamic Pulling Tx to Tx Switch Change
Pushing fVCO Change vs. AHI Change
Spurious Level Harmonics
10
5
5
−30
<−70
MHz
MHz
MHz/V
dBc
Spurious Level Nonharmonics
dBc
POWER SUPPLIES
AHI, TX_AHI, RF_AHI, VCO_AHI, DVDD
3.135
3.3
3.465
10
V
1
Total Current, ITOTAL
170
500
200
mA
µA
µA
Software Power-Down Mode
Hardware Power-Down Mode
Tx OUTPUT
Output Power
Output Impedance
On/Off Isolation
Tx to Tx Isolation
Power-Up/Power-Down Time
LO OUTPUT
2
8
dBm
Ω
dB
dB
ns
50
30
25
200
Single Tx output switched on/off
Output Power
Output Impedance
On/Off Isolation
−7
−9
−1
50
30
+5
0
dBm
Ω
dB
AUX PIN OUTPUT
Output Power
−5
dBm
Single-ended
Differential
Output Frequency
Divide by 2 Output
Divide by 4 Output
Output Impedance
On/Off Isolation
AUX to LO Isolation
TEMPERATURE SENSOR
Analog Accuracy
Digital Accuracy
12
6
12.125 GHz
6.0625 GHz
200
30
30
Ω
dB
dB
5
5
°C
°C
Following one-point calibration
Following one-point calibration
Sensitivity
6.4
mV/°C
Rev. A | Page 3 of 26
ADF5901
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ADC
Resolution
8
Bits
LSB
LSB
mV
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Least Significant Bit (LSB)
REFIN CHARACTERISITICS
REFIN Input Frequency
1
1
7.4
10
260
MHz
−5 dBm minimum to +9 dBm maximum biased
at AHI/2 (ac coupling ensures 1.8/2 bias); for
frequencies < 10 MHz, use a dc-coupled, CMOS-
compatible square wave with a slew rate >
25 V/µs
REFIN Input Capacitance
REFIN Input Current
LOGIC INPUTS
Input Voltage
1.2
100
pF
µA
High (VIH)
1.4
V
Low (VIL)
Input Current (IINH, IINL
0.6
1
10
V
µA
pF
)
Input Capacitance (CIN)
LOGIC OUTPUTS
Output Voltage
High (VOH)2
VDD
0.4
−
V
V
Low (VOL)
Output Current
High (IOH)
0.4
500
500
µA
µA
Low (IOL)
1 TA = 25°C; AHI = 3.3 V; fREFIN = 100 MHz; RF = 24.125 GHz following initialization sequence in the Initialization Sequence section.
2 VDD selected from IO level bit (DB11 in Register 3).
TIMING SPECIFICATIONS
AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = 3.3 V 5%, AGND = 0 V, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise
noted. Operating temperature range is −40°C to +105°C.
Table 2. Write Timing
Parameter
Limit at TMIN to TMAX
Unit
Description
t1
t2
t3
t4
t5
t6
t7
t8
t9
20
10
10
25
25
10
20
10
15
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
LE setup time to DOUT
CLK setup time to DOUT
Rev. A | Page 4 of 26
Data Sheet
ADF5901
Write Timing Diagram
t4
t5
CLK
t2
t3
DB2
(CONTROL BIT C3)
DB1
DB0 (LSB)
(CONTRO BIT C1)
DB30
DATA
LE
DB31 (MSB)
(CONTROL BIT C2)
L
t7
t1
t6
DB31
(MSB)
DOUT
DB30
DB1
DB0
t8
t9
Figure 2. Write Timing Diagram
500µA
I
OL
TO DOUT AND
MUXOUT PINS
V
/2
DD
C
L
10pF
500µA
I
OH
Figure 3. Load Circuit for DOUT/MUXOUT Timing, CL = 10 pF
Rev. A | Page 5 of 26
ADF5901
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses at or above those listed under Absolute Maximum
Parameter
Rating
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
AHI to GND
AHI to TX_AHI
AHI to RF_AHI
AHI to VCO_AHI
AHI to DVDD
VTUNE to GND
Digital Input/Output Voltage to GND
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +3.6 V
−0.3 V to DVDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
ESD CAUTION
θJA Thermal Impedance1 (Paddle
Soldered)
40.83 °C/W
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Transistor Count
CMOS
260°C
40 sec
177,381
2315
Bipolar
ESD
Charged Device Model
Human Body Model
250 V
2000 V
1 Two signal planes (that is, on top and bottom surfaces of the board), two
buried planes, and nine vias.
Rev. A | Page 6 of 26
Data Sheet
ADF5901
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
1
2
3
4
5
6
7
8
24 DOUT
23
22 DATA
21 CLK
TX
1
LE
OUT
GND
ADF5901
TOP VIEW
(Not to Scale)
TX_AHI
TX_AHI
GND
20
19
CE
GND
TX
2
18 VREG
17 DVDD
OUT
GND
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO GND.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 3, 6, 8,
10, 12, 13,
19
GND
RF Ground. Tie all ground pins together.
2
TXOUT
1
24 GHz Tx Output 1.
4, 5
TX_AHI
Voltage Supply for the Tx Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane
as close as possible to this pin. TX_AHI must be the same value as AHI.
7
9
11
14
TXOUT
ATEST
LOOUT
2
24 GHz Tx Output 2.
Analog Test Pin.
LO Output.
RF_AHI
Voltage Supply for the RF Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground plane
as close as possible to this pin. RF_AHI must be the same value as AHI.
15
REFIN
Reference Input. This pin is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input
resistance of 100 kΩ. See Figure 14. This input can be driven from a TTL or CMOS crystal oscillator, or it can be
ac-coupled.
16
17
AHI
Voltage Supply for the Analog Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin.
Digital Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors (0.1 μF, 1 nF,
and 10 pF) to the ground plane as close as possible to this pin. DVDD must be the same value as AHI.
DVDD
18
20
VREG
CE
Internal 1.8 V Regulator Output. Connect a 220 nF capacitor to ground as close as possible to this pin.
Chip Enable. A logic low on this pin powers down the device. Taking the pin high powers up the device,
depending on the status of the power-down bit, PD1.
21
22
23
CLK
DATA
LE
Serial Clock Input. This serial clock input clocks in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a high
impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
16 latches with the latch selected via the control bits.
24
25
DOUT
MUXOUT
Serial Data Output.
Multiplexer Output. This multiplexer output allows either the scaled RF or the scaled reference frequency to be
accessed externally.
26
RSET
Resistor Setting Pin. Connecting a 5.1 kΩ resistor between this pin and GND sets an internal current. The
nominal voltage potential at the RSET pin is 0.62 V.
27
28
29
30
AUX
AUX
Auxiliary Output. The VCO/2 output or VCO/4 is available.
Complementary Auxiliary Output. The VCO/2 output or VCO/4 is available.
Control Input to the VCO. This voltage determines the output.
Voltage Supply for the VCO Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground
plane as close as possible to this pin. VCO_AHI must be the same value as AHI.
VTUNE
VCO_AHI
Rev. A | Page 7 of 26
ADF5901
Data Sheet
Pin No.
31
32
Mnemonic Description
C1
C2
EP
Decoupling Capacitor 1. Place a 47 nF capacitor to ground as close as possible to this pin.
Decoupling Capacitor 2. Place a 220 nF capacitor to ground as close as possible to this pin.
Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.
Rev. A | Page 8 of 26
Data Sheet
ADF5901
TYPICAL PERFORMANCE CHARACTERISTICS
12
6
4
10
2
8
0
6
–2
–4
–6
–8
–40°C
+25°C
+105°C
–40°C
+25°C
+105°C
Tx1
Tx2
4
2
OUTSIDE OF SPECIFIED RANGE
OUTSIDE OF SPECIFIED RANGE
0
23.95
24.00
24.05
24.10
24.15
24.20
24.25
24.30
23.95
24.00
24.05
24.10
24.15
24.20
24.25
24.30
OUTPUT FREQUENCY (GHz)
OUTPUT FREQUENCY (GHz)
Figure 5. Tx Output Power vs. Output Frequency
Figure 8. LO Output Power vs. Output Frequency
12
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
10
8
6
–40°C
AUX
4
3.135V
3.300V
3.465V
–40°C
+25°C
+105°C
+25°C
+105°C
AUX
OUTSIDE OF SPECIFIED RANGE
2
OUTSIDE OF SPECIFIED RANGE
0
23.95
24.00
24.05
24.10
24.15
24.20
24.25
24.30
11.99
12.01
12.03
12.05
12.07
12.09
12.11
12.13
OUTPUT FREQUENCY (GHz)
OUTPUT FREQUENCY (GHz)
Figure 6. Transmitter 1 (Tx1) Output Power Variation with Temperature and
Supply vs. Output Frequency
AUX
Figure 9. AUX/
Output Power vs. Output Frequency with Divide by 2
Selected
5
4
15
–40°C
10
+25°C
3
+105°C
–40°C
AUX
5
2
+25°C
AUX
+105°C
1
OUTSIDE OF SPECIFIED RANGE
0
–5
0
–1
–2
–3
–4
–5
–10
–15
–20
5.99
6.00
6.01
6.02
6.03
6.04
6.05
6.06
6.07
0
10
20
30
40
50
60
70
80
90
100
OUTPUT FREQUENCY (GHz)
Tx AMPLITUDE CALIBRATION REFERENCE CODE
Figure 7. Tx Output Power vs. Tx Amplitude Calibration Reference Code
AUX
Figure 10. AUX/
Output Power vs. Output Frequency with Divide by 4
Selected
Rev. A | Page 9 of 26
ADF5901
Data Sheet
3.5
3.0
2.5
2.0
1.5
1.0
0.5
250
200
150
100
50
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40°C
+25°C
+105°C
OUTSIDE OF SPECIFIED RANGE
0
0
23.75
23.88
24.10
24.13
24.25
24.38
24.50
OUTPUT FREQUENCY (GHz)
TEMPERATURE (ºC)
Figure 11. VTUNE Frequency Range
Figure 13. ATEST Voltage and ADC Code vs. Temperature
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
Figure 12. Open-Loop Phase Noise on Tx1 Output at 24.125 GHz
Rev. A | Page 10 of 26
Data Sheet
ADF5901
THEORY OF OPERATION
REFERENCE INPUT SECTION
R DIVIDER
The reference input stage is shown in Figure 14. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This configuration ensures that there is no loading of
the REFIN pin on power-down.
5-BIT
R COUNTER
REF
IN
×2
DOUBLER
TO CAL
BLOCK
÷2
DIVIDER
POWER-DOWN
CONTROL
Figure 16. Reference Divider
R COUNTER
100kΩ
SW2
NC
The 5-bit R counter allows the input reference frequency (REFIN)
to be divided down to supply the reference clock to the VCO
calibration block. Division ratios from 1 to 32 are allowed.
TO R COUNTER
REF
IN
NC
SW1
BUFFER
SW3
NO
INPUT SHIFT REGISTER
Figure 14. Reference Input Stage
The ADF5901 digital section includes a 5-bit RF R counter,
a 12-bit RF N counter, and a 25-bit FRAC counter. Data is
clocked into the 32-bit input shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred from
the input shift register to one of 12 latches on the rising edge of
LE. The destination latch is determined by the state of the five
control bits (C5, C4, C3, C2, and C1) in the input shift register.
These are the five LSBs (DB4, DB3, DB2, DB1, and DB0,
respectively), as shown in Figure 2. Table 5 shows the truth table
for these bits. Figure 17 and Figure 18 show a summary of how
the latches are programmed.
RF INT DIVIDER
The RF INT counter allows a division ratio in the RF feedback
counter. Division ratios from 75 to 4095 are allowed.
INT, FRAC, AND R RELATIONSHIP
Generate the RF VCO frequency (RFOUT) using the INT and
FRAC values in conjunction with the R counter, as follows:
RFOUT = fREF × (INT + (FRAC/225)) × 2
where:
RFOUT is the output frequency of internal VCO.
REF is the internal reference frequency.
(1)
PROGRAM MODES
f
Table 5 and Figure 19 through Figure 30 show how to set up the
program modes in the ADF5901.
INT is the preset divide ratio of the binary 12-bit counter
(75 to 4095).
FRAC is the numerator of the fractional division (0 to 225 − 1).
Several settings in the ADF5901 are double buffered. These
include the LSB fractional value, R counter value (R divider),
reference doubler, clock divider, RDIV2, and MUXOUT. This
means that two events must occur before the device uses a new
value for any of the double-buffered settings. First, the new
value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R5.
f
REF = REFIN × ((1 + D)/(R × (1 + T)))
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable
reference counter (1 to 32).
For example, updating the fractional value can involve a write to
the 13 LSB bits in Register R6 and the 12 MSB bits in Register R5.
Write to Register R6 first, followed by the write to Register R5.
The frequency change begins after the write to Register R0.
Double buffering ensures that the bits written to in Register R6
do not take effect until after the write to Register R5.
T is the REFIN divide by 2 bit (0 or 1).
25
RF N DIVIDER
N = INT + FRAC/2
FROM RF
INPUT STAGE
TO CAL
BLOCK
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
FRAC
VALUE
Figure 15. RF N Divider
Rev. A | Page 11 of 26
ADF5901
Data Sheet
Table 5. C5, C4, C3, C2, and C1 Truth Table
Control Bits
C3 (DB2)
C5 (DB4)
C4 (DB3)
C2 (DB1)
C1 (DB0)
Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
Rev. A | Page 12 of 26
Data Sheet
ADF5901
REGISTER MAPS
REGISTER 0 (R0)
AUX BUFFER
GAIN
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
PRC PNC
1
Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C5(0)
C4(0) C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
AG2 AG1 AG0
AD
1
1
1
1
REGISTER 1 (R1)
CONTROL
BITS
RESERVED
Tx AMP CAL REF CODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0 C5(0) C4(0) C3(0) C2(0) C1(1)
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
REGISTER 2 (R2)
ADC
AVERAGE
CONTROL
RESERVED
ADC CLOCK DIVIDER
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AS
AA0 AA0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C5(0) C4(0) C3(0) C2(1) C1(0)
REGISTER 3 (R3)
CONTROL
BITS
1
DBR
RESERVED
MUXOUT
READBACK CONTROL
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
M3 M2
M1
M0
IOL RC5 RC4 RC3 RC2 RC1 RC0 C5(0) C4(0) C3(0) C2(1) C1(1)
REGISTER 4 (R4)
CONTROL
BITS
RESERVED
RESERVED
ANALOG TEST BUS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
NDM
0
0
0
0
TBA TBP AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 C5(0) C4(0) C3(1) C2(0) C1(0)
REGISTER 5 (R5)
CONTROL
RESERVED
INTEGER WORD
FRAC MSB WORD
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
F24 F23
F22 F21
F20 F19
F18 F17 F16 F15 F14 F13 C5(0) C4(0) C3(1) C2(0) C1(1)
REGISTER 6 (R6)
CONTROL
BITS
1
DBR
RESERVED
FRAC LSB WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 C5(0) C4(0) C3(1) C2(1) C1(0)
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Figure 17. Register Summary (Register 0 to Register 6)
Rev. A | Page 13 of 26
ADF5901
Data Sheet
REGISTER 7 (R7)
CONTROL
BITS
1
R DIVIDER DBR
1
RESERVED
CLOCK DIVIDER
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
RD2 RD
R4
R3
R2
R1
R0 C5(0)
C4(0) C3(1) C2(1) C1(1)
C1D3 C1D2 C1D1 C1D0
0
0
0
0
0
MR
1
C1D11C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4
REGISTER 8 (R8)
CONTROL
BITS
FREQENCY CAL DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FC9 FC8 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 C5(0) C4(1) C3(0) C2(0) C1(0)
REGISTER 9 (R9)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
C5(0) C4(1) C3(0) C2(0) C1(1)
REGISTER 10 (R10)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
C5(0) C4(1) C3(0) C2(1) C1(0)
REGISTER 11 (R11)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CR C5(0) C4(1) C3(0) C2(1) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 5.
Figure 18. Register Summary (Register 7 to Register 11)
Rev. A | Page 14 of 26
Data Sheet
ADF5901
AUX BUFFER
GAIN
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
PRC PNC
1
Tx2C Tx1C PVCO VCAL PADC PTx2 PTx1 PLO C5(0)
C4(0) C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
AG2 AG1 AG0
AD
1
1
1
1
PLO PUP LO
AD
0
AUX DIV
0
1
POWER DOWN LO
POWER UP LO
DIV 2
DIV 1
1
PTx1 PUP Tx1
0
1
POWER DOWN Tx1
POWER UP Tx1
PNC
PUP RCNTR
0
1
POWER DOWN RCNTR
POWER UP RCNTR
PTx2 PUP Tx2
0
1
POWER DOWN Tx2
POWER UP Tx2
PNC
PUP NCNTR
0
1
POWER DOWN NCNTR
POWER UP NCNTR
AG2 AG1 AG0
AUX BUFFER GAIN
BUFFER DISABLED
GAIN SETTING 1
GAIN SETTING 2
GAIN SETTING 3
GAIN SETTING 4
GAIN SETTING 5
GAIN SETTING 6
GAIN SETTING 7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PADC PUP ADC
0
1
POWER DOWN ADC
POWER UP ADC
Tx2C Tx2 AMP CAL
0
1
NORMAL OPERATION
Tx2 AMP CAL
VCAL VCO CAL
0
1
NORMAL OPERATION
VCO FULL CAL
Tx1C Tx1 AMP CAL
0
1
NORMAL OPERATION
Tx1 AMP CAL
PVCO PUP VCO
0
1
POWER DOWN VCO
POWER UP VCO
Figure 19. Register 0 (R0)
block. Setting this bit to 1 returns the counter block to normal
operation.
REGISTER 0
Control Bits
Tx2 Amplitude Calibration
With Bits[C5:C1] set to 00000, Register R0 is programmed.
Figure 19 shows the input data format for programming this
register.
Bit DB12 provides the control bit for amplitude calibration of
the Transmitter 2 (Tx2) output. Set this bit to 0 for normal
operation. Setting this bit to 1 performs an amplitude
calibration of the Tx2 output.
Auxiliary Buffer Gain
Bits[DB23:DB21] set the auxiliary output buffer gain (see
Figure 19).
Tx1 Amplitude Calibration
Bit DB11 provides the control bit for amplitude calibration of
the Tx1 output. Set this bit to 0 for normal operation. Setting
this bit to 1 performs an amplitude calibration of the Tx1
output.
Auxiliary Divide by 2
Bit DB20 selects the auxiliary output divider. Setting this bit to 0
selects divide by 2 (6 GHz output). Setting the bit to 1 selects
divide by 1 (12 GHz output).
Power-Up VCO
Power-Up R Counter
Bit DB10 provides the power-up bit for the VCO. Setting this bit
to 0 performs a power-down of the VCO. Setting this bit to 1
performs a power-up of the VCO.
Bit DB15 provides the power-up bit for the R counter block.
Setting this bit to 0 performs a power-down of the counter block.
Setting this bit to 1 returns the counter block to normal
operation.
VCO Calibration
Bit DB9 provides the control bit for frequency calibration of the
VCO. Set this bit to 0 for normal operation. Setting this bit to 1
performs a VCO frequency and amplitude calibration.
Power-Up N Counter
Bit DB14 provides the power-up bit for the N counter block.
Setting this bit to 0 performs a power-down of the counter
Rev. A | Page 15 of 26
ADF5901
Data Sheet
Power-Up ADC
Power-Up LO Output
Bit DB8 provides the power-up bit for the ADC. Setting this bit to
0 performs a power-down of the ADC. Setting this bit to 1
performs a power-up of the ADC.
Bit DB5 provides the power-up bit for the LO output. Setting
this bit to 0 performs a power-down of the LO output. Setting
this bit to 1 performs a power-up of the LO output.
Power-Up Tx2 Output
REGISTER 1
Bit DB7 provides the power-up bit for the Tx2 output. Setting
this bit to 0 performs a power-down of the Tx2 output. Setting
this bit to 1 performs a power-up of the Tx2 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7).
Control Bits
With Bits[C5:C1] set to 00001, Register R1 is programmed.
Figure 20 shows the input data format for programming this
register.
Tx Amplitude Calibration Reference Code
Power-Up Tx1 Output
Bits[DB12:DB5] set the Tx amplitude calibration reference code
(see Figure 20) for the two Tx outputs during calibration.
Calibrate the output power on the Tx outputs from −20 dBm to
8 dBm by setting the Tx amplitude calibration reference code
(see Figure 7).
Bit DB6 provides the power-up bit for the Tx1 output. Setting
this bit to 0 performs a power-down of the Tx1 output. Setting
this bit to 1 performs a power-up of the Tx1 output. Only one
Tx output can be powered up at any time, either Tx1 (DB6) or
Tx2 (DB7).
CONTROL
BITS
Tx AMP CAL REF CODE
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
TAR7 TAR6 TAR5 TAR4 TAR3 TAR2 TAR1 TAR0 C5(0) C4(0) C3(0) C2(0) C1(1)
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
TAR7 TAR6 .......... TAR1 TAR0
Tx AMP CAL REF CODE
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252
253
254
255
Figure 20. Register 1 (R1)
Rev. A | Page 16 of 26
Data Sheet
ADF5901
ADC
AVERAGE
CONTROL
BITS
RESERVED
ADC CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
AS
AA0 AA0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C5(0) C4(0) C3(0) C2(1) C1(0)
AS
0
ADC START
AC7 AC6
AC1
AC0
ADC CLOCK DIVIDER
.
NORMAL OPERATION
START ADC CONVERSION
0
0
.
0
0
.
0
1
.
1
0
.
1
.
1
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
AA1 AA0
ADC AVERAGE
.
.
.
.
.
0
0
1
1
0
1
0
1
1
2
3
4
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
124
125
126
127
Figure 21. Register 2 (R2)
ADC Average
REGISTER 2
Bits[DB14:DB13] program the ADC average, which is the
number of averages of the ADC output (see Figure 21).
Control Bits
With Bits[C5:C1] set to 00010, Register R2 is programmed.
Figure 21 shows the input data format for programming this
register.
ADC Clock Divider
Bits[DB12:DB5] program the clock divider, which is used as the
sampling clock for the ADC (see Figure 21). The output of the
R divider block clocks the ADC clock divider. Program a
divider value to ensure the ADC sampling clock is 1 MHz.
ADC Start
Bit DB15 starts the ADC conversion. Setting this bit to 1 starts
an ADC conversion.
Rev. A | Page 17 of 26
ADF5901
Data Sheet
CONTROL
BITS
MUXOUT DBR1
RESERVED
READBACK CONTRO L
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
M3 M2
M1
M0
IOL RC5 RC4 RC3 RC2 RC1 RC0 C5(0) C4(0) C3(0) C2(1) C1(1)
M3 M2 M1 M0
MUXOUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TRISTATE OUTPUT
LOGIC HIGH
LOGIC LOW
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
RESERVED
READBACK CONTRO L
RC5 RC4 RC3 RC2 RC1 RC0
0
0
0
0
0
0
0
0
1
1
1
1
1
.
0
0
0
0
1
1
1
1
0
0
0
0
1
.
0
0
1
1
0
0
1
1
0
0
1
1
0
.
0
1
0
1
0
1
0
1
0
1
0
1
0
.
NONE
0
0
0
0
0
0
0
0
0
0
0
0
0
.
0
0
0
0
0
0
0
0
0
0
0
0
0
.
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGSITER 5
REGISTER 6
REGISTER 7
REGISTER 8
REGISTER 9
REGISTER 10
REGISTER11
RESERVED
RESERVED
ADC READBACK
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CAL BUSY
RESERVED
RESERVED
RESERVED
R-DIVIDER/2
N-DIVIDER/2
RESERVED
RESERVED
RESERVED
0
0
0
.
1
1
1
.
0
1
1
.
1
0
1
.
0
0
0
.
1
1
1
.
1DBR = DOUBLE-BUFFERED REGISTER.
IOL
0
IO LEVEL
.
.
.
.
.
.
1
1
1
1
1
1
1.8V LOGIC OUTPUTS
3.3V LOGIC OUTPUTS
1
Figure 22. Register 3 (R3)
Input/Output (IO) Level
REGISTER 3
Bit DB11 controls the DOUT logic levels. Setting this bit to 0 sets
the DOUT logic level to 1.8 V. Setting this bit to 1 sets the DOUT
logic level to 3.3 V.
Control Bits
With Bits[C5:C1] set to 00011, Register R3 is programmed.
Figure 22 shows the input data format for programming this
register.
Readback Control
Bits[DB10:DB5] control the readback data to DOUT on the
ADF5901. See Figure 22 for the truth table.
MUXOUT Control
Bits[DB15:DB12] control the on-chip multiplexer of the
ADF5901. See Figure 22 for the truth table.
Rev. A | Page 18 of 26
Data Sheet
ADF5901
CONTROL
BITS
RESERVED
RESERVED
ANALOG TEST BUS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
NDM
0
0
0
0
TBA TBP AB9
AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 C5(0) C4(0) C3(1) C2(0) C1(0)
TBA TEST BUS TO ADC
0
1
NORMAL OPERATION
TEST BUS TO ADC
AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
ANALOG TEST BUS
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
NONE
259
TEMPERATURE SENSOR
NDM N DIV TO MUXOUT EN
0
1
ENABLE NDIV TO MUXOUT
NORMAL OPERATION
TBP TEST BUS TO PIN
0
1
NORMAL OPERATION
TEST BUS TO PIN
Figure 23. Register 4 (R4)
CONTROL
BITS
RESERVED
INTEGER WORD
FRAC MSB WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
F24 F23
F22 F21
F20 F19
F18 F17 F16 F15 F14 F13 C5(0) C4(0) C3(1) C2(0) C1(1)
N11
N10
0
...
N4
N3
N2
0
0
0
.
N1
0
0
1
.
N0
0
1
0
.
INTEGER WORD
FRAC MSB WORD
(FRAC)*
F24
F23
.......... F14
F13
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
0
.
0
0
0
.
NOT ALLOWED
0
NOT ALLOWED
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
1
0
1
.
0
0
NOT ALLOWED
1
.
...
2
0
0
0
.
0
0
0
0
.
1
1
1
.
0
0
1
.
1
1
0
.
0
1
0
.
NOT ALLOWED
3
0
75
.
0
76
.
.
.
.
.
.
...
.
.
.
.
.
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
4093
4094
4095
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
1
1
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2
13
.
Figure 24. Register 5 (R5)
Test Bus to Pin
REGISTER 4
Bit DB15 controls the ATEST pin. Setting this bit to 0 sets the
ATEST pin to high impedance. Setting this bit to 1 connects the
analog test bus to the ATEST pin.
Control Bits
With Bits[C5:C1] set to 00100, Register R4 is programmed.
Figure 23 shows the input data format for programming this
register.
Analog Test Bus
Bits[DB14:DB5] control the analog test bus. This analog test bus
allows access to internal test signals for the temperature sensor.
See Figure 23 for the truth table.
N Divider to MUXOUT Enable
Bit DB21 controls the internal N divider signal for MUXOUT.
Setting this bit to 0 enables the internal N divider signal to
MUXOUT. Setting this bit to 1 returns the device to normal
operation.
REGISTER 5
Control Bits
Test Bus to ADC
With Bits[C5:C1] set to 00101, Register R5 is programmed.
Figure 24 shows the input data format for programming this
register.
Bit DB16 controls the ATEST pin. Set this bit to 0 for normal
operation. Setting this bit to 1 connects the analog test bus to
the ADC input.
Rev. A | Page 19 of 26
ADF5901
Data Sheet
12-Bit Integer Value (INT)
REGISTER 6
These 12 bits (Bits[DB28:DB17]) set the INT value, which
determines the integer part of the RF division factor. This INT
value is used in Equation 5. See the RF Synthesis: a Worked
Example section for more information. All integer values from
75 to 4095 are allowed.
Control Bits
With Bits[C5:C1] set to 00110, Register R6 is programmed.
Figure 25 shows the input data format for programming
this register.
13-Bit LSB FRAC Value
12-Bit MSB Fractional Value (FRAC)
These 13 bits (Bits[DB17:DB5]), together with Bits[DB16:DB5]
(FRAC MSB word) in Register R5, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 13 bits are the least significant bits (LSB)
of the 25-bit FRAC value, and Bits[DB14:DB3] (FRAC MSB
word) in Register R5 are the most significant bits (MSB). See
the RF Synthesis: a Worked Example section for more
information.
These 12 bits (Bits[DB16:DB5]), together with Bits[DB17:DB5]
(FRAC LSB word) in Register R6, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 12 bits are the most significant bits (MSB)
of the 25-bit FRAC value, and Bits[DB17:DB5] (FRAC LSB
word) in Register R6 are the least significant bits (LSB). See the
RF Synthesis: a Worked Example section for more information.
CONTROL
BITS
1
DBR
RESERVED
FRAC LSB WORD
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F12
F11 F10
F9
F8
F7
F6
F5
F4
F3
F2 F1
F0 C5(0) C4(0) C3(1) C2(1) C1(0)
FRAC LSB WORD
(FRAC)*
F12
F11
.......... F1
F0
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
8188
8189
8190
8191
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2
1
13
DBR = DOUBLE-BUFFERED REGISTER.
.
Figure 25. Register 6 (R6)
Rev. A | Page 20 of 26
Data Sheet
ADF5901
CONTROL
BITS
1
R DIVIDER DBR
1
RESERVED
CLOCK DIVIDER
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RD2 RD R4 R3 R2 R1 R0 C5(0)
C4(0) C3(1) C2(1) C1(1)
0
C1D3 C1D2 C1D1 C1D0
0
0
0
0
0
MR
1
C1D11C1D10 C1D9 C1D8 C1D7 C1D6 C1D5 C1D4
MR
0
MASTER RESET
RD2 RDIV2
DISABLED
ENABLED
0
1
DISABLED
ENABLED
1
REF
DOUBLER
RD
C1D11 C1D10 .......... C1D2 C1D0
CLOCK DIVIDER
0
1
DISABLED
ENABLED
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
1
0
1
.
0
1
2
R4
R3
R1
R0
R DIVIDER (R)
R2
3
.
0
0
.
0
0
.
0
1
.
1
0
.
1
0
0
.
.
.
.
.
.
2
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
28
29
30
31
1
1
1
1
1
DBR = DOUBLE-BUFFERED REGISTER.
Figure 26. Register 7 (R7)
Reference Doubler
REGISTER 7
Setting DB10 to 0 feeds the REFIN signal directly to the 5-bit
R counter, disabling the doubler. Setting this bit to 1 multiplies
the REFIN frequency by a factor of 2 before the REFIN signal is
fed into the 5-bit R counter.
Control Bits
With Bits[C5:C1] set to 00111, Register R7 is programmed.
Figure 26 shows the input data format for programming
this register.
The maximum allowable REFIN frequency when the doubler is
enabled is 50 MHz.
Master Reset
Bit DB25 provides a master reset bit for the device. Setting this
bit to 1 performs a reset of the device and all register maps.
Setting this bit to 0 returns the device to normal operation.
5-Bit R Divider
The 5-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the VCO calibration block. Division ratios from 1 to 31 are
allowed.
Clock Divider
Bits[DB23:DB12] set a divider for the VCO frequency calibration.
Load the divider such that the time base is 10 µs (see Figure 26).
Divide by 2 (RDIV2)
Setting the DB11 bit to 1 inserts a divide by 2 toggle flip flop
between the R counter and VCO calibration block.
Rev. A | Page 21 of 26
ADF5901
Data Sheet
CONTROL
BITS
FREQENCY CAL DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
FC9 FC8 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 C5(0) C4(1) C3(0) C2(0) C1(0)
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FREQUENCY CAL
FC9 FC8
...
...
...
...
...
...
...
...
...
FC4 FC3 FC2 FC1 FC0
DIVIDER
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
0
1
2
...
.
.
.
.
.
.
.
...
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
1021
1023
1024
Figure 27. Register 8 (R8)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C5(0) C4(1) C3(0) C2(0) C1(1)
0
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
Figure 28. Register 9 (R9)
REGISTER 8
REGISTER 9
Control Bits
Control Bits
With Bits[C5:C1] set to 01000, Register R8 is programmed.
Figure 27 shows the input data format for programming this
register.
With Bits[C5:C1] set to 01001, Register R9 is programmed.
Figure 28 shows the input data format for programming this
register.
Frequency Calibration Clock
Bits[DB14:DB5] set a divider for the VCO frequency calibration
clock. Load the divider such that the time base is 10 µs (see
Figure 27).
Rev. A | Page 22 of 26
Data Sheet
ADF5901
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
1
1
0
1
0
0
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
C5(0) C4(1) C3(0) C2(1) C1(0)
Figure 29. Register 10 (R10)
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
CR C5(0) C4(1) C3(0) C2(1) C1(1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CR CNTR RESET
0
1
DISABLED
ENABLED
Figure 30. Register 11 (R11)
11. Write 0x00200004 to Register R4 to set the ATEST pin to
high impedance.
12. Write 0x01890803 to Register R3 to set the IO level to
REGISTER 10
Control Bits
With Bits[C5:C1] set to 01010, Register R10 is programmed.
Figure 29 shows the input data format for programming this
register.
V
DD = 3.3 V.
13. Write 0x00020642 to Register R2 to set the ADC clock to
1 MHz.
REGISTER 11
Control Bits
14. Write 0xFFF7FFE1 to Register R1 to set the Tx amplitude
level.
15. Write 0x809FE720 to Register R0 to set the VCO frequency
calibration (800 µs).
With Bits[C5:C1] set to 01011, Register R11 is programmed.
Figure 30 shows the input data format for programming this
register.
16. Write 0x809FE560 to Register R0 to power Tx1 on, Tx2 off,
and LO on.
Counter Reset
17. Write 0x809FED60 to Register R0 to set the Tx1 amplitude
calibration (400 µs).
18. Write 0x809FE5A0 to Register R0 to turn Tx1 off, Tx2 on,
and LO on.
Bit DB5 provides a counter reset bit for the counters. Setting
this bit to 1 performs a counter reset of the device counters.
Setting this bit to 0 returns the device to normal operation.
19. Write 0x809FF5A0 to Register R0 to set the Tx2 amplitude
calibration (400 µs).
20. Write 0x2800B929 to Register R9.
21. Write 0x809F25A0 to Register R0 to disable the R and N
counters.
INITIALIZATION SEQUENCE
After powering up the device, administer the following
programming sequence. The following sequence locks the VCO
to 24.125 GHz with a 100 MHz reference and a 50 MHz
reference divider frequency:
RECALIBRATION SEQUENCE
1. Write 0x02000007 to Register R7 to perform a master reset.
2. Write 0x0000002B to Register R11 to reset the counters.
3. Write 0x0000000B to Register R11 to enable the counters.
4. Write 0x1D32A64A to Register R10.
5. Write 0x2A20B929 to Register R9.
6. Write 0x40003E88 to Register R8 to set the frequency
calibration divider clock to 100 kHz.
The ADF5901 can be recalibrated after the initialization
sequence is complete and the device is powered up. The
recalibration sequence must be run for every 10°C temperature
change; the temperature can be monitored using the
temperature sensor (see the Temperature Sensor section).
1. Write 0x809FE520 to Register R0 to enable the counters.
Tx1 and Tx2 are off, and LO is on.
2. Write 0x2A20B929 to Register R9.
3. Write 0xFFF7FFE1 to Register R1 to set the Tx amplitude
level.
7. Write 0x809FE520 to Register R0 to power up the device
and LO (10 µs).
8. Write 0x011F4827 to Register R7 to set the R counter clock
to 50 MHz and the calibration clock to 100 kHz.
9. Write 0x00000006 to Register R6 to set the LSB FRAC = 0.
10. Write 0x01E28005 to Register R5 to set INT = 241 and
MSB FRAC = 1024. Therefore, N = 240.25.
4. Write 0x809FE720 to Register R0 to set the VCO frequency
calibration (800 µs).
Rev. A | Page 23 of 26
ADF5901
Data Sheet
5. Write 0x809FE560 to Register R0 to power Tx1 on, Tx2 off,
and LO on.
6. Write 0x809FED60 to Register R0 to set the Tx1 amplitude
calibration (400 µs).
7. Write 0x89FE5A0 to Register R0 to power Tx1 off, Tx2 on,
and LO on.
Convert the DOUT word to temperature with the following
equation:
((ADC ×VLSB
)
−VOFF
)
Temperature ( C) =
(4)
VGAIN
8. Write 0x809FF5A0 to Register R0 to set the Tx2 amplitude
where:
ADC is the ADC code read back on DOUT.
calibration (400 µs).
9. Write 0x2800B929 to Register R9.
10. Write 0x809F25A0 to Register R0 to disable the R and N
counters.
VLSB = 7.33 mV, the ADC LSB voltage.
VOFF = 0.699 V, the offset voltage.
V
GAIN = 6.4 × 10−3, the voltage gain.
TEMPERATURE SENSOR
RF SYNTHESIS: A WORKED EXAMPLE
The ADF5901 has an on-chip temperature sensor that can be
accessed on the ATEST pin or as a digital word on DOUT
following an ADC conversion. The temperature sensor operates
over the full operating temperature range of −40°C to +105°C.
The accuracy can be improved by performing a one-point
calibration at room temperature and storing the result in
memory.
The following equation governs how to program the ADF5901:
RFOUT = (INT + (FRAC/225)) × (fREF) × 2
(5)
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the fractionality.
f
REF = REFIN × ((1 + D)/(R × (1 + T)))
(6)
With the temperature sensor on the analog test bus and test bus
connected to the ATEST pin (Register 4 set to 0x0000A064) the
ATEST voltage can be converted to temperature with the
following equation:
where:
REFIN is the reference frequency input.
D is the reference doubler bit, DB10 in Register R7 (0 or 1).
R is the reference division factor.
(
VATEST − VOFF
)
Temperature ( C) =
(3)
T is the reference divide by 2 bit, DB11 in Register R7 (0 or 1).
VGAIN
For example, in a system where a 24.125 GHz RF frequency
output (RFOUT) is required and a 100 MHz reference frequency
input (REFIN) is available, fREF is set to 50 MHz.
where:
VATEST is the voltage on the ATEST pin.
VOFF = 0.699 V, the offset voltage.
V
GAIN = 6.4 × 10−3, the voltage gain.
From Equation 6,
f
REF = (100 MHz × (1 + 0)/(1 × (1 + 1)) = 50 MHz
From Equation 5,
24.125 GHz = 50 MHz × (N + FRAC/225) × 2
The temperature sensor result can be converted to a digital
word with the ADC and readback on DOUT with the following
sequence:
1. Write 0x809FA5A0 to Register R0 to enable the counters.
2. Write 0x00012064 to Register R4 to connect the analog test
bus to the ADC and VTEMP to the analog test bus.
3. Write 0x00028C82 to Register R2 to start the ADC
conversion.
4. Write 0x018902C3 to Register R3 to set the output ADC
data to DOUT.
5. Read back DOUT.
Calculating the N and FRAC values,
N = int(RFOUT/(fREF × 2)) = 241
FRAC = FMSB × 213 + FLSB
F
F
MSB = int(((RFOUT/(fREF × 2)) − N) × 212) = 1024
LSB = int(((((RFOUT/(fREF × 2)) − N) × 212) − FMSB) × 213) = 0
where:
F
F
MSB is the 12-bit MSB FRAC value in Register R5.
LSB is the 13-bit LSB FRAC value in Register R6.
6. Write 0x809F25A0 to Register R0 to disable R and N
counters.
int() makes an integer of the argument in parentheses.
Rev. A | Page 24 of 26
Data Sheet
ADF5901
APPLICATIONS INFORMATION
The ADF5904 downconverts the signal from the four receiver
antennas to baseband with the LO signal from the Tx MMIC.
APPLICATION OF THE ADF5901 IN FMCW RADAR
Figure 31 shows the application of the ADF5901 in a frequency
modulated continuous wave (FMCW) radar system.
The downconverted baseband signals from the four receiver
channels on the ADF5904 are fed to the ADAR7251 4-channel,
continuous time, Σ-Δ analog-to-digital converter (ADC).
In the FMCW radar system, the ADF4159 generates the
sawtooth or triangle ramps necessary for this type of radar to
operate.
A digital signal processor (DSP) follows the ADC to handle the
target information processing.
The ADF4159 controls the VTUNE pin on the ADF5901 (Tx)
MMIC and thus the frequency of the VCO and the Tx output
signal on TXOUT1 or TXOUT2. The LO signal from the ADF5901
is fed to the LO input on the ADF5904.
LOOP
FILTER
CP
V
TUNE
RF
RF
A
B
TX
TX
AUX
AUX
IN
OUT1
ADF5901
ADF4159
IN
OUT2
LO
OUT
LO_IN
RX1_RF
RX2_RF
RX3_RF
RX4_RF
DSP
ADAR7251
RX BASEBAND
ADF5904
Figure 31. FMCW Radar with ADF5901
Rev. A | Page 25 of 26
ADF5901
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
Figure 32. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
ORDERING GUIDE
Model1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
CP-32-12
CP-32-12
ADF5901WCCPZ
ADF5901WCCPZ-RL7
EV-ADF5901SD2Z
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
1 Z = RoHS Compliant Part.
AUTOMOTIVE PRODUCTS
The ADF5901W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their respective
owners.
D13336-0-7/16(A)
Rev. A | Page 26 of 26
相关型号：
ADF6-10-03.5-L-4-1
Board Stacking Connector, 40 Contact(s), 4 Row(s), Female, Straight, 0.025 inch Pitch, Surface Mount Terminal, Locking, Black Insulator, Socket,
SAMTEC
ADF6-10-03.5-LTL-4-1
Board Stacking Connector, 40 Contact(s), 4 Row(s), Female, Straight, 0.025 inch Pitch, Surface Mount Terminal, Locking, Black Insulator, Socket,
SAMTEC
©2020 ICPDF网 联系我们和版权申明