ADF7030BCPZN [ADI]
High Performance, Low Power, 169MHz ISM Band, Radio Transceiver IC;
| 型号： | ADF7030BCPZN |
| 厂家： | 
ADI |
| 描述： | High Performance, Low Power, 169MHz ISM Band, Radio Transceiver IC 电信 ISM频段 电信集成电路 |
| 文件： | 总24页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance, Low Power,
169 MHz ISM Band, Radio Transceiver IC
ADF7030
Data Sheet
Host microprocessor interface
FEATURES
Easy to use programming interface (SPI)
Configurable output and input interrupts
Suitable for systems targeting compliance with
ETSI EN 300 220
RF frequency range: 169.4 MHz to 169.6 MHz
Modulation: 2 Gaussian frequency key shifting (GFSK), 4GFSK
Data rates
2GFSK: 2.4 kbps and 4.8 kbps
4GFSK: 6.4 kbps (transmitter only)
Low power consumption
6 mm × 6 mm, 40-lead, standard lead LFCSP
APPLICATIONS
Wireless M-Bus Mode N (EN 13757-4)
Smart metering
1 nA sleep current
Receiver (Rx) performance
97 dB blocking at 10 MHz offset
93 dB blocking at 2 MHz offset
66 dB adjacent channel rejection
−122.8 dBm sensitivity at BER = 0.1%
Transmitter (Tx) performance
2 power amplifier (PA) outputs
−20 dBm to +17 dBm output power range
0.1 dB output power step resolution
Very low output power variation vs. temperature and supply
61 mA Tx current at 17 dBm
Social alarms
Active tag asset tracking
GENERAL DESCRIPTION
The ADF7030 is a low power, high performance, integrated
radio transceiver supporting narrow-band operation in the
169.4 MHz to 169.6 MHz ISM band. The ADF7030 supports
transmit and receive operation at 2.4 kbps and 4.8 kbps using
2GFSK modulation and transmit operation at 6.4 kbps using
4GFSK modulation.
Accurate digital received signal strength indication (RSSI)
Fast settling automatic frequency control (AFC) algorithm for
very short preambles
Autonomous automatic gain control (AGC) algorithm
On-chip ARM Cortex-M0 processor performs the following
functions:
The ADF7030 features an on-chip ARM® Cortex®-M0 processor
that performs radio control and calibration, as well as packet
management.
Radio control
Radio calibration
Packet management
FUNCTIONAL BLOCK DIAGRAM
ADF7030
LDOx
TCXO BUFFER
RECEIVER
INTERRUPT
CONTROLLER
ARM
CORTEX-M0
LNA
DIGITAL
BASEBAND
SPI
SLAVE
PA
SYNTHESIZER
TRANSMITTER
ROM
RAM
8×
CONFIGURABLE
GPIOs
PA
Figure 1.
Rev. 0
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADF7030
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Receiver........................................................................................ 12
Transmitter .................................................................................. 15
Theory of Operation ...................................................................... 19
Host Interface.............................................................................. 19
Radio State Machine .................................................................. 20
Packet Handling ......................................................................... 20
Supported Radio Configurations ............................................. 21
Applications Information .............................................................. 22
Typical Application Circuit....................................................... 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
General Specifications ................................................................. 3
Transmitter Specifications........................................................... 3
Receiver Specifications ................................................................ 5
Current Consumption Specifications ........................................ 7
Digital Input/Output Specifications........................................... 7
Digital Timing Specifications ..................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
REVISION HISTORY
7/15—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADF7030
SPECIFICATIONS
VDD = VBAT1 = VBAT2 = VBAT3 = VBAT4 = VBAT5 = VBAT6 = 2.2 V to 3.6 V, exposed pad (EPAD) = 0 V (ground), TA = TMIN to TMAX
,
unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C, unless otherwise noted. All VBATx pins must be tied together.
GENERAL SPECIFICATIONS
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TEMPERATURE RANGE, TA
VOLTAGE SUPPLY
Maximum Output Power
13 dBm
−40
+85
°C
All VBATx pins must be tied together
2.2
2.8
3.6
3.6
V
V
17 dBm
RF FREQUENCY
Frequency Range
Channel Frequency Resolution
REFERENCE INPUT
169.4
169.6
MHz
Hz
1
DC-coupled external TCXO into
HFXTALN pin, clipped sine wave
Frequency
Peak-to-Peak Voltage Level
26
MHz
V
0.8
1.8
Voltage Level with Respect to Ground
Duty Cycle
−0.1
40
+1.9
60
V
%
DATA RATE
2GFSK
2GFSK
4GFSK
2.4
4.8
6.4
kbps
kbps
kbps
Tx only
Tx only
FREQUENCY DEVIATION
2GFSK
4GFSK
2.4
3.2
0.5
kHz
kHz
GAUSSIAN FILTER BANDWIDTH TIME (BT) PRODUCT
TRANSMITTER SPECIFICATIONS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER AMPLIFIERS (PAs)
PA1
Transmit Power
Maximum
Minimum
13
−20
0.1
dBm
dBm
dB
Transmit Power Step Resolution
Transmit Power Variation vs.
Temperature
From −40°C to +85°C
13 dBm
−10 dBm
0.15
0.3
dB
dB
Transmit Power Variation vs. VDD
13 dBm
−10 dBm
From VDD = 2.2 V to VDD = 3.6 V
0.1
0.1
dB
dB
Transmit Power Accuracy
13 dBm
−10 dBm
0.3
0.9
dB
dB
Rev. 0 | Page 3 of 24
ADF7030
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PA2
Transmit Power
Maximum
The maximum output power level achievable on PA2
depends on the programmable PA LDO setting
2.8 V ≤ VDD ≤ 3.6 V
2.2 V ≤ VDD ≤ 3.6 V
Minimum
Step Resolution
Transmit Power Variation vs.
Temperature
17
13
−20
0.1
0.1
dBm
dBm
dBm
dB
dB
From −40°C to +85°C, transmit power = 17 dBm
Transmit Power Variation vs. VDD
Transmit Power Accuracy
0.1
0.25
dB
dB
From VDD = 3.0 V to VDD = 3.6 V, transmit power = 17 dBm
Transmit power = 17 dBm
ADJACENT CHANNEL POWER (ACP)
Measured according to ETSI EN 300 220-1 V2.4.1;
12.5 kHz channel spacing; spectrum analyzer settings:
measurement bandwidth (BW) = 8.5 kHz, resolution band-
width (RBW) = 100 Hz, video bandwidth (VBW) = 300 Hz
2.4 kbps
2GFSK, frequency deviation = 2.4 kHz, PA1, output
power = 13 dBm
Adjacent Channel
Alternate Channel
4.8 kbps
−81
−81
dBc
dBc
2GFSK, frequency deviation = 2.4 kHz, PA2, output
power = 17 dBm
Adjacent Channel
Alternate Channel
6.4 kbps
−59
−77
dBc
dBc
4GFSK, frequency deviation = 3.2 kHz, PA1, output
power = 13 dBm
Adjacent Channel
Alternate Channel
−68
−79
dBc
dBc
OCCUPIED BANDWIDTH
Occupied bandwidth is the bandwidth containing 99% of
the total integrated power; spectrum analyzer settings:
measurement BW = 8.5 kHz, RBW = 100 Hz, VBW = 300 Hz
2.4 kbps
4.8 kbps
6.4 kbps
6.3
7.8
8.1
kHz
kHz
kHz
2GFSK, frequency deviation = 2.4 kHz, PA1, output
power = 13 dBm
2GFSK, frequency deviation = 2.4 kHz, PA2, output
power = 17 dBm
4GFSK, frequency deviation = 3.2 kHz, PA1, output
power = 13 dBm
MAXIMUM SPURIOUS EMISSIONS
(EXCLUDING HARMONICS)
Measured according to ETSI EN 300 220-1 V2.4.1 on the
ADF7030 evaluation board; transmitting continuous
PN9 data on PA1 at 13 dBm
47 MHz to 74 MHz
−84
<−87
−87
−79
−69
−80
−84
−82
−84
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
74 MHz to 87.5 MHz
87.5 MHz to 118 MHz
118 MHz to 168.5 MHz
168.5 MHz to 170.5 MHz
170.5 MHz to 174 MHz
174 MHz to 230 MHz
230 MHz to 470 MHz
470 MHz to 862 MHz
862 MHz to 1 GHz
Excluding frequency range fCHANNEL 31.25 kHz
<−87
<−87
1 GHz to 4 GHz
Rev. 0 | Page 4 of 24
Data Sheet
ADF7030
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
MAXIMUM HARMONIC EMISSIONS
Measured conductively at antenna input, according to
ETSI EN 300 220-1 V2.4.1 on the ADF7030 evaluation
board; transmitting continuous PN9 data
17 dBm Output Power
Second Harmonic
Third Harmonic
Fourth Harmonic
All Other Harmonics
13 dBm Output Power
Second Harmonic
Third Harmonic
Fourth Harmonic
All Other Harmonics
OPTIMUM PA LOAD IMPEDANCE
PA1
PA2
−74
−86
−90
<−90
dBc
dBc
dBc
dBc
PA1
−73
−82
−90
<−90
dBc
dBc
dBc
dBc
47 + j10
38 + j10
Ω
Ω
PA2
RECEIVER SPECIFICATIONS
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SENSITIVITY, BIT ERROR ATE (BER)
At BER = 0.1%, AFC disabled, 2GFSK frequency deviation =
2.4 kHz
2.4 kbps
4.8 kbps
−122.8
−121.4
dBm
dBm
SENSITIVITY, PACKET ERROR RATE (PER)
At PER = 5%, preamble length = 2 bytes, sync word =
0xF672, payload length = 24 bytes, data rate error
tolerance = 400 ppm, RF frequency error range = 2 kHz,
AFC enabled, 2GFSK frequency deviation = 2.4 kHz
2.4 kbps
4.8 kbps
−121.2
−119.5
dBm
dBm
CHANNEL SELECTIVITY AND BLOCKING
BER-Based Test Method
Desired signal 3 dB above the input sensitivity level
(BER = 0.1%), carrier wave (CW) interferer power level
increased until BER = 0.1%, image calibrated, 12.5 kHz
channel spacing, 2GFSK frequency deviation = 2.4 kHz
2.4 kbps
Adjacent Channel ( 12.5 kHz)
Alternate Channel ( 25 kHz)
2 MHz
10 MHz
66
70
93
97
dB
dB
dB
dB
4.8 kbps
Adjacent Channel ( 12.5 kHz)
Alternate Channel ( 25 kHz)
2 MHz
63
69
93
96
dB
dB
dB
dB
10 MHz
Rev. 0 | Page 5 of 24
ADF7030
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PER-Based Test Method
Desired signal 3 dB above the input sensitivity level
(PER = 5%), CW interferer power level increased until
PER = 5%, image calibrated, AFC enabled, preamble
length = 2 bytes, sync word = 0xF672, payload length =
24 bytes, 12.5 kHz channel spacing, 2GFSK frequency
deviation = 2.4 kHz
2.4 kbps
Adjacent Channel ( 12.5 kHz)
Alternate Channel ( 25 kHz)
2 MHz
10 MHz
62
70
93
96
dB
dB
dB
dB
4.8 kbps
Adjacent Channel ( 12.5 kHz)
Alternate Channel ( 25 kHz)
2 MHz
55
69
91
95
dB
dB
dB
dB
10 MHz
ETSI EN 300 220-1 V2.4.1 Test Method
Measured as per EN 300 220-1 V2.4.1, image calibrated,
AFC disabled, 12.5 kHz channel spacing, 2GFSK
frequency deviation = 2.4 kHz
2.4 kbps
Wanted signal level = −106.7 dBm (3 dB above the
reference sensitivity level), receiver bandwidth = 8.7 kHz
2 MHz
10 MHz
−18
−14
dBm
dBm
4.8 kbps
Wanted signal level = −105.8 dBm (3 dB above the
reference sensitivity level), receiver bandwidth = 10.6 kHz
2 MHz
10 MHz
−18
−14
dBm
dBm
CO-CHANNEL REJECTION
PER-Based Test Method
Desired signal 3 dB above the input sensitivity level
(PER = 5%), CW interferer power level increased until
PER = 5%, AFC enabled, preamble length = 2 bytes, sync
word = 0xF672, payload length = 24 bytes, 2GFSK
frequency deviation = 2.4 kHz
2.4 kbps
4.8 kbps
−10
−10
dB
dB
BER-Based Test Method
Desired signal 3 dB above the input sensitivity level (BER =
0.1%), CW interferer power level increased until BER =
0.1%, AFC disabled, 2GFSK frequency deviation = 2.4 kHz
2.4 kbps
4.8 kbps
−8
−9
55
dB
dB
dB
IMAGE REJECTION
Desired signal 3 dB above the input sensitivity level
(PER = 5%), CW interferer power level increased until
PER = 5%, AFC enabled, preamble length = 2 bytes, sync
word = 0xF672, payload length = 24 bytes, 2GFSK
frequency deviation = 2.4 kHz
RECEIVER LINEARITY
Measured at maximum receiver gain
Input Third-Order Intercept (IP3)
−8.5
53
dBm
dBm
dBm
Receiver channel frequency = 169.43125 MHz, fSOURCE1
171.35 MHz, fSOURCE2 = 173.26875 MHz
Receiver channel frequency = 169.53125 MHz, fSOURCE1
171.55 MHz, fSOURCE2 = 171.63125 MHz
Receiver channel frequency = 169.43125 MHz, fSOURCE1
171.43125 MHz
=
=
=
Input Second-Order Intercept (IP2)
1 dB Compression Point (P1dB)
−18.7
Rev. 0 | Page 6 of 24
Data Sheet
ADF7030
Parameter
RSSI
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
Absolute Accuracy
0.25
2
dB
dB
RSSI range = −110 dBm to −12 dBm with one point
calibration at −70 dBm and result averaged over 20 RSSI
measurements
MAXIMUM RF INPUT LEVEL
DIFFERNTIAL LNA INPUT IMPEDANCE
Rx SPURIOUS EMISSIONS
10
dBm
Ω
78 + j17.7
Measured conductively at antenna input, according to ETSI
EN 300 220-1 V2.4.1 on the ADF7030 evaluation board
<1 GHz
1 GHz to 4 GHz
<−63
−50
dBm
dBm
CURRENT CONSUMPTION SPECIFICATIONS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TRANSMIT CURRENT CONSUMPTION
In the PHY_TX state
10 dBm
13 dBm
17 dBm
35.5
44
61
mA
mA
mA
mA
PA1
PA1
PA2
RECEIVE CURRENT CONSUMPTION
LOW POWER MODE
Deep Sleep
26
In the PHY_RX state, waiting for preamble
1
nA
No memory retained
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 5.
Parameter
LOGIC INPUTS
Input Voltage
High
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VINH
VINL
CIN
0.7 × VDD
V
V
pF
Low
0.2 × VDD
Input Capacitance
LOGIC OUTPUTS
Output Voltage
High
3.6
VOH
VOL
VDD − 0.4
V
V
IOH = 500 µA
IOL = 500 µA
Low
0.4
Rev. 0 | Page 7 of 24
ADF7030
Data Sheet
DIGITAL TIMING SPECIFICATIONS
VDD = VBAT1 = VBAT2 = VBAT3 = VBAT4 = VBAT5 = VBAT6 = 2.2 V to 3.6 V. EPAD = 0 V (ground), TA = TMIN to TMAX, unless
otherwise noted.
Table 6. SPI Interface Timing
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
t1
t2
Falling edge to MISO setup time
CS low to SCLK setup time
SCLK high time
SCLK low time
SCLK period
SCLK falling edge to MISO delay
MOSI to SCLK rising edge setup time
MOSI to SCLK rising edge hold time
SCLK falling edge to CS hold time
CS high time
15
40
40
40
80
t3
t4
t5
t6
t7
t8
t9
10
5
5
40
80
t10
t11
t12
CS low to MISO high wake-up time
MISO high to SCLK setup time
92
SCLK low time
Timing Diagrams
CS
t10
t2
t3 t4
t5
t9
SCLK
MISO
t1
t6
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 7
BIT 0
X
BIT 7
t8
t7
MOSI
7
6
5
4
3
2
1
0
7
7
Figure 2. SPI Interface Timing
CS
t9
t12
SCLK
7
6
5
4
3
2
1
0
t11
t6
MISO
X
SPI STATE
SLEEP
WAKE UP
SPI READY
Figure 3. PHY_SLEEP to SPI Ready State Timing
Rev. 0 | Page 8 of 24
Data Sheet
ADF7030
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All VBATx pins must be tied
together. The LNAIN1 and LNAIN2 inputs must be ac-coupled.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 7.
Parameter
Rating
Supply Pins
VBAT1, VBAT2, VBAT3, VBAT4, VBAT5,
VBAT6 to Ground
−0.3 V to +3.9 V
Connect the exposed pad of the device to ground.
LNAIN1, LNAIN2
PAOUT1, PAOUT2
HFXTALP, HFXTALN
CLF
CREG1, CREG2, CREG4, CREG5, CREG6,
CREG7
−0.3 V to +1.98 V
−0.3 V to +3.9 V
−0.3 V to +1.98 V
−0.3 V to +1.98 V
−0.3 V to +1.98 V
This device is a high performance, RF integrated circuit with an
ESD rating of <2 kV; it is ESD sensitive. Take proper precautions
for handling and assembly.
ESD CAUTION
CREG3
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−40°C to +85°C
−65°C to +125°C
150°C
Digital Inputs/Outputs, GPIOx
MOSI, MISO, SCLK, CS, RST
Industrial Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
θJA Thermal Impedance
Reflow Soldering
26°C/W
Peak Temperature
Time at Peak Temperature
260°C
40 sec
Rev. 0 | Page 9 of 24
ADF7030
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
30 DNC
29 GPIO6
28 CS
RST
VBAT1
CREG1
VBAT2
CREG2
LNAIN1
LNAIN2
DNC
1
2
3
4
5
6
7
8
9
27 SCLK
26 MISO
25 MOSI
24 VBAT5
23 VBAT4
22 GPIO5
21 GPIO4
ADF7030
TOP VIEW
(Not to Scale)
CREG3
DNC 10
NOTES
1. DNC = DO NOT CONNECT.
2. CONNECT THE EXPOSED PAD TO GROUND.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
RST
External Reset, Active Low.
Power Supply Pin 1 to the Internal Regulators.
Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise
rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin.
VBAT1
CREG1
4
5
6
7
8
9
VBAT2
CREG2
LNAIN1
LNAIN2
DNC
Power Supply Pin 2 to the Internal Regulators.
Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
LNA Input 1.
LNA Input 2.
Do Not Connect. Do not connect to this pin.
Regulator Output 3. Connect to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor between
this pin and ground for regulator stability and noise rejection.
CREG3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DNC
DNC
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Single-Ended PA1 Output.
PAOUT1
PAOUT2
VBAT3
CREG4
GPIO0
GPIO1
GPIO2
GPIO3
DNC
GPIO4
GPIO5
VBAT4
VBAT5
MOSI
Single-Ended PA2 Output.
Power Supply Pin 3 to the Internal Regulators.
Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
Digital General-Purpose Input/Output (GPIO) Pin 0.
Digital GPIO Pin 1.
Digital GPIO Pin 2.
Digital GPIO Pin 3.
Do Not Connect. Do not connect to this pin.
Digital GPIO Pin 4.
Digital GPIO Pin 5.
Power Supply Pin 4 to the Internal Regulators.
Power Supply Pin 5 to the Internal Regulators.
Serial Port Master Out/Slave In.
MISO
SCLK
CS
Serial Port Master In/Slave Out.
Serial Port Clock.
Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host processor from
inadvertently waking the ADF7030 from sleep.
Rev. 0 | Page 10 of 24
Data Sheet
ADF7030
Pin No. Mnemonic Description
29
30
31
32
33
34
35
36
37
38
39
40
GPIO6
DNC
DNC
GPIO7
DNC
CREG5
HFXTALP
HFXTALN
CREG6
CREG7
CLF
Digital GPIO Pin 6
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Digital GPIO Pin 7.
Do Not Connect. Do not connect to this pin.
Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
Do Not Connect. Do not connect to this pin.
Reference Input. Connect this pin to an external 26 MHz reference (typically a TCXO).
Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.
External Loop Filter Capacitor to CREG1. Place a 1.2 nF capacitor between this pin and the CREG1 pin.
Power Supply Pin 6 to the Internal Regulators.
VBAT6
EPAD
Exposed Pad. Connect the exposed pad to ground.
Rev. 0 | Page 11 of 24
ADF7030
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
RECEIVER
0
–1
–2
–3
–4
–5
–6
–7
100
+10.0dBm
–40°C, 2.2V
90
80
70
60
50
40
30
20
10
0
–100.0dBm
–119.2dBm
–120.2dBm
–121.2dBm
–40°C, 3.6V
+25°C, 2.2V
+25°C, 3.6V
+85°C, 2.2V
+85°C, 3.6V
–126 –125 –124 –123 –122 –121 –120 –119 –118 –117 –116 –115
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
RF INPUT POWER (dBm)
RF FREQUENCY ERROR (kHz)
Figure 5. Packet Error Rate vs. RF Frequency Error and RF Input Power,
Data Rate = 2.4 kbps, AFC Enabled, VDD = 3.0 V, TA = 25°C
Figure 8. Log10 (Bit Error Rate) vs. RF Input Power, Temperature, and VDD
,
Data Rate = 4.8 kbps, AFC Disabled
100
100
+10.0dBm
–40°C, 3.6V
–40°C, 2.2V
+85°C, 3.6V
+85°C, 2.2V
90
90
80
70
60
50
40
30
20
10
0
–100.0dBm
–117.7dBm
–118.7dBm
–119.7dBm
80
70
60
50
40
30
20
10
0
–124
–122
–120
–118
–116
–114
–112
–110
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
RF INPUT POWER (dBm)
RF FREQUENCY ERROR (kHz)
Figure 9. Packet Error Rate vs. RF Input Power, Temperature, and VDD
,
Figure 6. Packet Error Rate vs. RF Frequency Error and RF Input Power,
Data Rate = 4.8 kbps, AFC Enabled, VDD = 3.0 V, TA = 25°C
Data Rate = 2.4 kbps
0
100
–40°C, 3.6V
–40°C, 2.2V
+85°C, 3.6V
+85°C, 2.2V
–40°C, 2.2V
90
–40°C, 3.6V
+25°C, 2.2V
+25°C, 3.6V
+85°C, 2.2V
+85°C, 3.6V
–1
–2
–3
–4
–5
–6
–7
80
70
60
50
40
30
20
10
0
–126 –125 –124 –123 –122 –121 –120 –119 –118 –117 –116 –115
–124
–122
–120
–118
–116
–114
–112
–110
RF INPUT POWER (dBm)
RF INPUT POWER (dBm)
Figure 7. Log10 (Bit Error Rate) vs. RF Input Power, Temperature, and VDD
,
Figure 10. Packet Error Rate vs. RF Input Power, Temperature, and VDD
,
Data Rate = 2.4 kbps, AFC Disabled
Data Rate = 4.8 kbps
Rev. 0 | Page 12 of 24
Data Sheet
ADF7030
10
9
8
7
6
5
4
3
2
1
0
80
70
60
50
40
30
20
10
0
+25°C, 2.2V
+25°C, 3.6V
+85°C, 2.2V
+85°C, 3.6V
–40°C, 2.2V
–40°C, 3.6V
–10
–120–110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
10
–0.20 –0.15 –0.10 –0.05
0
0.05
0.10
0.15
0.20
RF INPUT POWER (dBm)
FREQUENCY (MHz)
Figure 11. Packet Error Rate vs. RF Input Power,
Data Rate = 2.4 kbps, VDD = 3.0 V, TA = 25°C
Figure 14. Receiver Close-In Blocking vs. Temperature and VDD
Data Rate = 4.8 kbps, CW Interferer, Wanted Signal 3 dB Above the
Sensitivity Level of PER = 5%, PER-Based Test
,
80
70
60
50
40
30
10
9
8
7
6
5
4
3
2
1
0
20
10
–40°C, 2.2V
–40°C, 3.6V
+25°C, 2.2V
+25°C, 3.6V
+85°C, 2.2V
+85°C, 3.6V
0
–10
–120–110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
10
–200 –175 –150 –125 –100 –75 –50 –25
0
25 50 75 100
RF INPUT POWER (dBm)
FREQUENCY (kHz)
Figure 12. Packet Error Rate vs. RF Input Power,
Data Rate = 4.8 kbps, VDD = 3.0 V, TA = 25°C
Figure 15. Receiver Close-In Blocking vs. Temperature and VDD
Data Rate = 2.4 kbps, CW Interferer, Wanted Signal 3 dB Above the
Sensitivity Level of BER = 0.1%, BER-Based Test
,
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
–40°C, 2.2V
20
+25°C, 2.2V
+25°C, 3.6V
+85°C, 2.2V
+85°C, 3.6V
–40°C, 2.2V
–40°C, 3.6V
–40°C, 3.6V
+25°C, 2.2V
+25°C, 3.6V
+85°C, 2.2V
10
0
+85°C, 3.6V
–10
–10
–0.20 –0.15 –0.10 –0.05
0
0.05
0.10
0.15
0.20
–200 –175 –150 –125 –100 –75 –50 –25
0
25 50 75 100
FREQUENCY (kHz)
FREQUENCY (MHz)
Figure 16. Receiver Close-In Blocking vs. Temperature and VDD
,
Figure 13. Receiver Close-In Blocking vs. Temperature and VDD
,
Data Rate = 4.8 kbps, CW Interferer, Wanted Signal 3 dB Above the
Sensitivity Level of BER = 0.1%, BER-Based Test
Data Rate = 2.4 kbps, CW Interferer, Wanted Signal 3 dB Above the
Sensitivity Level of PER = 5%, PER-Based Test
Rev. 0 | Page 13 of 24
ADF7030
Data Sheet
110
100
90
80
70
60
50
40
30
20
10
0
110
100
90
80
70
60
50
40
30
20
10
0
–40°C, 2.2V
–40°C, 3.6V
+25°C, 2.2V
+25°C, 3.6V
+85°C, 2.2V
+85°C, 3.6V
–10
–10
–60 –50 –40 –30 –20 –10
0
10 20 30 40 50 60
–28 –24 –20 –16 –12 –8 –4
0
4
8
12 16 20 24 28
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17. Receiver Wideband Blocking, TA = 25°C, VDD = 3.6 V,
Data Rate = 2.4 kbps, CW Interferer, Wanted Signal 3 dB Above the
Sensitivity Level of PER = 5%, PER-Based Test
Figure 20. Receiver Wideband Blocking vs. Temperature and VDD,
Data Rate = 4.8 kbps, CW Interferer, Wanted Signal 3 dB Above the
Sensitivity Level of BER = 0.1%, BER-Based Test
110
100
90
80
70
60
50
40
30
20
10
0
2.0
ERROR (dB)
1.5
STANDARD DEVIATION (dB)
1.0
0.5
0
–0.5
–1.0
–1.5
–10
–2.0
–28 –24 –20 –16 –12 –8 –4
0
4
8
12 16 20 24 28
–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10
FREQUENCY (MHz)
RF INPUT POWER (dBm)
Figure 18. Receiver Wideband Blocking, TA = 25°C, VDD = 3.0 V,
Data Rate = 4.8 kbps, CW Interferer, Wanted Signal 3 dB Above the
Sensitivity Level of PER = 5%, PER-Based Test
Figure 21. RSSI Error vs. RF Input Power with One-Point Calibration at −70
dBm, VDD = 2.2 V, TA = 25°C (Error is Based on the Mean of
20 RSSI Measurements)
110
100
90
80
70
60
50
40
–40°C, 3.6V
–40°C, 2.2V
+25°C, 3.6V
+25°C, 2.2V
+85°C, 3.6V
+85°C, 2.2V
30
20
10
0
–10
–60 –50 –40 –30 –20 –10
0
10 20 30 40 50 60
FREQUENCY (MHz)
Figure 19. Receiver Wideband Blocking vs. Temperature and VDD
,
Data Rate = 2.4 kbps, CW Interferer, Wanted Signal 3 dB Above the
Sensitivity Level of BER = 0.1%, BER-Based Test
Rev. 0 | Page 14 of 24
Data Sheet
ADF7030
TRANSMITTER
PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the
range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output
power. This value can be programmed in the range of 2 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides
a microadjustment (typically <0.1 dB) of the PA output power. This value can be programmed in the range of 1 to 31 for both PA1 and PA2.
15
15
10
10
5
5
0
0
–5
–45°C, 3.6V
–45°C, 3.0V
–45°C, 2.2V
+25°C, 3.6V
+25°C, 3.0V
+25°C, 2.2V
+95°C, 3.6V
+95°C, 3.0V
+95°C, 2.2V
–10
–15
–20
–25
–30
–5
PA_COARSE = 1
PA_COARSE = 2
PA_COARSE = 3
PA_COARSE = 4
PA_COARSE = 5
PA_COARSE = 6
–10
–15
–20
2
12 22 32 42 52 62 72 82 92 102 112 122
PA_FINE SETTING
2
12 22 32 42 52 62 72 82 92 102 112 122
PA_FINE SETTING
Figure 24. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting,
DD =3.0 V, TA = 25°C
Figure 22. PA1 Output Power vs. PA_FINE Setting, Temperature, and VDD with
PA_COARSE = 6, Maximum Recommended Temperature = 85°C, Minimum
Recommended Temperature = −40°C; −45°C and +95°C Operation Only Shown
for Robustness
V
55
15
10
PA_COARSE = 1
PA_COARSE = 2
PA_COARSE = 3
PA_COARSE = 4
PA_COARSE = 5
PA_COARSE = 6
–45°C, 3.6V
–45°C, 3.0V
50
–45°C, 2.2V
45
40
35
30
25
20
15
10
+25°C, 3.6V
+25°C, 3.0V
+25°C, 2.2V
+95°C, 3.6V
+95°C, 3.0V
+95°C, 2.2V
5
0
–5
–10
–15
–20
–25
–30
–20
–15
–10
–5
0
5
10
15
2
20
PA_FINE SETTING
200
PA1 OUTPUT POWER (dBm)
Figure 23. VBATx Supply Current vs. PA1 Output Power, Temperature, and
Figure 25. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting
with PA_FINE on a Logarithmic Scale, VDD = 3.0 V, TA = 25°C
V
DD with PA_COARSE = 6, Maximum Recommended Temperature = 85°C,
Minimum Recommended Temperature = −40°C; −45°C and +95°C
Operation Only Shown for Robustness
Rev. 0 | Page 15 of 24
ADF7030
Data Sheet
15.0
14.5
14.0
13.5
13.0
12.5
12.0
13.4
13.3
13.2
13.1
13.0
12.9
12.8
12.7
12.6
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
PA_MICRO SETTING
2.2
3.0
3.6
SUPPLY VOLTAGE (V)
Figure 26. Microadjustment of the PA1 Output Power Using a PA_MICRO
Setting Around 13 dBm with PA_COARSE = 6 and PA_FINE = 100, VDD = 3.0 V,
Figure 29. PA1 Output Power vs. Supply Voltage (VDD), PA_COARSE = 6,
PA_FINE = 97, PA_MICRO = 16, TA = 25°C
T
A = 25°C
20
15
10
5
–17.5
–18.0
–18.5
–19.0
–19.5
–20.0
–20.5
–21.0
0
–45°C, 3.6V
–45°C, 3.0V
+25°C, 3.6V
+25°C, 3.0V
+95°C, 3.6V
+95°C, 3.0V
–5
–10
–15
2
12 22 32 42 52 62 72 82 92 102 112 122
PA_FINE SETTING
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
PA_MICRO SETTING
Figure 30. PA2 Output Power vs. PA_FINE Setting, Temperature, and VDD
,
Figure 27. Microadjustment of the PA1 Output Power Using a PA_MICRO
Setting Around −20 dBm with PA_COARSE = 6 and PA_FINE = 2,
PA_COARSE = 6, Maximum Recommended Temperature = 85°C, Minimum
Recommended Temperature = −40°C; −45°C and +95°C Operation Only
Shown for Robustness
VDD = 3.0 V, TA = 25°C
80
13.4
13.3
13.2
13.1
13.0
12.9
12.8
12.7
12.6
75
–45°C, 3.6V
70
65
60
55
50
45
40
35
30
25
20
15
10
–45°C, 3.0V
+25°C, 3.6V
+25°C, 3.0V
+95°C, 3.6V
+95°C, 3.0V
–16
–12
–8
–4
0
4
8
12
16
20
–45
25
95
PA2 OUTPUT POWER (dBm)
TEMPERATURE (°C)
Figure 31. VBATx Supply Current vs. PA2 Output Power, Temperature, and
Figure 28. PA1 Output Power vs. Temperature, PA_COARSE = 6, PA_FINE = 97,
PA_MICRO = 16, Maximum Recommended Temperature = 85°C, Minimum
Recommended Temperature = −40°C; −45°C and +95°C Operation Only
Shown for Robustness
V
DD, PA_COARSE = 10, Maximum Recommended Temperature = 85°C,
Minimum Recommended Temperature = −40°C; −45°C and +95°C
Operation Only Shown for Robustness
Rev. 0 | Page 16 of 24
Data Sheet
ADF7030
19.0
18.5
20
15
10
5
18.0
17.5
17.0
16.5
16.0
0
–5
PA_COARSE = 2
PA_COARSE = 3
PA_COARSE = 4
PA_COARSE = 5
PA_COARSE = 6
PA_COARSE = 7
PA_COARSE = 8
PA_COARSE = 9
PA_COARSE = 10
–10
–15
–20
–25
–30
2
12 22 32 42 52 62 72 82 92 102 112 122
PA_FINE SETTING
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31
PA_MICRO SETTING
Figure 32. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting,
Figure 34. Microadjustment of the PA2 Output Power Using a PA_MICRO
Setting Around 17 dBm, PA_COARSE = 10, PA_FINE = 100, VDD = 3.0 V, TA = 25°C
VDD = 3.0 V, TA = 25°C
20
15
–13.0
–13.5
–14.0
–14.5
–15.0
–15.5
–16.0
–16.5
10
5
0
–5
PA_COARSE = 2
PA_COARSE = 3
PA_COARSE = 4
PA_COARSE = 5
PA_COARSE = 6
PA_COARSE = 7
PA_COARSE = 8
PA_COARSE = 9
PA_COARSE = 10
–10
–15
–20
–25
–30
2
20
200
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31
PA_MICRO SETTING
PA_FINE SETTING
Figure 33. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting
with PA_FINE on a Logarithmic Scale, VDD = 3.0 V, TA = 25°C
Figure 35. Microadjustment of the PA2 Output Power Using a PA_MICRO
Setting Around −15 dBm, PA_COARSE = 10, PA_FINE = 2, VDD = 3.0 V, TA = 25°C
Rev. 0 | Page 17 of 24
ADF7030
Data Sheet
17.4
17.3
17.2
17.1
17.0
16.9
16.8
16.7
16.6
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
1k
10k
100k
1M
10M
–45
25
95
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 36. PA1 Output Power vs. Temperature, PA_COARSE = 10, PA_FINE = 93,
and PA_MICRO = 16; Maximum Recommended Temperature = 85°C, Minimum
Recommended Temperature = −40°C; −45°C and +95°C Operation Only
Shown for Robustness
Figure 38. Transmit Phase Noise, VDD = 3 V, TA = 25°C,
RF Frequency = 169.43125 MHz
17.4
17.3
17.2
17.1
17.0
16.9
16.8
16.7
16.6
3.0
3.6
SUPPLY VOLTAGE (V)
Figure 37. PA2 Output Power Stability vs. Supply Voltage (VDD),
PA_COARSE = 10, PA_FINE = 93, and PA_MICRO = 16, TA = 25°C
Rev. 0 | Page 18 of 24
Data Sheet
ADF7030
THEORY OF OPERATION
HOST INTERFACE
Table 10. Special Radio Commands
Physical Interface
Command
Description
CMD_SYSTEM_RESET
Performs a system reset of the
ADF7030
Configures the ADF7030 to use a
downloaded firmware module by
restarting the ADF7030
The ADF7030 provides a host interface (HIF) that consists of a
RST
4-wire standard SPI, a hardware reset pin (
), and GPIOs.
CMD_RAM_LOAD_DONE
The ADF7030 always acts as a slave to the host processor. The
host processor uses the SPI interface to perform the following
operations on the ADF7030:
CMD_IRQ1_DIS_IRQ0_DIS Disables IRQ_IN0 and IRQ_IN1 in
triggering preloaded radio
•
•
•
Reads and writes to the ADF7030 memory.
Configures and controls the ADF7030 radio.
Receives and transmits packets over the air.
commands
CMD_IRQ1_DIS_IRQ0_EN Disables IRQ_IN1 and enables
IRQ_IN0 in triggering preloaded
radio commands
CMD_IRQ1_EN_IRQ0_DIS Enables IRQ_IN1 and disables
IRQ_IN0 in triggering preloaded
Host Interface Protocol
The ADF7030 implements a very simple protocol over the SPI
interface. Using this protocol, the host processor can perform a
number of operations as described in the following sections.
radio commands
CMD_IRQ1_EN_IRQ0_EN
Enables IRQ_IN1 and IRQ_IN0 in
triggering preloaded radio
commands
Memory Access
The memory access commands allow the host processor to read
from and write to the internal memory of the ADF7030. Typically,
the host uses these commands to update the configuration of
the ADF7030 and to write packets for transmission or read
received packets.
Status Byte
The status byte of the ADF7030 (STATUS) is returned at
specific times over the MISO during an SPI transaction. The
status byte is described in Table 11.
Radio Commands
Table 11. Status Byte Description
There are two types of radio commands: a state machine radio
command and a special radio command. A state machine
command triggers a change of radio state as described in
Table 9. A special radio command generates specific actions,
such as to perform a system reset or to disable IRs as described
in Table 10.
Bit
Name
Description
7
SPI_READY
0: SPI is not ready for access
1: SPI is ready for access
0: no pending interrupt condition
1: pending interrupt condition
6
5
IRQ_STATUS
CMD_READY
0: the ADF7030 is not ready to
receive a radio command
Table 9. State Machine Radio Commands
Command
1: the ADF7030 is ready to receive
a radio command
Description
CMD_PHY_OFF
Performs a transition of the device into
the PHY_OFF state
Performs a transition of the device into
the PHY_ON state
Performs a transition of the device into
the PHY_RX state
4
3
Reserved
ERR
Reserved
0: no error
CMD_PHY_ON
CMD_PHY_RX
1: error (for example, an
unsupported destination state or
an internal error)
[2:1] TRANSITION_STATUS 0: transition in progress
1: executing in a state
CMD_PHY_TX
Performs a transition of the device into
the PHY_TX state
2: idle in a state
CMD_CONFIG_DEV
Configures the ADF7030 based on the
radio profile
0
Reserved
Reserved
CMD_GET_RSSI
Performs an RSSI measurement
CMD_RAM_LOAD_INIT Prepares the program RAM for a
firmware module download
CMD_DO_CAL
Executes selected calibration routines
Rev. 0 | Page 19 of 24
ADF7030
Data Sheet
Table 13. ADF7030 Firmware Modules
Firmware Module Functionality
RADIO STATE MACHINE
TheADF7030 operates as a simple state machine. The host
processor can transition the ADF7030 between states by issuing
single-byte commands over the SPI interface. The ADF7030
processor handles the sequencing of various radio circuits and
critical timing functions, thereby simplifying radio operation
and easing the burden on the host processor.
RAM_CODE_VX_XXT.DAT This module is the transmit firmware
module and supports all radio states,
except PHY_RX, CALIBRATING, and
MEASURE_RSSI. VX_XX refers to the
version number.
RAM_CODE_VX_XXR.DAT This module is the receive firmware
module and supports all radio
The ADF7030 has eight states designated as PHY_SLEEP,
PHY_OFF, PHY_ON, PHY_RX, PHY_TX, MEASURE_RSSI,
RAM_LOAD_INIT, and CALIBRATING, described in Table 12.
states, except PHY_TX and
CALIBRATING. VX_XX refers to the
version number.
RAM_CODE_VX_XXC.DAT This module is the calibrate
firmware module and supports all
radio states, except PHY_TX, PHY_RX,
and MEASURE_RSSI. VX_XX refers to
the version number.
Table 12. ADF7030 Radio States
State
Description
PHY_SLEEP
In this state, the ADF7030 is in a deep sleep
state with no configuration memory
retained.
PHY_OFF
PHY_ON
In this state, the ADF7030 executes using its
own internal oscillator clock. The host loads the
firmware module from this state. The host
configures the radio from this state.
In this state, the external reference clock
source is enabled. After entering this state,
the ADF7030 is ready for the transmission
and reception of packets.
In this state, the ADF7030 can receive and
process an incoming packet.
In this state, the ADF7030 transmits the
programmed packet data.
In this state, the ADF7030 continuously
measures the RSSI level in the selected
channel and stores this value in dBm for
access by the host. The ADF7030 remains in
this state until commanded to move back to
PHY_ON.
PACKET HANDLING
The ADF7030 includes comprehensive transmit and receive
packet management capabilities and can be configured for use
with a wide variety of packet-based radio protocols.
The ADF7030 can be programmed to transmit and receive
variable and fixed length packets. The packet data to be
transmitted must be written by the host processor into the
ADF7030 internal memory. Received packet data is available
from the ADF7030 internal memory.
PHY_RX
PHY_TX
There are 256 bytes of dedicated RAM available to store,
transmit, and receive packets. In transmit mode, a preamble,
sync word, and cyclic redundancy check (CRC) can be added by
the ADF7030 to the payload data stored in the RAM. In receive
mode, the ADF7030 can qualify received packets based on
preamble detection, sync word detection, or CRC validation.
On reception of a valid packet, the received payload data is
loaded to packet memory.
MEASURE_RSSI
RAM_LOAD_INIT In this state, the host can write a firmware
module to the ADF7030 RAM memory.
CALIBRATING
In this state, the ADF7030 executes a receive
radio calibration.
To transmit or receive a packet, the host processor must first
configure the ADF7030. Then, the host processor issues the
commands to place the ADF7030 into the PHY_RX state or the
PHY_TX state. After either state is entered, the ADF7030
automatically starts transmitting or receiving a packet.
Firmware Modules
The host must download firmware modules to the ADF7030
RAM to enable certain aspects of the radio state machine. There
are three firmware modules: transmit, receive, and calibrate.
These modules are described in Table 13.
The host can track the progress of the transmission or reception
of a packet by monitoring the interrupt signals coming from the
ADF7030. There are two independent logical interrupts from
the ADF7030, and events can be configured to trigger one or
both of these logical interrupts.
The ADF7030 provides two frames in its radio profile that give
flexibility in choosing what packet formats to use in the transmit
and receive operations. A frame can be configured to use one of
several packet formats; it is also possible to switch between these
formats before entering the PHY_TX state or the PHY_RX state.
Rev. 0 | Page 20 of 24
Data Sheet
ADF7030
The configurations ensure that the RF communication layer
SUPPORTED RADIO CONFIGURATIONS
operates seamlessly, thereby allowing the user to concentrate on
the protocol and system level design. Three radio configurations
are supported in total, described in Table 14.
To eliminate many of the RF related design challenges users
typically face, Analog Devices, Inc., provides a set of optimized
radio profile configurations for the ADF7030.
Table 14. Supported Radio Configurations
Data
Rate
(kbps)
Frequency Receiver
Operation
Supported
Deviation
Modulation (kHz)
Bandwidth
(kHz)
Channel
Spacing (kHz) Tolerance (kHz)
Receiver Frequency
Radio Profile
ADF7030_USECASE_0 Tx and Rx
ADF7030_USECASE_2 Tx and Rx
ADF7030_USECASE_9 Tx only
2.4
4.8
6.4
2GFSK
2GFSK
4GFSK
2.4
2.4
3.2
8.7
12.5
12.5
2
2
10.6
Not applicable Not applicable Not applicable
Rev. 0 | Page 21 of 24
ADF7030
Data Sheet
APPLICATIONS INFORMATION
operation of the device are shown. The bottom of the LFCSP
package has an exposed pad that must be soldered to ground on
the printed circuit board (PCB).
TYPICAL APPLICATION CIRCUIT
Typical application circuits for the ADF7030 are shown in
Figure 39 and Figure 40. All external components required for
TCXO
100kΩ
V
DD
26MHz
100nF
100pF
1.2nF
RST
40 39 38 37 36 35 34 33 32 31
V
DD
V
HOST
MICROPROCESSOR
DD
100nF
100pF
1
2
30
29
28
27
26
25
24
23
22
21
DNC
100kΩ
GPIO
VBAT1
GPIO6
CS
220nF
220nF
3
CREG1
VBAT2
CREG2
LNAIN1
LNAIN2
DNC
CS
4
SCLK
MISO
MOSI
VBAT5
VBAT4
GPIO5
GPIO4
SCLK
MISO
MOSI
INT2
5
ADF7030
6
V
DD
7
V
DD
100pF
100nF
8
INT1
220nF
100pF
9
CREG3
DNC
Rx MATCH
100pF
100nF
10
11 12 13 14 15 16 17 18 19 20
100kΩ
100kΩ
220nF
HARMONIC
FILTER
V
DD
PA1 MATCH
100pF
100nF
HARMONIC
FILTER
PA2 MATCH
Figure 39. Application Circuit with Both PAs and LNA Matched, Without External PA or Tx/Rx Switch
Rev. 0 | Page 22 of 24
Data Sheet
ADF7030
TCXO
100kΩ
V
DD
26MHz
100nF
100pF
1.2nF
RST
40 39 38 37 36 35 34 33 32 31
V
DD
V
HOST
MICROPROCESSOR
DD
100nF
100pF
1
2
30
29
28
27
26
25
24
23
22
21
DNC
100kΩ
GPIO
VBAT1
GPIO6
CS
220nF
220nF
3
CREG1
VBAT2
CREG2
LNAIN1
LNAIN2
DNC
CS
4
SCLK
MISO
MOSI
VBAT5
VBAT4
GPIO5
GPIO4
SCLK
MISO
MOSI
INT2
5
ADF7030
6
V
DD
100nF
7
V
DD
100pF
8
INT1
220nF
9
CREG3
DNC
Rx MATCH
100pF
100nF
10
100pF
HARMONIC
FILTER
11 12 13 14 15 16 17 18 19 20
100kΩ
100kΩ
220nF
PA
HARMONIC
FILTER
V
DD
OPTIONAL
GPIO CONNECTIONS
FROM ADF7030
PA1 MATCH
100pF
100nF
Figure 40. Application Circuit with Tx/Rx Switch and External PA
Rev. 0 | Page 23 of 24
ADF7030
Data Sheet
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
40
1
30
0.50
BSC
4.60
4.50 SQ
4.40
EXPOSED
PAD
10
21
11
20
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 41. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CP-40-17
CP-40-17
ADF7030BCPZN
ADF7030BCPZN-RL
EVAl-ADF7030DB7Z
EVAL-ADF7XXXMB4Z
−40°C to +85°C
−40°C to +85°C
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board (RF Daughter Board)
Evaluation Board (Motherboard)
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11299-0-7/15(0)
Rev. 0 | Page 24 of 24
相关型号：
ADF7242BCPZ
SPECIALTY TELECOM CIRCUIT, QCC32, 5 X 5 MM, ROHS COMPLIANT, MO-220WHHD, LFCSP-32
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