ADF7901BRUZ-RL [ADI]
High Performance ISM Band ASK/FSK Transmitter IC;
| 型号： | ADF7901BRUZ-RL |
| 厂家： | 
ADI |
| 描述： | High Performance ISM Band ASK/FSK Transmitter IC ISM频段 |
| 文件： | 总12页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance ISM Band
ASK/FSK Transmitter IC
Preliminary Technical Data
ADF7901
is capable of Frequency Shift Keying (FSK) modulation on
8 different channels, selectable by 3 external control lines. OOK
modulation is performed by modulating the PA control line.
FEATURES
Single chip low power UHF transmitter
369.5 MHz to 395.9 MHz frequency operation using
Fractional-N
PLL and fully integrated VCO
The on-chip VCO operates at 2 × the output frequency. The
divide by 2 at the output of the VCO reduces the amount of PA
feedthrough. As a result of this, OOK modulation depths of
greater than 50 dB are easily achievable.
3.0 V supply voltage
Data rates supported < 2.5 kbps
Low current consumption 26 mA at 12 dBm
Output at 384 MHz
Power-down mode (< 1 µA)
24-Lead TSSOP package
The FSK_ADJ and ASK_ADJ resistors can be adjusted in the
system to optimize output power, for each modulation scheme.
An additional 1.5 dB of output power is provided for the lower
bank of channels to adjust for antenna performance. The CE
line allows the transmitter to be powered down completely. In
this mode, the leakage current is typically 0.1 µA.
GENERAL DESCRIPTION
The ADF7901 is a low power OOK/FSK UHF transmitter
designed for use in RF Remote Control Devices. The device
FUNCTIONAL BLOCK DIAGRAM
C
REG2
PA_EN
C
VCO
OSC1
OSC2
V
DD
VCO
RF
OUT
PA
DV
DD
R = 1
RF
GND
PDF
CHARGE
PUMP
C
REG1
LDO
REGULATOR
#1
÷ FRACTIONAL N
LDO
REGULATOR
#2
C
2
REG
TXDATA
SIGMA-DELTA
FSK
CHANNEL SELECT
RS ET
OOK_SEL
CE
D
FSK1 FSK2 FSK3
GND
RSET_FSK
RSET_OOK
Figure 1.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
ADF7901
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Circuit Description........................................................................... 9
Internal Register Settings ............................................................ 9
Loop Filter ..................................................................................... 9
Layout Guidelines....................................................................... 10
Decoupling.............................................................................. 10
Regulator Stability.................................................................. 10
Grounding............................................................................... 10
Supply ...................................................................................... 10
Digital Lines............................................................................ 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
1/05—Revision PrD
Rev. PrD | Page 2 of 12
Preliminary Technical Data
ADF7901
SPECIFICATIONS
VDD =3.0 V; GND = 0 V; TA = TMIN to TMAX unless otherwise noted. Typical specifications TA = 25°C.
Table 1.
Parameter1
Min
Typ
Max
Unit
RF CHARACTERISTICS
Output Frequency Ranges
Channel 1
369.5
371.1
375.3
376.9
384.0
388.3
391.5
394.3
395.9
9.8304
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Phase Frequency Detector Frequency
TRANSMISSION PARAMETERS
Transmit Rate
FSK
2
2.5
kbps
kbps
OOK
Frequency Shift Keying
FSK Separation2
−34.8
+34.8
kHz, Data = 1
kHz, Data = 0
On/Off Keying
Modulation Depth3
83
dB, Output Power = 12 dBm
Output Power
Min/Max Range4
15
dB
fOUT ≤ 384 MHz
fOUT > 384 MHz
10
7
12
10.5
dBm
dBm
Occupied 20 dB BW
OOK at 1 kbits/s
28
26
461.9
461.9
kHz
kHz
FSK (PA Off/On) at10 Hz5
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
POWER SUPPLIES
2.124
V
V
µA
pF
0.2 × VDD
1
10
Voltage Supply
DVDD
3.0
V
Transmit Current Consumption
369.5–376.9 MHz at +12 dBm
384 MHz at +12 dBm
388.3–395.9 MHz at +10.5 dBm
384 MHz at +5 dBm
Power-Down Mode
Low Power Sleep Mode6
26
26
21
17
mA
mA
mA
mA
0.2
1
µA
Rev. PrD | Page 3 of 12
ADF7901
Preliminary Technical Data
Parameter1
Min
Typ
Max
Unit
PHASE-LOCKED LOOP
VCO Gain
30
MHz/V at 384 MHz
100 kHz loop BW
Spurious7,
3
Integer Boundary
Reference
–45
−70
−23
−23
dBc
dBc
Harmonics
3
Second Harmonic VDD = 3.0 V
Third Harmonic VDD = 3.0 V
All Other Harmonics
−24
−14
−21
−11
−18
dBc
dBc
dBc
REFERENCE INPUT
Crystal Reference
POWER AMPLIFIER
PA Output Impedance
9.8304
MHz
97 Ω + 6.4
pF
At 384 MHz
TIMING INFORMATION
Crystal Oscillator to PLL Lock
3
2
100
3
250
50
ms
µs
°C
PA Enable to PA ready–PLL Settle8
TEMPERATURE RANGE – TA
0
1 Operating temperature range is as follows: 0°C to +50°C.
2 Frequency Deviation = 34 × (9.8304 MHz )/214. Error in the crystal will be reflected in variation in the desired deviation.
3 Not production tested. Based on characterization.
4 The output power can be varied in both ASK/FSK mode by altering the relevant external resistor.
5 Measured using Spectrum Analyzer, 1 MHz span, 100 kHz RBW, MAX HOLD enabled.
6 Maximum power-down current spec applies for the OSC2 pin grounded.
7 Measured > 461.9 kHz away from channel.
8 This spec refers to the time taken for the PLL to regain lock after the PA has been enabled. The PA is should only be enabled after the PLL has settled to the correct
frequency.
Rev. PrD | Page 4 of 12
Preliminary Technical Data
ADF7901
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter1
Value
VDD to GND2
RFVDD to GND
−0.3 V to +4.0 V
−0.3 V to +4.0 V
−0.3 V to VDD + 0.3 V
Digital I/O Voltage to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
0°C to +50°C
−65°C to +125°C
125°C
150.4°C/W
235°C
240°C
Infrared (15 sec)
1 This device is a high performance RF integrated circuit with an ESD rating of
<1 kV and it is ESD sensitive. Proper precautions should be taken for
handling and assembly.
2 GND = RFGND = DGND = 0 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrD | Page 5 of 12
ADF7901
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
C
DV
1
24
REG2
DD
C
2
23
REG1
R
SET
CP
3
22 PA_EN
OUT
DV
TxDATA
4
21
20
19
18
17
16
15
14
13
DD
D
5
GND
RF
RF
OUT
ADF7901
NC
6
GND
TOP VIEW
(Not to Scale)
D
7
GND
VCO
IN
OSC1
OSC2
8
C
VCO
9
RSET_FSK
RSET_OOK
CE
10
OOK_SEL
FSK1 11
12
FSK3
FSK2
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Function
1
2
3
DVDD
CREG1
CPOUT
Positive Supply for the Digital Circuitry. This must be 3.0 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin.
A 2.2 µF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor
will improve regulator power-on time but may cause higher spurious.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated
current changes the control voltage on the input to the VCO.
Digital FSK data to be transmitted is inputted on this pin.
Ground for Digital Section.
4
TxDATA
5
6
7
8
DGND
NC
DGND
OSC1
No Connect.
Ground for Digital Section.
The reference crystal should be connected between this pin and OSC2. The necessary crystal load capacitor
should be tied between this pin and ground.
9
OSC2
The reference crystal should be connected between this pin and OSC1. The necessary crystal load capacitor
should be tied between this pin and ground.
A high on this pin selects operation in OOK mode at 384 MHz when CE is high.
FSK Channel Select Pin. This represents the LSB of the channels select pins
10
OOK_SEL
11
12
13
FSK1
FSK2
FSK3
FSK Channel Select Pin.
FSK Channel Select Pin.
Bringing CE low puts the ADF7901 into power-down drawing < 1 µA of current.
14
15
CE
RSET_OOK
The value of this resistor sets the output power for data = 1 in OOK mode. A resistor of 3.6 kΩ will provide the
maximum output power. Increasing the resistor will reduce the power and the current consumption. A lower
resistor value than 3.6 kΩ can be used to increase the power to a maximum of +14 dBm. The PA will not be
operating efficiently in this mode.
16
RSET_FSK
The value of this resistor sets the output power in FSK mode. A resistor of 3.6 kΩ will provide max output power.
Increasing the resistor will reduce the power and the current consumption. A lower resistor value than 3.6 kΩ can
be used to increase the power to a maximum of +14 dBm. The PA will not be operating efficiently in this mode.
17
18
CVCO
A 220 nF capacitor should be tied between CVCO and CREG2 pin. This line should run underneath the ADF7901.
This capacitor is necessary to ensure stable VCO operation.
The tuning voltage on this pin determines the output frequency of the Voltage Controlled Oscillator (VCO).
The higher the tuning voltage the higher the output frequency. The output of the loop filter is connected here.
VCOIN
19
20
RFGND
RFOUT
Ground for Output Stage of Transmitter.
The modulated signal is available at this pin. Output power levels are from –5 dBm to +12 dBm. The output
should be impedance matched using suitable components to the desired load.
21
DVDD
Voltage Supply for VCO, and PA section. This should be supplied with 3.0 V. Decoupling capacitors to the ground
Rev. PrD | Page 6 of 12
Preliminary Technical Data
ADF7901
Pin No. Mnemonic
Function
plane should be placed as close as possible to this pin.
22
PA_EN
This pin is used to enable the Power Amplifier. This should be modulated with the OOK data in OOK mode. In
FSK mode, it should be enabled when the PLL is locked.
23
24
RSET
CREG2
External resistor to set charge pump current and some internal bias currents. Use 3.6 kΩ as default.
A 2.2 µF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor
will improve regulator power-on time but may cause higher spurious.
Rev. PrD | Page 7 of 12
ADF7901
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Mkr1 10.00kHz
Noise –89.55dB/Hz
Ref 15dBm
Avg
Atten 30dB
16
Log
1R
10
dB/
12
8
RBW
300.0000000Hz
PAvg
1
W1 S2
S3 FS
AA
4
£(f):
f<50k
Swp
0
2
3
4
5
6
7
8
9
10
Center 395.948 29MHz
#Res BW 300Hz
Span 50kHz
Sweep 2.118 s (601 pts)
VBW 300Hz
RSET
Figure 5. Phase Noise at Channel 9
Figure 3. Output Power vs. RSET FSK, Upper FSK Channels, Measured into 50 Ω
Mkr4 1.59GHz
–21.30dB
Ref 15dBm
Peak
Atten 30dB
35
30
Log
10
dB/
Marker Trace Type X Axis
Amplitude
Freq 400MHz –25.56dB
Freq 800MHz –13.89dB
Freq 1.19GHz –34.53dB
Freq 1.59GHz –21.30dB
4R
1
2
3
4
(1)
(1)
(1)
(1)
2
4
1
3
25
20
15
10
LgAv
Center 5.50GHz
#Res BW 1MHz
4
5
6
7
8
9
10
Span 10.5GHz
Sweep 17.52 ms (601 pts)
VBW 1MHz
OUTPUT POWER (dBm)
Figure 4. Current Consumption vs. Output Power, Upper FSK Channels,
Figure 6. Harmonic Levels–Up to 4th Harmonic. Measured at Channel 9
Measured into 50 Ω
in to 50 Ω
Rev. PrD | Page 8 of 12
Preliminary Technical Data
ADF7901
CIRCUIT DESCRIPTION
Table 4.
REG3
PLL Enable 1
PA Enable (PA_EN Line)
CLKout EN 0 (Off)
Data Invert 0
Charge Pump 1 (3/7)
CP Bleed 0
MuxOut 0
VCOBias 3
Frequency MHz
FSK3
FSK2
FSK1
OOK_SEL
369.5
371.1
375.3
376.9
384.0
388.3
391.5
394.3
0
0
0
0
X
1
1
1
1
0
0
1
1
X
0
0
1
1
0
1
0
0
X
0
1
0
1
0
0
0
0
1
0
0
0
0
PA Bias External R
VCO Band (Switched)
395.9
INTERNAL REGISTER SETTINGS
LOOP FILTER
Based on PFD = 9.8304 MHz
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. The loop filter design recommended on this design is
300 kHz. This is based on the trade-off between attenuation of
beat note spurious and the need to minimize chirp when the PA
is turned on.
REG0
Error Correction 0
R Value 1
XOE 1 (Enabled)
Clock Out 0 (Disabled)
REG1
Ch #1 Integer = 37, Frac = 2406
Ch #2 Integer = 37, Frac = 3073
Ch #3 Integer = 38, Frac = 727
Ch #4 Integer = 38, Frac = 1394
Ch #5(OOK) Integer = 39, Frac = 256
Ch #6 Integer = 39, Frac = 2048
Ch #7 Integer = 39, Frac = 3381
Ch #8 Integer = 40, Frac = 452
Ch #9 Integer = 40, Frac = 1118
VCO Band 1 (Divide-by-2)
LD Precision 1 (Don’t care)
CHARGE
PUMP OUT
VCO
Figure 7.
C1 = 680 pF
C2 = 15 nF
C3 = 150 pF
R1 = 120 Ω
R2 = 3.3 kΩ
REG2
Mod Scheme 0 (FSK)
PA (External R)
Mod Deviation 58 ( 35 kHz)
Prescaler 0 (4/5)
Rev. PrD | Page 9 of 12
ADF7901
Preliminary Technical Data
2.2mF
2.2mF
C
220nF
C
MATCHING RFOUT TO 50V
DV
C
DD
REG1
VCO REG2
R
SET
27nH
5.6pF
5TH ORDER LOW PASS FILTER
3.6kΩ
1.5pF
22nH
22nH
RF
OUT
ANTENNA
36nH
3pF
8pF
3pF
VCO
CP
OUT
IN
VCO
IN
ADF7901
MATCHING 50 V
TO ANTENNA
RSET_FSK
RSET_OOK
3.6kΩ
3.6kΩ
TxDATA
FSK1
FSK2
OSC2
OSC1
FSK3
9.8304MHz
OOK_SEL
PA_EN
33pF 33pF
CE
GND
NOTES
1. DECOUPLING CAPACITORS HAVE
BEEN OMITTED FOR CLARITY.
Figure 8. Applications Diagram for the ADF7901 in a Remote Control System
Grounding
LAYOUT GUIDELINES
Emphasis should be placed on the grounding once the
decoupling capacitors have been added. The PA stage switches
currents of 15 mA in max power mode. This will cause changes
in the ground resulting in large return currents which can
radiate to other parts of the board. The shortest and least
obstructed ground from RFGND back to the ground of the
battery should be ensured. A 4-layer board will help, as well as
flooding of the top layer. The ground paths should not have any
vias, and should be wide tracks.
The layout of the board is crucial to ensuring low levels of
spurious and harmonics.
Decoupling
Decoupling capacitors (high frequency 22 pF, low frequency
100 nF) should be placed as close as possible to the supply pins
on the part. Low size 0402 and 0603 components are recom-
mended for the high frequency rejection on the supply.
Regulator Stability
Supply
A minimum of 1 µF is needed on both CREG1 and CREG2 to ensure
stability. An additional 22 pF capacitor can be added to reject
higher frequency noise. Since many of the internal block run off
the regulator it is critical to reduce the noise on this. Low size
0402 and 0603 components are recommended for the high
frequency rejection on the supply.
The supply tracks can be routed through vias, as these act as
free inductors on the board and make layout easier on a 2-layer
board. See the Decoupling section. Tracks should be wide.
Digital Lines
Any digital lines should contain a large resistor in series. This
impedance will block signals of many frequencies including
harmonics and the carrier frequency. Long control lines can act
as an antenna. It can be useful to add capacitance to ground.
There will be some capacitance to ground provided by the lines,
and at the input of the digital pins.
Rev. PrD | Page 10 of 12
Preliminary Technical Data
OUTLINE DIMENSIONS
ADF7901
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AD
Figure 9. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
RU-24
ADF7901BRU
0°C to +50°C
24-Lead Thin Shrink Small Outline Pacakage [TSSOP]
Rev. PrD | Page 11 of 12
ADF7901
NOTES
Preliminary Technical Data
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05349–0–1/05(PrD)
Rev. PrD | Page 12 of 12
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ADI
ADF7901BRUZ-RL7
TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PDSO24, LEAD FREE, MO-153AD, TSSOP-24
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