ADF7902BRUZ-RL71 [ADI]
ISM Band FSK Receiver IC; ISM频段FSK接收器IC
| 型号： | ADF7902BRUZ-RL71 |
| 厂家： | 
ADI |
| 描述： | ISM Band FSK Receiver IC |
| 文件： | 总12页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISM Band
FSK Receiver IC
ADF7902
FEATURES
GENERAL DESCRIPTION
Single-chip, low power UHF receiver
Companion receiver to ADF7901 transmitter
Frequency range: 369.5 MHz to 395.9 MHz
Eight RF channels selectable with three digital inputs
Modulation parameters supported
FSK demodulation
2 kbps data rate
34.8 kHz frequency deviation
5.0 V supply voltage
The ADF7902 is a low power UHF receiver. The device demodu-
lates frequency shift keyed (FSK) signals with 34.8 kHz frequency
deviation and at data rates of up to 2 kbps. There are eight specific
RF channels ranging from 369.5 MHz to 395.9 MHz on which the
receiver can operate. Each channel is selectable by configuring
three digital control lines.
The ADF7902 is designed for low power applications, consuming
18.5 mA (typical) during normal operation and 1 μA (maximum)
in standby mode.
Low power consumption
18.5 mA with receiver enabled
1 μA standby current
24-lead TSSOP
FUNCTIONAL BLOCK DIAGRAM
GND
CE
ADF7902
LNA_1
LNA
FSK
DEMODULATOR
IF FILTER
Rx_DATA
LNA_2
VBAT1
LDO1
CREG1
CH1_SEL
CH2_SEL
CH3_SEL
N DIVIDER
SELECT
VBAT2
LDO2
CREG2
VCO
CLKOUT
CP
PFD
OSC
LNA_RSET
BIAS
CLKOUT_ENB
RSET CVCO
VCOIN
CPOUT
OSC1 OSC2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADF7902
TABLE OF CONTENTS
Typical Performance Characteristics ..............................................6
Applications Information.................................................................7
Applications Circuits ....................................................................7
Test Modes..........................................................................................9
Outline Dimensions....................................................................... 10
Ordering Guide .......................................................................... 10
Features .............................................................................................. 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADF7902
SPECIFICATIONS
VDD =5.0 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Typical specifications TA = 25°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
CHANNEL FREQUENCIES
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
369.5
371.1
375.3
376.9
388.3
391.5
394.3
395.9
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
RECEIVER PARAMETERS
Data Rate
Frequency Deviation
2
kbps
kHz
kHz
dBm
Ω
−34.8
+34.8
−110
128 − j125
Data = 0
Data = 1
Input Sensitivity
LNA Input Impedance
CHANNEL FILTERING
IF Filter Bandwidth
fRF = 388.3 MHz
200
60
kHz
dB
−3 dB bandwidth
1 MHz offset
Adjacent Channel Rejection
Desired signal 3 dB above input sensitivity level,
with interferer power increased until BER = 10−3
PHASE-LOCKED LOOP
CE High to Receive Data
REFERENCE INPUT
Crystal Reference
4
ms
9.8304
MHz
25 ppm frequency accuracy
INPUT LOGIC LEVELS
Input High Voltage, VIH
Input Low Voltage, VIL
OUTPUT LOGIC LEVELS
Output High Voltage, VOH
Output Low Voltage, VOL
Output Drive Level
POWER SUPPLY
0.7 × VDD
4.5
V
V
0.2 × VDD
V
V
mA
0.4
2
Voltage Supply
VDD
5
V
Current Consumption
Receiver Enabled
Low Power Sleep Mode
18.5
mA
μA
CE = 1
CE = 0
1
Rev. 0 | Page 3 of 12
ADF7902
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
VBAT to GND1
Digital I/O Voltage to GND
LNA_1, LNA_2
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +6.0 V
−0.3 V to VBAT + 0.3 V
0 dBm
Operating Temperature Range
Industrial (B Version)
−40°C to +85°C
−40°C to +125°C
125°C
Storage Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
ESD CAUTION
150.4°C/W
235°C
240°C
Infrared (15 sec)
1 GND = GND1 = GND1B = GND2 = 0 V.
Rev. 0 | Page 4 of 12
ADF7902
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CREG2
TEST
1
24 VCOIN
2
23
22
21
20
GND2
VBAT2
3
CVCO
CE
Rx_DATA
GND1
4
RSET
5
LNA_RSET
ADF7902
TOP VIEW
6
19 LNA_1
CH1_SEL
CH2_SEL
CLKOUT
7
18
(Not to Scale)
LNA_2
8
17
16
CREG1
VBAT1
9
10
11
12
CH3_SEL
CLKOUT_ENB
CPOUT
15 OSC1
14 OSC2
13
GND1B
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
CREG2
A 0.1 μF capacitor should be added at CREG2 to reduce regulator noise and improve stability. A reduced
capacitor improves regulator power-on time but may cause higher spurs.
2
3
TEST
VBAT2
Test Output Pin. Leave as no connect.
5 V Power Supply for RF Circuitry. Decoupling capacitors to the analog ground plane should be placed as close
as possible to this pin.
4
5
6
7
8
9
CE
Rx_DATA
GND1
CH1_SEL
CH2_SEL
CLKOUT
Chip Enable Input. Driving CE low puts the part into power-down mode, drawing <1 μA.
Receiver Output. Demodulated data appears on this pin.
Ground for Digital Circuitry.
Channel Select Pin. This represents the LSB of the channel select pins.
Channel Select Pin.
Square Wave Clock Output at the Crystal Frequency. This can be used to drive the OSC2 pin of a partnering
ADF7902. The output has a 50:50 mark-space ratio and switches between 0 V and 2.2 V. If CLKOUT is disabled
by setting Pin 11 high, then CLKOUT must be tied low.
10
11
CH3_SEL
Channel Select Pin.
CLKOUT_ENB CLKOUT Enable Input. This should be driven low to enable the reference clock signal to appear on the CLKOUT pin.
Driving the pin high removes the clock signal on CLKOUT. It should be driven high when an external reference is used.
12
CPOUT
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated
current changes the control voltage on the input to the VCO.
13
14
GND1B
OSC2
Ground for Digital Circuitry.
The reference crystal should be connected between this pin and OSC1. The necessary crystal load capacitor
should be tied between this pin and ground. A square wave signal can be applied to this pin as an external
reference source.
15
OSC1
The reference crystal should be connected between this pin and OSC2. The necessary crystal load capacitor
should be tied between this pin and ground. This pin should be connected to ground when OSC2 is driven by an
external reference.
16
17
18
VBAT1
CREG1
LNA_2
5 V Power Supply for Digital Circuitry. Decoupling capacitors to the analog ground plane should be placed as
close as possible to this pin.
A 0.1 μF capacitor should be added at CREG1 to reduce regulator noise and improve stability. A reduced
capacitor improves regulator power-on time but may cause higher spurs.
LNA Input. Input matching is required between the antenna and the differential LNA input to ensure maximum
power transfer.
19
20
21
22
LNA_1
LNA_RSET
RSET
Complementary LNA Input.
External Bias Resistor for LNA. A value of 1.1 kꢀ is recommended.
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. A value of 3.6 kꢀ is recommended.
Voltage Controlled Oscillator (VCO) Capacitor. A 22 nF capacitor should be placed between this pin and CREG2
to reduce VCO noise.
CVCO
23
24
Ground for RF Circuitry.
GND2
VCOIN
The tuning voltage on this pin determines the output frequency of the VCO. The higher the tuning voltage,
the higher the output frequency. The output of the loop filter is connected here.
Rev. 0 | Page 5 of 12
ADF7902
TYPICAL PERFORMANCE CHARACTERISTICS
0
70
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CARRIER ONLY
INTERFERER SIGNAL
–1
60
–2
–3
50
40
–4
–5
30
FSK INTERFERER SIGNAL
20
–6
–7
10
0
–8
–125
–10
375.5
–120
–115
–110
–105
–100
376.0
376.50
377.0
377.5
378.0
378.5
RF INPUT LEVEL (dBm)
FREQUENCY (MHz)
Figure 3. Narrow-Band Interference Rejection Plot
Figure 5. Sensitivity Plot
100
80
60
40
20
0
CARRIER ONLY
INTERFERER SIGNAL
FSK INTERFERER SIGNAL
355
365
375
385
395
FREQUENCY (MHz)
Figure 4. Wideband Interference Rejection Plot
Rev. 0 | Page 6 of 12
ADF7902
APPLICATIONS INFORMATION
Table 4. Channel Frequency Truth Table
CH1_SEL
CH2_SEL
CH3_SEL
Channel Frequency (MHz)
0
1
0
1
0
1
0
1
0
0
0
1
1
0
1
1
0
0
1
0
0
1
1
1
369.5
371.1
375.3
376.9
388.3
391.5
394.3
395.9
APPLICATIONS CIRCUITS
22nF
VCOIN
GND2
CREG2
TEST
VBAT2
CE
0.1µF
62pF
ADF7902
5V
ANTENNA
CVCO
RSET
MICROCONTROLLER
3.6kΩ
1.1kΩ
0.1µF
MATCHING
Rx_DATA
GND1
LNA_RSET
LNA_1
LNA_2
CREG1
VBAT1
OSC1
10pF
CH1_SEL
CH2_SEL
CLKOUT
68nH
3.9pF
5V
0.1µF
CH3_SEL
CLKOUT_ENB
62pF
9.8304MHz
5V
OSC2
0.1µF
33pF
33pF
GND2
CPOUT
CRYSTAL
3.3kΩ
820Ω
680pF
LOOP FILTER
150pF
15nF
Figure 6. Single Receiver Applications Circuit
Rev. 0 | Page 7 of 12
ADF7902
22nF
VCOIN
GND2
CVCO
RSET
CREG2
TEST
VBAT2
CE
0.1µF
62pF
ADF7902
(Rx1)
5V
MICROCONTROLLER
3.6kΩ
1.1kΩ
0.1µF
MATCHING
6.8pF
Rx_DATA
GND1
LNA_RSET
LNA_1
CH1_SEL
CH2_SEL
CLKOUT
LNA_2
62nH
3.9pF
CREG1
5V
VBAT1
OSC1
OSC2
GND2
0.1µF
CH3_SEL
CLKOUT_ENB
62pF
Y1
0.1µF
33pF
33pF
CRYSTAL
CPOUT
ANTENNA
3.3kΩ
820Ω
680pF
LOOP FILTER
150pF
15nF
22nF
VCOIN
GND2
CREG2
TEST
0.1µF
62pF
ADF7902
5V
VBAT2 (Rx2)
CVCO
RSET
3.6kΩ
1.1kΩ
CE
0.1µF
MATCHING
10pF
Rx_DATA
GND1
LNA_RSET
LNA_1
LNA_2
CREG1
VBAT1
OSC1
CH1_SEL
CH2_SEL
CLKOUT
68nH
5V
3.9pF
0.1µF
CH3_SEL
CLKOUT_ENB
0.1µF
62pF
5V
OSC2
GND2
CPOUT
3.3kΩ
820Ω
680pF
LOOP FILTER
150pF
15nF
Figure 7. Dual Receiver Applications Circuit
Rev. 0 | Page 8 of 12
ADF7902
TEST MODES
If CLKOUT_ENB is tied high, CLKOUT is disabled. The
CLKOUT pin is reconfigured as a test enable input. If the
CLKOUT pin is then tied low, the part operates as is normal
with CLKOUT off. If it is tied high (2.2 V), the part is in test
mode. Test mode is described in Table 5.
When CLKOUT_ENB = 0, RSSI appears on the test output pin
(Pin 2), and CLKOUT is configured as an output with a 9.8 MHz
clock coming out.
When test mode is enabled, the channel frequency is set to
369.5 MHz (Channel 1).
Table 5. Test Modes
CH1_SEL
CH2_SEL
CH3_SEL
Test Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
agc gain is set to maximum (filti is also set to maximum on test output pin)
filti on test output pin
filtq on test output pin
Charge pump output is set to maximum (test pin is also tri-state)
Charge pump output is set to minimum (also n-divider output ÷ 2 on test output pin)
Charge pump is tri-state (test pin is also tri-state)
n-divider output ÷ 2 on test output pin
Recovered data clock on test output pin
Rev. 0 | Page 9 of 12
ADF7902
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 8. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADF7902BRUZ1
ADF7902BRUZ-RL1
ADF7902BRUZ-RL71
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP], 13’’REEL RU-24
24-Lead Thin Shrink Small Outline Package [TSSOP], 7’’REEL
RU-24
RU-24
1 Z = Pb-free part.
Rev. 0 | Page 10 of 12
ADF7902
NOTES
Rev. 0 | Page 11 of 12
ADF7902
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06456-0-4/07(0)
Rev. 0 | Page 12 of 12
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