ADG1208YCPZ-REEL71 [ADI]
Low Capacitance, 4-/8-Channel 15 V/12 V iCMOS Multiplexers; 低电容，4 / 8通道15 V / 12 V的iCMOS多路复用器
| 型号： | ADG1208YCPZ-REEL71 |
| 厂家： | 
ADI |
| 描述： | Low Capacitance, 4-/8-Channel 15 V/12 V iCMOS Multiplexers |
| 文件： | 总20页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Capacitance, 4-/8-Channel,
± ±1 ꢀ/ꢁ±ꢂ ꢀ iCMOS Multiplexers
ADG±ꢂ08/ADG±ꢂ09
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
<1 pC charge injection over full signal range
1 pF off capacitance
33 V supply range
ADG1208
ADG1209
S1
S1A
S4A
DA
DB
120 Ω on resistance
Fully specified at 1ꢀ V/+12 V
3 V logic compatible inputs
Rail-to-rail operation
Break-before-make switching action
Available in 16-lead TSSOP, 4 mm × 4 mm LFCSP_VQ, and
16-lead SOIC
D
S1B
S4B
S8
1-OF-8
DECODER
1-OF-4
DECODER
Typical power consumption < 0.03 μW
A0 A1 A2 EN
A0 A1 EN
APPLICATIONS
Figure 1.
Audio and video routing
Automatic test equipment
Data-acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
GENERAL DESCRIPTION
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data acquisition
and sample-and-hold applications, where low glitch and fast
settling are required. Figure 2 shows that there is minimum
charge injection over the entire signal range of the device.
iCMOS construction also ensures ultralow power dissipation,
making the parts ideally suited for portable and battery-
powered instruments.
The ADG1208 and ADG1209 are monolithic, iCMOS® analog
multiplexers comprising eight single channels and four differential
channels, respectively. The ADG1208 switches one of eight
inputs to a common output as determined by the 3-bit binary
address lines A0, A1, and A2. The ADG1209 switches one of
four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An
EN input on both devices is used to enable or disable the device.
When disabled, all channels are switched off. When on, each
channel conducts equally well in both directions and has an
input signal range that extends to the supplies.
1.0
MUX (SOURCE TO DRAIN)
T
= 25°C
A
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metal-
oxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
V
V
= +15V
= –15V
DD
SS
V
V
= +12V
= 0V
DD
SS
0.1
0
V
V
= +5V
= –5V
DD
SS
–15
–10
–5
0
5
10
15
V
(V)
S
Figure 2. Source to Drain Charge Injection vs. Source Voltage
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved.
ADG±ꢂ08/ADG±ꢂ09
TABLE OF CONTENTS
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions............................8
Typical Performance Characteristics ........................................... 10
Terminology.................................................................................... 14
Test Circuits..................................................................................... 15
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
REVISION HISTORY
1/09—Rev. A to Rev. B
Change to IDD Parameter, Table 1 ................................................... 4
Change to IDD Parameter, Table 2 ................................................... 6
4/07—Rev. 0 to Rev. A
Added 16-lead SOIC ..........................................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Figure 10 and Figure 11............................................. 10
Updated Outline Dimensions....................................................... 17
Changes to Ordering Guide .......................................................... 18
4/06—Revision 0: Initial Version
Rev. B | Page 2 of 20
ADG±ꢂ08/ADG±ꢂ09
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V 10%, VSS = –15 V 10%, GND = 0 V, unless otherwise noted.1
Table 1.
−40ºC to −40ºC to
Parameter
+2ꢀºC +8ꢀºC
+12ꢀºC
VSS to VDD
270
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
V
120
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 10 V, IS = −1 mA, see Figure 29
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
200
3.5
6
20
64
240
10
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (On)
12
VS = −5 V/0 V/+5 V, IS = −1 mA
76
83
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.003
0.1
0.003
0.1
0.1
0.02
0.2
0.2
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = 10 V, VS = −10 V, see Figure 30
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30
0.6
1
Drain Off Leakage, ID (Off)
ADG1208
ADG1209
Channel On Leakage, ID, IS (On)
ADG1208
0.6
0.6
1
1
VS = VD = 10 V, see Figure 31
0.6
0.6
1
1
ADG1209
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA max
μA max
pF typ
0.005
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
2
80
130
75
95
83
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 34
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 34
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V, see Figure 33
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz,
see Figure 39
165
105
125
185
115
140
10
tON (EN)
tOFF (EN)
100
25
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
0.4
−85
−85
0.15
−3 dB Bandwidth
CS (Off)
550
1
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, see Figure 37
f = 1 MHz, VS = 0 V
1.5
6
7
3.5
4.5
pF max
pF typ
pF max
pF typ
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
CD (Off) ADG1208
CD (Off) ADG1209
pF max
f = 1 MHz, VS = 0 V
Rev. B | Page 3 of 20
ADG±ꢂ08/ADG±ꢂ09
−40ºC to −40ºC to
Parameter
+2ꢀºC +8ꢀºC
+12ꢀºC
Unit
Test Conditions/Comments
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
CD, CS (On) ADG1208
7
8
5
6
pF typ
pF max
pF typ
pF max
CD, CS (On) ADG1209
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
0.002
220
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
1.0
380
1.0
1.0
IDD
Digital inputs = 5 V
ISS
0.002
0.002
Digital inputs = 0 V or VDD
Digital inputs = 5 V
ISS
VDD/VSS
5/ 16.5 V min/max |VDD | = |VSS|
1 Temperature range is as follows: Y version: –40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 20
ADG±ꢂ08/ADG±ꢂ09
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.1
Table 2.
−40ºC to −40ºC to
Parameter
+2ꢀºC +8ꢀºC
+12ꢀºC
0 to VDD
625
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
V
300
475
5
16
60
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA, see Figure 29
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
567
26
On Resistance Match Between Channels, ∆RON
27
On Resistance Flatness, RFLAT (On)
LEAKAGE CURRENTS
VS = 3 V/6 V/9 V, IS = −1 mA
VDD = 13.2 V
Source Off Leakage, IS (Off)
0.003
0.1
0.003
0.1
0.1
0.02
0.2
0.2
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30
0.6
1
Drain Off Leakage, ID (Off)
ADG1208
ADG1209
Channel On Leakage ID, IS (On)
ADG1208
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30
VS = VD = 1 V or 10 V, see Figure 31
0.6
0.6
1
1
0.6
0.6
1
1
ADG1209
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
0.001
0.1
μA max
pF typ
VIN = VINL or VINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
3
100
170
90
110
105
130
45
ns typ
ns typ
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 34
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 34
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 33
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
RL = 50 Ω, CL = 5 pF, see Figure 37
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
210
140
155
235
160
175
20
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
pF typ
pF max
pF typ
pF max
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
−0.2
−85
−85
450
1.2
1.8
7.5
9
4.5
5.5
9
10.5
6
CD (Off) ADG1208
CD (Off) ADG1209
CD, CS (On) ADG1208
CD, CS (On) ADG1209
7.5
f = 1 MHz, VS = 6 V
Rev. B | Page 5 of 20
ADG±ꢂ08/ADG±ꢂ09
−40ºC to −40ºC to
Parameter
+2ꢀºC +8ꢀºC
+12ꢀºC
Unit
Test Conditions/Comments
VDD = 13.2 V
Digital inputs = 0 V or VDD
POWER REQUIREMENTS
IDD
0.002
220
μA typ
μA max
μA typ
μA max
1.0
IDD
Digital inputs = 5 V
380
VDD
5/16.5
V min/max VSS = 0 V, GND = 0 V
1 Temperature range is as follows: Y version: –40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 6 of 20
ADG±ꢂ08/ADG±ꢂ09
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog, Digital Inputs1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA (whichever occurs first)
30 mA
Continuous Current, S or D
Peak Current, S or D (Pulsed at
1 ms, 10% Duty Cycle Maximum)
100 mA
ESD CAUTION
Operating Temperature Range
Industrial (Y Version)
Storage Temperature
–40°C to +125°C
–65°C to +150°C
150°C
Junction Temperature
θJA, Thermal Impedance, TSSOP
112°C/W
θJA, Thermal Impedance, LFCSP_VQ 30.4°C/W
θJA, Thermal Impedance, SOIC_N
77°C/W
Reflow Soldering Peak
Temperature (Pb-Free)
260(+0/−5)°C
1 Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
Rev. B | Page 7 of 20
ADG±ꢂ08/ADG±ꢂ09
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
EN
A2
PIN 1
INDICATOR
V
GND
SS
12 GND
ADG1208
TOP VIEW
(Not to Scale)
V
1
2
3
4
SS
S1
V
S1
S2
S3
11 V
DD
DD
ADG1208
TOP VIEW
(Not to Scale)
10 S5
S2
S3
S4
D
S5
S6
S7
S8
9
S6
Figure 4. ADG1208 Pin Configuration (LFCSP_VQ),
Exposed Pad Tied to Substrate, VSS
Figure 3. ADG1208 Pin Configuration (TSSOP/SOIC)
Table 4. ADG1208 Pin Function Descriptions
Pin Number
TSSOP/SOIC LFCSP_VQ
Mnemonic
Description
1
2
15
16
A0
EN
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When
high, Ax logic inputs determine on switches.
3
1
VSS
Most Negative Power Supply Potential. In single-supply applications, it can be
connected to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
9
10
11
12
13
14
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
Source Terminal 1. Can be an input or an output.
Source Terminal 2. Can be an input or an output.
Source Terminal 3. Can be an input or an output.
Source Terminal 4. Can be an input or an output.
Drain Terminal. Can be an input or an output.
Source Terminal 8. Can be an input or an output.
Source Terminal 7. Can be an input or an output.
Source Terminal 6. Can be an input or an output.
Source Terminal 5. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Table 5. ADG1208 Truth Table
A2
X
0
0
0
0
1
1
1
A1
X
0
0
1
1
0
0
1
A0
X
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
On Switch
None
1
2
3
4
5
6
7
8
1
1
1
1
Rev. B | Page 8 of 20
ADG±ꢂ08/ADG±ꢂ09
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
EN
A1
GND
V
V
PIN 1
INDICATOR
SS
DD
ADG1209
TOP VIEW
(Not to Scale)
12 V
V
1
2
3
4
DD
SS
S1A
S1B
S2B
S3B
S4B
DB
S1A
S2A
S3A
11 S1B
10 S2B
ADG1209
TOP VIEW
(Not to Scale)
S2A
S3A
S4A
DA
9
S3B
Figure 5. ADG1209 Pin Configuration (TSSOP/SOIC)
Figure 6. ADG1209 Pin Configurations (LFCSP_VQ),
Exposed Pad Tied to Substrate, VSS
Table 6. ADG1209 Pin Function Descriptions
Pin Number
TSSOP/SOIC LFCSP_VQ
Mnemonic Description
1
2
15
16
A0
EN
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
3
1
VSS
Most Negative Power Supply Potential. In single-supply applications, it can be
connected to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
9
10
11
12
13
14
S1A
S2A
S3A
S4A
DA
Source Terminal 1A. Can be an input or an output.
Source Terminal 2A. Can be an input or an output.
Source Terminal 3A. Can be an input or an output.
Source Terminal 4A. Can be an input or an output.
Drain Terminal A. Can be an input or an output.
Drain Terminal B. Can be an input or an output.
Source Terminal 4B. Can be an input or an output.
Source Terminal 3B. Can be an input or an output.
Source Terminal 2B. Can be an input or an output.
Source Terminal 1B. Can be an input or an output.
Most Positive Power Supply Potential.
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
Ground (0 V) Reference.
Logic Control Input.
Table 7. ADG1209 Truth Table
A1
A0
EN
0
On Switch Pair
X
X
None
0
0
1
1
0
1
0
1
1
1
1
1
1
2
3
4
Rev. B | Page 9 of 20
ADG±ꢂ08/ADG±ꢂ09
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
V
V
= +15V
= –15V
DD
SS
T
= 25°C
A
V
V
= +15V
= –15V
DD
SS
180
160
140
120
100
80
V
V
= +13.5V
= –13.5V
DD
SS
200
150
T
T
= +125°C
= +85°C
A
A
T
= +25°C
= –40°C
A
A
V
V
= +16.5V
= –16.5V
DD
SS
100
T
60
50
0
40
20
0
–15
–10
–5
0
5
10
15
–18 –15 –12 –9 –6 –3
0
3
6
9
12 15 18
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
Figure 7. On Resistance as a Function of VD (VS) for Dual Supply
600
600
V
V
= 12V
= 0V
DD
SS
T
= 25°C
V
V
= +4.5V
= –4.5V
A
DD
SS
T
= +125°C
A
500
400
300
200
500
V
V
= +5V
= –5V
DD
SS
T
= +85°C
A
400
300
T
= +25°C
A
V
V
= +5.5V
= –5.5V
DD
SS
T
= –40°C
A
200
100
0
100
0
0
2
4
6
8
10
12
–6
–4
–2
0
2
4
6
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 8. On Resistance as a Function of VD (VS) for Dual Supply
400
450
V
V
V
= +15V
= –15V
T
= 25°C
DD
SS
V
V
= 10.8V
= 0V
A
DD
SS
400
350
300
250
200
150
100
300
200
= +10V/–10V
BIAS
V
= 12V
= 0V
I
,
(ON) + +
S
DD
D
V
SS
I
(OFF) + –
I
D
100
(OFF) + –
S
V
V
= 13.2V
= 0V
0
DD
SS
I
,
(ON) – –
S
D
–100
–200
–300
–400
I
(OFF) – +
D
I
(OFF) – +
S
50
0
0
10 20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (°C)
0
2
4
6
8
10
12
14
SOURCE OR DRAIN VOLTAGE (V)
Figure 12. ADG1208 Leakage Currents as a Function of Temperature, Dual Supply
Figure 9. On Resistance as a Function of VD (VS) for Single Supply
Rev. B | Page 10 of 20
ADG±ꢂ08/ADG±ꢂ09
150
100
50
6
4
DEMUX (DRAIN TO SOURCE)
= 25°C
V
V
V
= 12V
= 0V
DD
SS
T
A
= 1V/10V
BIAS
I
(OFF) + –
V
V
= +5V
= –5V
S
DD
SS
I
,
(ON) + +
S
D
2
I
(OFF) + –
D
0
0
V
V
= +12V
= 0V
DD
SS
I
(OFF) – +
S
I
,
(ON) – –
S
D
V
V
= +15V
= –15V
DD
SS
–50
–100
–150
–2
I
(OFF) – +
D
–4
–6
0
10 20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (°C)
–15
–10
–5
0
5
10
15
V
(V)
S
Figure 13. ADG1208 Leakage Currents as a Function of Temperature,
Single Supply
Figure 16. Drain-to-Source Charge Injection vs. Source Voltage
350
300
200
I
T
PER CHANNEL
= 25°C
DD
180
160
140
120
100
80
A
V
V
= +5V
= –5V
DD
SS
V
V
= +15V
= –15V
DD
250
200
150
100
50
SS
V
V
= +12V
= 0V
DD
SS
V
V
= +15V
= –15V
60
DD
SS
40
V
V
= +12V
= 0V
DD
SS
20
0
0
–40
–20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
LOGIC, IN (V)
TEMPERATURE (°C)
X
Figure 14. IDD vs. Logic Level
Figure 17. tON/tOFF Times vs. Temperature
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
MUX (SOURCE TO DRAIN)
= 25°C
V
V
= +15V
= –15V
DD
SS
T
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
= 25°C
A
V
V
= +15V
= –15V
DD
SS
V
V
= +12V
= 0V
DD
SS
0.1
0
V
V
= +5V
= –5V
–100
–110
DD
SS
10k
100k
1M
10M
100M
1G
–15
–10
–5
0
5
10
15
FREQUENCY (Hz)
V
(V)
S
Figure 15. Source-to-Drain Charge Injection vs. Source Voltage
Figure 18. Off Isolation vs. Frequency
Rev. B | Page 11 of 20
ADG±ꢂ08/ADG±ꢂ09
20
10
V
V
T
= +15V
= –15V
= 25°C
DD
SS
LOAD = 10kΩ
= 25°C
T
A
0
–20
–40
–60
–80
A
1
V
V
= +5V, V = –5V, V = +3.5Vrms
SS S
DD
ADJACENT CHANNELS
= +15V, V = –15V, V = +5Vrms
DD
SS
S
0.1
NONADJACENT
CHANNELS
–100
–120
0.01
10k
100k
1M
10M
100M
1G
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 19. ADG1208 Crosstalk vs. Frequency
Figure 22. THD + N vs. Frequency
0
–20
12
10
8
V
V
= +15V
= –15V
= 25°C
DD
SS
T
A
–40
SOURCE/DRAIN ON
DRAIN OFF
ADJACENT CHANNELS
–60
6
–80
4
–100
–120
2
0
SOURCE OFF
NONADJACENT
CHANNELS
10k
100k
1M
10M
100M
1G
–15
–10
–5
0
5
10
15
FREQUENCY (Hz)
V
(V)
BIAS
Figure 23. ADG1208 Capacitance vs. Source Voltage,
15 V Dual Supply
Figure 20. ADG1209 Crosstalk vs. Frequency
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–10.0
12
10
8
V
V
= 12V
= 0V
= 25°C
DD
SS
T
A
SOURCE/DRAIN ON
DRAIN OFF
6
4
SOURCE OFF
2
0
10k
100k
1M
10M
100M
1G
0
2
4
6
8
10
12
FREQUENCY (Hz)
V
(V)
BIAS
Figure 24. ADG1208 Capacitance vs. Source Voltage,
12 V Single Supply
Figure 21. On Response vs. Frequency
Rev. B | Page 12 of 20
ADG±ꢂ08/ADG±ꢂ09
12
10
8
8
7
6
5
4
3
2
V
V
= 12V
= 0V
= 25°C
DD
SS
T
A
SOURCE/DRAIN ON
DRAIN OFF
SOURCE/DRAIN ON
DRAIN OFF
V
V
= +5V
= –5V
= 25°C
DD
SS
6
T
A
4
SOURCE OFF
2
1
0
SOURCE OFF
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
2
4
6
8
10
12
V
(V)
V
(V)
BIAS
BIAS
Figure 25. ADG1208 Capacitance vs. Source Voltage, 5 V Dual Supply
Figure 27. ADG1209 Capacitance vs. Source Voltage, 12 V Single Supply
8
8
V
V
= +15V
= –15V
= 25°C
DD
SS
7
6
5
4
3
2
1
0
7
6
5
4
3
2
SOURCE/DRAIN ON
DRAIN OFF
T
A
SOURCE/DRAIN ON
V
V
= +5V
= –5V
= 25°C
DD
SS
DRAIN OFF
T
A
SOURCE OFF
SOURCE OFF
1
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
–15
–10
–5
0
5
10
15
V
(V)
V
(V)
BIAS
BIAS
Figure 26. ADG1209 Capacitance vs. Source Voltage, 15 V Dual Supply
Figure 28. ADG1209 Capacitance vs. Source Voltage, 5 V Dual Supply
Rev. B | Page 13 of 20
ADG±ꢂ08/ADG±ꢂ09
TERMINOLOGY
tTRANSITION
RON
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
Ohmic resistance between D and S.
ΔRON
Difference between the RON of any two channels.
TBBM
IS (Off)
Off time measured between the 80% point of both switches
when switching from one address state to another.
Source leakage current when the switch is off.
ID (Off)
VINL
Drain leakage current when the switch is off.
Maximum input voltage for Logic 0.
ID, IS (On)
VINH
Channel leakage current when the switch is on.
Minimum input voltage for Logic 1.
VD (VS)
I
INL (IINH)
Analog voltage on Terminal D, Terminal S.
Input current of the digital input.
CS (Off)
IDD
Channel input capacitance for off condition.
Positive supply current.
CD (Off)
ISS
Channel output capacitance for off condition.
Negative supply current.
CD, CS (On)
On switch capacitance.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CIN
Charge Injection
A measure of the glitch impulse transferred from the digital
Digital input capacitance.
t
ON (EN)
input to the analog output during switching.
Delay time between the 50% and 90% points of the digital input
and switch on condition.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
t
OFF (EN)
On Response
Delay time between the 50% and 90% points of the digital input
The frequency response of the on switch.
and switch off condition.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
Rev. B | Page 14 of 20
ADG±ꢂ08/ADG±ꢂ09
TEST CIRCUITS
V
I
(ON)
A
I
(OFF)
A
I
(OFF)
A
D
S
D
S
D
S
D
NC
S
D
I
DS
V
V
D
V
D
S
NC = NO CONNECT
V
S
Figure 29. On Resistance
Figure 30. Off Leakage
Figure 31. On Leakage
V
V
V
V
DD
DD
SS
SS
3V
tr < 20ns
tf < 20ns
ADDRESS
DRIVE (V
50%
50%
A0
A1
A2
)
IN
S1
V
V
S1
S8
0V
V
IN
50Ω
S2–S7
tTRANSITION
tTRANSITION
90%
S8
ADG12081
OUTPUT
D
2.4V
EN
OUTPUT
300Ω
GND
35pF
90%
1
SIMILAR CONNECTION FOR ADG1209.
Figure 32. Address to Output Switching Times, tTRANSITION
V
V
V
DD
SS
SS
3V
V
DD
ADDRESS
A0
A1
A2
DRIVE (V
)
IN
S1
V
S
V
IN
50Ω
0V
S2–S7
S8
ADG12081
80%
80%
OUTPUT
OUTPUT
D
2.4V
EN
300Ω
GND
35pF
tBBM
1
SIMILAR CONNECTION FOR ADG1209.
Figure 33. Break-Before-Make Delay, tBBM
V
V
V
V
DD
DD
SS
SS
3V
A0
A1
A2
ENABLE
DRIVE (V
50%
50%
)
S1
S2–S8
V
IN
S
0V
ADG12081
tON (EN)
tOFF (EN)
OUTPUT
0.9V
0.9V
O
D
EN
O
OUTPUT
V
35pF
IN
50Ω
300Ω
GND
1
SIMILAR CONNECTION FOR ADG1209.
Figure 34. Enable Delay, tON (EN), tOFF (EN)
Rev. B | Page 15 of 20
ADG±ꢂ08/ADG±ꢂ09
V
V
V
V
DD
SS
SS
DD
3V
A0
A1
A2
V
V
IN
ADG12081
R
S
S
D
OUT
V
OUT
ΔV
OUT
EN
C
1nF
L
V
Q
= C × ΔV
L OUT
S
INJ
GND
V
IN
1
SIMILAR CONNECTION FOR ADG1209.
Figure 35. Charge Injection
V
V
DD
SS
V
V
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
V
DD
SS
V
OUT
S1
R
L
50Ω
S
50Ω
50Ω
D
R
V
S
50Ω
S2
D
V
OUT
V
R
S
L
50Ω
GND
V
GND
V
OUT
OUT
OFF ISOLATION = 20 log
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
V
S
Figure 38. Channel-to-Channel Crosstalk
Figure 36. Off Isolation
V
V
DD
SS
0.1µF
0.1µF
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
AUDIO PRECISION
V
V
DD
SS
S
50Ω
R
S
V
S
S
D
IN
V
V p-p
S
V
OUT
R
50Ω
L
D
V
OUT
V
GND
IN
R
L
10kΩ
GND
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 39. THD + Noise
Figure 37. Bandwidth
Rev. B | Page 16 of 20
ADG±ꢂ08/ADG±ꢂ09
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.00
BSC SQ
0.60 MAX
(BOTTOM VIEW)
0.60 MAX
PIN 1
INDICATOR
13
12
16
1
PIN 1
INDICATOR
0.65 BSC
2.25
TOP
VIEW
3.75
BSC SQ
2.10 SQ
1.95
0.75
0.60
0.50
9
4
8
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.35
0.30
0.25
0.20 REF
COPLANARITY
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad (CP-16-4)
Dimensions shown in millimeters
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 42. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-16)
Dimensions shown in millimeters and (inches)
Rev. B | Page 17 of 20
ADG1208/ADG1209
ORDERING GUIDE
Model
ADG1208YRUZ1
ADG1208YRUZ-REEL71
ADG1208YCPZ-REEL1
ADG1208YCPZ-REEL71
ADG1208YRZ1
ADG1208YRZ-REEL71
ADG1209YRUZ1
Temperature Range
Package Description
Package Option
RU-16
RU-16
CP-16-4
CP-16-4
R-16
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Narrow Body Small Outline Package [SOIC_N]
R-16
RU-16
RU-16
CP-16-4
CP-16-4
R-16
ADG1209YRUZ-REEL71
ADG1209YCPZ-REEL1
ADG1209YCPZ-REEL71
ADG1209YRZ1
ADG1209YRZ-REEL71
R-16
1 Z = RoHS compliant part.
Rev. B | Page 18 of 20
ADG±ꢂ08/ADG±ꢂ09
NOTES
Rev. B | Page 19 of 20
ADG±ꢂ08/ADG±ꢂ09
NOTES
©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0ꢀ713-0-1/09(B)
Rev. B | Page 20 of 20
相关型号：
ADG1208YRU
IC 8-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16, MS-153AB, TSSOP-16, Multiplexer or Switch
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ADG1209YCP
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