ADG1212-EP [ADI]
Low Capacitance, Low Charge Injection; 低电容，低电荷注入
| 型号： | ADG1212-EP |
| 厂家： | 
ADI |
| 描述： | Low Capacitance, Low Charge Injection |
| 文件： | 总12页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Capacitance, Low Charge Injection,
± ±1 ꢀV/±ꢁ ꢀ iCMOS Quad SPST Switches
Enhanced Product
ADG±ꢁ±ꢁ-EP
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1 pF off capacitance
S1
IN1
2.6 pF on capacitance
<1 pC charge injection
33 V supply range
D1
S2
IN2
120 Ω on resistance
D2
ADG1212-EP
S3
Fully specified at 1ꢀ V, +12 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP
IN3
D3
S4
IN4
Typical power consumption: <0.03 μW
D4
NOTES
1. SWITCHES SHOWN ARE
FOR LOGIC 1 INPUT.
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC
standard)
Military temperature range: −ꢀꢀ°C to +12ꢀ°C
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request
Figure 1.
The ultralow capacitance and charge injection of this switch
makes it an ideal solution for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth makes
the part suitable for video signal switching.
iCMOS construction ensures ultralow power dissipation, making
the part ideally suited for portable and battery-powered instruments.
APPLICATIONS
The ADG1212-EP contains four independent single-pole/
single-throw (SPST) switches. Each switch conducts equally
well in both directions when on and has an input signal range
that extends to the supplies. In the off condition, signal levels up
to the supplies are blocked.
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Additional application and technical information can be found
in the ADG1212 data sheet.
Video signal routing
Communication systems
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG1212-EP is a monolithic complementary metal-oxide
semiconductor (CMOS) device containing four independently
selectable switches designed on an iCMOS® (industrial CMOS)
process. iCMOS is a modular manufacturing process combining
high voltage CMOS and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no previous generation
of high voltage parts has been able to achieve. Unlike analog
ICs using conventional CMOS processes, iCMOS components
can tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.
1. Ultralow capacitance.
2. <1 pC charge injection.
3. 3 V logic compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
4. No VL logic power supply required.
5. Ultralow power dissipation: <0.03 μW.
6. 16-lead TSSOP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADG±ꢁ±ꢁ-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Single Supply..................................................................................4
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Test Circuits........................................................................................9
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Enhanced Product Features ............................................................ 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply................................................................................... 3
REVISION HISTORY
11/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Enhanced Product
SPECIFICATIONS
ADG±ꢁ±ꢁ-EP
DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
−40°C to
+8ꢀ°C
−ꢀꢀ°C to
+12ꢀ°C
2ꢀ°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VDD to VSS
260
V
120
190
2.5
6
20
57
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 10 V, IS = −1 mA; see Figure 15
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
230
10
On Resistance Match Between Channels (∆RON)
11
On Resistance Flatness (RFLAT(ON)
)
VS = −5 V/0 V/+5 V; IS = −1 mA
72
79
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.02
0.1
0.02
0.1
0.02
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 10 V, VD = m 10 V; see Figure 11
0.6
0.6
0.6
1
1
1
Drain Off Leakage, ID (Off)
VS = 10 V, VD = m 10 V; see Figure 11
Channel On Leakage, ID, IS (On)
VS = VD = 10 V; see Figure 12
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.005
2.5
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
65
80
80
100
−0.3
80
90
0.15
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 18
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 13
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 14
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 17
95
110
135
tOFF
115
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
1000
0.9
1.1
1
1.2
2.6
3
MHz typ RL = 50 Ω, CL = 5 pF; see Figure 16
pF typ
pF max
pF typ
pF max
pF typ
pF max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
0.001
220
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
1.0
420
1.0
1.0
IDD
ISS
ISS
Digital inputs = 5 V
0.001
0.001
Digital inputs = 0 V or VDD
Digital inputs = 5 V
1 Guaranteed by design, not subject to production test.
Rev. 0 | Page 3 of 12
ADG±ꢁ±ꢁ-EP
Enhanced Product
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
−40°C to −ꢀꢀ°C to
Parameter
2ꢀ°C
+8ꢀ°C
+12ꢀ°C
0 V to VDD
625
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
V
300
475
4.5
12
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; see Figure 15
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
567
26
On Resistance Match Between Channels (ΔRON)
27
On Resistance Flatness (RFLAT(ON)
)
60
VS = 3 V/6 V/9 V, IS = −1 mA
LEAKAGE CURRENTS
VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.02
0.1
0.02
0.1
0.02
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 11
0.6
0.6
0.6
1
1
1
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 11
VS = VD = 1 V or 10 V; see Figure 12
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.001
3
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
80
105
90
115
0
80
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 18
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 13
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 14
125
140
140
165
tOFF
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
90
900
1.2
1.4
1.3
1.5
3.2
3.9
MHz typ RL = 50 Ω, CL = 5 pF; see Figure 16
pF typ
pF max
pF typ
pF max
pF typ
pF max
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
CD (Off)
CD, CS (On)
POWER REQUIREMENTS
IDD
0.001
220
μA typ
μA max
μA typ
μA max
Digital inputs = 0 V or VDD
1.0
IDD
Digital inputs = 5 V
420
1 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 12
Enhanced Product
ADG±ꢁ±ꢁ-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Table 3.
Parameter
Rating
VDD to VSS
35 V
VDD to GND
VSS to GND
Analog Inputs1
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V
or 30 mA, whichever
occurs first
Only one absolute maximum rating may be applied at any
one time.
Digital Inputs1
GND – 0.3 V to
VDD + 0.3 V or 30 mA,
whichever occurs first
Table 4. ADG1212-EP Truth Table
ADG1212-EP INx
Switch Condition
Peak Current, S or D
100 mA (pulsed at
1 ms, 10% duty cycle
maximum)
1
0
On
Off
Continuous Current per Channel, S or D
Operating Temperature Range
Storage Temperature Range
Junction Temperature
25 mA
−40°C to +125°C
−65°C to +150°C
150°C
ESD CAUTION
16-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board)
112°C/W
Lead Temperature, Soldering
As per JEDEC J-STD-020
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. 0 | Page 5 of 12
ADG±ꢁ±ꢁ-EP
Enhanced Product
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
D1
S1
IN2
D2
S2
ADG1212-EP
TOP VIEW
(Not to Scale)
V
V
DD
SS
GND
NC
S3
S4
D4
D3
IN3
IN4
NOTES
1. NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
NC
VDD
S2
D2
Description
1
2
3
4
5
6
7
8
Logic Control Input.
Drain Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. This pin can be an input or output.
Drain Terminal. This pin can be an input or output.
Logic Control Input.
9
Logic Control Input.
10
11
12
13
14
15
16
Drain Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
No Connection.
Most Positive Power Supply Potential.
Source Terminal. This pin can be an input or output.
Drain Terminal. This pin can be an input or output.
Logic Control Input.
IN2
Rev. 0 | Page 6 of 12
Enhanced Product
ADG±ꢁ±ꢁ-EP
TYPICAL PERFORMANCE CHARACTERISTICS
250
200
T
= +25°C
V
V
= +15V
= –15V
A
DD
SS
180
160
140
120
100
80
V
V
= +13.5V
= –13.5V
DD
200
150
100
50
SS
T
= +125°C
= +85°C
A
T
A
T
T
= +25°C
= –40°C
A
V
V
= +15V
= –15V
V
V
= +16.5V
= –16.5V
DD
DD
A
SS
SS
60
40
T
= –55°C
A
20
0
0
–15
–18 –15 –12 –9 –6
–3
0
3
6
9
12 15 18
–10
–5
0
5
10
15
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 3. On Resistance as a Function of VD (VS) for Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
450
600
T
= +25°C
V
V
= 15V
= 0V
A
DD
SS
400
350
300
250
200
T = +125°C
A
500
T
= +85°C
A
V
V
= +5.5V
= –5.5V
DD
SS
400
300
200
100
0
T
= –40°C
A
T
= +25°C
A
150
100
T
= –55°C
A
50
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
450
0.20
T
= 25°C
V
V
V
= +15V
= –15V
A
DD
SS
400
350
300
250
200
150
0.15
0.10
0.05
V
V
= 12V
= 0V
= +10V/–10V
DD
SS
BIAS
V
V
= 10.8V
DD
I
, I (ON)
S
D
= 0V
SS
I
(OFF)
D
V
V
= 13.2V
= 0V
0
–0.05
–0.10
DD
SS
I
(OFF)
S
100
–0.15
–0.20
50
0
0
2
4
6
8
10
12
0
20
40
60
80
100
120
SOURCE OR DRAIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 5. On Resistance as a Function of VD (VS) for Single Supply
Figure 8. Leakage Currents as a Function of Temperature, Dual Supply
Rev. 0 | Page 7 of 12
ADG±ꢁ±ꢁ-EP
Enhanced Product
0.30
140
120
100
V
V
V
= 12V
= 0V
DD
SS
0.25
0.20
0.15
= 1V/10V
BIAS
tOFF (12V SINGLE SUPPLY)
I
, I (ON)
S
D
tON (12V SINGLE
SUPPLY)
80
60
0.10
0.05
tON (15V DUAL SUPPLY)
I
(OFF)
S
tOFF (15V DUAL SUPPLY)
40
20
0
0
–0.05
–0.10
I
(OFF)
D
0
20
40
60
80
100
120
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. tON/tOFF Times vs. Temperature
Figure 9. Leakage Currents as a Function of Temperature, Single Supply
Rev. 0 | Page 8 of 12
Enhanced Product
TEST CIRCUITS
ADG±ꢁ±ꢁ-EP
I
(ON)
A
I
(OFF)
A
I
(OFF)
A
D
S
D
S
D
S
D
NC
V
V
V
D
S
D
NC = NO CONNECT
Figure 11. Off Leakage
Figure 15. On Resistance
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
I
DS
S
50Ω
IN
V
S
D
V1
V
OUT
V
IN
R
L
50Ω
S
D
GND
V
R
= V1/I
S
ON
DS
V
WITH SWITCH
OUT
INSERTION LOSS = 20 LOG
V
WITHOUT SWITCH
OUT
Figure 12. On Leakage
Figure 16. Bandwidth
V
V
V
DD
V
DD
SS
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
AUDIO PRECISION
V
V
V
DD
V
DD
SS
SS
R
S
S
S
50Ω
50Ω
IN
IN
V
S
V
S
V p-p
D
D
V
V
OUT
OUT
V
V
IN
R
R
L
IN
L
50Ω
10kΩ
GND
GND
V
OUT
OFF ISOLATION = 20 LOG
V
S
Figure 13. Off Isolation
Figure 17. THD + Noise
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
V
OUT
S1
R
L
50Ω
D
R
50Ω
S2
V
S
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
S
Figure 14. Channel-to-Channel Crosstalk
Rev. 0 | Page 9 of 12
ADG±ꢁ±ꢁ-EP
Enhanced Product
V
V
DD
DD
SS
0.1µF
0.1µF
ADG1212-EP
V
V
SS
V
50%
50%
IN
V
L
OUT
S
D
90%
90%
R
300Ω
C
L
V
V
OUT
S
35pF
IN
GND
tOFF
tON
Figure 18. Switching Times
V
V
DD
DD
SS
ADG1212-EP
V
S
V
SS
V
IN
ON
OFF
V
R
OUT
S
D
C
1nF
L
V
S
V
IN
OUT
∆V
OUT
Q
= C × ∆V
L
OUT
INJ
GND
Figure 19. Charge Injection
Rev. 0 | Page 10 of 12
Enhanced Product
ADG±ꢁ±ꢁ-EP
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 20. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG1212SRU-EP-RL7
−55°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
RU-16
Rev. 0 | Page 11 of 12
ADG±ꢁ±ꢁ-EP
NOTES
Enhanced Product
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10012-0-11/11(0)
Rev. 0 | Page 12 of 12
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