ADG1236YRUZ [ADI]
Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS, Dual SPDT Switch;
| 型号： | ADG1236YRUZ |
| 厂家： | 
ADI |
| 描述： | Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS, Dual SPDT Switch 开关 光电二极管 |
| 文件： | 总16页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 pF Off Capacitance, 1 pC Charge Injection,
1ꢀ ꢁV12 ꢁ
i
CMOS™ Dual SPDT Switch
Preliminary Technical Data
ADG1236
FEATURES
FUNCTIONAL BLOCK DIAGRAM
2 pF off capacitance
1 pC charge injection
ADG1236
S1A
33 V supply range
D1
S1B
120 Ω on resistance
Fully specified at +12 V, 1ꢀ V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
IN1
IN2
16-lead TSSOP and 12-lead LFCSP packages
Typical power consumption: <0.03 µW
S2A
D2
S2B
APPLICATIONS
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Automatic test equipment
Data aquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Figure 1.
Communication systems
GENERAL DESCRIPTION
The ADG1236 is a monolithic CMOS device containing two
independently selectable SPDT switches. It is designed on an
iCMOS process. iCMOS (industrial-CMOS) is a modular
manufacturing process combining high voltage CMOS
(complementary metal-oxide semiconductor) and bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 30 V operation in a footprint
that no previous generation of high voltage parts has been able
to achieve. Unlike analog ICs using conventional CMOS proc-
esses, iCMOS components can tolerate high supply voltages,
while providing increased performance, dramatically lower
power consumption, and reduced package size.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.
PRODUCT HIGHLIGHTS
1. 2 pF off capacitance ( 1ꢀ V supply).
2. 1 pC charge injection.
3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
4. No VL logic power supply required.
ꢀ. Ultralow power dissipation: <0.03 µW.
The ultralow capacitance and charge injection of the part make
it an ideal solution for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth make the
part suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the part ideally
suited for portable and battery-powered instruments.
6. 16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP
packages.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADG1236
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Pin Configurations and Function Descriptions............................7
Terminology .......................................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits ..................................................................................... 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings............................................................ 6
Truth Table For Switches ............................................................. 6
ESD Caution.................................................................................. 6
REVISION HISTORY
11/04—Revision PrD: Preliminary Version
Rev. PrD | Page 2 of 16
Preliminary Technical Data
ADG1236
SPECIFICATIONS
DUAL SUPPLY
VDD = 1ꢀ V 10ꢁ, VSS = −1ꢀ V 10ꢁ, GND = 0 V, unless otherwise noted.
Table 1.
Parameters
2ꢀ°C
8ꢀ°C
Y Version1 Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VDD to VSS
26ꢀ
V
Ω typ
Ω max
Ω typ
VS = 1ꢀ Vꢁ IS = −1ꢀ mA; Figure 21
VS = 1ꢀ Vꢁ IS = −1ꢀ mA
12ꢀ
5
22ꢀ
On Resistance Match between
Channels (∆RON)
Ω max
Ω typ
On Resistance Flatness (RFLAT(ON)
)
25
VS = −5 V/ꢀ V/+5 V; IS = −1ꢀ mA
5ꢀ
Ω max
LEAKAGE CURRENTS
VDD = +1ꢀ Vꢁ VSS = −1ꢀ V
Source Off Leakageꢁ IS (Off)
ꢀ.ꢀ1
ꢀ.5
ꢀ.ꢀ1
ꢀ.5
ꢀ.ꢀ0
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = ꢀ V/1ꢀ Vꢁ VD = 1ꢀ V/ꢀ V; Figure 22
1
1
2
5
5
5
Drain Off Leakageꢁ ID (Off)
VS = ꢀ V/1ꢀ Vꢁ VD = 1ꢀ V/ꢀ V; Figure 22
VS = VD = ꢀ V or 1ꢀ V; Figure 23
Channel On Leakageꢁ IDꢁ IS (On)
DIGITAL INPUTS
Input High Voltageꢁ VINH
Input Low Voltageꢁ VINL
Input Currentꢁ IINL or IINH
2.ꢀ
ꢀ.8
V min
V max
µA typ
µA max
pF typ
ꢀ.ꢀꢀ5
5
VIN = VINL or VINH
ꢀ.5
Digital Input Capacitanceꢁ CIN
DYNAMIC CHARACTERISTICS2
tON
5ꢀ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
RL = 5ꢀ Ωꢁ CL = 35 pF
VS = 1ꢀ V; Figure 20
RL = 5ꢀ Ωꢁ CL = 35 pF
VS = 1ꢀ V; Figure 20
RL = 5ꢀ Ωꢁ CL = 35 pF
VS1 = VS2 = 1ꢀ V; Figure 25
VS = ꢀ Vꢁ RS = ꢀ Ωꢁ CL = 1 nF; Figure 26
RL = 5ꢀ Ωꢁ CL = 5 pFꢁ f = 1 MHz; Figure 27
RL = 5ꢀ Ωꢁ CL = 5 pFꢁ f = 1 MHz; Figure 28
RL = 6ꢀꢀ Ωꢁ 5 V rmsꢁ f = 2ꢀ Hz to 2ꢀ kHz
RL = 5ꢀ Ωꢁ CL = 5 pF; Figure 29
tOFF
2ꢀ
1ꢀꢀ
Break-before-Make Time Delayꢁ tD
15
0ꢀ
1
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off)
1
75
85
ꢀ.ꢀꢀ2
7ꢀꢀ
2
MHz typ
pF typ
pF typ
pF typ
CD(Off)
CDꢁ CS (On)
2
5
POWER REQUIREMENTS
IDD
VDD = +16.5 Vꢁ VSS = −16.5 V
Digital Inputs = ꢀ V or VDD
ꢀ.ꢀꢀ1
15ꢀ
µA typ
µA max
µA typ
µA max
µA typ
µA max
5.ꢀ
3ꢀꢀ
5.ꢀ
IDD
ISS
Digital Input = 5 V
ꢀ.ꢀꢀ1
Digital Inputs = ꢀ V or VDD
Rev. PrD | Page 3 of 16
ADG1236
Preliminary Technical Data
Parameters
2ꢀ°C
8ꢀ°C
Y Version1 Unit
µA typ
Test Conditions/Comments
IGND
ꢀ.ꢀꢀ1
Digital Inputs = ꢀ V or VDD
5.ꢀ
µA max
µA typ
µA max
IGND
15ꢀ
Digital Input = 5 V
3ꢀꢀ
1 Temperature range for Y Version is −0ꢀ°C to +125°C.
2 Guaranteed by designꢁ not subject to production test.
SINGLE SUPPLY
VDD = 12 V 10ꢁ, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameters
2ꢀ°C
8ꢀ°C
Y Version1 Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
ꢀ V to VDD
V
Ω typ
Ω max
Ω typ
VS = +1ꢀ Vꢁ IS = −1ꢀ mA; Figure 21
VS = +1ꢀ Vꢁ IS = −1ꢀ mA
220
On Resistance Match between
Channels (∆RON)
1ꢀ
Ω max
Ω typ
On Resistance Flatness (RFLAT(ON)
)
0ꢀ
VS = +3 V/+6 V/+9 Vꢁ IS = −1ꢀ mA
VDD = 12 V
LEAKAGE CURRENTS
Source Off Leakageꢁ IS (Off)
ꢀ.ꢀ1
ꢀ.5
ꢀ.ꢀ1
ꢀ.5
ꢀ.ꢀ0
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/1ꢀ Vꢁ VD = 1ꢀ V/1 V; Figure 22
1
1
2
5
5
5
Drain Off Leakageꢁ ID (Off)
VS = 1 V/1ꢀ Vꢁ VD = 1ꢀ V/1 V; Figure 22
VS = VD = 1 V or 1ꢀ Vꢁ Figure 23
Channel On Leakageꢁ IDꢁ IS (On)
DIGITAL INPUTS
Input High Voltageꢁ VINH
Input Low Voltageꢁ VINL
Input Currentꢁ IINL or IINH
2.ꢀ
ꢀ.8
V min
V max
µA typ
µA max
pF typ
ꢀ.ꢀꢀ1
5
VIN = VINL or VINH
ꢀ.5
Digital Input Capacitanceꢁ CIN
DYNAMIC CHARACTERISTICS2
tON
5ꢀ
15
15
5
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 5ꢀ Ωꢁ CL = 35 pF
VS = 8 V; Figure 20
RL = 5ꢀ Ωꢁ CL = 35 pF
VS = 8 V; Figure 20
RL = 5ꢀ Ωꢁ CL = 35 pF
VS1 = VS2 = 8 V; Figure 25
VS = ꢀ Vꢁ RS = ꢀ Ωꢁ CL = 1 nF; Figure 26
tOFF
Break-before-Make Time Delayꢁ tD
Charge Injection
1
Off Isolation
75
85
7ꢀꢀ
2
2
5
RL = 5ꢀ Ωꢁ CL = 5 pFꢁ f = 1 MHz; Figure 27;
RL = 5ꢀ Ωꢁ CL = 5 pFꢁ f = 1 MHz; Figure 28
RL = 5ꢀ Ωꢁ CL = 5 pF; Figure 29
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
CD (Off)
CDꢁ CS (On)
Rev. PrD | Page 0 of 16
Preliminary Technical Data
ADG1236
Parameters
2ꢀ°C
8ꢀ°C
Y Version1 Unit
µA typ
Test Conditions/Comments
POWER REQUIREMENTS
IDD
VDD = 13.2 V
Digital Inputs = ꢀ V or VDD
ꢀ.ꢀꢀ1
15ꢀ
5.ꢀ
µA max
µA typ
µA max
IDD
Digital Inputs = 5 V
3ꢀꢀ
1 Temperature range for Y Version is −0ꢀ°C to +125°C.
2 Guaranteed by designꢁ not subject to production test.
Rev. PrD | Page 5 of 16
ADG1236
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 2ꢀ°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Ratings
VDD to VSS
38 V
VDD to GND
VSS to GND
Analog Inputs1
−ꢀ.3 V to +25 V
+ꢀ.3 V to −25 V
VSS − ꢀ.3 V to VDD + ꢀ.3 V
Digital Inputs
1
GND − ꢀ.3 V to VDD + ꢀ.3 V or
3ꢀ mAꢁ whichever occurs first
Peak Currentꢁ S or D
1ꢀꢀ mA (pulsed at 1 msꢁ 1ꢀ%
duty cycle max)
3ꢀ mA
TRUTH TABLE FOR SWITCHES
Table 4.
Continuous Currentꢁ S or D
Operating Temperature Range
Industrial (B Version)
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
IN
Switch A
Off
Switch B
On
Off
ꢀ
−0ꢀ°C to +85°C
−0ꢀ°C to +125°C
−65°C to +15ꢀ°C
15ꢀ°C
1
On
16-Lead TSSOPꢁ θJA Thermal
Impedance
15ꢀ.0°C/W
12-Lead LFCSPꢁ θJA Thermal
Impedance
TBD°C/W
Lead Temperatureꢁ Soldering
Vapor Phase (6ꢀ s)
Infrared (15 s)
215°C
22ꢀ°C
1 Over voltages at INꢁ Sꢁ or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 0ꢀꢀꢀ V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitryꢁ permanent damage may occur on devices subjected to high energy
electrostatic discharges. Thereforeꢁ proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrD | Page 6 of 16
Preliminary Technical Data
ADG1236
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
IN1
S1A
D1
1
2
3
4
5
6
7
8
16 NC
15 NC
14
NC
V
PIN 1
INDICATOR
ADG1236 13
TOP VIEW
S1B
DD
9
8
7
V
DD
D1
1
2
3
12
V
S2B
D2
SS
(Not to Scale)
ADG1236
TOP VIEW
(Not to Scale)
S2B
D2
S1B
11
10
9
GND
NC
V
SS
S2A
IN2
NC
NC = NO CONNECT
NC = NO CONNECT
Figure 2.TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
LFCSP
Mnemonic
IN1
Function
TSSOP
1
2
3
11
12
1
Logic Control Input.
S1A
D1
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (ꢀ V) Reference.
0
5
2
3
S1B
VSS
6
0
1ꢀ
5
GND
NC
IN2
7ꢁ 8ꢁ 10–16
9
No Connect.
Logic Control Input.
1ꢀ
11
12
13
6
7
8
9
S2A
D2
S2B
VDD
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Positive Power Supply Potential.
Rev. PrD | Page 7 of 16
ADG1236
Preliminary Technical Data
TERMINOLOGY
IDD
CD (Off)
The positive supply current.
The off switch drain capacitance, measured with reference to
ground.
ISS
The negative supply current.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
VD (VS)
The analog voltage on Terminals D and S.
CIN
The digital input capacitance.
RON
The ohmic resistance between D and S.
tON
The delay between applying the digital control input and the
output switching on. See Figure 24.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
tOFF
The delay between applying the digital control input and the
output switching off.
IS (Off)
The source leakage current with the switch off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ID (Off)
The drain leakage current with the switch off.
Off Isolation
ID, IS (On)
A measure of unwanted signal coupling through an off switch.
The channel leakage current with the switch on.
Crosstalk
VINL
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
The maximum input voltage for Logic 0.
VINH
Bandwidth
The minimum input voltage for Logic 1.
The frequency at which the output is attenuated by 3 dB.
IINL (IINH
)
On Response
The frequency response of the on switch.
The input current of the digital input.
CS (Off)
Insertion Loss
The loss due to the on resistance of the switch.
The off switch source capacitance, measured with reference to
ground.
Rev. PrD | Page 8 of 16
Preliminary Technical Data
ADG1236
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. On Resistance as a Function of VD (VS) for Single Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 5, On Resistance as a Function of VD (VS) for Dual Supply
Figure 8, On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
Figure 6. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
Figure 9. Leakage Current as a Function of VD (VS)
Rev. PrD | Page 9 of 16
ADG1236
Preliminary Technical Data
Figure 13. Leakage Currents as a Function of Temperature
Figure 14. Supply Currents vs. Input Switching Frequency
Figure 15. Charge Injection vs. Source Voltage
Figure 10. Leakage Currents as a Function of VD (VS)
Figure 11. Leakage Current as a Function of VD (VS)
Figure 12. Leakage Currents as a Function of Temperature
Rev. PrD | Page 1ꢀ of 16
Preliminary Technical Data
Figure 16. tON/tOFF Times vs. Temperature
Figure 17. Off Isolation vs. Frequency
Figure 18. Crosstalk vs. Frequency
ADG1236
Figure 19. On Response vs. Frequency
Figure 20. THD + N vs. Frequency
Rev. PrD | Page 11 of 16
ADG1236
Preliminary Technical Data
TEST CIRCUITS
V
I
(ON)
A
I
(OFF)
A
I
(OFF)
A
D
S
D
S
D
S
D
S
D
NC
I
DS
V
V
D
V
V
D
S
S
NC = NO CONNECT
Figure 21. Test Circuit 1—On Resistance
Figure 22. Test Circuit 2— Off Resistance
Figure 23. Test Circuit 3—On Leakage
V
V
DD
SS
0.1µF
0.1µF
V
V
IN
50%
50%
50%
50%
V
V
SS
DD
SB
V
IN
S
D
V
OUT
SA
R
C
35pF
L
50Ω
L
90%
90%
IN
V
OUT
V
IN
GND
tON
tOFF
Figure 24. Test Circuit 4—Switching Times
V
V
DD
DD
SS
0.1µF
0.1µF
V
IN
V
V
SS
SB
V
S
D
V
OUT
SA
80%
V
R
C
OUT
L
L
35pF
50Ω
IN
tBBM
tBBM
V
IN
GND
Figure 25. Test Circuit 5—Break-before-Make Time Delay
V
V
V
DD
SS
0.1µF
0.1µF
V
(NORMALLY
IN
CLOSED SWITCH)
V
DD
SS
ON
OFF
SB
NC
V
D
V
S
V
(NORMALLY
IN
OUT
SA
OPEN SWITCH)
C
L
IN
1nF
V
∆V
OUT
OUT
V
IN
Q
= C × ∆V
L
OUT
GND
INJ
Figure 26. Test Circuit 6—Charge Injection
Rev. PrD | Page 12 of 16
Preliminary Technical Data
ADG1236
V
V
DD
SS
V
V
0.1µF
0.1µF
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
NETWORK
ANALYZER
DD
SS
V
V
DD
SS
SA
V
OUT
NC
50Ω
R
L
50Ω
ꢀ
SA
SB
50Ω
SB
IN
D
R
V
S
50Ω
D
IN
V
OUT
V
V
IN
R
L
S
50Ω
GND
GND
V
OUT
V
OUT
OFF ISOLATION = 20 LOG
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
V
S
S
Figure 29. Test Circuit 9— Bandwidth
Figure 27. Test Circuit 7—Off Isolation
V
V
DD
SS
0.1µF
0.1µF
V
V
DD
SS
NETWORK
ANALYZER
0.1µF
0.1µF
V
V
DD
SS
NC
50Ω
AUDIO PRECISION
V
V
DD
SS
SA
SB
50Ω
IN
R
S
V
S
S
D
IN
V
OUT
V
V p-p
V
S
IN
R
L
50Ω
D
GND
V
OUT
V
IN
R
L
600Ω
GND
V
WITH SWITCH
OUT
INSERTION LOSS = 20 LOG
V
WITHOUT SWITCH
OUT
Figure 30. Test Circuit 10—THD + Noise
Figure 28. Test Circuit 8—Channel-to-Channel Crosstalk
Rev. PrD | Page 13 of 16
ADG1236
Preliminary Technical Data
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in inches and (millimeters
0.75
0.55
0.35
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
10 11 12
0.45
1
9
PIN 1
INDICATOR
TOP
VIEW
2.75
BSC SQ
8
7
2
3
6
5
4
EXPOSED PAD
(BOTTOM VIEW)
0.25 MIN
0.50
BSC
0.80 MAX
0.65 TYP
12 MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.20 REF
0.30
0.23
0.18
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 32. 12-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG1236YRU
ADG1236YCP
Temperature Range
−0ꢀ°C to +125°C
−0ꢀ°C to +125°C
Package Description
Package Option
RU-16
CP-12-1
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Rev. PrD | Page 10 of 16
Preliminary Technical Data
NOTES
ADG1236
Rev. PrD | Page 15 of 16
ADG1236
NOTES
Preliminary Technical Data
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04776–0–11/04(PrD)
Rev. PrD | Page 16 of 16
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