ADG1309 [ADI]
4- and 8-Channel +-15 V/+12 V Multiplexers; 4和8通道±15 V / + 12 V多路复用器
| 型号： | ADG1309 |
| 厂家： | 
ADI |
| 描述： | 4- and 8-Channel +-15 V/+12 V Multiplexers |
| 文件： | 总16页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4- and 8-Channel
± ±1 ꢀV/±ꢁ ꢀ ꢂMlꢃtileꢄeꢅr
ADG±308VADG±309
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
33 V supply range
ADG1308
ADG1309
130 Ω on resistance
S1
S1A
S4A
Fully specified at 1ꢀ V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
DA
DB
D
Break-before-make switching action
16-lead TSSOP and 16-lead SOIC_N
Upgrade for the ADGꢀ08A/ADGꢀ09A
S1B
S4B
S8
APPLICATIONS
Audio and video routing
Test equipment
Data acquisition systems
Battery-powered systems
Communication systems
Signal routing
1-OF-8
1-OF-4
DECODER
DECODER
A0 A1 A2 EN
A0 A1 EN
Figure 1.
GENERAL DESCRIPTION
The ADG1308 and ADG1309 are monolithic analog multi-
plexers consisting of eight single channels and four differential
channels, respectively. The ADG1308 switches one of eight
inputs to a common output as determined by the 3-bit binary
address lines A0, A1, and A2. The ADG1309 switches one of
four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An EN
input on both devices is used to enable or disable the device.
When disabled, all channels are switched off.
Fast switching speed coupled with high signal bandwidth makes
the parts suitable for video signal switching. CMOS
construction ensures ultra low power dissipation, making the
parts ideally suited for portable and battery-powered
instruments.
PRODUCT HIGHLIGHTS
1. 16-lead TSSOP and 16-lead SOIC_N available.
2. Pin compatible with the ADG508AKR and the
ADG509AKR devices.
When the switches are on, each switch conducts equally well
in both directions and has an input signal range that extends to
the power supplies. In the off condition, signal levels up to the
supplies are blocked. All switches exhibit break-before-make
switching action for use in multiplexer applications. Inherent in
the design is the low charge injection for minimum transients
when switching the digital inputs.
3. 3 V, logic-compatible digital input where:
VIH = 2.0 V and VIL = 0.8 V.
4. VL logic power supply not required.
5. Low power consumption.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADG±308VADG±309
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Pin Configurations and Function Descriptions............................7
ADG1308 Truth Table ..................................................................7
ADG1309 Truth Table ..................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 11
Terminology.................................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply................................................................................... 3
Single Supply................................................................................. 5
Absolute Maximum Ratings............................................................ 6
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADG±308VADG±309
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V 10%, VSS = –15 V 10%, GND = 0 V, unless otherwise noted.1
Table 1.
−40ºC to +10ꢀºC
Parameter
+2ꢀºC
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VSS to VDD
300
V
130
210
5
10
25
70
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 10 V, IS = −1 mA; see Figure 13
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
On Resistance Match Between Channels, ∆RON
On Resistance Flatness, RFLAT (On)
VS = −5 V, 0 V, +5 V, IS = −1 mA
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
1
1
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 10 V, VS = −10 V; see Figure 14
VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 14
VS = VD = 10 V; see Figure 15
50
50
50
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA max
μA max
pF typ
0.005
5
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
80
130
80
100
85
100
25
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 16
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 17
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 21
RL = 50 Ω, CL = 5 pF; see Figure 22
f = 1 MHz, VS = 0 V
190
120
150
10
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
2
80
80
500
5
CD (Off)
ADG1308
ADG1309
15
10
pF typ
pF typ
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
CD, CS (On)
ADG1308
ADG1309
20
15
pF typ
pF typ
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
Rev. 0 | Page 3 of 16
ADG±308VADG±309
−40ºC to +10ꢀºC
Parameter
+2ꢀºC
Unit
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
POWER REQUIREMENTS
IDD
0.002
220
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/V max
1.0
IDD
Digital inputs = 5 V
Digital inputs = 0 V or VDD or 5 V
|VDD| = |VSS|
320
ISS
0.002
1.0
5/ 16.5
VDD/VSS
1 Temperature range for B version is –40°C to +105°C.
2 Guaranteed by design; not subject to production test.
Rev. 0 | Page 4 of 16
ADG±308VADG±309
SINGLE SUPPLY
VDD = 12 V, V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.1
Table 2.
Parameter
+2ꢀºC
−40ºC to +10ꢀºC Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 to VDD
660
V
325
500
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; see Figure 13
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
On Resistance Match Between Channels, ∆RON 10
20
On Resistance Flatness, RFLAT (On)
LEAKAGE CURRENTS
65
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
Source Off Leakage, IS (Off)
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 14
50
50
50
Drain Off Leakage, ID (Off)
1
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 14
VS = VD = 1 V or 10 V; see Figure 15
Channel On Leakage, ID, IS (On)
1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
0.001
0.1
μA max
pF typ
VIN = VINL or VINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
3
100
170
90
110
105
130
45
ns typ
ns typ
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 16
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 17
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 21
RL = 50 Ω, CL = 5 pF; see Figure 22
f = 1 MHz, VS = 6 V
240
170
180
20
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tBBM
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
2
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
80
80
500
5
CD (Off)
ADG1308
ADG1309
10
15
pF typ
pF typ
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
CD, CS (On)
ADG1308
ADG1309
20
15
pF typ
pF typ
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
VDD = 13.2 V
POWER REQUIREMENTS
IDD
0.002
220
μA typ
μA max
μA typ
μA max
Digital inputs = 0 V or VDD
1.0
IDD
Digital inputs = 5
320
VDD
5/16.5
V min/V max VSS = 0 V, GND = 0 V
1 Temperature range for the B version is –40°C to +105°C.
2 Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 16
ADG±308VADG±309
ABSOLUTE ꢂAXIꢂUꢂ RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to VSS
35 V
VDD to GND
VSS to GND
Analog, Digital Inputs1
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA (whichever occurs first)
Continuous Current, S or D pins
30 mA
Peak Current, S or D pins
(Pulsed at 1 ms, 10% Duty
Cycle Maximum)
100 mA
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
–40°C to +105°C
–65°C to +150°C
150°C
TSSOP, θJA,
112°C/W
Thermal Impedance
16-Lead SOIC, θJA,
77°C/W
Thermal Impedance
Reflow Soldering Peak
Temperature (Pb-free)
260 (+0/−5)°C
1 Overvoltages at A, EN, S, or D pins are clamped by internal diodes. Current
should be limited to the maximum ratings provided.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 16
ADG±308VADG±309
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
EN
A2
V
GND
SS
ADG1308
TOP VIEW
(Not to Scale)
S1
V
DD
S2
S3
S4
D
S5
S6
S7
S8
Figure 2. ADG1308 Pin Configuration (TSSOP and SOIC_N)
Table 4. ADG1308 Pin Function Descriptions
Pin Number
Mnemonic
Description
1
2
A0
EN
Logic Control Input A0.
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
3
VSS
Most Negative Power Supply Potential. In single supply applications, this pin can be
connected to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
Source Terminal 1. Can be an input or an output.
Source Terminal 2. Can be an input or an output.
Source Terminal 3. Can be an input or an output.
Source Terminal 4. Can be an input or an output.
Drain Terminal. Can be an input or an output.
Source Terminal 8. Can be an input or an output.
Source Terminal 7. Can be an input or an output.
Source Terminal 6. Can be an input or an output.
Source Terminal 5. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input A2.
Logic Control Input A1.
ADG1308 TRUTH TABLE
Table 5.
A2
X1
0
0
0
0
1
1
1
A1
X1
0
0
1
1
0
0
1
A0
X1
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
ON SWITCH
NONE
1
2
3
4
5
6
7
8
1
1
1
1
1 X = Don’t care.
Rev. 0 | Page 7 of 16
ADG±308VADG±309
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
EN
A1
GND
V
V
DD
SS
ADG1309
TOP VIEW
(Not to Scale)
S1A
S1B
S2B
S3B
S4B
DB
S2A
S3A
S4A
DA
Figure 3. ADG1309 Pin Configuration (TSSOP and SOIC_N)
Table 6. ADG1309 Pin Function Descriptions
Pin Number
SOIC/TSSOP Mnemonic Description
1
2
A0
EN
Logic Control Input A0.
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
3
VSS
Most Negative Power Supply Potential. In single supply applications, this pin can be
connected to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
S1A
S2A
S3A
S4A
DA
Source Terminal 1A. Can be an input or an output.
Source Terminal 2A. Can be an input or an output.
Source Terminal 3A. Can be an input or an output.
Source Terminal 4A. Can be an input or an output.
Drain Terminal A. Can be an input or an output.
Drain Terminal B. Can be an input or an output.
Source Terminal 4B. Can be an input or an output.
Source Terminal 3B. Can be an input or an output.
Source Terminal 2B. Can be an input or an output.
Source Terminal 1B. Can be an input or an output.
Most Positive Power Supply Potential.
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
Ground (0 V) Reference.
Logic Control Input A1.
ADG1309 TRUTH TABLE
Table 7.
Al
X1
0
0
1
A0
X1
0
1
0
EN
0
1
1
1
ON SWITCH PAIR
NONE
1
2
3
4
1
1
1
1 X = Don’t care.
Rev. 0 | Page 8 of 16
ADG±308VADG±309
TYPICAL PERFORꢂANCE CHARACTERISTICS
200
600
500
400
300
200
T
= 25°C
V
V
= 12V
= 0V
A
DD
SS
180
160
140
120
100
80
T
= +85°C
A
V
= +15V
DD
= –15V
V
SS
60
40
T
= –40°C
A
T
= +25°C
A
100
0
20
0
–15 –12
–9
–6
–3
0
3
6
9
12
15
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 4. On Resistance as a Function of VD (VS ) for Dual Supply
Figure 7. On Resistance as a Function of VD (VS ) for Different Temperatures,
Single Supply
450
6
T
= 25°C
T
= 25°C
A
A
V
V
= +15V
= –15V
DD
SS
400
350
300
250
200
150
4
2
V
V
= +5V
= –5V
DD
SS
V
V
= 12V
= 0V
DD
SS
0
V
V
= +12V
= 0V
DD
SS
–2
100
–4
–6
50
0
0
2
4
6
8
10
12
–15
–10
–5
0
5
10
15
SOURCE OR DRAIN VOLTAGE (V)
V
(V)
S
Figure 5. On Resistance as a Function of VD (VS ) for Single Supply
Figure 8. Charge Injection vs. Source Voltage
250
160
V
V
= +15V
= –15V
DD
SS
V
V
= +15V
= –15V
DD
SS
140
120
100
80
200
150
100
T
ON
T
T
= +85°C
OFF
A
60
T
= +25°C
A
T
= –40°C
A
40
50
0
20
0
–15
–10
–5
0
5
10
15
–40
–20
0
20
40
60
80
SOURCE OR DRAIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 6. On Resistance as a Function of VD (VS ) for Different Temperatures,
Dual Supply
Figure 9. TON/TOFF Time vs. Temperature
Rev. 0 | Page 9 of 16
ADG±308VADG±309
0
–10
–20
–30
–40
–50
–60
–70
–80
V
V
= +15V
= –15V
DD
SS
V
V
= +15V
= –15V
= 25°C
DD
SS
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
= 25°C
A
T
A
SxA – SxB
S1x – S2x
–90
–100
–110
–100
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10. Off Isolation vs. Frequency
Figure 12. Crosstalk vs. Frequency
12
10
8
V
V
= +15V
= –15V
= 25°C
DD
SS
T
A
SOURCE/DRAIN ON
DRAIN OFF
6
4
2
0
SOURCE OFF
–15
–10
–5
0
5
10
15
V
(V)
BIAS
Figure 11. ADG1308 Capacitance vs. Source Voltage, 15 V Dual Supply
Rev. 0 | Page 10 of 16
ADG±308VADG±309
TEST CIRCUITS
I
(ON)
A
I
(OFF)
A
I
(OFF)
A
D
S
D
V
S
D
S
D
NC
S
D
V
V
V
D
S
D
NC = NO CONNECT
I
DS
V
S
Figure 14. Off Leakage
Figure 15. On Leakage
Figure 13. On Resistance
V
V
V
V
DD
DD
SS
SS
3V
tr < 20ns
tf < 20ns
ADDRESS
DRIVE (V
50%
50%
A0
A1
A2
)
IN
S1
V
V
S1
0V
V
IN
50Ω
S2–S7
tTRANSITION
tTRANSITION
S8
S8
ADG13081
90%
OUTPUT
D
2.4V
EN
OUTPUT
300Ω
GND
35pF
90%
1
SIMILAR CONNECTION FOR ADG1309.
Figure 16. Address to Output Switching Times, tTRANSITION
V
V
V
DD
DD
SS
3V
V
SS
ADDRESS
A0
A1
A2
DRIVE (V
)
IN
S1
V
S
V
IN
50Ω
0V
S2–S7
S8
ADG13081
80%
80%
OUTPUT
OUTPUT
D
2.4V
EN
300Ω
GND
35pF
tBBM
1
SIMILAR CONNECTION FOR ADG1309.
Figure 17. Break-Before-Make Delay, tBBM
V
V
V
V
DD
DD
SS
SS
3V
A0
A1
A2
ENABLE
DRIVE (V
50%
50%
)
S1
S2–S8
V
IN
S
0V
ADG13081
tON (EN)
tOFF (EN)
OUTPUT
0.9V
0.9V
O
D
EN
O
OUTPUT
V
35pF
IN
50Ω
300Ω
GND
1
SIMILAR CONNECTION FOR ADG1309.
Figure 18. Enable Delay, tON (EN), tOFF (EN)
Rev. 0 | Page 11 of 16
ADG±308VADG±309
V
V
V
V
DD
SS
SS
DD
3V
A0
A1
A2
V
V
IN
ADG13081
R
S
S
D
OUT
V
ΔV
OUT
OUT
EN
C
1nF
L
V
Q
= C × ΔV
L OUT
S
INJ
GND
V
IN
1
SIMILAR CONNECTION FOR ADG1309.
Figure 19. Charge Injection
V
V
DD
SS
V
V
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
V
DD
SS
S
50Ω
S
50Ω
50Ω
V
S
V
S
D
D
V
OUT
V
R
50Ω
OUT
L
R
50Ω
L
GND
GND
V
OUT
V
WITH SWITCH
OFF ISOLATION = 20 log
OUT
V
S
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 20. Off Isolation
Figure 22. Bandwidth
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
V
OUT
S1
R
L
50Ω
D
R
50Ω
S2
V
S
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 21. Channel-to-Channel Crosstalk
Rev. 0 | Page 12 of 16
ADG±308VADG±309
TERꢂINOLOGY
RON
tTRANSITION
Ohmic resistance between D and S.
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
ΔRON
Difference between the RON of any two channels.
TBBM
IS (Off)
Off time measured between the 80% point of both switches
when switching from one address state to another.
Source leakage current when the switch is off.
ID (Off)
VINL
Drain leakage current when the switch is off.
Maximum input voltage for Logic 0.
ID, IS (On)
VINH
Channel leakage current when the switch is on.
Minimum input voltage for Logic 1.
VD (VS)
IINL (IINH
Input current of the digital input.
)
Analog voltage on Terminal D and Terminal S.
CS (Off)
IDD
Channel input capacitance for off condition.
Positive supply current.
CD (Off)
ISS
Channel output capacitance for off condition.
Negative supply current.
CD, CS (On)
On switch capacitance.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CIN
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
tOFF (EN)
On Response
Delay time between the 50% and 90% points of the digital input
and switch off condition.
The frequency response of the on switch.
Rev. 0 | Page 13 of 16
ADG±308VADG±309
OUTLINE DIꢂENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
10.00 (0.3937)
9.80 (0.3858)
16
1
9
8
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.75 (0.0689)
1.35 (0.0531)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
× 45°
0.25 (0.0098)
0.10 (0.0039)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 24. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
RU-16
RU-16
R-16
ADG1308BRUZ1
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Narrow Body Small Outline Package [SOIC_N]
16-Lead Narrow Body Small Outline Package [SOIC_N]
ADG1308BRUZ-REEL71
ADG1308BRZ1
ADG1308BRZ-REEL71
ADG1309BRUZ1
ADG1309BRUZ-REEL71
ADG1309BRZ1
ADG1309BRZ-REEL71
R-16
RU-16
RU-16
R-16
R-16
1 Z = Pb-free part.
Rev. 0 | Page 14 of 16
ADG±308VADG±309
NOTES
Rev. 0 | Page 15 of 16
ADG±308VADG±309
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06009-0-4/06(0)
Rev. 0 | Page 16 of 16
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