ADG3304BRUZ [ADI]
Low Voltage, 1.15 V to 5.5 V, 4-Channel, Bidirectional Logic Level Translator; 低电压， 1.15 V至5.5 V ， 4通道，双向逻辑电平转换器
| 型号： | ADG3304BRUZ |
| 厂家： | 
ADI |
| 描述： | Low Voltage, 1.15 V to 5.5 V, 4-Channel, Bidirectional Logic Level Translator |
| 文件： | 总20页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage, 1.15 V to 5.5 V, 4-Channel,
Bidirectional Logic Level Translator
Data Sheet
ADG3304
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Bidirectional level translation
Operates from 1.15 V to 5.5 V
Low quiescent current < 5 µA
No direction pin
V
V
CCY
CCA
A1
A2
A3
A4
EN
Y1
Y2
Y3
Y4
Qualified for automotive applications
APPLICATIONS
SPI®, MICROWIRE™ level translation
Low voltage ASIC level translation
Smart card readers
Cell phones and cell phone cradles
Portable communications devices
Telecommunications equipment
Network switches and routers
Storage systems (SAN/NAS)
Computing/server applications
GPS
GND
Figure 1.
Portable POS systems
Low cost serial interfaces
GENERAL DESCRIPTION
The ADG3304 is a bidirectional logic level translator that con-
tains four bidirectional channels. It can be used in multivoltage
digital system applications, such as data transfer, between a low
voltage digital signal processing controller and a higher voltage
device using SPI and MICROWIRE interfaces. The internal
architecture allows the device to perform bidirectional logic
level translation without an additional signal to set the direction
in which the translation takes place.
The enable pin (EN) provides three-state operation on both the
A side and the Y side pins. When the EN pin is pulled low, the
terminals on both sides of the device are in the high impedance
state. The EN pin is referred to the VCCA supply voltage and
driven high for normal operation.
The ADG3304 is available in compact 14-lead TSSOP, 12-ball
WLCSP, and 20-lead LFCSP. It is guaranteed to operate over
the 1.15 V to 5.5 V supply voltage range.
The voltage applied to VCCA sets the logic levels on the A side of
the device, while VCCY sets the levels on the Y side. For proper
operation, VCCA must always be less than VCCY. The VCCA-com-
patible logic signals applied to the A side of the device appear as
PRODUCT HIGHLIGHTS
1. Bidirectional level translation.
2. Fully guaranteed over the 1.15 V to 5.5 V supply range.
3. No direction pin.
V
CCY-compatible levels on the Y side. Similarly, VCCY-compatible
logic levels applied to the Y side of the device appear as VCCA
compatible logic levels on the A side.
-
4. Available in 14-lead TSSOP, 12-ball WLCSP, and 20-lead
LFCSP.
Rev. D
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ADG3304
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits..................................................................................... 12
Terminology .................................................................................... 15
Theory of Operation ...................................................................... 16
Level Translator Architecture ................................................... 16
Input Driving Requirements..................................................... 16
Output Load Requirements ...................................................... 16
Enable Operation ....................................................................... 16
Power Supplies............................................................................ 16
Data Rate ..................................................................................... 17
Applications..................................................................................... 18
Layout Guidelines....................................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Automotive Products................................................................. 20
REVISION HISTORY
4/13—Rev. C to Rev. D
12/05—Rev. A to Rev. B
Changes to Figure 3 and Table 4..................................................... 7
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................6
Changes to Figure 3 and Table 4......................................................7
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide.......................................................... 21
12/12—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 6
Changes to VCCY Description, Table 3 and Table 4....................... 7
Changes to Ordering Guide .......................................................... 20
Added Automotive Products Section........................................... 20
6/05—Rev. 0 to Rev. A
Added LFCSP Package.......................................................Universal
1/05—Revision 0: Initial Version
Rev. D | Page 2 of 20
Data Sheet
ADG3304
SPECIFICATIONS
VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V, TA = 25°C. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version1
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
LOGIC INPUTS/OUTPUTS
A Side
Input High Voltage2
VIHA
VCCA = 1.2 V + 0.1 V/−0.05 V
VCCA = 1.8 V 0.15 V
VCCA = 2.5 V 0.2 V
VCCA × 0.88
VCCA × 0.72
1.7
V
V
V
VCCA = 3.3 V 0.3 V
2.2
V
VCCA = 5 V 0.5 V
VCCA = 1.2 V + 0.1 V/−0.05 V
VCCA = 1.8 V 0.15 V
VCCA × 0.7
V
V
Input Low Voltage2
VILA
VCCA × 0.35
VCCA × 0.35
0.7
V
V
VCCA = 2.5 V 0.2 V
VCCA = 3.3 V 0.3 V
0.8
V
VCCA = 5 V 0.5 V
VCCA × 0.3
V
Output High Voltage
Output Low Voltage
Capacitance2
VOHA
VOLA
CA
VCCA − 0.4
V
VY = VCCY, IOH = 20 µA, see Figure 29
VY = 0 V, IOL = 20 µA, see Figure 29
f = 1 MHz, EN = 0, see Figure 34
VA = 0 V/VCCA, EN = 0, see Figure 31
0.4
1
V
9
pF
µA
Leakage Current
ILA, Hi-Z
Y Side
Input High Voltage2
VIHY
VCCY = 1.8 V 0.15 V
VCCY × 0.67
V
VCCY = 2.5 V 0.2 V
1.7
V
VCCY = 3.3 V 0.3 V
2
V
VCCY = 5 V 0.5 V
VCCY = 1.8 V 0.15 V
VCCY × 0.7
V
V
Input Low Voltage2
VILY
VCCY × 0.35
0.7
VCCY = 2.5 V 0.2 V
V
VCCY = 3.3 V 0.3 V
0.8
V
VCCY = 5 V 0.5 V
VCCY × 0.25
V
Output High Voltage
Output Low Voltage
Capacitance2
VOHY
VOLY
CY
VCCY − 0.4
V
VA = VCCA, IOH = 20 µA, see Figure 30
VA = 0 V, IOL = 20 µA, see Figure 30
f = 1 MHz, EN = 0, see Figure 35
VY = 0 V/VCCY, EN = 0, see Figure 32
0.4
1
V
6
pF
µA
Leakage Current
ILY, Hi-Z
Enable (EN)
Input High Voltage2
VIHEN
VCCA = 1.2 V + 0.1 V/−0.05 V
VCCA = 1.8 V 0.15 V
VCCA = 2.5 V 0.2 V
VCCA = 3.3 V 0.3 V
VCCA = 5 V 0.5 V
VCCA × 0.88
VCCA × 0.72
1.7
2.2
VCCA × 0.7
V
V
V
V
V
Input Low Voltage2
VILEN
VCCA = 1.2 V + 0.1 V/−0.05 V
VCCA = 1.8 V 0.15 V
VCCA = 2.5 V 0.2 V
VCCA = 3.3 V 0.3 V
VCCA = 5 V 0.5 V
VCCA × 0.35
VCCA × 0.35
0.7
0.8
VCCA × 0.3
1
V
V
V
V
V
µA
pF
µs
Leakage Current
Capacitance2
Enable Time2
ILEN
CEN
tEN
V
EN = 0 V/VCCA, VA = 0 V, see Figure 33
3
1
1.8
RS = RT = 50 Ω, VA = 0 V/VCCA (A→Y),
VY = 0 V/VCCY (Y→A), see Figure 36
Rev. D | Page 3 of 20
ADG3304
Data Sheet
B Version1
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
SWITCHING CHARACTERISTICS2
3.3 V 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V 0.5 V
A→Y Level Translation
Propagation Delay
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
6
2
2
10
ns
tP, A→Y
Rise Time
3.5
3.5
ns
tR, A→Y
Fall Time
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
50
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
2
4
3
ns
Y→A Level Translation
Propagation Delay
Rise Time
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
4
1
3
7
3
7
ns
tP, Y→A
ns
tR, Y→A
Fall Time
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
50
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
3.5
2
ns
1.8 V 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay
8
2
2
11
5
ns
tP, A→Y
Rise Time
ns
tR, A→Y
Fall Time
5
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
50
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
2
4
4
ns
Y→A Translation
Propagation Delay
Rise Time
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
5
2
2
8
ns
tP, Y→A
3.5
3.5
ns
tR, Y→A
Fall Time
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
50
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
3
3
ns
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay
Rise Time
9
3
2
18
5
ns
tP, A→Y
ns
tR, A→Y
Fall Time
5
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
40
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
2
5
10
ns
Y→A Translation
Propagation Delay
Rise Time
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
5
2
2
9
4
4
ns
tP, Y→A
ns
tR, Y→A
Fall Time
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
40
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
4
4
ns
Rev. D | Page 4 of 20
Data Sheet
ADG3304
B Version1
Parameter
Symbol
Test Conditions/Comments
Min
Typ Max
Unit
1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V 0.3 V
A→Y Translation
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay
12
7
25
12
5
ns
tP, A→Y
Rise Time
ns
tR, A→Y
Fall Time
3
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
25
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
2
5
15
ns
Y→A Translation
Propagation Delay
Rise Time
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
14
5
35
16
6.5
ns
tP, Y→A
ns
tR, Y→A
Fall Time
2.5
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
2.5 V 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V 0.3 V
A→Y Translation
25
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
3
6.5
23.5
ns
RS = RT = 50 Ω, CL = 50 pF, see Figure 37
Propagation Delay
7
10
4
ns
tP, A→Y
Rise Time
2.5
2
ns
tR, A→Y
Fall Time
5
ns
tF, A→Y
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
Y→A Translation
Propagation Delay
Rise Time
60
Mbps
ns
DMAX, A→Y
tSKEW, A→Y
tPPSKEW, A→Y
1.5
2
4
ns
RS = RT = 50 Ω, CL = 15 pF, see Figure 38
5
1
3
8
4
5
ns
tP, Y→A
ns
tR, Y→A
Fall Time
ns
tF, Y→A
Maximum Data Rate
Channel-to-Channel Skew
Part-to-Part Skew
60
Mbps
ns
DMAX, Y→A
tSKEW, Y→A
tPPSKEW, Y→A
2
3
3
ns
POWER REQUIREMENTS
Power Supply Voltages
VCCA
VCCY
ICCA
VCCA ≤ VCCY
1.15
1.65
5.5
5.5
5
V
V
µA
Quiescent Power Supply Current
VA = 0 V/VCCA, VY = 0 V/VCCY
VCCA = VCCY = 5.5 V, EN = 1
VA = 0 V/VCCA, VY = 0 V/VCCY
VCCA = VCCY = 5.5 V, EN = 1
,
,
0.17
0.27
ICCY
5
µA
Three-State Mode Power Supply Current
IHi-Z, A
IHi-Z, Y
VCCA = VCCY = 5.5 V, EN = 0
VCCA = VCCY = 5.5 V, EN = 0
0.1
0.1
5
5
µA
µA
1 TA for typical specifications is 25°C.
2 Guaranteed by design, not production tested.
Rev. D | Page 5 of 20
ADG3304
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VCCA to GND
VCCY to GND
−0.3 V to +7 V
VCCA to +7 V
Digital Inputs (A)
Digital Inputs (Y)
EN to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance (4-Layer Board)
14-Lead TSSOP
−0.3 V to (VCCA + 0.3 V)
−0.3 V to (VCCY + 0.3 V)
−0.3 V to +7 V
−40°C to +85°C
−65°C to +150°C
150°C
Only one absolute maximum rating can be applied at any one
time.
ESD CAUTION
89.21°C/W
12-Ball WLCSP
120°C/W
20-Lead LFCSP
30.4°C/W
Lead Temperature, Soldering
As per JEDEC J-STD-020
Rev. D | Page 6 of 20
Data Sheet
ADG3304
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
BALL A1
INDICATOR
1
2
3
PIN 1
INDICATOR
NC
A2
A3
A4
NC
1
2
3
4
5
15 NC
1
2
3
4
5
6
7
V
14
13
12
11
V
CCA
CCY
V
V
Y1
A1
CCY
14 Y2
13 Y3
12 Y4
11 NC
ADG3304
TOP VIEW
(Not to Scale)
A1
A2
Y1
Y2
Y3
A
B
C
D
ADG3304
TOP VIEW
(Not to Scale)
Y2
Y3
Y4
A2
A3
A4
CCA
A3
EN
A4
10 Y4
9
8
NC
NC
EN
GND
NC = NO CONNECT
GND
NOTES
1. THE EXPOSED PADDLE CAN BE TIED TO GND
OR LEFT FLOATING. DO NOT TIE IT TO V or V
TOP VIEW
(BALLS AT THE BOTTOM)
Not to Scale
CCA CCY.
NC = NO CONNECT
Figure 2. 14-Lead TSSOP
Pin Configuration
Figure 3. 12-Ball WLCSP
Pin Configuration
Figure 4. 20-Lead LFCSP_VQ
Pin Configuration
Table 3. 14-Lead TSSOP and 20-lead LFCSP Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
VCCA
A1
A2
A3
A4
NC
GND
EN
Description
Power Supply Voltage Input for the A1 to A4 I/O Pins (1.15 V ≤ VCCA ≤ VCCY).
1
2
3
4
5
6, 9
7
19
20
2
3
Input/Output A1. Referenced to VCCA
Input/Output A2. Referenced to VCCA
Input/Output A3. Referenced to VCCA
Input/Output A4. Referenced to VCCA
No Connect.
.
.
.
.
4
1, 5, 6, 7, 10, 11, 15, 16
8
9
Ground.
Active High Enable Input.
8
10
11
12
13
14
12
13
14
17
18
Y4
Y3
Y2
Y1
Input/Output Y4. Referenced to VCCY
Input/Output Y3. Referenced to VCCY
Input/Output Y2. Referenced to VCCY
Input/Output Y1. Referenced to VCCY
Power Supply Voltage Input for the Y1 to Y4 I/O Pins (1.65 V ≤ VCCY ≤ 5.5 V).
.
.
.
.
VCCY
Table 4. 12-Ball WLCSP Pin Function Descriptions
Bump No.
Mnemonic
Description
Input/Output Y1. Referenced to VCCY
Input/Output Y2. Referenced to VCCY
Input/Output Y3. Referenced to VCCY
Input/Output Y4. Referenced to VCCY.
A1
B1
C1
D1
Y1
Y2
Y3
Y4
.
.
.
A2
B2
C2
VCCY
VCCA
EN
Power Supply Voltage Input for the Y1 to Y4 I/O Pins (1.65 V ≤ VCCY ≤ 5.5 V).
Power Supply Voltage Input for the A1 to A4 I/O Pins (1.15 V ≤ VCCA ≤ VCCY).
Active High Enable Input.
D2
A3
GND
A1
Ground.
Input/Output A1. Referenced to VCCA
Input/Output A2. Referenced to VCCA
Input/Output A3. Referenced to VCCA
Input/Output A4. Referenced to VCCA
.
.
.
.
B3
C3
D3
A2
A3
A4
Rev. D | Page 7 of 20
ADG3304
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
C
1 CHANNEL
= 15pF
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
= 50pF
C
L
L
V
= 3.3V, V
CCY
= 5V
CCA
V
= 3.3V, V = 5V
CCY
CCA
V
= 1.8V, V
= 3.3V
CCA
CCY
V
= 1.8V, V
= 3.3V
CCA
CCY
V
= 1.2V, V
= 1.8V
40
V
= 1.2V, V
CCY
= 1.8V
CCA
CCY
CCA
25
DATA RATE (Mbps)
0
5
10
15
20
30
35
40
45
50
0
5
10
15
20
25
30
35
45
50
DATA RATE (Mbps)
Figure 5. ICCA vs. Data Rate (A→Y Level Translation)
Figure 8. ICCY vs. Data Rate (Y→A Level Translation)
10
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
C
1 CHANNEL
V
V
9
8
7
6
5
4
3
2
1
0
= 50pF
L
= 1.2V
= 1.8V
CCA
CCY
20Mbps
V
= 3.3V, V = 5V
CCY
CCA
10Mbps
5Mbps
V
= 1.8V, V = 3.3V
CCY
CCA
V
= 1.2V, V = 1.8V
CCY
CCA
1Mbps
53
0
5
10
15
20
25
30
35
40
45
50
13
23
33
43
63
73
DATA RATE (Mbps)
CAPACITIVE LOAD (pF)
Figure 9. ICCY vs. Capacitive Load at Pin Y for A→Y (1.2 V→1.8 V)
Figure 6. ICCY vs. Data Rate (A→Y Level Translation)
Level Translation
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
= 15pF
1 CHANNEL
V
V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
C
L
= 1.2V
=1.8V
CCA
CCY
V
= 3.3V, V = 5V
CCY
CCA
20Mbps
V
= 1.8V, V
= 3.3V
CCA
CCY
10Mbps
5Mbps
V
= 1.2V, V
CCY
= 1.8V
CCA
1Mbps
0
5
10
15
20
25
30
35
40
45
50
13
23
33
CAPACITIVE LOAD (pF)
43
53
DATA RATE (Mbps)
Figure 10. ICCA vs. Capacitive Load at Pin A for Y→A (1.8 V→1.2 V)
Figure 7. ICCA vs. Data Rate (Y→A Level Translation)
Level Translation
Rev. D | Page 8 of 20
Data Sheet
ADG3304
9
7
6
5
4
3
2
1
0
T
= 25°C
A
T
= 25°C
A
1 CHANNEL
V
V
1 CHANNEL
V
V
8
7
6
5
4
3
2
1
0
= 1.8V
= 3.3V
CCA
CCY
= 3.3V
= 5V
CCA
CCY
50Mbps
50Mbps
30Mbps
20Mbps
30Mbps
20Mbps
10Mbps
5Mbps
10Mbps
5Mbps
63
13
23
33
43
53
73
13
23
33
43
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 11. ICCY vs. Capacitive Load at Pin Y for A→Y (1.8 V→3.3 V)
Figure 14. ICCA vs. Capacitive Load at Pin A for Y→A (5 V→3.3 V)
Level Translation
Level Translation
5.0
10
T
= 25°C
T = 25°C
A
A
1 CHANNEL
1 CHANNEL
DATA RATE = 50kbps
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
9
8
7
6
5
4
3
2
1
0
V
V
= 1.8V
= 3.3V
V
= 1.2V, V = 1.8V
CCY
CCA
CCY
CCA
50Mbps
30Mbps
V
= 1.8V, V
= 3.3V, V
= 3.3V
= 5V
CCA
CCY
20Mbps
10Mbps
V
CCA
CCY
5Mbps
13
23
33
43
53
13
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 12. ICCA vs. Capacitive Load at Pin A for Y→A (3.3 V→1.8 V)
Figure 15. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation)
Level Translation
4.0
12
T
= 25°C
T
= 25°C
A
A
1 CHANNEL
DATA RATE = 50kbps
1 CHANNEL
V
V
50Mbps
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 3.3V
= 5V
CCA
CCY
V
= 1.2V, V = 1.8V
CCY
10
8
CCA
30Mbps
20Mbps
V
= 1.8V, V = 3.3V
CCY
CCA
6
4
V
= 3.3V, V = 5V
CCY
CCA
10Mbps
5Mbps
2
0
13
13
23
33
43
53
63
73
23
33
43
53
63
73
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 13. ICCY vs. Capacitive Load at Pin Y for A→Y (3.3 V→5 V)
Figure 16. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation)
Level Translation
Rev. D | Page 9 of 20
ADG3304
Data Sheet
10
12
10
8
DATA RATE = 50kbps
T
= 25°C
A
V
= 1.2V, V = 1.8V
CCY
A
T
= 25°C
CCA
1 CHANNEL
DATA RATE = 50kbps
9
8
7
6
5
4
3
2
1
0
1 CHANNEL
V
= 1.2V, V = 1.8V
CCY
CCA
6
V
= 1.8V, V = 3.3V
CCY
CCA
4
V
= 1.8V, V = 3.3V
CCY
CCA
2
V
= 3.3V, V
63
= 5V
73
CCA
CCY
V
= 3.3V, V
CCY
= 5V
53
CCA
0
13
23
33
43
53
13
18
23
28
33
38
43
48
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 20. Propagation Delay (tPHL) vs.
Capacitive Load at Pin Y (A→Y Level Translation)
Figure 17. Rise Time vs. Capacitive Load at Pin A (Y→A Level Translation)
9
8
7
6
5
4
3
2
1
0
4.0
T = 25°C
A
1 CHANNEL
DATA RATE = 50kbps
T
= 25°C
A
1 CHANNEL
DATA RATE = 50kbps
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 1.2V, V = 1.8V
CCY
CCA
V
= 1.2V, V = 1.8V
CCY
CCA
V
= 1.8V, V
CCY
= 3.3V
= 5V
CCA
V
V
= 1.8V, V = 3.3V
CCY
= 3.3V, V
CCY
CCA
CCA
V
= 3.3V, V
43
= 5V
CCA
CCY
13
18
23
28
33
38
48
53
13
18
23
28
33
38
43
48
53
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
Figure 21. Propagation Delay (tPLH) vs.
Capacitive Load at Pin A (Y→A Level Translation)
Figure 18. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation)
9
8
7
6
5
4
3
2
1
0
T
= 25°C
A
14
1 CHANNEL
DATA RATE = 50kbps
T
= 25°C
A
1 CHANNEL
DATA RATE = 50kbps
V
= 1.2V, V = 1.8V
CCY
CCA
12
10
8
V
= 1.2V, V = 1.8V
CCY
CCA
6
V
= 1.8V, V = 3.3V
CCY
CCA
V
= 1.8V, V = 3.3V
CCY
CCA
V
= 3.3V, V = 5V
CCY
4
CCA
V
= 3.3V, V = 5V
CCY
CCA
2
13
18
23
28
33
38
43
48
53
0
13
23
33
43
53
63
CAPACITIVE LOAD (pF)
73
CAPACITIVE LOAD (pF)
Figure 19. Propagation Delay (tPLH) vs.
Capacitive Load at Pin Y (A→Y Level Translation)
Figure 22. Propagation Delay (tPHL) vs.
Capacitive Load at Pin A (Y→A Level Translation)
Rev. D | Page 10 of 20
Data Sheet
ADG3304
T
= 25°C
A
T
= 25°C
A
DATA RATE = 25Mbps
C
1 CHANNEL
DATA RATE = 50Mbps
= 15pF
= 50pF
L
C
L
1 CHANNEL
400mV/DIV
5ns/DIV
400mV/DIV
3ns/DIV
Figure 26. Eye Diagram at A Output
(3.3 V to 1.8 V Level Translation, 50 Mbps)
Figure 23. Eye Diagram at Y Output
(1.2 V to 1.8 V Level Translation, 25 Mbps)
T
= 25°C
C
= 50pF
A
L
T
= 25°C
A
DATA RATE = 25Mbps
1 CHANNEL
DATA RATE = 50Mbps
CL = 50pF
1 CHANNEL
200mV/DIV
5ns/DIV
1V/DIV
3ns/DIV
Figure 27. Eye Diagram at Y Output
(3.3 V to 5 V Level Translation, 50 Mbps)
Figure 24. Eye Diagram at A Output
(1.8 V to 1.2 V Level Translation, 25 Mbps)
T
= 25°C
T
= 25°C
C = 50pF
L
A
A
DATA RATE = 50Mbps
C
DATA RATE = 50Mbps 1 CHANNEL
= 15pF
L
1 CHANNEL
500mV/DIV
3ns/DIV
3ns/DIV
800mV/DIV
Figure 25. Eye Diagram at Y Output
Figure 28. Eye Diagram at A Output
(1.8 V to 3.3 V Level Translation, 50 Mbps)
(5 V to 3.3 V Level Translation, 50 Mbps)
Rev. D | Page 11 of 20
ADG3304
Data Sheet
TEST CIRCUITS
EN
V
ADG3304
CCY
V
CCA
0.1µF
0.1µF
EN
V
Y
ADG3304
CCY
V
CCA
A
Y
0.1µF
0.1µF
K2
K1
K
A
GND
A
I
I
OH
OL
GND
Figure 29. VOH/VOL Voltages at Pin A
Figure 32. Three-State Leakage Current at Pin Y
EN
ADG3304
V
CCA
V
Y
CCY
0.1µF
0.1µF
V
ADG3304
CCY
V
CCA
0.1µF
K2
A
0.1µF
K1
Y
A
GND
EN
A
I
I
OH
GND
OL
K
Figure 33. EN Pin Leakage Current
Figure 30. VOH/VOL Voltages at Pin Y
EN
EN
V
ADG3304
CCY
V
ADG3304
CCY
V
CCA
V
CCA
0.1µF
0.1µF
A
Y
Y
A
A
K
CAPACITANCE
METER
GND
GND
Figure 34. Capacitance at Pin A
Figure 31. Three-State Leakage Current at Pin A
Rev. D | Page 12 of 20
Data Sheet
ADG3304
EN
V
Y
ADG3304
CCY
V
CCA
A
CAPACITANCE
METER
GND
Figure 35. Capacitance at Pin Y
AY DIRECTION
V
V
CCA
CCY
ADG3304
+
+
0.1F
10F
0.1F
10F
1M
A
Y
V
A
V
Y
K1
K2
50pF
1M
SIGNAL SOURCE
EN
GND
Z
= 50
R
0
V
S
EN
50
R
50
T
YA DIRECTION
V
V
CCA
CCY
ADG3304
+
+
0.1F
10F
0.1F
10F
1M
A
Y
V
V
A
Y
K1
1M
K2
15pF
SIGNAL SOURCE
EN
GND
Z
= 50
0
R
S
V
EN
50
R
50
T
V
CCA
tEN1
V
EN
0V
V
/V
CCA CCY
V
/V
A
Y
0V
V
/V
CCY CCA
90%
V
/V
Y
A
0V
V
CCA
tEN2
V
EN
0V
V
/V
A
Y
V
/V
CCA CCY
0V
V
/V
CCY CCA
V
/V
A
Y
10%
0V
NOTES
1. tEN IS WHICHEVER IS LARGER BETWEEN tEN1 AND tEN2
IN BOTH AY AND YA DIRECTIONS.
Figure 36. Enable Time
Rev. D | Page 13 of 20
ADG3304
Data Sheet
V
V
CCY
CCY
EN
EN
ADG3304
ADG3304
+
+
V
V
+
CCA
CCA
0.1µF
10µF
0.1µF
10µF
+
SIGNAL
SOURCE
SIGNAL
SOURCE
0.1µF
10µF
0.1µF
= 50Ω
10µF
Z
0
= 50Ω
R
S
Z
A
Y
V
R
R
S
0
V
A
V
V
A
Y
Y
A
Y
50Ω
R
50Ω
T
T
15pF
50pF
50Ω
50Ω
GND
GND
V
Y
V
A
50%
90%
50%
90%
tP,Y→A
tP,Y→A
tP,A→Y
tP,A→Y
V
A
V
Y
50%
10%
50%
10%
tF,Y→A
tR,Y→A
tF,A→Y
tR,A→Y
Figure 38. Switching Characteristics (Y→A Level Translation)
Figure 37. Switching Characteristics (A→Y Level Translation)
Rev. D | Page 14 of 20
Data Sheet
ADG3304
TERMINOLOGY
VIHA
TF, A→Y
Logic input high voltage at Pin A1 to Pin A4.
Fall time when translating logic levels in the A→Y direction.
VILA
DMAX, A→Y
Logic input low voltage at Pin A1 to Pin A4.
Guaranteed data rate when translating logic levels in the A→Y
direction under the driving and loading conditions specified in
Table 1.
VOHA
Logic output high voltage at Pin A1 to Pin A4.
TSKE W, A→Y
VOLA
Difference between propagation delays on any two channels
when translating logic levels in the A→Y direction.
Logic output low voltage at Pin A1 to Pin A4.
CA
tPPSKEW, A→Y
Capacitance measured at Pin A1 to Pin A4 (EN = 0).
Difference in propagation delay between any one channel and
the same channel on a different part (under same driving/
loading conditions) when translating in the A→Y direction.
ILA, Hi-Z
Leakage current at Pin A1 to Pin A4 when EN = 0 (high
impedance state at Pin A1 to Pin A4).
tP, Y → A
VIHY
Propagation delay when translating logic levels in the Y→A
direction.
Logic input high voltage at Pin Y1 to Pin Y4.
VILY
tR, Y→A
Logic input low voltage at Pin Y1 to Pin Y4.
Rise time when translating logic levels in the Y→A direction.
VOHY
tF, Y→A
Logic output high voltage at Pin Y1 to Pin Y4.
Fall time when translating logic levels in the Y→A direction.
VOLY
DMAX, Y→A
Logic output low voltage at Pin Y1 to Pin Y4.
Guaranteed data rate when translating logic levels in the Y→A
direction under the driving and loading conditions specified in
Table 1.
CY
Capacitance measured at Pin Y1 to Pin Y4 (EN = 0).
ILY, Hi-Z
tSKE W, Y→ A
Leakage current at Pin Y1 to Pin Y4 when EN = 0 (high
impedance state at Pin Y1 to Pin Y4).
Difference between propagation delays on any two channels
when translating logic levels in the Y→A direction.
VIHEN
tPPSKEW, Y→A
Logic input high voltage at the EN pin.
Difference in propagation delay between any one channel and
the same channel on a different part (under the same driving/
loading conditions) when translating in the Y→A direction.
VILEN
Logic input low voltage at the EN pin.
VCCA
CEN
V
CCA supply voltage.
Capacitance measured at EN pin.
VCCY
ILEN
VCCY supply voltage.
Enable (EN) pin leakage current.
ICCA
tEN
V
CCA supply current.
Three-state enable time for Pin A1 to Pin A4 and Pin Y1 to
Pin Y4.
ICCY
VCCY supply current.
tP, A →Y
Propagation delay when translating logic levels in the A→Y
direction.
IHi-Z, A
V
CCA supply current during three-state mode (EN = 0).
tR, A→Y
IHi-Z, Y
Rise time when translating logic levels in the A→Y direction.
V
CCY supply current during three-state mode (EN = 0).
Rev. D | Page 15 of 20
ADG3304
Data Sheet
THEORY OF OPERATION
The ADG3304 level translator allows the level shifting
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, VCCA and
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3304, the circuit that
drives the input of the ADG3304 channels should have an
output impedance of less than or equal to 150 Ω and a
minimum peak current driving capability of 36 mA.
V
CCY (VCCA ≤ VCCY). These supplies set the logic levels on each
side of the device. When driving the A pins, the device translates
the VCCA-compatible logic levels to VCCY-compatible logic levels
available at the Y pins. Similarly, because the device is capable of
OUTPUT LOAD REQUIREMENTS
bidirectional translation, when driving the Y pins, the VCCY
-
The ADG3304 level translator is designed to drive CMOS-
compatible loads. If current-driving capability is required, it is
recommended to use buffers between the ADG3304 outputs
and the load.
compatible logic levels are translated to VCCA-compatible logic
levels available at the A pins. When EN = 0, Pin A1 to Pin A4
and Pin Y1 to Pin Y4 are three-stated. When EN is driven high,
the ADG3304 goes into normal operation mode and performs
level translation.
ENABLE OPERATION
The ADG3304 provides three-state operation at the A and Y
I/O pins by using the enable pin (EN), as shown in Table 5.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3304 consists of four bidirectional channels. Each
channel can translate logic levels in either the A→Y or the Y→A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics. Figure 39 shows a
simplified block diagram of a bidirectional channel.
Table 5. Truth Table
EN
Y I/O Pins
A I/O Pins
Hi-Z1
Normal operation2
0
1
Hi-Z1
Normal operation2
1 High impedance state.
V
V
CCY
2 In normal operation, the ADG3304 performs level translation.
CCA
While EN = 0, the ADG3304 enters into three-state mode. In this
mode, the current consumption from both the VCCA and VCCY
supplies is reduced, allowing the user to save power, which is
critical, especially on battery-operated systems. The EN input pin
can be driven with either VCCA-compatible or VCCY-compatible
logic levels.
T1
T2
6kΩ
U1
U2
P
A
ONE-SHOT GENERATOR
Y
N
POWER SUPPLIES
For proper operation of the ADG3304, the voltage applied to
the VCCA must be less than or equal to the voltage applied to VCCY
To meet this condition, the recommended power-up sequence
is VCCY first and then VCCA. The ADG3304 operates properly
only after both supply voltages reach their nominal values. It is
not recommended to use the part in a system where, during
power-up, VCCA can be greater than VCCY due to a significant
increase in the current taken from the VCCA supply. For
optimum performance, the VCCA pin and VCCY pin should be
decoupled to GND as close as possible to the device.
.
U4
U3
6kΩ
T4
T3
Figure 39. Simplified Block Diagram of an ADG3304 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y→A direction is performed using Inverter U3
and Inverter U4. The one-shot generator detects a rising or
falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS
transistors (T1 to T2) for a rising edge, or the NMOS transistors
(T3 to T4) for a falling edge. This charges/discharges the
capacitive load faster, which results in faster rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding VCC rail (VCCA or VCCY) or to GND.
Rev. D | Page 16 of 20
Data Sheet
ADG3304
DATA RATE
The maximum data rate at which the device is guaranteed to
operate is a function of the VCCA and VCCY supply voltage
combination and the load capacitance. It is given by the
maximum frequency of a square wave that can be applied to the
device, which meets the VOH and VOL levels at the output and
does not exceed the maximum junction temperature (see the
Absolute Maximum Ratings section). Table 6 shows the
guaranteed data rates at which the ADG3304 can operate in
both directions (A→Y or Y→A level translation) for various VCCA
and VCCY supply combinations.
Table 6. Guaranteed Data Rate (Mbps)1
VCCY
1.8 V
(1.65 V to 1.95 V)
2.5 V
(2.3 V to 2.7 V)
3.3 V
(3.0 V to 3.6 V)
5 V
VCCA
(4.5 V to 5.5 V)
1.2 V (1.15 V to 1.3 V)
1.8 V (1.65 V to 1.95 V)
2.5 V (2.3 V to 2.7 V)
3.3 V (3.0 V to 3.6 V)
5 V (4.5 V to 5.5 V)
25
-
-
-
-
30
45
-
-
-
40
50
60
-
40
50
50
50
-
-
1 The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction.
Rev. D | Page 17 of 20
ADG3304
Data Sheet
APPLICATIONS
The ADG3304 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pins, and the higher voltage logic signals are connected to the
Y pins. The ADG3304 can provide level translation in both
directions from A→Y or Y→A on all four channels, eliminating
the need for a level translator IC for each direction. The internal
architecture allows the ADG3304 to perform bidirectional level
translation without an additional signal to set the direction in
which the translation is made. It also allows simultaneous data
flow in both directions on the same part, for example, when two
channels translate in A→Y direction while the other two translate
in Y→A direction. This simplifies the design by eliminating the
timing requirements for the direction signal and reducing the
number of ICs used for level translation.
100nF
100nF
V
V
CCA
CCY
Y1
1.8V
3.3V
I/O
H1
A1
A2
A3
I/O
I/O
I/O
I/O
L1
ADG3304
I/O
H2
Y2
L2
L3
L4
MICROPROCESSOR/
MICROCONTROLLER/
DSP
PERIPHERAL
DEVICE 1
Y3
I/O
H3
A4
EN
Y4
I/O
H4
GND
CS
GND
GND
100nF
100nF
V
V
CCA
CCY
3.3V
A1
A2
A3
Y1
I/O
I/O
I/O
I/O
H1
H2
H3
H4
ADG3304
Y2
PERIPHERAL
DEVICE 2
Figure 40 shows an application where two microprocessors
operating at 1.8 V and 3.3 V, respectively, can transfer data
simultaneously using two full-duplex serial links, TX1/RX1
and TX2/RX2.
Y3
A4
EN
Y4
GND
GND
Figure 41. 1.8 V to 3.3 V Level Translation Circuit
Using the Three-State Feature
100nF
100nF
LAYOUT GUIDELINES
V
V
CCA
CCY
1.8V
3.3V
As with any high speed digital IC, the printed circuit board
layout is important for the overall performance of the circuit.
Care should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each VCC pin (VCCA and
RX1
TX1
RX2
A1
A2
A3
Y1
TX1
RX1
TX2
RX2
ADG3304
Y2
MICROPROCESSOR/
MICROCONTROLLER/
DSP
MICROPROCESSOR/
MICROCONTROLLER/
DSP
Y3
V
CCY) should be bypassed using low effective series resistance
A4
EN
Y4
TX2
GND
GND
GND
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the VCCA pin and the VCCY pin. The parasitic
inductance of the high speed signal track may cause significant
overshoot. This effect can be reduced by keeping the length of
the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.
Figure 40. 1.8 V to 3.3 V Level Translation Circuit on
Two Full-Duplex Serial Links
When the application requires level translation between a micro-
processor and multiple peripheral devices, the ADG3304 I/O
pins can be three-stated by setting EN = 0. This feature allows
the ADG3304 to share the data buses with other devices without
causing contention issues. Figure 41 shows an application where
a 1.8 V microprocessor is connected to a 3.3 V peripheral
device using the three-state feature.
Rev. D | Page 18 of 20
Data Sheet
ADG3304
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
0.15
0.05
COPLANARITY
0.10
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 42. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
1.670
1.610
1.550
BOTTOM VIEW
(BALL SIDE UP)
3
2
1
A
BALL A1
IDENTIFIER
2.070
2.010
1.950
1.50
REF
B
C
D
0.50
BSC
TOP VIEW
(BALL SIDE DOWN)
0.17
1.00
REF
0.15
0.13
0.370
0.350
0.330
0.650
0.590
0.530
END VIEW
COPLANARITY
0.10
SEATING
PLANE
0.280
0.240
0.220
0.360
0.320
0.280
Figure 43. 12-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-12-1)
Dimensions shown in millimeters
Rev. D | Page 19 of 20
ADG3304
Data Sheet
4.10
4.00 SQ
3.90
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.50
BSC
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
EXPOSED
PAD
3.75
BCS SQ
10
11
6
0.75
0.60
0.50
0.25 MIN
BOTTOM VIEW
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 44. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model1, 2
Temperature Range
−40°C to +85°C
Package Description
Branding3 Option
ADG3304BRUZ
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12-Ball Wafer Level Chip Scale Package [WLCSP]
12-Ball Wafer Level Chip Scale Package [WLCSP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
RU-14
RU-14
RU-14
CP-20-1
CP-20-1
CB-12-1
CB-12-1
RU-14
ADG3304BRUZ-REEL
ADG3304BRUZ-REEL7
ADG3304BCPZ-REEL
ADG3304BCPZ-REEL7
ADG3304BCBZ-REEL
ADG3304BCBZ-REEL7
ADG3304WBRUZ-REEL
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
SDC
SDC
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Branding on these packages is limited to three characters due to space constraints.
AUTOMOTIVE PRODUCTS
The ADG3304W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
© 2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04860-0-4/13(D)
Rev. D | Page 20 of 20
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