ADG3308BRU [ADI]
Low Voltage 1.2 V to 5.5 V, Bidirectional, Logic Level Translators; 低电压1.2 V至5.5 V ，双向逻辑电平转换器
| 型号： | ADG3308BRU |
| 厂家： | 
ADI |
| 描述： | Low Voltage 1.2 V to 5.5 V, Bidirectional, Logic Level Translators |
| 文件： | 总5页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
Low Voltage 1.2 V to 5.5 V,
a
Bidirectional,LogicLevelTranslators
Preliminary Technical Data
ADG3308
FEATURES
F U NC T IO NAL B LO C K D IAG RAM
Bidirectional Level Translation
Operates from 1.2 V to 5.5 V
Low Quiescent Current <5µA
V
V
CCY
CCA
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
A3
A4
A5
A6
A7
APPLICATIONS
SPITM, Microw ireTM and I2CTM Translation
Low Voltage ASIC level Translation
Sm art Card Readers
Cell Phones & Cell-Phone Cradles
Portable Com m unication Devices
Telecom m unicatons Equipm ent
Netw ork Sw itches and Routers
Storage System s (SAN/ NAS)
Com puting/ Server Applications
GPS
A8
EN
Portable POS System s
Low Cost Serial Interfaces
GND
G E NE R AL D E S C R IP T IO N
P R O D U C T H IG H LIG H T S
1. Bidirectional Level T ranslation.
2. T he ADG3308 is fully guaranteed from 1.2 V to
5.5 V supply range.
T he ADG3308 is an 8-Channel bidirectional level transla-
tor. Its function is to provide level shifting in a multi-
voltage system. T he voltage applied to VCCA sets up the
logic levels on the A side of the device, while VCCY sets
the levels on the Y side. In this way, signals applied to the
VCCA side of the device appear as VCCY compatible logic
on the other side of the device and vice versa as the device
is designed to handle bidirectional signals. T he device is
guaranteed for operation over the supply range 1.2 V to
5.5 V.
3. 20 lead T SSOP and LFCSP (4mm x4mm) packages.
T hese devices are suited to applications like data transfer
between a low voltage DSP/Controller and a higher
voltage device. Other applications include high end
consumer products where constant changes to the chipset
desgins result in multiple supply levels in the application.
VCCY operates from +1.65 to 5.5 V while VCCA from +1.2
to VCCY. VCCA must always operate from a supply that is
lower than VCCY. When the device Enable pin (EN) is
pulled low, the Ax and Yx inputs/outputs are tri-stated.
T he EN pin is driven high for normal operation. EN pin
is referred to VCCY voltage.
REV. PrE Feb 2004
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w.analog.com
Analog Devices, Inc., 2004
PRELIMINARY TECHNICAL DATA
1
ADG3308–SPECIFICATIONS
(VCCY = +1.65 to 5.5 V, VCCA = +1.1 to V , GND = 0 V, All specifications TMIN to TMAX unless otherwise noted)
CCY
P ar am eter
Sym bol
Conditions
Min
Typ2 Max
Units
LOGIC INPUT S/OUT PUT S
Input High Voltage
VIH
VCCY -0.4
VCCA -0.4
V
V
Input Low Voltage
Output High Voltage
Output Low Voltage
V
0.4
0.4
V
V
V
V
IL
VOH
VOL
IOH = 20 µA,
IOH = 20 µA,
IOL = 20 µA,
VCCY -0.4
VCCA -0.4
0.4
V
IOL = 20 µA,
0.4
V
Input Leakage Current
Output Leakage Current
Input Capacitance3
II
IO
CIN
CO
0 Յ VIN Յ 3.6 V
0 Յ VIN Յ 3.6 V
f = 1 MHz, VA/Y = VCCA/Y or GND
f = 1 MHz, VA/Y = VCCY/A or GND
± 1
± 1
µA
µA
pF
pF
5
5
Output Capacitance3
SWIT CHING CHARACT ERIST ICS3
3.3V ± 0.3V
Յ VCCA Յ VCCY Յ 5V ± 0.5V
Propagation Delay, tPD
Y - A
A - Y
tR_Y
tF_Y
tR_A
RS = 50Ω, CA = 15 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CA = 15 pF
RS = 50Ω, CA = 15 pF
5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
Rise T ime
Fall T ime
Rise T ime
Fall T ime
tF_A
Maximum Data Rate
Channel T o Channel Skew
Part T o Part Skew
RS = 50Ω, CY = 50 pF, CA = 15 pF
RS = 50Ω, CY = 50 pF, CA = 15 pF
RS = 50Ω, CY = 50 pF, CA = 15 pF
40
Mbps
ns
ns
tSKEW
tPPSKEW
tbd
tbd
1.8V ± 0.15V
Propagation Delay, tPD
Յ
V
CCA Յ VCCY
Յ
3.3V ±0.3V
Y - A
RS = 50Ω, CA = 15 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CA = 15 pF
RS = 50Ω, CA = 15 pF
10
15
10
10
10
10
ns
ns
ns
ns
ns
ns
A - Y
tR_Y
tF_Y
Rise T ime
Fall T ime
Rise T ime
Fall T ime
tR_A
tF_A
Maximum Data Rate
Channel T o Channel Skew
RS = 50Ω, CY = 50 pF, CA = 15 pF
RS = 50Ω, CY = 50 pF, CA = 15 pF
35
Mbps
ns
tSKEW
5
1.2V ± 0.1 V
Յ VCCA Յ VCCY Յ 3.3 ± 0.3 V
Propagation Delay, tPD
Y - A
A - Y
RS = 50Ω, CA = 15 pF
RS = 50Ω, CY = 50 pF
20
20
ns
ns
Rise T ime
Fall T ime
Rise T ime
Fall T ime
tR_Y
tF_Y
tR_A
tF_A
RS = 50Ω, CY = 50 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CA = 15 pF
RS = 50Ω, CA = 15 pF
15
15
15
15
ns
ns
ns
ns
Maximum Data Rate
Channel T o Channel Skew
RS = 50Ω, CY = 50 pF, CA = 15 pF
RS = 50Ω, CY = 50 pF, CA = 15 pF
20
Mbps
ns
tSKEW
5
2.5V ± 0.2V
Յ VCCA Յ VCCY Յ 3.3V ± 0.3V
Propagation Delay, tPD
Y - A
A - Y
tR_Y
tF_Y
tR_A
RS = 50Ω, CA = 15 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CY = 50 pF
RS = 50Ω, CA = 15 pF
RS = 50Ω, CA = 15 pF
8.5
8.5
8.5
8.5
8.5
8.5
ns
ns
ns
ns
ns
ns
Rise T ime
Fall T ime
Rise T ime
Fall T ime
tF_A
Maximum Data Rate
Channel T o Channel Skew
RS = 50Ω, CY = 50 pF, CA = 15 pF
RS = 50Ω, CY = 50 pF, CA = 15 pF
40
Mbps
ns
tSKEW
10
POWER REQUIREMENT S
Power Supply Voltages
VCCY
VCCA
ICCY
ICCA
1.65
1.1
5.5
5.5
5
V
V
µA
µA
Quiescent Power Supply Current
Digital Inputs = 0 V or VCCY
Digital Inputs = 0 V or VCCA
5
N O T E S
1T emperature range is as follows:
B
Version: –40°C to + 85°C .
+25°C unless otherwise stated.
G uaranteed by design, not subject to production test.
2
3
All typical vlaues are at T A
=
Specifications subject to change without notice.
REV. PrE
–2 –
PRELIMINARY TECHNICAL DATA
ADG3308
AB SO LU T E M AXIM U M RAT ING S1
P in C on figu r a t ion
(T A
= 25°C unless otherwise noted)
20 Lead TSSO P (RU-20)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
Y
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
VA
A
1
2
3
4
5
6
7
VY
Y1
Y2
20
19
Digtal Inputs (A) . . . . . . . . . . . . . . -0.3 V to (VCC +0.3V)
A
A1
A2
A3
Digtal Inputs (Y) . . . . . . . . . . . . . . -0.3 V to (VCC +0.3V)
Y
18
17
EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
Operating T emperature Range
Industrial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
20 Lead T SSOP
ADG3308
Y3
Y4
Y5
(Not to Scale) 16
15
A4
A5
A6
A7
14
13
12
11
Y6
8
9
Y7
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . 143°C /W
20 Lead LFCSP - 4 layer board
A8
EN
Y8
10
GND
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 32°C /W
Lead T emperature, Soldering (10seconds) . . . . . . . 300°C
IR Reflow, Peak T emperature (<20 seconds) . . . + 235°C
20 Lead 4m m x4m m LFC SP
( C P - 2 0 )
N O T E S
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. T his is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specifcation is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be applied at
any one time.
A2
A3
A4
A5
A6
1
2
3
4
5
15Y3
14Y4
13 Y5
12Y6
11Y7
PIN 1
INDICATOR
ADG3308
TOP VIEW
O R D E R ING G U ID E
Model
Tem perature Range
P ackage D escription
P ackage O ption
AD G 3308BRU
AD G 3308BC P
–40°C to +85°C
–40°C to +85°C
T SSO P
L F C SP
RU -20
C P-20
C A U T I O N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD G 3308 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper
E SD p recau tion s are recom m en d ed to avoid p erform an ce d egrad ation or loss of
fu n ction ality.
WARNING!
ESD SENSITIVE DEVICE
REV. PrE
–3 –
PRELIMINARY TECHNICAL DATA
ADG3308
G E NE R AL D E S C R IP T IO N
large mos devices in the output stage to help speed up the
rate of switching. T he output stage is inactive and three
state except when transistions are present on either side of
the translator. When this happens the one shot fires turn-
ing on the output stage and driving the load capacitance
faster than if it were driven through the resistor. As the
device is bi-directional, both input stages will be active
during this period. While this design gives maximum
speed from the device, it can result in some current driv-
ing back into the source driving the input of the translator.
T he ADG3308 level translator allows the required level
shifting necessary for data transfer in a system where mul-
tiple voltages are used. T he device requires two supplies,
VCCA and VCCY. T hese supplies set the logic levels on
each side of the device. T he device translates data present
on the VA side of the device to the higher voltage level at
the VY side of the device. Similarly, as the device is ca-
pable of bidirectional translation, data applied to the VY
side will be translated to the voltage referenced to VA.
P ower Supplies
T he voltage applied to VCCA must always be less than or
T o ensure correct operation, the input driver should meet
the following requirements - 50 Ω maximum output im-
pedance with minimum of 20mA output current when
driving 20M bps.
equal to VCCY
.
While EN is low, the VCCA supply may be removed, and
both A and Y I/O’s will remain tri-stated.
E n a b le O p er a tion
Level T r a n sla tor Ar ch itectu r e
When pulled low, the EN input allows the user to tri-state
both sides (A and Y) of the level translator. EN pin is
referred to VCCY voltage.
T he forward channel consists of a string of inverters and a
level translator, while the reverse channel consists simply
of inverters. A level translator is not required in the re-
verse path (Y-A) as the supply voltage VCCY must always
be greater than or equal to VCCA. A current limiting resis-
tor is used in series with each channel to prevent any con-
tention issues, see figure 1.
VCCY
VCCA
One Shot
Generator
6k
A
Y
One Shot
Generator
6k
Figure 1. Sim plified Functional Diagram of one channel.
As the driven side has to drive a load capacitance through
this 6k resistance, one shot generators are used to drive
REV. PrE
–4 –
PRELIMINARY TECHNICAL DATA
ADG3308
O U T LINE D IM E NS IO NS
D imensions shown in inches and (mm).
20-Lead T SSO P
(RU- 20)
0.260 (6.60)
0.252 (6.40)
20
11
10
1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.0433
(1.10)
MAX
8o
0o
0.028 (0.70)
0.020 (0.50)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
20-Lead LFCSP
(C P - 20)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.010 (0.25)
0.157 (4.0)
BSC SQ
MIN
BOTTOM
VIEW
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
16
15
20
1
PIN 1
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
0.030 (0.75)
0.024 (0.60)
0.020 (0.50)
0.080 (2.25)
0.083 (2.10) SQ
0.077 (1.95)
INDICATOR
0.148 (3.75)
BSC SQ
TOP
VIEW
11
10
5
6
0.028 (0.70) MAX
0.026 (0.65) NOM
12o MAX
0.080 (2.00)
REF
0.035 (0.90) MAX
0.033 (0.85) NOM
0.002 (0.05)
0.0004 (0.01)
0.0 (0.0)
SEATING
PLANE
0.020 (0.50)
BSC
0.008 (0.20)
REF
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. PrE
–5 –
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