ADG333ABRZ-REEL [ADI]
Quad SPDT Switch;
| 型号： | ADG333ABRZ-REEL |
| 厂家： | 
ADI |
| 描述： | Quad SPDT Switch 开关 光电二极管 |
| 文件： | 总8页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Quad SPDT Switch
ADG333A
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
44 V Supply Maxim um Ratings
VSS to VDD Analog Signal Range
Low On Resistance (45 ⍀ m ax)
Low ∆RON (5 ⍀ m ax)
S4A
D2
S1A
D1
S4B
S1B
Low RON Match (4 ⍀ m ax)
Low Pow er Dissipation
Fast Sw itching Tim es
IN1
IN4
ADG333A
IN2
IN3
tON < 175 ns
tOFF < 145 ns
S2B
D2
S3B
D3
Low Leakage Currents (5 nA m ax)
Low Charge Injection (10 pC m ax)
Break-Before-Make Sw itching Action
S2A
S3A
SWITCHES SHOWN FOR A LOGIC “1” INPUT
APPLICATIONS
Audio and Video Sw itching
Battery Pow ered System s
Test Equipm ent
Com m unication System s
P RO D UCT H IGH LIGH TS
GENERAL D ESCRIP TIO N
1. Extended Signal Range
T he ADG333A is a monolithic CMOS device comprising four
independently selectable SPDT switches. It is designed on an
LC2MOS process which provides low power dissipation yet
achieves a high switching speed and a low on resistance.
T he ADG333A is fabricated on an enhanced LC2MOS
process, giving an increased signal range which extends
to the supply rails.
2. Low Power Dissipation
3. Low RON
T he on resistance profile is very flat over the full analog input
range ensuring good linearity and low distortion when switching
audio signals. High switching speed also makes the part suitable
for video signal switching. CMOS construction ensures ultralow
power dissipation making the part ideally suited for portable,
battery powered instruments.
4. Single Supply Operation
For applications where the analog signal is unipolar,
the ADG333A can be operated from a single rail power
supply. T he part is fully specified with a single +12 V
supply.
When they are ON, each switch conducts equally well in both
directions and has an input signal range which extends to the
power supplies. In the OFF condition, signal levels up to the
supplies are blocked. All switches exhibit break-before-make
switching action for use in multiplexer applications. Inherent in
the design is low charge injection for minimum transients when
switching the digital inputs.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
1
ADG333A–SPECIFICATIONS
(V = +15 V, V = –15 V, GND = 0 V, unless otherwise noted)
DUAL SUPPLY
DD
SS
–40؇C to
+85؇C
P aram eter
+25؇C
Units
Test Conditions/Com m ents
ANALOG SWIT CH
Analog Signal Range
RON
VSS to VDD
V
20
45
Ω typ
Ω max
Ω max
Ω max
VD = ±10 V, IS = –1 mA
45
5
4
∆RON
RON Match
VD = ±5 V, IS = –10 mA
VD = ±10 V, IS = –10 mA
LEAKAGE CURRENT S
Source OFF Leakage IS (OFF)
VDD = +16.5 V, VSS = –16.5 V
VD = ±15.5 V, VS = +15.5 V
T est Circuit 2
VS = VD = ±15.5 V
T est Circuit 3
±0.1
±0.25
±0.1
±0.4
nA typ
nA max
nA typ
nA max
±3
±5
Channel ON Leakage ID, IS (ON)
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
I
INL or IINH
±0.005
±0.5
µA typ
µA max
VIN = 0 V or VDD
DYNAMIC CHARACT ERIST ICS2
tON
90
80
10
ns typ
ns max
ns typ
ns max
ns min
RL = 300 Ω, CL = 35 pF;
VS = ±10 V; T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = ±10 V; T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = +5 V; T est Circuit 5
VD = 0 V, RD = 0 Ω, CL = 10 nF;
VDD = +15 V, VSS = –15 V; T est Circuit 6
RL = 75 Ω, CL = 5 pF, f = 1 MHz;
VS = 2.3 V rms, T est Circuit 7
RL = 75 Ω, CL = 5 pF, f = 1 MHz;
VS = 2.3 V rms, T est Circuit 8
175
145
tOFF
Break-Before-Make Delay, tOPEN
Charge Injection
2
10
72
pC typ
pC max
dB typ
OFF Isolation
Channel-to-Channel Crosstalk
85
dB typ
CS (OFF)
CD, CS (ON)
5
20
pF typ
pF typ
POWER REQUIREMENT S
IDD
0.05
0.25
0.01
1
mA typ
mA max
µA typ
Digital Inputs = 0 V or 5 V
0.35
ISS
5
µA max
VDD/VSS
±3/±20
V min/V max | VDD| = | VSS|
NOT ES
1T emperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG333A
(V = +12 V, V = 0 V ؎ 10%, GND = 0 V, unless otherwise noted)
SINGLE SUPPLY
DD
SS
–40؇C to
+85؇C
P aram eter
+25؇C
Units
Test Conditions/Com m ents
ANALOG SWIT CH
Analog Signal Range
RON
0 to VDD
75
V
35
Ω typ
Ω max
VD = +1 V, +10 V, IS = –1 mA
LEAKAGE CURRENT S
VDD = +13.2 V
Source OFF Leakage IS (OFF)
±0.1
±0.25
±0.1
±0.4
nA typ
nA max
nA typ
nA max
VD = 12.2 V/1 V, VS = 1 V/12.2 V
T est Circuit 2
VS = VD = 12.2 V/1 V
T est Circuit 3
±3
±5
Channel ON Leakage ID, IS (ON)
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
I
INL or IINH
±0.005
±0.5
µA typ
µA max
VIN = 0 V or VDD
DYNAMIC CHARACT ERIST ICS2
tON
110
100
10
5
ns typ
ns max
ns typ
ns max
ns min
ns min
pC typ
RL = 300 Ω, CL = 35 pF;
VS = +8 V; T est Circuit 4
RL = 300 Ω, CL = 35 pF;
VS = +8 V; T est Circuit 4
RL = 300 Ω , CL = 35 pF;
VS = +5 V; T est Circuit 5
VD = 6 V, RD = 0 Ω, CL = 10 nF;
VDD = +12 V, VSS = –0 V; T est Circuit 6
RL = 75 Ω, CL = 5 pF, f = 1 MHz;
VS = 1.15 V rms, T est Circuit 7
RL = 75 Ω, CL = 5 pF, f = 1 MHz;
VS = 1.15 V rms, T est Circuit 8
200
180
tOFF
Break-Before-Make Delay, tOPEN
Charge Injection
OFF Isolation
72
85
dB typ
dB typ
Channel-to-Channel Crosstalk
CS (OFF)
CD, CS (ON)
5
20
pF typ
pF typ
POWER REQUIREMENT S
IDD
VDD = +13.5 V
Digital Inputs = 0 V or 5 V
0.05
0.25
mA typ
mA max
0.35
VDD
+3/+30
V min/V max
NOT ES
1T emperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
ADG333A
ABSO LUTE MAXIMUM RATINGS1
(T A = +25°C unless otherwise noted)
SOIC Package
JA, T hermal Impedance . . . . . . . . . . . . . . . . . . . . . 74°C/W
θ
Lead T emperature, Soldering
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –30 V
Analog, Digital Inputs2 . . . . . . . . . . . . VSS – 2 V to VDD + 2 V
. . . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package
θ
JA, T hermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
Operating T emperature Range
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Only one absolute maximum rating may be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +125°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic Package
θ
JA, T hermal Impedance . . . . . . . . . . . . . . . . . . . . 103°C/W
Lead T emperature, Soldering (10 sec) . . . . . . . . . . +260°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG333A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
O RD ERING GUID E
Tem perature Range
Table I. Truth Table
Model
P ackage O ption*
Logic
Switch A
Switch B
ADG333ABN
ADG333ABR
ADG333ABRS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-20
R-20
RS-20
0
1
OFF
ON
ON
OFF
*N = Plastic DIP, R = Small Outline IC (SOIC). RS = Shrink Small Outline
Package (SSOP).
–4–
REV. 0
ADG333A
TERMINO LO GY
S
CD, CS (ON)
tON
“ON” Switch Capacitance.
Source T erminal. May be an input or output.
Drain T erminal. May be an input or output.
Logic Control Input.
Delay between applying the digital control in-
put and the output switching on.
D
IN
tOFF
Delay between applying the digital control in-
put and the output switching off.
RON
∆RON
Ohmic resistance between D and S.
tOPEN
Break Before Make delay when switches are
configured as a multiplexer.
RON variation due to a change in the analog
input voltage with a constant load current.
VINL
VINH
Maximum input voltage for logic “0.”
Minimum input voltage for logic “1.”
Input current of the digital input.
RON Match
IS (OFF)
Difference between the RON of any two
channels.
Source leakage current with the switch
“OFF.”
IINL (IINH
Crosstalk
)
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
I
D (OFF)
Drain leakage current with the switch
“OFF.”
ID, IS (ON)
Channel leakage current with the switch
“ON.”
Off Isolation
A measure of unwanted signal coupling
through an “OFF” switch.
VD (VS)
Analog voltage on terminals D, S.
“OFF” Switch Source Capacitance.
“OFF” Switch Drain Capacitance.
Charge Injection A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
CS (OFF)
CD (OFF)
P IN CO NFIGURATIO N
D IP /SO IC/SSO P
1
2
3
4
5
6
7
8
20
19
18
17
16
IN1
S1A
D1
IN4
S4A
D4
S1B
S4B
V
V
ADG333A
TOP VIEW
(Not to Scale)
SS
DD
15 NC
14 S3B
13 D3
GND
S2B
D2
S3A
IN3
12
11
S2A
IN2
9
10
NC = NO CONNECT
REV. 0
–5–
ADG333A–Typical Performance Graphs
60
20
15
60
V
V
= +15V
C
= 10nF
DD
SS
L
T
= +25°C
A
= 0V
50
40
30
20
10
50
40
30
20
10
10
V
V
= +5V
= –5V
DD
SS
+85°C
+125°C
5
V
V
= +16.5V
= –16.5V
DD
SS
0
V
V
= +12V
= –0V
DD
SS
V
V
= +10V
–5
DD
= –10V
SS
–10
–15
–20
+25°C
–40°C
V
V
= +15V
= –15V
DD
SS
0
3
6
9
12
15
–15
–10
–5
0
5
10
15
–15
–10
–5
0
5
10
15
V
, V – Volts
S
V
– Volts
D
S
V
, V – Volts
S
D
Figure 4. RON as a Function of VD (VS)
for Different Tem peratures: Single
Supply
Figure 7. Charge Injection as a
Function of VS
Figure 1. RON as a Function of VD
(VS): Dual Supply
160
0.004
100
V
V
= +2V
= –2V
T
= +25°C
D
S
V
V
T
= +16.5V
= –16.5V
A
DD
SS
90
80
70
60
50
40
30
20
0.002
0
V
V
= +5V
= 0V
I
(OFF)
DD
SS
140
120
100
80
S
= +25°C
A
–0.002
–0.004
–0.006
–0.008
–0.01
I
(ON)
S
V
V
= +10V
DD
SS
I
(ON)
D
= 0V
V
V
= +15V
= 0V
DD
SS
60
–15
–10
–5
0
5
10
15
0
5
10
15
20
0
3
6
9
12
15
V
– Volts
V
, V – Volts
S
V
, V – Volts
DD
D
D
S
Figure 8. Switching Tim e as a
Function of VDD
Figure 5. Leakage Currents as a
Function of VD (VS): Dual Supply
Figure 2. RON as a Function of VD (VS):
Single Power Supply
1
0.001
45
V
V
T
= +16.5V
= –16.5V
V
V
= +15V
= –15V
DD
SS
I
(OFF)
DD
SS
S
40
35
30
25
20
15
10
0.8
0.6
0.4
0.2
0
0
–0.001
–0.002
–0.003
–0.004
= +25°C
A
V
V
T
= +16.5V
= –16.5V
DD
SS
= +25°C
A
+125°C
+85°C
I
(ON)
D
I
(ON)
S
–40°C
+25°C
0
200
400
600
800
1000
0
3
6
9
12
–15
–10
–5
0
5
10
15
V
, V – Volts
SWITCHING FREQUENCY – kHz
D
S
V
, V – Volts
S
D
Figure 9. IDD as a Function of
Switching Frequency
Figure 6. Leakage Currents as a
Function of VD (VS): Single Supply
Figure 3. RON as a Function of VD (VS)
for Different Tem peratures: Dual
Supply
–6–
REV. 0
ADG333A
I
DS
V
1
I
(OFF)
A
S
I
(ON)
A
D
S
D
NC
V
D
S
D
V
D
S
D
V
V
D
S
R
= V /I
1
ON
DS
Test Circuit 1. On Resistance
Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage
V
DD
0.1µF
3V
V
DD
50%
50%
V
IN
SB
–10V
+10V
D
0V
V
V
S
OUT
SA
R
C
L
L
IN
+10V
0V
tOFF
300Ω
35pF
V
S
V
GND
SS
50%
50%
tON
–10V
0.1µF
V
SS
Test Circuit 4. Switching Tim es
V
DD
0.1µF
3V
V
DD
V
IN
SB
SA
D
V
S
V
0V
OUT
R
L
300Ω
C
35pF
L
IN
V
S
50%
50%
V
OUT
V
GND
SS
tOPEN
0.1µF
V
SS
Test Circuit 5. Break-Before-Make Delay, tOPEN
V
DD
V
DD
3V
R
D
V
IN
V
V
OUT
D
0V
D
SA
V
IN
C
L
10nF
V
OUT
∆V
OUT
Q
= CL x ∆V
INJ
OUT
GND
SS
0V
V
SS
Test Circuit 6. Charge Injection
V
DD
0.1µF
V
V
DD
DD
75Ω
0.1µF
S
D
V
DD
V
S
V
V
IN1
IN2
V
OUT
S
D
R
L
S
D
V
IN
75Ω
NC
V
OUT
V
S
V
GND
V
SS
SS
GND
R
L
75Ω
CHANNEL TO CHANNEL
CROSSTALK
0.1µF
0.1µF
20 x LOG
|
V
/ V
|
S
OUT
V
V
SS
SS
Test Circuit 7. Off Isolation
Test Circuit 8. Channel-to-Channel Crosstalk
REV. 0
–7–
ADG333A
AP P LICATIO NS INFO RMATIO N
AD G333A Supply Voltages
can be clearly seen from the characteristic curves in this data
sheet.
T he ADG333A can operate off a dual or signal supply. VSS
should be connected to GND when operating with a single
supply. When using a dual supply the ADG333A can also oper-
ate with unbalanced supplies, for example VDD = 20 V and VSS
= –5 V. T he only restrictions are that VDD to GND must not
exceed 30 V, VSS to GND must not drop below –30 V and VDD
to VSS must not exceed +44 V. It is important to remember that
the ADG333A supply voltage directly affects the input signal
range, the switch ON resistance and the switching times of the
part. T he effects of the power supplies on these characteristics
P ower Supply Sequencing
When using CMOS devices care must be taken to ensure
correct power-supply sequencing. Incorrect power-supply
sequencing can result in the device being subjected to stresses
beyond those maximum ratings listed in the data sheet. T his is
also true for the ADG333A. Always sequence VDD on first
followed by VSS and the logic signals. An external signal within
the maximum specified ratings can then be safely presented to
the source or drain of the switch
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-P in P lastic D IP (N-20)
20-P in SO IC (R-20)
1.060 (26.90)
0.925 (23.50)
0.5118 (13.00)
0.4961 (12.60)
20
1
11
0.280 (7.11)
20
11
0.240 (6.10)
10
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.300 (7.62)
PIN 1
0.210 (5.33)
MAX
1
10
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.1043 (2.65)
0.0926 (2.35)
0.015 (0.381)
0.008 (0.204)
PIN 1
0.0291 (0.74)
0.0098 (0.25)
SEATING
PLANE
0.100
(2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.022 (0.558)
0.014 (0.356)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
20-P in SSO P (RS-20)
0.295 (7.50)
0.271 (6.90)
20
11
10
1
0.07 (1.78)
0.078 (1.98)
0.068 (1.73)
PIN 1
0.066 (1.67)
0.037 (0.94)
8°
0°
0.0256
(0.65)
BSC
0.022 (0.559)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
LEADS WILL BE EITHER TIN PLATED OR SOLDIER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
–8–
REV. 0
相关型号：
©2020 ICPDF网 联系我们和版权申明