ADG419BRMZ-REEL7 [ADI]

LC2MOS Precision Mini-DIP Analog Switch;
ADG419BRMZ-REEL7
型号: ADG419BRMZ-REEL7
厂家: ADI    ADI
描述:

LC2MOS Precision Mini-DIP Analog Switch

光电二极管
文件: 总8页 (文件大小:113K)
中文:  中文翻译
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LC2MOS Precision  
Mini-DIP Analog Switch  
a
ADG419  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
44 V Supply Maximum Ratings  
VSS to VDD Analog Signal Range  
Low On Resistance (< 35 )  
Ultralow Power Dissipation (< 35 W)  
Fast Transition Time (160 ns max)  
Break-Before-Make Switching Action  
Plug-In Replacement for DG419  
D
S2  
IN  
S1  
ADG419  
SWITCH SHOWN FOR A  
LOGIC "1" INPUT  
APPLICATIONS  
Precision Test Equipment  
Precision Instrumentation  
Battery Powered Systems  
Sample Hold Systems  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
The ADG419 is a monolithic CMOS SPDT switch. This  
switch is designed on an enhanced LC2MOS process that pro-  
vides low power dissipation yet gives high switching speed, low  
on resistance and low leakage currents.  
1. Extended Signal Range  
The ADG419 is fabricated on an enhanced LC2MOS pro-  
cess, giving an increased signal range that extends to the  
supply rails.  
The on resistance profile of the ADG419 is very flat over the full  
analog input range, ensuring excellent linearity and low distor-  
tion. The part also exhibits high switching speed and high signal  
bandwidth. CMOS construction ensures ultralow power dissipa-  
tion, making the parts ideally suited for portable and battery  
powered instruments.  
2. Ultralow Power Dissipation  
3. Low RON  
4. Single Supply Operation  
For applications where the analog signal is unipolar, the  
ADG419 can be operated from a single rail power supply.  
The part is fully specified with a single +12 V power supply  
and will remain functional with single supplies as low as  
+5 V.  
Each switch of the ADG419 conducts equally well in both  
directions when ON and has an input signal range that extends  
to the supplies. In the OFF condition, signal levels up to the  
supplies are blocked. The ADG419 exhibits break-before-  
make switching action.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1998  
ADG419–SPECIFICATIONS1  
(VDD = +15 V ؎ 10%, VSS = –15 V ؎ 10%, VL = +5 V ؎ 10%, GND = 0 V, unless otherwise noted)  
Dual Supply  
B Version  
–40؇C to  
T Version  
–55؇C to  
+25؇C +125؇C  
Parameter  
+25؇C  
+85؇C  
Units  
Test Conditions/Comments  
ANALOG SWITCH  
Analog Signal Range  
RON  
VSS to VDD  
45  
VSS to VDD  
V
25  
35  
25  
35  
typ  
max  
VD = ±12.5 V, IS = –10 mA  
VDD = +13.5 V, VSS = –13.5 V  
45  
LEAKAGE CURRENTS  
Source OFF Leakage IS (OFF)  
VDD = +16.5 V, VSS = –16.5 V  
VD = ±15.5 V, VS = ϯ15.5 V;  
Test Circuit 2  
VD = ±15.5 V, VS = ϯ15.5 V;  
Test Circuit 2  
±0.1  
±0.25  
±0.1  
±0.75  
±0.4  
±0.75  
±0.1  
±0.25  
±0.1  
±0.75  
±0.4  
±0.75  
nA typ  
nA max  
nA typ  
nA max  
nA typ  
nA max  
±5  
±5  
±5  
±15  
±30  
±30  
Drain OFF Leakage ID (OFF)  
Channel ON Leakage ID, IS (ON)  
VS = VD = ±15.5 V;  
Test Circuit 3  
DIGITAL INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current  
2.4  
0.8  
2.4  
0.8  
V min  
V max  
IINL or IINH  
±0.005  
±0.5  
±0.005  
±0.5  
µA typ  
µA max  
VIN = VINL or VINH  
DYNAMIC CHARACTERISTICS2  
tTRANSITION  
160  
200  
145  
200  
ns max  
RL = 300 , CL = 35 pF;  
VS1 = ±10 V, VS2 = ϯ10 V;  
Test Circuit 4  
Break-Before-Make Time  
Delay, tD  
30  
5
30  
5
ns typ  
ns min  
RL = 300 , CL = 35 pF;  
VS1 = VS2 = ±10 V;  
Test Circuit 5  
OFF Isolation  
80  
90  
80  
70  
dB typ  
dB typ  
RL = 50 , f = 1 MHz;  
Test Circuit 6  
RL = 50 , f = 1 MHz;  
Test Circuit 7  
Channel-to-Channel Crosstalk  
CS (OFF)  
CD, CS (ON)  
6
55  
6
55  
pF typ  
pF typ  
f = 1 MHz  
f = 1 MHz  
POWER REQUIREMENTS  
IDD  
VDD = +16.5 V, VSS = –16.5 V  
VIN = 0 V or 5 V  
0.0001  
1
0.0001  
1
0.0001  
1
0.0001  
1
0.0001  
1
0.0001  
1
µA typ  
µA max  
µA typ  
µA max  
µA typ  
µA max  
2.5  
2.5  
2.5  
2.5  
2.5  
2.5  
ISS  
IL  
VL = +5.5 V  
NOTES  
1Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.  
2Guaranteed by design, not subject to production test.  
Specifications subject to change without notice.  
–2–  
REV. A  
ADG419  
(V = +12 V ؎ 10%, V = 0 V, V = +5 V ؎ 10%, GND = 0 V, unless otherwise noted)  
Single Supply  
DD  
SS  
L
B Version  
T Version  
–55؇C to  
+25؇C +125؇C  
–40؇C to  
+85؇C  
Parameter  
+25؇C  
Units  
Test Conditions/Comments  
ANALOG SWITCH  
Analog Signal Range  
RON  
0 to VDD  
60  
0 to VDD  
V
40  
40  
typ  
max  
VD = +3 V, +8.5 V, IS = –10 mA  
VDD = +10.8 V  
70  
LEAKAGE CURRENT  
VDD = +13.2 V  
Source OFF Leakage IS (OFF)  
Drain OFF Leakage ID (OFF)  
Channel ON Leakage ID, IS (ON)  
±0.1  
±0.25  
±0.1  
±0.75  
±0.4  
±0.75  
±0.1  
±0.25  
±0.1  
±0.75  
±0.4  
±0.75  
nA typ  
nA max  
nA typ  
nA max  
nA typ  
nA max  
VD = 12.2 V/1 V, VS = 1 V/12.2 V;  
Test Circuit 2  
VD = 12.2 V/1 V, VS = 1 V/12.2 V;  
Test Circuit 2  
VS = VD = 12.2 V/1 V;  
Test Circuit 3  
±5  
±5  
±5  
±15  
±30  
±30  
DIGITAL INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current  
2.4  
0.8  
2.4  
0.8  
V min  
V max  
IINL or IINH  
±0.005  
±0.5  
±0.005  
±0.5  
µA typ  
µA max  
VIN = VINL or VINH  
DYNAMIC CHARACTERISTICS2  
tTRANSITION  
180  
60  
250  
170  
60  
250  
ns max  
ns typ  
RL = 300 , CL = 35 pF;  
VS1 = 0 V/8 V, VS2 = 8 V/0 V;  
Test Circuit 4  
RL = 300 , CL = 35 pF;  
VS1 = VS2 = +8 V;  
Test Circuit 5  
Break-Before-Make Time  
Delay, tD  
OFF Isolation  
80  
90  
80  
70  
dB typ  
dB typ  
RL = 50 , f = 1 MHz;  
Test Circuit 6  
RL = 50 , f = 1 MHz;  
Test Circuit 7  
Channel-to-Channel Crosstalk  
CS (OFF)  
CD, CS (ON)  
13  
65  
13  
65  
pF typ  
pF typ  
f = 1 MHz  
f = 1 MHz  
POWER REQUIREMENTS  
IDD  
VDD = +13.2 V  
VIN = 0 V or 5 V  
0.0001  
1
0.0001  
1
0.0001  
1
0.0001  
1
µA typ  
µA max  
µA typ  
µA max  
2.5  
2.5  
2.5  
2.5  
IL  
VL = +5.5 V  
NOTES  
1Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.  
2Guaranteed by design, not subject to production test.  
Specifications subject to change without notice.  
Table I. Truth Table  
PIN CONFIGURATION  
DIP/SOIC/SOIC  
Logic  
Switch 1  
Switch 2  
0
1
ON  
OFF  
OFF  
ON  
1
2
3
4
8
7
6
5
S2  
V
D
S1  
ADG419  
TOP VIEW  
(Not to Scale)  
SS  
GND  
IN  
V
ORDERING GUIDE  
Temperature Ranges  
V
DD  
L
Model  
Package Options*  
ADG419BN  
ADG419BR  
ADG419BRM –40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
N-8  
SO-8  
RM-8  
Q-8  
ADG419TQ –55°C to +125°C  
*N = Plastic DIP, Q = Cerdip, RM = µSOIC, SO = 0.15" Small Outline IC (SOIC).  
REV. A  
–3–  
ADG419  
ABSOLUTE MAXIMUM RATINGS1  
(TA= +25°C unless otherwise noted)  
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 400 mW  
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 100°C/W  
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C  
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 400 mW  
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 155°C/W  
µSOIC Package, Power Dissipation . . . . . . . . . . . . . . . 315 mW  
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 205°C/W  
Lead Temperature, Soldering  
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V  
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V  
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V  
VL to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V  
Analog, Digital Inputs2 . . . . . . . . . . . . VSS – 2 V to VDD + 2 V  
or 30 mA, Whichever Occurs First  
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA  
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA  
(Pulsed at 1 ms, 10% Duty Cycle Max)  
Vapor Phase (60 sec). . . . . . . . . . . . . . . . . . . . . . . +215°C  
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C  
NOTES  
1Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those listed in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability. Only one absolute  
maximum rating may be applied at any one time.  
Operating Temperature Range  
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C  
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C  
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C  
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C  
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 600 mW  
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 110°C/W  
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C  
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be  
limited to the maximum ratings given.  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the ADG419 features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
TERMINOLOGY  
VDD  
VSS  
CD, CS (ON)  
tTRANSITION  
“ON” switch capacitance.  
Delay time between the 50% and 90% points  
of the digital inputs and the switch “ON”  
condition when switching from one address  
state to another.  
Most positive power supply potential.  
Most negative power supply potential in dual  
supplies. In single supply applications, it  
may be connected to GND.  
VL  
GND  
S
Logic power supply (+5 V).  
tD  
“OFF” time or “ON” time measured be-  
tween the 90% points of both switches  
when switching from one address state  
to the other.  
Maximum input voltage for logic “0.”  
Minimum input voltage for logic “1.”  
Input current of the digital input.  
A measure of unwanted signal which is  
coupled through from one channel to  
another as a result of parasitic capacitance.  
A measure of unwanted signal coupling  
through an “OFF” channel.  
Positive supply current.  
Negative supply current.  
Ground (0 V) reference.  
Source terminal. May be an input or an  
output.  
Drain terminal. May be an input or an  
output.  
VINL  
VINH  
D
I
INL (IINH  
)
IN  
RON  
IS (OFF)  
Logic control input.  
Crosstalk  
Ohmic resistance between D and S.  
Source leakage current with the switch  
“OFF.”  
Drain leakage current with the switch  
“OFF.”  
Off Isolation  
I
D (OFF)  
IDD  
ISS  
ID, IS (ON)  
Channel leakage current with the switch  
“ON.”  
V
D (VS)  
Analog voltage on terminals D, S.  
CS (OFF)  
“OFF” switch source capacitance.  
–4–  
REV. A  
Typical Performance Characteristics–ADG419  
50  
40  
30  
100  
T
= +25؇C  
A
T
= +25؇C  
A
V
= +5V  
= –5V  
DD  
V
SS  
V
= +5V  
= 0V  
80  
DD  
V
SS  
V
= +10V  
= –10V  
60  
40  
20  
0
DD  
V
V
= +10V  
= 0V  
SS  
DD  
V
= +12V  
= 0V  
DD  
V
SS  
V
SS  
20  
10  
0
V
V
= +12V  
DD  
= –12V  
SS  
V
= +15V  
= –15V  
DD  
V
= +15V  
V
DD  
SS  
V
= 0V  
SS  
0
5
10  
15  
–15  
–10  
–5  
0
, V – Volts  
5
10  
15  
V
, V – Volts  
D
V
S
S
D
Figure 1. RON as a Function of VD (VS): Dual Supply Voltage  
Figure 4. RON as a Function of VD (VS): Single Supply  
Voltage  
100  
50  
V
V
V
= +12V  
= 0V  
DD  
SS  
V
V
V
= +15V  
= –15V  
DD  
SS  
= +5V  
L
= +5V  
L
80  
60  
40  
40  
30  
20  
+125؇C  
+125؇C  
+85؇C  
+25؇C  
20  
0
10  
0
+85؇C  
+25؇C  
0
0
3
6
9
12  
–15  
–10  
–5  
5
10  
15  
V
, V – Volts  
D
V
, V – Volts  
D
S
S
Figure 2. RON as a Function of VD (VS) for Different  
Temperatures  
Figure 5. RON as a Function of VD (VS) for Different  
Temperatures  
0.006  
0.02  
V
V
T
= +15V  
= –15V  
V
V
T
= +12V  
= 0V  
I
(ON)  
DD  
DD  
SS  
D
SS  
= +25؇C  
= +25؇C  
A
I (ON)  
D
A
0.01  
0.00  
0.004  
0.002  
0.000  
I
(OFF)  
S
I
(OFF)  
S
I
(OFF)  
D
I
(OFF)  
–0.01  
D
– 0.02  
–0.03  
–0.002  
–0.004  
0
–15  
–10  
–5  
5
10  
15  
0
2
4
6
8
10  
12  
V
, V – Volts  
D
V
, V – Volts  
D
S
S
Figure 3. Leakage Currents as a Function of VS (VD)  
Figure 6. Leakage Currents as a Function of VS (VD)  
REV. A  
–5–  
ADG419  
220  
200  
180  
160  
10mA  
V
V
V
= +15V  
= –15V  
DD  
SS  
1mA  
100A  
10A  
= +5V  
L
I+, I–  
SINGLE SUPPLY  
= 0V/5V  
140  
120  
100  
80  
1A  
V
IN  
I
L
100nA  
DUAL SUPPLY  
V
= ؎5V  
10nA  
1nA  
IN  
2
3
4
5
6
7
6
8
10  
12  
14  
16  
10  
10  
10  
10  
10  
10  
SUPPLY VOLTAGE – Volts  
FREQUENCY – Hz  
Figure 8. Transition Time vs. Power Supply Voltage  
Figure 7. Supply Current vs. Input Switching Frequency  
Test Circuits  
I
DS  
V1  
I
(ON)  
I
(OFF)  
I
(OFF)  
D
D
S
S
D
S
D
S
D
V
V
D
V
V
D
S
V
S
S
R
= V /I  
1
ON  
DS  
Test Circuit 2. Off Leakage  
Test Circuit 3. On Leakage  
Test Circuit 1. On Resistance  
+15V  
+5V  
3V  
V
V
L
50%  
50%  
V
DD  
IN  
S1  
0V  
D
V
V
S1  
OUT  
tTRANSITION  
tTRANSITION  
90%  
S2  
R
V
C
L
L
S2  
300⍀  
35pF  
IN  
OUTPUT  
V
V
GND  
IN  
SS  
90%  
–15V  
Test Circuit 4. Transition Time, tTRANSITION  
+15V  
+5V  
V
V
L
DD  
3V  
ADDRESS  
D
S1  
S2  
DRIVE(V  
)
V
V
OUT  
IN  
S1  
0V  
V
V
C
R
S2  
L
L
tD  
tD  
35pF  
300⍀  
IN  
OUT  
0.9V  
0.9V  
0.9V  
0.9V  
O
O
O
O
V
V
IN  
GND  
SS  
–15V  
Test Circuit 5. Break-Before-Make Time Delay, tD  
–6–  
REV. A  
ADG419  
+15V  
0.1F  
+5V  
0.1F  
+15V  
0.1F  
+5V  
0.1F  
V
V
L
DD  
S1  
V
V
L
DD  
50⍀  
D
S
D
V
OUT  
V
S
R
L
S2  
50⍀  
V
IN  
OUT  
R
L
50⍀  
V
GND  
SS  
V
V
IN  
S
V
IN  
V
GND  
SS  
0.1F  
–15V  
0.1F  
–15V  
CHANNEL-TO-CHANNEL CROSSTALK = 20 
؋
 LOG | V /V  
|
OUT  
S
Test Circuit 6. Off Isolation  
Test Circuit 7. Crosstalk  
REV. A  
–7–  
ADG419  
OUTLINE DIMENSIONS  
Dimensions shown in inches and (mm).  
8-Lead Plastic DIP (N-8)  
8-Lead Cerdip (Q-8)  
0.430 (10.92)  
0.348 (8.84)  
0.055 (1.4)  
MAX  
0.005 (0.13)  
MIN  
8
5
8
5
0.280 (7.11)  
0.240 (6.10)  
0.310 (7.87)  
1
4
0.220 (5.59)  
4
0.325 (8.25)  
0.300 (7.62)  
1
0.060 (1.52)  
0.015 (0.38)  
PIN 1  
PIN 1  
0.195 (4.95)  
0.115 (2.93)  
0.320 (8.13)  
0.290 (7.37)  
0.210 (5.33)  
MAX  
0.405 (10.29)  
MAX  
0.130  
(3.30)  
MIN  
0.060 (1.52)  
0.015 (0.38)  
0.160 (4.06)  
0.115 (2.93)  
0.200 (5.08)  
MAX  
0.015 (0.381)  
0.008 (0.204)  
SEATING  
PLANE  
0.150  
(3.81)  
MIN  
0.100  
(2.54)  
BSC  
0.022 (0.558)  
0.014 (0.356)  
0.070 (1.77)  
0.045 (1.15)  
0.200 (5.08)  
0.125 (3.18)  
0.015 (0.38)  
0.008 (0.20)  
SEATING  
0.070 (1.78)  
0.030 (0.76)  
0.023 (0.58)  
0.014 (0.36)  
0.100  
(2.54)  
BSC  
15°  
0°  
PLANE  
8-Lead SOIC (SO-8)  
(Narrow Body)  
8-Lead SOIC (RM-8)  
0.122 (3.10)  
0.114 (2.90)  
0.1968 (5.00)  
0.1890 (4.80)  
8
1
5
4
5
4
8
1
0.1574 (4.00)  
0.1497 (3.80)  
0.2440 (6.20)  
0.2284 (5.80)  
0.122 (3.10)  
0.114 (2.90)  
0.199 (5.05)  
0.187 (4.75)  
PIN 1  
0.0688 (1.75)  
0.0532 (1.35)  
0.0196 (0.50)  
x 45°  
PIN 1  
0.0098 (0.25)  
0.0040 (0.10)  
0.0099 (0.25)  
0.0256 (0.65) BSC  
0.120 (3.05)  
0.112 (2.84)  
0.120 (3.05)  
0.112 (2.84)  
8°  
0°  
0.0500  
(1.27)  
BSC  
0.0192 (0.49)  
0.0138 (0.35)  
SEATING  
PLANE  
0.0098 (0.25)  
0.0075 (0.19)  
0.0500 (1.27)  
0.0160 (0.41)  
0.043 (1.09)  
0.037 (0.94)  
0.006 (0.15)  
0.002 (0.05)  
33؇  
27؇  
0.018 (0.46)  
0.008 (0.20)  
0.011 (0.28)  
0.003 (0.08)  
0.028 (0.71)  
0.016 (0.41)  
SEATING  
PLANE  
–8–  
REV. A  

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