ADG426BRSZ [ADI]
LC2MOS 8-/16-Channel High Performance Analog Multiplexers; LC2MOS 8位/ 16通道高性能模拟多路复用器
| 型号： | ADG426BRSZ |
| 厂家： | 
ADI |
| 描述： | LC2MOS 8-/16-Channel High Performance Analog Multiplexers |
| 文件： | 总20页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS 8-/16-Channel
High Performance Analog Multiplexers
ADG406/ADG407/ADG426
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
44 V supply maximum ratings
ADG406
VSS to VDD analog signal range
S1
Low on resistance (80 Ω maximum)
Low power
Fast switching
D
t
t
ON < 160 ns
OFF < 150 ns
Break-before-make switching action
S16
APPLICATIONS
1 OF 16
DECODER
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery powered systems
Sample hold systems
Communication systems
Avionics
A0 A1 A2 A3 EN
Figure 1.
ADG407
S1A
DA
S8A
PRODUCT HIGHLIGHTS
1. Extended Signal Range.
2. The ADG406/ADG407/ADG426 are fabricated on an
enhanced LC2MOS process giving an increased signal
range which extends to the supply rails.
S1B
S8B
DB
3. Low Power Dissipation.
1 OF 8
DECODER
4. Low RON
.
5. Single/Dual Supply Operation.
6. Single Supply Operation.
A0 A1 A2 EN
Figure 2.
7. For applications where the analog signal is unipolar, the
ADG406/ADG407/ADG426 can be operated from a single
rail power supply. The parts are fully specified with a single
+12 V power supply and remain functional with single
supplies as low as +5 V.
ADG426
S1
D
S16
WR
DECODER/
LATCHES
A0 A1 A2 A3 EN RS
Figure 3.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1994–2010 Analog Devices, Inc. All rights reserved.
ADG406/ADG407/ADG426
TABLE OF CONTENTS
Features .............................................................................................. 1
ADG426 Timing Diagrams..........................................................7
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions............................9
Typical Performance Characteristics ........................................... 12
Test Circuits..................................................................................... 15
Terminology.................................................................................... 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Dual Supply ................................................................................... 4
Single Supply ................................................................................. 6
REVISION HISTORY
5/10—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 20
6/09—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Removed T Grade...............................................................Universal
Added Table 4.................................................................................... 9
Added Table 6.................................................................................. 10
Added Table 8.................................................................................. 11
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
4/94—Revision 0: Initial Version
Rev. B | Page 2 of 20
ADG406/ADG407/ADG426
GENERAL DESCRIPTION
The ADG406, ADG407, and ADG426 are monolithic CMOS
analog multiplexers. The ADG406 and ADG426 switch one of
sixteen inputs to a common output as determined by the 4-bit
binary address lines: A0, A1, A2, and A3. The ADG426 has
on-chip address and control latches that facilitate microprocessor
interfacing. The ADG407 switches one of eight differential
inputs to a common differential output as determined by the
3-bit binary address lines A0, A1 and A2. An EN input on all
devices is used to enable or disable the device. When disabled,
all channels are switched off.
The ADG406/ADG407/ADG426 are designed on an enhanced
LC2MOS process that provides low power dissipation yet gives
high switching speed and low on resistance. These features make
the parts suitable for high speed data acquisition systems and
audio signal switching. Low power dissipation makes the parts
suitable for battery powered systems. Each channel conducts
equally well in both directions when on and has an input signal
range which extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. All channels exhibit break-
before-make switching action preventing momentary shorting
when switching channels. Inherent in the design is low charge
injection for minimum transients when switching the digital
inputs.
Rev. B | Page 3 of 20
ADG406/ADG407/ADG426
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter1
+25°C −40°C to +85°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
VSS to VDD
V
50
80
4
Ω typ
Ω max
Ω typ
VD = 10 V, IS = −1 mA
VDD = +13.5 V, VSS = −13.5 V
VD = 0 V, IS = −1 mA
125
20
RON Match
LEAKAGE CURRENTS
Source Off Leakage IS (Off)
Drain Off Leakage ID (Off)
ADG406, ADG426
ADG407
VDD = +16.5 V, VSS = −16.5 V
0.5
nA max VD = 10 V, VS = +10 V, see Figure 26
VD = 10 V, VS = +10 V; see Figure 27
1
1
20
20
nA max
nA max
Channel On Leakage ID, IS (On)
ADG406, ADG426
ADG407
VS = VD = 10 V; see Figure 28
1
1
20
20
nA max
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
1
μA max VIN = 0 or VDD
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
8
pF typ
f = 1 MHz
120
150
10
ns typ
ns max
ns min
RL = 300 Ω, CL = 35 pF; V1 = 10 V, V2 = +10 V; see Figure 29
RL = 300 Ω, CL = 35 pF; VS = +5 V, see Figure 30
RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31
RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31
250
10
Break Before Make Delay, tOPEN
tON (EN, WR)
120
160
110
150
175
225
130
180
ns typ
ns max
ns typ
ns max
tOFF (EN, RS)
ADG426 Only
tW, Write Pulse Width
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulse Width
Charge Injection
100
100
10
ns min
ns min
ns min
ns min
pC typ
100
VS = +5 V
VS = 0 V, RS = 0 Ω, CL = 1 nF;
See Figure 34
8
Off Isolation
−75
dB typ
RL = 1 k Ω, f = 100 kHz;
VEN = 0 V, see Figure 35
RL = 1 k Ω, f = 100 kHz, see Figure 36
f = 1 MHz
Channel-to-Channel Crosstalk
CS (Off)
85
5
dB typ
pF typ
CD (Off)
f = 1 MHz
ADG406, ADG426
ADG407
50
25
pF typ
pF typ
CD, CS (On)
f = 1 MHz
ADG406, ADG426
ADG407
60
40
pF typ
pF typ
Rev. B | Page 4 of 20
ADG406/ADG407/ADG426
Parameter1
+25°C −40°C to +85°C
Unit
Test Conditions/Comments
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
VIN = 0 V, VEN = 0 V
1
5
1
5
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
ISS
IDD
ISS
100
200
VIN = 0 V, VEN = 2.4 V
500
1
5
1 Temperature ranges is −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 5 of 20
ADG406/ADG407/ADG426
SINGLE SUPPLY
VDD = +12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter1
+25°C −40°C to +85°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
0 to VDD
200
V
90
125
Ω typ
Ω max
VD = +3 V, +8.5 V, IS = −1 mA;
VDD = +10.8 V
LEAKAGE CURRENTS
Source Off Leakage IS (Off)
Drain Off Leakage ID (Off)
ADG406, ADG426
ADG407
VDD = +13.2 V
nA max VD = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 26
0.5
20
VD = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 27
1
1
20
20
nA max
nA max
Channel On Leakage ID, IS (On)
ADG406, ADG426
ADG407
VS = VD = 8 V/0.1 V, see Figure 28
1
1
20
20
nA max
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
1
ꢀA max VIN = 0 or VDD
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
8
pF typ
f = 1 MHz
180
220
10
180
240
135
180
ns typ
ns max
ns typ
ns typ
ns max
ns typ
ns max
RL = 300 Ω, CL = 35 pF; V1 = 8 V/0 V, V2 = 0 V/8 V; see Figure 29
350
Break Before Make Delay, tOPEN
tON (EN, WR)
RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 30
RL = 300 Ω, CL = 35 pF;
350
220
VS = +5 V, see Figure 31
RL = 300 Ω, CL = 35 pF; VS = 5 V, see Figure 31
tOFF (EN, RS)
ADG426 Only
tW, Write Pulse Width
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulse Width
Charge Injection
Off Isolation
100
100
10
ns min
ns min
ns min
ns min
pC typ
dB typ
dB typ
pF typ
100
VS = +5 V
5
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 34
RL = 1 kΩ, f = 100 kHz; see Figure 35
RL = 1 kΩ, f = 100 kHz; see Figure 36
f = 1 MHz
−75
85
8
Channel-to-Channel Crosstalk
CS (Off)
CD (Off)
f = 1 MHz
ADG406, ADG426
ADG407
80
40
pF typ
pF typ
f = 1 MHz
CD, CS (On)
ADG406, ADG426
ADG407
100
50
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = +13.2 V
VIN = 0 V, VEN = 0 V
1
5
ꢀA typ
ꢀA max
ꢀA typ
ꢀA max
IDD
100
200
VIN = 0 V, VEN = 2.4 V
500
1 Temperature range is −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 6 of 20
ADG406/ADG407/ADG426
ADG426 TIMING DIAGRAMS
3V
0V
3V
WR
RS
50%
50%
50%
50%
0V
tW
tW
tS
tH
tOFF (RS)
3V
2V
V
0
A0, A1, A2, (A3)
0.8V
SWITCH
OUTPUT
0
0.8V
EN
0V
0V
Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs
Figure 5. Reset Pulse Width and Reset Turn Off Time
Figure 4 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
Figure 5 shows the reset pulse width, trs, and the reset turn off
RS
time, tOFF
(
).
WR
therefore, while
the switches respond to the address and enable inputs. This
WR
is held low, the latches are transparent and
Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V; tR = tF = 20 ns.
input data is latched on the rising edge of
.
Rev. B | Page 7 of 20
ADG406/ADG407/ADG426
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to VSS
44 V
VDD to GND
VSS to GND
Analog, Digital Inputs1
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 2 V to VDD + 2 V or 20 mA,
whichever occurs first
ESD CAUTION
Continuous Current, S or D
Peak Current, S or D
20 mA
40 mA
(Pulsed at 1 ms, 10% duty
cycle max)
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
Plastic Package
−40°C to +85°C
−65°C to +150°C
150°C
θJA, Thermal Impedance
Lead Temperature, Soldering
(10 sec)
75°C/W
260°C
PLCC Package
θJA, Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
80°C/W
215°C
220°C
SSOP Package
θJA, Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
122°C/W
215°C
220°C
1
WR
RS
should be limited to the maximum ratings given.
Overvoltages at A, S, D,
, or will be clamped by internal diodes. Current
Rev. B | Page 8 of 20
ADG406/ADG407/ADG426
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
28
D
1
2
3
4
DD
NC
NC
27
V
SS
4
3
2
1
28 27 26
26 S8
25 S7
24 S6
23 S5
22 S4
21 S3
20 S2
19 S1
18 EN
17 A0
16 A1
15 A2
S16
S15
S14
S13
S12
S11
S10
S9
PIN 1
INDENTFIER
5
6
25
24
23
22
21
20
S15
S14
S13
S12
S11
S10
S7
S6
S5
S4
S3
S2
5
6
ADG406
TOP VIEW
7
7
ADG406
TOP VIEW
(Not to scale)
(Not to Scale)
8
8
9
9
10
11
12
13
14
10
S9 11
19 S1
GND
NC
12 13 14 15 16 17 18
A3
NC = NO CONNECT
NC = NO CONNECT
Figure 6. 28-Lead PDIP
Figure 7. 28-Lead PLCC
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD
NC
S16 to S9
GND
Most Positive Power Supply Potential.
No Connect.
Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs.
Ground (0 V) Reference.
2, 3, 13
4 to 11
12
14 to 17 A3 to A0
18 EN
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin
is high, the Ax logic inputs determine which switch is turned on.
19 to 26 S1 to 8
Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
Drain Terminal. This pin can be an input or an output.
27
28
VSS
D
Table 5. Truth Table (ADG406)
A3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
On Switch
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Rev. B | Page 9 of 20
ADG406/ADG407/ADG426
V
1
2
28 DA
27
DD
DB
NC
V
SS
4
3
2
1
28 27 26
3
26 S8A
25 S7A
24 S6A
23 S5A
22 S4A
4
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
PIN 1
INDENTFIER
5
6
25
24
23
22
21
20
S7B
S6B
S5B
S4B
S3B
S2B
S7A
S6A
S5A
S4A
S3A
S2A
5
ADG407
6
TOP VIEW
7
7
ADG407
TOP VIEW
(Not to scale)
(Not to Scale)
8
21
S3A
8
20 S2A
19 S1A
18 EN
17 A0
16 A1
15 A2
9
9
10
11
12
13
14
10
S1B 11
19 S1A
12 13 14 15 16 17 18
NC
NC = NO CONNECT
NC = NO CONNECT
Figure 8. 28-Lead PDIP
Figure 9. 28-Lead PLCC
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
VDD
DB
Most Positive Power Supply Potential.
Drain Terminal B. This pin can be an input or an output.
No Connect.
3, 13, 14 NC
4 to 11
12
15 to 17 A2 to A0
18 EN
S8B to S1B
GND
Source Terminal 8B to Source Terminal 1B. These pins can be inputs or outputs.
Ground (0 V) Reference.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin
is high, the Ax logic inputs determine which switch is turned on.
19 to 26 S1A to S8A Source Terminal 1A to Source Terminal 8A. These pins can be inputs or outputs.
27
28
VSS
DA
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
Drain Terminal A. This pin can be an input or an output.
Table 7. Truth Table (ADG407)
A2
X
0
0
0
0
1
1
1
A1
X
0
0
1
1
0
0
1
A0
X
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
On Switch Pair
None
1
2
3
4
5
6
7
8
1
1
1
1
Rev. B | Page 10 of 20
ADG406/ADG407/ADG426
V
1
2
3
4
5
6
7
8
9
28
27
D
DD
NC
RS
V
SS
26 S8
25 S7
24 S6
23 S5
22 S4
21 S3
20 S2
19 S1
18 EN
17 A0
16 A1
15 A2
S16
S15
S14
S13
S12
S11
ADG426
TOP VIEW
(Not to Scale)
S10 10
S9 11
GND 12
WR 13
A3 14
NC = NO CONNECT
Figure 10. 28-Lead PDIP/SSOP
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
VDD
NC
RS
Most Positive Power Supply Potential.
No Connect.
Active Low Logic Input. When this pin is low, all switches are open, and address and enable latches registers are
cleared to 0.
4 to 11
12
S16 to S9
GND
Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs.
Ground (0 V) Reference.
13
WR
The rising edge of the WR signal latches the state of the address control lines and the enable line.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin
is high, the Ax logic inputs determine which switch is turned on.
14 to 17 A3 to A0
18 EN
19 to 26 S1 to S8
Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs.
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground.
Drain Terminal. This pin can be an input or an output.
27
28
VSS
D
Table 9. Truth Table (ADG426)
WR
RS
A3
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
X
X
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
On switch
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Retains previous switch condition
None (address and enable latches cleared)
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. B | Page 11 of 20
ADG406/ADG407/ADG426
TYPICAL PERFORMANCE CHARACTERISTICS
150
400
350
300
250
200
150
100
50
T
= 25°C
A
T
= 25°C
A
V
V
= +5V
= 0V
120
90
60
30
0
DD
SS
V
V
= +5V
= –5V
DD
SS
V
V
= +10V
= –10V
DD
SS
V
V
= +10V
= 0V
DD
SS
V
V
= +12V
= 0V
DD
SS
V
V
= +15V
= –15V
V
V
= +12V
= –12V
DD
SS
DD
SS
V
V
= +15V
= 0V
DD
SS
0
–15
–10
–5
0
5
10
15
0
2.5
5.0
7.5
V (V ) (V)
D
10
12.5
15
V
(V ) (V)
D
S
S
Figure 11. RON as a Function of VD (VS): Dual Supplies
Figure 14. RON as a Function of VD (VS): Single Supplies
100
80
60
40
20
0
150
120
90
60
30
0
V
V
= +15V
= –15V
V
V
= 12V
= 0V
DD
SS
DD
SS
125°C
125°C
85°C
25°C
85°C
25°C
–15
–10
–5
0
5
10
15
0
2
4
6
8
10
12
V
(V ) (V)
V (V ) (V)
D S
D
S
Figure 12. RON as a Function of VD (VS) for Different Temperatures
Figure 15. RON as a Function of VD (VS) for Different Temperatures
0.10
0.02
V
V
T
= +12V
= 0V
= +25°C
DD
SS
V
V
= +15V
= –15V
= +25°C
DD
SS
0.08
0.06
0.04
0.02
0
A
T
A
0.01
0
I
(ON)
D
I (OFF)
S
I
(OFF)
D
I
(OFF)
D
I
(ON)
D
–0.01
–0.02
I
(OFF)
5
S
–0.02
–15
–10
–5
0
10
15
0
2
4
6
8
10
12
V
(V ) (V)
V (V ) (V)
D S
D
S
Figure 13. Leakage Currents as a Function of VD (VS)
Figure 16. Leakage Currents as a Function of VD (VS)
Rev. B | Page 12 of 20
ADG406/ADG407/ADG426
100
10
1
100
10
V
V
= +15V
= –15V
DD
SS
V
V
= +15V
= –15V
DD
SS
1
EN = 2.4V
0.1
EN = 0V
EN = 2.4V
0.01
0.001
0.0001
EN = 0V
0.1
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 17. Positive Supply Current vs. Switching Frequency
Figure 20. Negative Supply Current vs. Switching Frequency
160
140
120
100
80
220
V
V
= +12V
= 0V
DD
SS
V
V
= +15V
= –15V
DD
SS
tON
200
180
160
140
120
100
80
tON
tTRANSITION
tTRANSITION
tOFF
tOFF
60
2
4
6
8
10
12
1
3
5
7
9
11
13
15
V
(V)
V
(V)
IN
IN
Figure 18. Switching Time vs. VIN (Bipolar Supply)
Figure 21. Switching Time vs. VIN (Single Supply)
300
200
100
0
500
400
300
200
100
0
V
= +5V
IN
V
= +5V
IN
tTRANSITION
tON
tON
tTRANSITION
tOFF
tOFF
±5
±7
±9
±11
±13
±15
±17
±19
±21
5
7
9
11
13
15
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 22. Switching Time vs. Single Supply
Figure 19. Switching Time vs. Bipolar Supply
Rev. B | Page 13 of 20
ADG406/ADG407/ADG426
140
120
100
80
140
120
100
80
V
V
= +15V
= –15V
V
V
= +15V
= –15V
DD
SS
DD
SS
60
60
40
100
40
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Off Isolation vs. Frequency
Figure 24. Crosstalk vs. Frequency
Rev. B | Page 14 of 20
ADG406/ADG407/ADG426
TEST CIRCUITS
I
DS
V
V
SS
DD
DD
V1
V
V
SS
S1
S2
I
(OFF)
A
D
D
S
D
S16
V
D
V
S
EN
+0.8V
V
S
R
= V1/I
ON
DS
Figure 27. ID (Off)
Figure 25. On Resistance
V
V
V
V
SS
V
DD
SS
DD
V
V
V
DD
SS
I
(OFF)
A
DD
SS
S
S1
S2
I
(ON)
A
D
D
S1
D
S16
S16
V
V
D
S
EN
+2.4V
EN
+0.8V
V
V
D
S
Figure 28. ID (On)
Figure 26. IS (Off)
V
V
V
SS
DD
3V
V
DD
SS
ADDRESS
S1
A3
V
DRIVE (V
)
50%
50%
1
IN
V
A2
A1
A0
IN
50Ω
S2 THRU S15
S16
V
2
ADG4261
90%
EN
RS
2.4V
D
V
OUT
V
OUT
R
300Ω
C
35pF
L
L
GND
WR
90%
tTRANSITION
tTRANSITION
1
SIMILAR CONNECTION FOR ADG406/ADG407
Figure 29. Switching Time of Multiplexer, tTRANSITION
V
V
V
DD
SS
3V
V
DD
SS
ADDRESS
S1
A3
V
S
DRIVE (V
)
IN
V
IN
A2
A1
A0
50Ω
S2 THRU S15
S16
ADG4261
RS
EN
V
D
OUT
80%
OUTPUT
0V
R
300Ω
80%
C
35pF
L
L
2.4V
GND
WR
tOPEN
1
SIMILAR CONNECTION FOR ADG406/ADG407
Figure 30. Break-Before-Make Delay, tOPEN
Rev. B | Page 15 of 20
ADG406/ADG407/ADG426
V
V
DD
SS
3V
V
V
DD
SS
ENABLE
S1
A3
V
S
50%
50%
DRIVE (V
)
IN
A2
A1
A0
S2 THRU S16
0V
tOFF (EN)
90%
ADG4261
V
O
90%
2.4V
RS
EN
V
D
OUT
OUTPUT
0V
R
300Ω
C
35pF
L
L
GND
WR
V
IN
50Ω
tON (EN)
1
SIMILAR CONNECTION FOR ADG406/ADG407
Figure 31. Enable Delay, tON (EN), tOFF (EN)
V
V
V
DD
SS
V
DD
SS
3V
S1
A3
V
S
WR
50%
A2
A1
A0
S2 THRU S16
0V
ADG426
V
0
tON(WR)
EN
2.4V
V
D
OUT
OUTPUT
0V
R
300Ω
C
35pF
L
L
0.2V
RS
0
WR
V
RS
GND
V
WR
Figure 32. Write Turn-On Time, tON (WR)
V
V
V
DD
SS
V
DD
SS
3V
S1
A3
V
S
50%
RS
0V
A2
A1
A0
S2 THRU S16
ADG426
tOFF(RS)
EN
RS
2.4V
V
V
D
OUT
0
R
300Ω
C
35pF
L
L
0.8V
0
OUTPUT
0V
WR
GND
V
IN
Figure 33. Reset Turn-Off Time, tOFF (RS)
Rev. B | Page 16 of 20
ADG406/ADG407/ADG426
V
V
V
DD
SS
V
DD
SS
A3
2.4V
3V
RS
A2
A1
LOGIC
INPUT
(V
)
ADG4261
IN
A0
S
R
S
D
V
OUT
C
V
L
S
EN
ΔV
1nF
OUT
V
OUT
Q
= C × ΔV
INJ
L
OUT
V
IN
WR
GND
1
SIMILAR CONNECTION FOR ADG406/ADG407.
Figure 34. Charge Injection
V
V
DD
S16
DD
V
V
DD
V
D
S2
S1
OUT
V
IN
1kΩ
1kΩ
DD
S1
A3
A2
A1
A0
A0
A1
A2
A3
EN
ADG4261
S16
V
IN
ADG4261
2.4V
RS
EN
2.4V
V
D
OUT
R
1kΩ
L
RS
V
V
GND WR
SS
GND WR
SS
SS
V
V
SS
1
1
SIMILAR CONNECTION FOR ADG406/ADG407.
SIMILAR CONNECTION FOR ADG406/ADG407.
Figure 35. Off Isolation
Figure 36. Crosstalk
Rev. B | Page 17 of 20
ADG406/ADG407/ADG426
TERMINOLOGY
t
OFF (EN)
VDD
Delay time between the 50% and 90% points of the digital input
and switch off condition.
Most positive power supply potential.
VSS
tTRANSITION
Most negative power supply potential in dual supplies. In single
supply applications, it may be connected to ground.
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from
one address state to another.
GND
Ground (0 V) reference.
tOPEN
RON
Off time measured between 80% points of both switches when
switching from one address state to another.
Ohmic resistance between the D and S terminals.
RON Match
VINL
Difference between the RON of any two channels.
Maximum input voltage for Logic 0.
IS (Off)
VINH
Source leakage current when the switch is off.
Minimum input voltage for Logic 1.
ID (Off)
IINL (IINH)
Drain leakage current when the switch is off.
Input current of the digital input.
ID, IS (On)
Crosstalk
Channel leakage current when the switch is on.
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
VD (VS)
Analog voltage on Terminal D, Terminal S.
Off Isolation
A measure of unwanted signal coupling through an off channel.
CS (Off)
Channel input capacitance for off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD (Off)
Channel output capacitance for off condition.
IDD
CD, CS (ON)
Positive supply current.
On switch capacitance.
ISS
CIN
Negative supply current.
Digital input capacitance.
t
ON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
Rev. B | Page 18 of 20
ADG406/ADG407/ADG426
OUTLINE DIMENSIONS
1.565 (39.75)
1.380 (35.05)
28
1
15
14
0.580 (14.73)
0.485 (12.31)
0.625 (15.88)
0.600 (15.24)
0.100 (2.54)
BSC
0.195 (4.95)
0.125 (3.17)
0.250 (6.35)
MAX
0.015 (0.38)
GAUGE
PLANE
0.015
(0.38)
MIN
0.200 (5.08)
0.115 (2.92)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.700 (17.78)
MAX
0.022 (0.56)
0.014 (0.36)
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
COMPLIANT TO JEDEC STANDARDS MS-011
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.
Figure 37. 28-Lead Plastic Dual In-Line Package {PDIP}
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.020 (0.51)
MIN
0.042 (1.07)
4
5
26
25
0.048 (1.22)
0.042 (1.07)
0.021 (0.53)
0.013 (0.33)
PIN 1
IDENTIFIER
BOTTOM
VIEW
(PINS UP)
0.050
(1.27)
BSC
0.430 (10.92)
0.390 (9.91)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
11
12
19
18
0.045 (1.14)
0.025 (0.64)
R
0.456 (11.582)
0.450 (11.430)
SQ
0.120 (3.04)
0.090 (2.29)
0.495 (12.57)
SQ
0.485 (12.32)
COMPLIANT TO JEDEC STANDARDS MO-047-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28)
Dimensions shown in inches and (millimeters)
Rev. B | Page 19 of 20
ADG406/ADG407/ADG426
10.50
10.20
9.90
15
28
5.60
5.30
5.00
8.20
7.80
7.40
1
14
0.25
0.09
1.85
1.75
1.65
2.00 MAX
0.05 MIN
8°
4°
0°
0.95
0.75
0.55
0.38
0.22
SEATING
PLANE
COPLANARITY
0.10
0.65 BSC
COMPLIANT TO JEDEC STANDARDS MO-150-AH
Figure 39. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead PDIP
28-Lead PDIP
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PDIP
28-Lead PDIP
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
Package Option2
ADG406BN
ADG406BNZ
ADG406BP
ADG406BP-REEL
ADG406BPZ
ADG406BPZ-REEL
ADG407BN
ADG407BNZ
ADG407BP
ADG407BP-REEL
ADG407BPZ
ADG407BPZ-RL
ADG407BCHIPS
ADG426BN
ADG426BNZ
ADG426BRS
N-28-2
N-28-2
P-28
P-28
P-28
P-28
N-28-2
N-28-2
P-28
P-28
P-28
P-28
DIE
28-Lead PDIP
28-Lead PDIP
28-Lead SSOP
28-Lead SSOP
28-Lead SSOP
28-Lead SSOP
28-Lead SSOP
N-28-2
N-28-2
RS-28
RS-28
RS-28
RS-28
RS-28
ADG426BRS-REEL
ADG426BRS-REEL7
ADG426BRSZ
ADG426BRSZ-REEL
1 Z = RoHS Compliant Part.
2 N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small Outline Package (SSOP).
©1994–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00026-0-5/10(B)
Rev. B | Page 20 of 20
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