ADG426 [ADI]
LC2MOS 8-/16-Channel High Performance Analog Multiplexers; LC2MOS 8位/ 16通道高性能模拟多路复用器
| 型号： | ADG426 |
| 厂家： | 
ADI |
| 描述： | LC2MOS 8-/16-Channel High Performance Analog Multiplexers |
| 文件： | 总12页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS 8-/16-Channel
a
High Performance Analog Multiplexers
ADG406/ADG407/ADG426
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
44 V Supply Maximum Ratings
VSS to VDD Analog Signal Range
Low On Resistance (80 Ω max)
Low Power
Fast Switching
tON < 160 ns
ADG406
ADG407
S1
S1A
S8A
DA
DB
D
S1B
S8B
tOFF < 150 ns
S16
Break Before Make Switching Action
Plug-In Upgrade for
1 OF 16
DECODER
1 OF 8
DECODER
DG506A/ADG506A, DG507A/ADG507A,
DG526/ADG526A
A0 A1 A2 A3 EN
A0 A1 A2 EN
ADG406/ADG407 are Plug-In Replacements for
DG406/DG407
ADG426
S1
APPLICATIONS
Audio and Video Routing
Automatic Test Equipment
Data Acquisition Systems
Battery Powered Systems
Sample Hold Systems
Communication Systems
Avionics
D
S16
WR
DECODER/
LATCHES
A0 A1 A2 A3 EN RS
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. Extended Signal Range
The ADG406, ADG407 and ADG426 are monolithic CMOS
analog multiplexers. The ADG406 and ADG426 switch one of
sixteen inputs to a common output as determined by the 4-bit
binary address lines A0, A1, A2 and A3. The ADG426 has on-
chip address and control latches that facilitate microprocessor
interfacing. The ADG407 switches one of eight differential
inputs to a common differential output as determined by the 3-
bit binary address lines A0, A1 and A2. An EN input on all
devices is used to enable or disable the device. When disabled,
all channels are switched OFF.
The ADG406/ADG407/ADG426 are fabricated on an
enhanced LC2MOS process giving an increased signal range
which extends to the supply rails
2. Low Power Dissipation
3. Low RON
4. Single/Dual Supply Operation
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG406/ADG407/ADG426 can be operated from a single
rail power supply. The parts are fully specified with a single
+12 V power supply and will remain functional with single
supplies as low as +5 V.
The ADG406/ADG407/ADG426 are designed on an enhanced
LC2MOS process that provides low power dissipation yet gives
high switching speed and low on resistance. These features
make the parts suitable for high speed data acquisition systems
and audio signal switching. Low power dissipation makes the
parts suitable for battery powered systems. Each channel
conducts equally well in both directions when ON and has an
input signal range which extends to the supplies. In the OFF
condition, signal levels up to the supplies are blocked. All
channels exhibit break before make switching action preventing
momentary shorting when switching channels. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
ADG406/ADG407/ADG426–SPECIFICATIONS1
(VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted)
DUAL SUPPLY
B Version
–40°C to
+85°C
T Version
–55°C to
Parameter
+25°C
+25°C
+125°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
V
SS to VDD
VSS to VDD
125
V
50
80
4
50
80
4
Ω
Ω
Ω
typ
max
typ
VD = ±10 V, IS = –1 mA
125
V
DD = +13.5 V, VSS = –13.5 V
RON Match
VD = 0 V, IS = –1 mA
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG406, ADG426
VDD = +16.5 V, VSS = –16.5 V
±0.5
±20
±0.5
±50
nA max
VD = ±10 V, VS = ϯ10 V, Test Circuit 2
VD = ±10 V, VS = ϯ10 V;
Test Circuit 3
±1
±1
±20
±20
±1
±1
±200
±100
nA max
nA max
ADG407
Channel ON Leakage ID, IS (ON)
ADG406, ADG426
ADG407
VS = VD = ±10 V;
Test Circuit 4
±1
±1
±20
±20
±1
±1
±200
±100
nA max
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
CIN, Digital Input Capacitance
±1
±1
µA max
pF typ
VIN = 0 or VDD
f = 1 MHz
8
8
DYNAMIC CHARACTERISTICS2
tTRANSITION
120
150
120
150
ns typ
ns max
RL = 300 Ω, CL = 35 pF;
V1 = ±10 V, V2 = ϯ10 V;
Test Circuit 5
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 7
250
10
250
10
Break Before Make Delay, tOPEN
tON (EN, WR)
10
10
ns min
120
160
110
150
175
225
130
180
120
160
110
150
175
225
130
180
ns typ
ns max
ns typ
ns max
tOFF (EN, RS)
ADG426 Only
tW, Write Pulse Width
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulse Width
Charge Injection
100
100
10
100
100
10
ns min
ns min
ns min
ns min
pC typ
100
100
VS = +5 V
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 10
8
8
OFF Isolation
–75
–75
dB typ
RL = 1 kΩ, f = 100 kHz;
VEN = 0 V, Test Circuit 11
RL = 1 kΩ, f = 100 kHz, Test Circuit 12
f = 1 MHz
Channel-to-Channel Crosstalk
CS (OFF)
85
5
85
5
dB typ
pF typ
CD (OFF)
f = 1 MHz
ADG406, ADG426
ADG407
50
25
50
25
pF typ
pF typ
CD, CS (ON)
f = 1 MHz
ADG406, ADG426
ADG407
60
40
60
40
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = –16.5 V
VIN = 0 V, VEN = 0 V
1
5
1
5
1
5
1
5
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
ISS
IDD
ISS
100
200
100
200
VIN = 0 V, VEN = 2.4 V
500
1
5
500
1
5
N
OTES
1 Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–2–
ADG406/ADG407/ADG426
(VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
SINGLE SUPPLY
B Version
–40°C to
T Version
–55°C to
Parameter
+25°C
+85°C
+25°C
+125°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
0 to VDD
200
0 to VDD
200
V
90
125
90
125
Ω typ
Ω max
VD = +3 V, +8.5 V, IS = –1 mA;
VDD = +10.8 V
LEAKAGE CURRENTS
VDD = +13.2 V
Source OFF Leakage IS (OFF)
±0.5
±20
±0.5
±50
nA max
VD = 8 V/0.1 V, VS = 0.1 V/8 V;
Test Circuit 2
Drain OFF Leakage ID (OFF)
ADG406, ADG426
ADG407
VD = 8 V/0.1 V, VS = 0.1 V/8 V;
Test Circuit 3
±1
±1
±20
±20
±1
±1
±200
±100
nA max
nA max
Channel ON Leakage ID, IS (ON)
ADG406, ADG426
ADG407
VS = VD = 8 V/0.1 V, Test Circuit 4
±1
±1
±20
±20
±1
±1
±200
±100
nA max
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
2.4
0.8
V min
V max
IINL or IINH
CIN, Digital Input Capacitance
±1
±1
µA max
pF typ
VIN = 0 or VDD
f = 1 MHz
8
8
DYNAMIC CHARACTERISTICS2
tTRANSITION
180
220
180
220
ns typ
ns max
RL = 300 Ω, CL = 35 pF;
V1 = 8 V/0 V, V2 = 0 V/8 V;
Test Circuit 5
350
350
Break Before Make Delay, tOPEN
tON (EN, WR)
10
10
ns typ
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = +5 V, Test Circuit 7
180
240
135
180
180
240
135
180
ns typ
ns max
ns typ
ns max
350
220
350
220
tOFF (EN, RS)
ADG426 Only
tW, Write Pulse Width
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulse Width
Charge Injection
100
100
10
100
100
10
ns min
ns min
ns min
ns min
pC typ
100
100
VS = +5 V
VS = 6 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 10
5
5
OFF Isolation
–75
85
8
–75
85
8
dB typ
dB typ
pF typ
RL = 1 kΩ, f = 100 kHz;
Test Circuit 11
RL = 1 kΩ, f = 100 kHz;
Test Circuit 12
Channel-to-Channel Crosstalk
CS (OFF)
f = 1 MHz
CD (OFF)
f = 1 MHz
ADG406, ADG426
ADG407
80
40
80
40
pF typ
pF typ
CD, CS (ON)
ADG406, ADG426
ADG407
f = 1 MHz
100
50
100
50
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = +13.2 V
VIN = 0 V, VEN = 0 V
1
5
1
5
µA typ
µA max
µA typ
µA max
IDD
100
200
100
200
VIN = 0 V, VEN = 2.4 V
500
500
NOTES
1Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
ADG406/ADG407/ADG426
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
ORDERING GUIDE
Temperature Range
Model
Package Option*
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
V
V
DD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
SS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
ADG406BN
ADG406BP
–40°C to +85°C
–40°C to +85°C
N-28
P-28A
Analog, Digital Inputs2. . . . . . . . . . . . . VSS – 2 V to VDD + 2 V
or 20 mA, Whichever Occurs First
ADG407BN
ADG407BP
ADG426BN
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-28
P-28A
N-28
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
ADG426BRS –40°C to +85°C
RS-28
Operating Temperature Range
*N = Plastic DIP, P = Plastic Leaded Chip Carrier (PLCC), RS = Shrink Small
Outline Package (SSOP).
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
PLCC Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 80°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
SSOP Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Only
one absolute maximum rating may be applied at any one time.
2Overvoltages at A, S, D, WR or RS will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–4–
ADG406/ADG407/ADG426
Table I. Truth Table (ADG406)
PIN CONFIGURATIONS
DIP
PLCC
A3 A2 A1 A0 EN ON SWITCH
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
V
1
2
3
4
5
6
7
8
9
28
27
D
DD
NC
NC
V
SS
4
3
2
1
28 27 26
26 S8
25 S7
24 S6
23 S5
22 S4
21 S3
20 S2
19 S1
18 EN
17 A0
16 A1
15 A2
S16
S15
S14
S13
S12
S11
S15
S14
S13
S12
S11
5
6
7
8
9
25 S7
24 S6
23 S5
22 S4
21 S3
20 S2
19 S1
ADG406
TOP VIEW
(Not to Scale)
ADG406
TOP VIEW
(Not to Scale)
8
9
S10 10
S9 11
10
11
12
13
14
15
16
S10 10
S9 11
12 13 14 15 16 17 18
GND 12
NC 13
A3 14
NC = NO CONNECT
Table II. Truth Table (ADG407)
A2 A1 A0 EN ON SWITCH PAIR
VDD
DB
1
2
3
4
5
6
7
8
9
28 DA
27
26 S8A
25
VSS
4
3
2
1
28 27 26
NC
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
25
24
23
22
21
S7B
S6B
S5B
S4B
S3B
5
6
7
8
9
S7A
S6A
S5A
S4A
S3A
S2A
S1A
S8B
S7B
S6B
S5B
S7A
1
2
3
4
5
6
7
8
24 S6A
23 S5A
22 S4A
21 S3A
20 S2A
19 S1A
18 EN
17 A0
ADG407
TOP VIEW
(Not to Scale)
ADG407
TOP VIEW
(Not to Scale)
S4B
S3B
20
19
S2B 10
S1B 11
S2B 10
S1B 11
GND 12
NC 13
12 13 14 15 16 17 18
Table III. Truth Table (ADG426)
A3 A2 A1 A0 EN WR RS ON SWITCH
16 A1
NC = NO CONNECT
NC 14
15 A2
X
X
X
X
X
X
X
X
X
X
1
0
Retains Previous
Switch Condition
NONE (Address
and Enable
X
PIN CONFIGURATION
DIP/SSOP
Latches Cleared)
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
VDD
NC
1
2
28
27
D
VSS
RS
3
26 S8
25
24 S6
23
22 S4
21
4
S16
S15
S14
S13
S12
S11
S10
S7
5
6
S5
ADG426
TOP VIEW
(Not to Scale)
7
8
9
8
S3
20 S2
19
18 EN
17
9
10
11
12
13
14
15
16
10
S1
S9 11
12
GND
WR 13
14
A0
16 A1
15 A2
A3
NC = NO CONNECT
REV. 0
–5–
ADG406/ADG407/ADG426
TIMING DIAGRAMS (ADG426)
TERMINOLOGY
VDD
VSS
Most positive power supply potential.
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
3V
WR
50%
50%
0V
tW
GND
RON
Ground (0 V) reference.
tS
tH
3V
Ohmic resistance between D and S.
Difference between the RON of any two
channels.
2V
A0, A1, A2, (A3)
R
ON Match
0.8V
EN
0V
IS (OFF)
ID (OFF)
ID, IS (ON)
Source leakage current when the switch is off.
Drain leakage current when the switch is off.
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and
the switches respond to the address and enable inputs. This
input data is latched on the rising edge of WR.
Channel leakage current when the switch
is on.
Analog voltage on terminals D, S.
Channel input capacitance for “OFF”
condition.
VD (VS)
CS (OFF)
CD (OFF)
Channel output capacitance for “OFF”
condition.
“ON” switch capacitance.
Digital input capacitance.
3V
RS
50%
50%
CD, CS (ON)
CIN
0V
tRS
tON (EN)
Delay time between the 50% and 90%
points of the digital input and switch “ON”
condition.
tOFF (RS)
V0
0V
0.8V0
SWITCH
OUTPUT
t
OFF (EN)
Delay time between the 50% and 90%
points of the digital input and switch “OFF”
condition.
Delay time between the 50% and 90%
points of the digital inputs and the switch
“ON” condition when switching from one
address state to another.
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
Figure 2.
tTRANSITION
Figure 2 shows the Reset Pulse Width, tRS, and the Reset Turn
Off Time, tOFF (RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tR = tF = 20 ns.
tOPEN
VINL
VINH
Maximum input voltage for logic “0.”
Minimum input voltage for logic “1.”
Input current of the digital input.
IINL (IINH
)
Crosstalk
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” channel.
Charge
Injection
A measure of the glitch impulse
transferred from the digital input to the analog
output during switching.
IDD
ISS
Positive supply current.
Negative supply current.
REV. 0
–6–
ADG406/ADG407/ADG426
Typical Performance Graphs
150
400
350
300
250
200
150
100
50
T
= +25°C
T
= +25°C
A
A
V
V
= +5V
= 0V
DD
SS
120
V
= +5V
DD
V
= –5V
SS
V
V
= +10V
= –10V
90
60
30
0
DD
SS
V
V
= +10V
= 0V
DD
SS
V
V
= +12V
DD
= 0V
SS
V
= +12V
= –12V
DD
V
= +15V
= –15V
DD
V
SS
V
SS
V
V
= +15V
= 0V
DD
SS
0
–15
–10
–5
0
5
10
15
0
2.5
5
7.5
10
12.5
15
V
(V ) – Volts
S
V
(V ) – Volts
S
D
D
Figure 6. RON as a Function of VD (VS): Single Supplies
Figure 3. RON as a Function of VD (VS): Dual Supplies
100
150
VDD = +15V
VSS = –15V
VDD = +12V
VSS = 0V
80
120
+125°C
+125°C
60
90
+85°C
+25°C
+85°C
40
60
+25°C
20
30
0
0
–15
–10
–5
0
5
10
15
0
2
4
6
8
10
12
VD (VS) – Volts
VD (VS) – Volts
Figure 7. RON as a Function of VD (VS) for Different
Temperatures
Figure 4. RON as a Function of VD (VS) for Different
Temperatures
0.10
0.02
V
= +15V
= –15V
VDD = +12V
DD
V
T
V
SS = 0V
SS
0.08
0.06
0.04
0.02
0.00
–0.02
= +25°C
T
A = +25°C
A
0.01
0.00
I
(ON)
D
IS(OFF)
I
(OFF)
D
ID(OFF)
ID(ON)
–0.01
–0.02
I
(OFF)
5
S
–15
–10
–5
0
10
15
0
2
4
6
8
10
12
VD (VS) – Volts
V
(V ) – Volts
S
D
Figure 8. Leakage Currents as a Function of VD (VS)
Figure 5. Leakage Currents as a Function of VD (VS)
REV. 0
–7–
ADG406/ADG407/ADG426
100
100
V
V
= +15V
= –15V
DD
SS
VDD = +15V
SS = –15V
V
10
1
10
EN = 2.4V
0.1
EN = 0V
EN = 2.4V
EN = 0V
1
0.01
0.001
0.0001
0.1
10
2
3
4
5
6
7
102
103
104
FREQUENCY – Hz
105
106
107
10
10
10
10
10
FREQUENCY – Hz
Figure 9. Positive Supply Current vs. Switching
Frequency
Figure 12. Negative Supply Current vs. Switching
Frequency
160
220
V
V
= +15V
= –15V
DD
SS
VDD = +12V
VSS = 0V
tON
200
140
120
100
80
tON
tTRANSITION
180
tTRANSITION
160
140
120
tOFF
tOFF
100
60
80
1
3
5
7
9
11
13
15
2
4
6
8
10
12
V
– V
IN
VIN – V
Figure 10. Switching Time vs. VIN (Bipolar Supply)
Figure 13. Switching Time vs. VIN (Single Supply)
300
500
V
= +5V
V
= +5V
IN
IN
400
300
200
100
0
tTRANSITION
tON
200
100
0
tON
tTRANSITION
tOFF
tOFF
5
7
9
11
13
15
±5
±7
±9
±11
±13
±15
±17
±19
±21
SUPPLY VOLTAGE – Volts
SUPPLY VOLTAGE – Volts
Figure 11. Switching Time vs. Bipolar Supply
Figure 14. Switching Time vs. Single Supply
REV. 0
–8–
ADG406/ADG407/ADG426
140
120
100
80
140
120
100
80
V
V
= +15V
= –15V
DD
V
V
= +15V
= –15V
DD
SS
SS
60
60
40
40
2
4
5
3
6
7
2
4
5
3
6
7
10
10
10
10
10
10
10
10
10
10
10
10
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16. Crosstalk vs. Frequency
Figure 15. OFF Isolation vs. Frequency
Test Circuits
I
DS
VDD
VSS
V1
VDD
VSS
S1
S2
ID (OFF)
A
D
S
D
VD
S16
V
S
+0.8V
EN
VS
R
= V1/I
ON
DS
Test Circuit 3. ID (OFF)
Test Circuit 1. On Resistance
VDD
VSS
V
V
V
V
DD
DD
SS
I
(OFF)
A
S
SS
VDD
VSS
S1
S2
ID (ON)
A
D
D
S1
VD
S16
S16
V
S
+0.8V
EN
EN
2.4V
V
D
VS
Test Circuit 4. ID (ON)
Test Circuit 2. IS (OFF)
REV. 0
–9–
ADG406/ADG407/ADG426
VDD
VSS
3V
VDD
A3
VSS
S1
V1
V2
ADDRESS
DRIVE – VIN
50%
50%
VIN
S2 THRU S15
S16
A2
A1
A0
EN
RS
50Ω
ADG426*
D
VOUT
2.4V
90%
RL
300Ω
VOUT
CL
35pF
GND
WR
90%
tTRANSITION
tTRANSITION
*SIMILAR CONNECTION FOR ADG406/ADG407
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
VDD
VSS
VDD
A3
VSS
S1
3V
VS
ADDRESS
VIN
DRIVE – VIN
A2
A1
S2 THRU S15
50Ω
ADG426*
A0
RS
S16
D
VOUT
EN
2.4V
OUTPUT
0V
80%
80%
RL
300Ω
CL
35pF
GND
WR
tOPEN
*SIMILAR CONNECTION FOR ADG406/ADG407
Test Circuit 6. Break-Before-Make Delay, tOPEN
V
V
SS
DD
V
V
SS
DD
3V
0V
A3
S1
V
S
ENABLE
A2
A1
A0
RS
EN
50%
50%
S2 THRU S16
DRIVE–V
IN
ADG426*
tOFF (EN)
90%
V
2.4V
O
90%
D
V
OUT
OUTPUT
GND
C
35pF
V
WR
R
300Ω
L
IN
L
0V
50Ω
tON (EN)
*SIMILAR CONNECTION FOR ADG406/ADG407
Test Circuit 7. Enable Delay, tON (EN), tOFF (EN)
REV. 0
–10–
ADG406/ADG407/ADG426
VDD
VSS
VDD
VSS
S1
A3
A2
3V
VS
S2 THRU S16
WR
50%
A1
A0
ADG426
0V
V0
VOUT
D
EN
RS
WR
2.4V
t
ON(WR)
RL
300Ω
CL
35pF
OUTPUT
0V
0.2V0
VRS
GND
VWR
Test Circuit 8. Write Turn-On Time, tON (WR)
V
V
V
DD
DD
SS
V
3V
SS
A3
V
S1
S
50%
RS
0V
A2
A1
A0
S2 THRU S16
ADG426
tOFF (RS)
V
0
2.4V
EN
RS
0.8V
0
D
V
OUT
OUTPUT
0V
R
300Ω
L
C
L
GND
V
WR
IN
35pF
Test Circuit 9. Reset Turn-Off Time, tOFF (RS)
V
V
V
DD
SS
SS
V
DD
A3
2.4V
RS
3V
A2
A1
ADG426*
LOGIC
INPUT
A0
S
D
(V
)
IN
V
OUT
R
S
C
L
V
S
EN
∆ V
OUT
1nF
V
OUT
Q
= C x ∆V
L OUT
V
INJ
IN
GND
WR
*SIMILAR CONNECTION FOR ADG406/ADG407
Test Circuit 10. Charge Injection
REV. 0
–11–
ADG406/ADG407/ADG426
V
DD
V
DD
V
DD
S16
S2
V
DD
D
V
OUT
A3
A2
A1
A0
S1
V
IN
S1
1kΩ
1kΩ
S16
V
IN
ADG426*
A0
A1
A2
A3
EN
ADG426*
RS
2.4V
V
D
OUT
EN
R
1kΩ
2.4V
L
V
V
WR
SS
GND
RS
V
WR
GND
SS
SS
*SIMILAR CONNECTION FOR ADG406/407
V
SS
*SIMILAR CONNECTION FOR ADG406/407
Test Circuit 11. OFF Isolation
Test Circuit 12. Crosstalk
OUTLINE DIMENSIONS
Dimensions shown in inches an (mm).
28-Pin Plastic (N-28)
28-Pin PLCC (P-28A)
0.180 (4.57)
0.165 (4.19)
0.056 (1.42)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
15
28
1
0.048 (1.21)
0.042 (1.07)
4
26
25
PIN 1
IDENTIFIER
5
0.580 (14.73)
0.485 (12.32)
0.021 (0.53)
0.013 (0.33)
PIN 1
0.050
(1.27)
BSC
14
0.430 (10.92)
0.390 (9.91)
TOP VIEW
0.625 (15.87)
0.600 (15.24)
1.565 (39.70)
1.380 (35.10)
0.060 (1.52)
0.015 (0.38)
0.032 (0.81)
0.250
(6.35)
MAX
0.195 (4.95)
0.125 (3.18)
0.026 (0.66)
19
18
11
0.150
(3.81)
MIN
12
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.020
0.040 (1.01)
0.025 (0.64)
0.008 (0.204)
(0.50)
R
0.456 (11.58)
SQ
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
MAX
0.450 (11.43)
SEATING
PLANE
0.110 (2.79)
0.085 (2.16)
0.495 (12.57)
0.485 (12.32)
SQ
28-Pin SSOP (RS-28)
28
15
0.212 (5.38)
0.205 (5.207)
0.311 (7.9)
0.301 (7.64)
PIN 1
1
14
0.07 (1.78)
0.407 (10.34)
0.397 (10.08)
0.066 (1.67)
0.03 (0.762)
8
0
°
°
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
0.0256 (0.65)
BSC
0.009 (0.229)
0.005 (0.127)
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
REV. 0
–12–
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