ADG429_技术文档

LC²MOS Latchable 4-/8-Channel

a

High Performance Analog Multiplexers

ADG428/ADG429

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

44 V Supply Maximum Ratings

V_SSto V_DDAnalog Signal Range

Low On Resistance (60 ⍀ typ)

Low Power Consumption (1.6 mW max)

Low Charge Injection (<4 pC typ)

Fast Switching

ADG428

ADG429

S1

S1A

DA

DB

S4A

S1B

Break-Before-Make Switching Action

Plug-In Replacement for DG428/DG429

D

APPLICATIONS

S8

S4B

Automatic Test Equipment

Data Acquisition Systems

Communication Systems

Avionics and Military Systems

Microprocessor Controlled Analog Systems

Medical Instrumentation

DECODERS/DRIVERS

LATCHES

DECODERS/DRIVERS

LATCHES

WR

RS

A2

A1

A0

EN

A1

A0

EN

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The ADG428 and ADG429 are monolithic CMOS analog

multiplexers comprising eight single channels and four differen-

tial channels respectively. On-chip address and control latches

facilitate microprocessor interfacing. The ADG428 switches one

of eight inputs to a common output as determined by the 3-bit

binary address lines A0, A1 and A2. The ADG429 switches one

of four differential inputs to a common differential output as

determined by the 2-bit binary address lines A0 and A1. An EN

input on both devices is used to enable or disable the device.

When disabled, all channels are switched OFF. All the control

inputs, address and enable inputs are TTL compatible over the

full specified operating temperature range. This makes the part

suitable for bus-controlled systems such as data acquisition sys-

tems, process controls, avionics and ATEs because the TTL-

compatible address latches simplify the digital interface design

and reduce the board space required.

1. Extended Signal Range

The ADG428/ADG429 are fabricated on an enhanced

LC²MOS process, giving an increased signal range that ex-

tends to the supply rails.

2. Low Power Dissipation

3. Low R_ON

4. Single/Dual Supply Operation

5. Single Supply Operation

For applications where the analog signal is unipolar, the

ADG428/ADG429 can be operated from a single rail power

supply. The parts are fully specified with a single +12 V

power supply and will remain functional with single supplies

as low as +5 V.

The ADG428/ADG429 are designed on an enhanced LC²MOS

process that provides low power dissipation yet gives high switching

speed and low on resistance. Each channel conducts equally well

in both directions when ON and has an input signal range that

extends to the supplies. In the OFF condition, signal levels up to

the supplies are blocked. All channels exhibit break-before-make

switching action, preventing momentary shorting when switching

channels. Inherent in the design is low charge injection for mini-

mum transients when switching the digital inputs.

The ADG428/ADG429 are improved replacements for the

DG428/DG429 Analog Multiplexers.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADG428/ADG429–SPECIFICATIONS

DUAL SUPPLY¹

(V_DD= +15 V, V_SS= –15 V, GND = 0 V, WR = 0 V, RS = 2.4 V unless otherwise noted)

B Version T Version

–40؇C to –55؇C to

+25؇C +85؇C +25؇C +125؇C

Parameter

Units

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

R_ON

V_SSto V_DD

125

V_SSto V_DD

125

V

60

100

10

60

100

10

Ω typ

Ω max

% max

V_D= ±10 V, I_S= –1 mA

∆R_ON

–10 V < V_S< 10 V, I_S= –1 mA

LEAKAGE CURRENTS

Source OFF Leakage I_S(OFF)

±0.03 ±0.3

±0.5 ±50

±0.03 ±0.3

±0.5 ±50

nA typ

V_D= ±10 V, V_S= ϯ10 V;

nA max Test Circuit 2

V_D= ±10 V, V_S= ϯ10 V;

Test Circuit 3

Drain OFF Leakage I_D(OFF)

ADG428

±0.07 ±0.7

nA typ

nA max

nA typ

nA max

±1

±100

±1

±100

ADG429

±0.05 ±0.5

±1

±50

±1

±50

Channel ON Leakage I_D, I_S(ON)

ADG428

ADG429

V_S= V_D= ±10 V;

nA max Test Circuit 4

nA max

±1

±100

±50

±1

±100

±50

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.4

0.8

2.4

0.8

V min

V max

I_INLor I_INH

±0.1 ±1

µA max V_IN= 0 or V_DD

C_IN, Digital Input Capacitance

8

pF typ

f = 1 MHz

DYNAMIC CHARACTERISTICS²

t_TRANSITION

110

250

110

250

ns typ

R_L= 1 MΩ, C_L= 35 pF;

300

ns max V_S1= ±10 V, V_S8= ϯ10 V;

Test Circuit 5

t_OPEN

10

ns min

R_L= 1 kΩ, C_L= 35 pF;

V_S= +5 V; Test Circuit 6

R_L= 1 kΩ, C_L= 35 pF;

V_S= +5 V; Test Circuit 7

R_L= 1 kΩ, C_L= 35 pF;

V_S= +5 V; Test Circuit 7

t_ON(EN, WR)

t_OFF(EN, RS)

115

150

105

150

115

150

105

150

ns typ

ns max

ns typ

ns max

ns min

pC typ

225

300

100

10

300

100

10

t_W, Write Pulsewidth

t_S, Address, Enable Setup Time

t_H, Address, Enable Hold Time

t_RS, Reset Pulsewidth

100

V_S= +5 V

V_S= 0 V, R_S= 0 Ω, C_L= 10 nF;

Test Circuit 10

Charge Injection

4

OFF Isolation

–75

–60

85

–75

–60

85

dB typ

R_L= 1 kΩ, C_L= 15 pF, f = 100 kHz;

dB min V_S= 7 V rms, V_EN= 0 V; Test Circuit 11

Channel-to-Channel Crosstalk

dB typ

pF typ

R_L= 1 kΩ, C_L= 15 pF, f = 100 kHz;

Test Circuit 12

f = 1 MHz

C_S(OFF)

C_D(OFF)

ADG428

ADG429

C_D, C_S(ON)

ADG428

ADG429

11

f = 1 MHz

40

20

40

20

pF typ

f = 1 MHz

54

34

54

34

pF typ

POWER REQUIREMENTS

I_DD

V_IN= 0 V, V_EN= 0 V

20

µA typ

µA max

µA typ

µA max

100

0.001

5

100

0.001

5

I_SS

NOTES

¹Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

REV. C

ADG428/ADG429

SINGLE SUPPLY¹

(V_DD= +12 V, V_SS= 0 V, GND = 0 V, WR = 0 V, RS = 2.4 V unless otherwise noted)

B Version T Version

–40؇C to

+25؇C +85؇C

–55؇C to

Parameter

+25؇C

+125؇C

Units

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

R_ON

0 to V_DD

200

V

90

10

90

10

Ω typ

Ω max

% max

V_D= +10 V, I_S= –500 µA

200

∆R_ON

0 V < V_S< 10 V, I_S= –1 mA

LEAKAGE CURRENTS

Source OFF Leakage I_S(OFF)

±0.005

±0.5

±0.005

±0.5

nA typ

V_D= 10 V/0 V, V_S= 0 V/10 V;

±50

nA max Test Circuit 2

V_D= 10 V/0 V, V_S= 0 V/10 V;

Test Circuit 3

Drain OFF Leakage I_D(OFF)

ADG428

±0.015

±1

±0.008

±1

±0.015

±1

±0.008

±1

nA typ

nA max

nA typ

nA max

±100

±50

±100

±50

ADG429

Channel ON Leakage I_D, I_S(ON)

ADG428

V_S= V_D= 10 V/0 V;

Test Circuit 4

±0.02

±1

±0.01

±1

±0.02

±1

±0.01

±1

nA typ

±100

±50

±100

±50

nA max

ADG429

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.4

0.8

2.4

0.8

V min

V max

I_INLor I_INH

±1

µA max V_IN= 0 or V_DD

C_IN, Digital Input Capacitance

8

pF typ

f = 1 MHz

DYNAMIC CHARACTERISTICS²

t_TRANSITION

250

350

250

350

ns typ

ns max

R_L= 1 MΩ, C_L= 35 pF;

V_S1= 10 V/0 V, V_S8= 0 V/10 V;

Test Circuit 5

R_L= 1 kΩ, C_L= 35 pF;

V_S= +5 V; Test Circuit 6

R_L= 1 kΩ, C_L= 35 pF;

V_S= +5 V; Test Circuit 7

R_L= 1 kΩ, C_L= 35 pF;

V_S= +5 V; Test Circuit 7

450

10

450

10

t_OPEN

25

ns min

t_ON(EN, WR)

t_OFF(EN, RS)

200

300

80

200

300

80

ns typ

ns max

ns typ

ns max

ns min

pC typ

400

300

400

100

10

300

400

100

10

t_W, Write Pulsewidth

t_S, Address, Enable Setup Time

t_H, Address, Enable Hold Time

t_RS, Reset Pulsewidth

100

V_S= +5 V

V_S= 6 V, R_S= 0 Ω, C_L= 10 nF;

Test Circuit 10

Charge Injection

4

OFF Isolation

–75

–60

85

–75

–60

85

dB typ

R_L= 1 kΩ, C_L= 15 pF, f = 100 kHz;

dB min V_S= 7 V rms, V_EN= 0 V; Test Circuit 11

Channel-to-Channel Crosstalk

dB typ

pF typ

R_L= 1 kΩ, C_L= 15 pF, f = 100 kHz;

Test Circuit 12

f = 1 MHz

C_S(OFF)

C_D(OFF)

ADG428

ADG429

C_D, C_S(ON)

ADG428

ADG429

11

f = 1 MHz

40

20

40

20

pF typ

f = 1 MHz

54

34

54

34

pF typ

POWER REQUIREMENTS

I_DD

V_IN= 0 V, V_EN= 0 V

20

100

20

100

µA typ

µA max

NOTES

¹Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. C

–3–

ADG428/ADG429

ABSOLUTE MAXIMUM RATINGS¹

(T_A= +25°C unless otherwise noted.)

ADG428 PIN CONFIGURATIONS

DIP/SOIC PLCC

V_DDto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

V_SSto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V

Analog, Digital Inputs². . . . . . . . . . V_SS– 2 V to V_DD+ 2 V or

30 mA, Whichever Occurs First

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

(Pulsed at 1 ms, 10% Duty Cycle Max)

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

RS

WR

A0

3

2

1

20 19

A1

PIN 1

IDENTIFIER

EN

A2

4

5

6

7

8

18

17

16

15

14

EN

A2

V

GND

SS

V

GND

SS

ADG428

TOP VIEW

(Not to Scale)

ADG428

TOP VIEW

(Not to Scale)

S1

V

DD

S1

S2

S3

S4

D

V

DD

S2

S3

S5

S6

S5

S6

S7

S8

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 73°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C

Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W

Lead Temperature, Soldering

9

10 11 12 13

NC = NO CONNECT

ADG429 PIN CONFIGURATIONS

PLCC

DIP

1

18

RS

WR

A0

3

2

1

20 19

2

3

4

5

6

7

8

9

17

16

15

14

13

12

11

10

A1

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

PLCC Package, Power Dissipation . . . . . . . . . . . . . . . 800 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W

Lead Temperature, Soldering

PIN 1

IDENTIFIER

EN

GND

18

4

5

6

7

8

EN

GND

V

17

16

15

14

SS

DD

V

SS

ADG429

TOP VIEW

(Not to Scale)

DD

ADG429

TOP VIEW

(Not to Scale)

S1A

S1B

S2B

S3B

S1A

S2A

S3A

S4A

DA

S1B

S2B

S3B

S4B

DB

S2A

S3A

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

9

10 11 12 13

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability. Only one absolute

maximum rating may be applied at any one time.

NC = NO CONNECT

²Overvoltages at A, EN, WR, RS, S or D will be clamped by internal diodes. Current

should be limited to the maximum ratings given.

ORDERING GUIDE

Model¹

Temperature Range

Package Options²

ADG428BN

ADG428BP

ADG428BR

ADG428TQ

–40°C to +85°C

–55°C to +125°C

N-18

P-20A

R-18

Q-18

ADG429BN

ADG429BP

ADG429TQ

–40°C to +85°C

–55°C to +125°C

N-18

P-20A

Q-18

NOTES

¹For availability of MIL-STD-883, Class B processed parts, contact factory.

²N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;

R = Small Outline IC (SOIC).

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADG428/ADG429 features proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. C

ADG428/ADG429

ADG428 Truth Table

TERMINOLOGY

V_DD

V_SS

Most positive power supply potential.

A2

A1

A0

EN

WR RS

ON SWITCH

Most negative power supply potential in dual

supplies. In single supply applications, it may

be connected to ground.

Latching

X

g

1

0

Maintains Previous

Switch Condition

GND

R_ON

Ground (0 V) reference.

Reset

X

Ohmic resistance between D and S.

X

NONE

(Latches Cleared)

∆R_ON

Difference between the R_ONof any two

channels.

Transparent Operation

I_S(OFF)

Source leakage current when the switch is off.

Drain leakage current when the switch is off.

I

_D(OFF)

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

NONE

1

2

3

4

5

6

7

8

I_D, I_S(ON)

Channel leakage current when the switch is

on.

V

_D(V_S)

Analog voltage on terminals D, S.

C_S(OFF)

Channel input capacitance for “OFF”

condition.

C

_D(OFF)

Channel output capacitance for “OFF”

condition.

C_D, C_S(ON)

C_IN

“ON” switch capacitance.

Digital input capacitance.

ADG429 Truth Table

A1

A0

EN

WR

RS

ON SWITCH PAIR

t

_ON(EN)

Delay time between the 50% and 90% points

of the digital input and switch “ON”

condition.

Latching

X

g

1

Maintains Previous

Switch Condition

t

_OFF(EN)

Delay time between the 50% and 90% points

of the digital input and switch “OFF”

condition.

Reset

X

t_TRANSITlON

Delay time between the 50% and 90% points

of the digital inputs and the switch “ON”

condition when switching from one address

state to another.

X

0

NONE

(Latches Cleared)

Transparent Operation

X

0

1

X

0

1

0

1

0

1

0

1

NONE

t_OPEN

“OFF” time measured between 80% points of

both switches when switching from one

address state to another.

1

2

3

4

V_INL

V_INH

Maximum input voltage for Logic “0.”

Minimum input voltage for Logic “1.”

Input current of the digital input.

I

_INL(I_INH

)

Crosstalk

A measure of unwanted signal which is

coupled through from one channel to another

as a result of parasitic capacitance.

Off Isolation

A measure of unwanted signal coupling

through an “OFF” channel.

Charge

Injection

A measure of the glitch impulse transferred

from the digital input to the analog output

during switching.

I_DD

I_SS

Positive supply current.

Negative supply current.

REV. C

–5–

ADG428/ADG429

TIMING DIAGRAMS

3V

0V

3V

50%

RS

50%

WR

0V

t_RS

t_W

t_OFF(RS)

t_S

t_H

V

O

3V

2V

0.8V

O

SWITCH

OUTPUT

A0, A1, (A2)

EN

0.8V

0V

Figure 1.

Figure 2.

Figure 1 shows the timing sequence for latching the switch

address and enable inputs. The latches are level sensitive; there-

fore, while WR is held low, the latches are transparent and the

switches respond to the address and enable inputs. This input

data is latched on the rising edge of WR.

Figure 2 shows the Reset Pulsewidth, t_RS, and the Reset Turnoff

Time, t_OFF, (RS).

Note: All digital input signals rise and fall times are measured

from 10% to 90% of 3 V. tr = tf = 20 ns.

Typical Characteristics

140

600

T

= +25؇C

A

T

= +25؇C

A

550

500

130

120

110

100

90

V

= +5V

= 0V

DD

SS

450

400

350

300

250

200

V

= +5V

= –5V

DD

SS

V

= +10V

DD

SS

V

= 0V

80

V

= +15V

= –15V

V

= +15V

= 0V

DD

SS

DD

SS

V

= +12V

= 0V

DD

SS

V

= +12V

= –12V

DD

SS

V

= +10V

= –10V

DD

SS

70

150

100

50

60

50

40

–15

0

3

6

9

12

15

–10

–5

0

5

10

15

V

(V ) – Volts

S

V

(V ) – Volts

S

D

Figure 3. R_ONas a Function of V_D(V_S): Dual Supply

Voltage

Figure 5. R_ONas a Function of V_D(V_S): Single Supply

Voltage

80

160

V

= +15V

= –15V

V

= +12V

= 0V

DD

SS

DD

SS

150

140

130

120

110

100

90

75

70

65

60

55

50

45

40

+125؇C

+85؇C

+125؇C

+85؇C

+25؇C

80

+25؇C

70

60

–15

–10

0

5

10

15

–5

0

2

4

6

8

10

15

V

(V ) – Volts

S

V

(V ) – Volts

S

D

Figure 4. R_ONas a Function of V_D(V_S) for Different

Temperatures

Figure 6. R_ONas a Function of V_D(V_S) for Different

Temperatures

–6–

REV. C

ADG428/ADG429

6000

1000

V

= +15V

= –15V

DD

SS

V

= +15V

= –15V

DD

SS

5500

5000

4500

4000

3500

100

10

1

3000

2500

2000

1500

1000

EN = 2.4V

EN = 0V

EN = 2.4V

EN = 0V

500

0

0.1

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

SWITCHING FREQUENCY – Hz

Figure 7. Positive Supply Current vs. Switching Frequency

Figure 10. Negative Supply Current vs. Switching

Frequency

130

200

V

= +12V

= 0V

V

= +15V

= –15V

DD

SS

t

DD

SS

TRANSITION

120

110

100

90

180

160

t

TRANSITION

t

(EN)

ON

t

(EN)

ON

140

120

100

80

t

(EN)

OFF

80

70

60

50

t

(EN)

OFF

60

40

1

3

5

7

9

11

13

15

3

5

7

9

11

13

V

– Volts

V

– Volts

IN

Figure 8. Switching Time vs. V_IN(Bipolar Supply)

Figure 11. Switching Time vs. V_IN(Single Supply)

500

300

V

= +5V

IN

V

= +5V

IN

275

250

225

200

175

150

125

100

75

450

400

350

300

250

200

150

100

50

t

(EN)

ON

t

(EN)

ON

t

TRANSITION

t

TRANSITION

t

(EN)

OFF

50

t

(EN)

OFF

25

0

؎5

5

6

7

8

9

10

– Volts

11

12

13

14

15

؎7

؎9

؎11

– Volts

؎13

؎15

V

SUPPLY

V

SUPPLY

Figure 12. Switching Time vs. Single Supply

Figure 9. Switching Time vs. Bipolar Supply

REV. C

–7–

ADG428/ADG429

100

95

90

85

80

75

70

65

60

55

50

45

40

110

105

100

95

V

= +15V

= –15V

V

= +15V

= –15V

DD

SS

DD

SS

90

85

80

75

70

65

60

55

50

1k

100

1k

10k

100k

1M

10M

10k

100k

1M

10M

FREQUENCY – Hz

Figure 13. OFF Isolation vs. Frequency

Figure 15. Crosstalk vs. Frequency

0.04

0.03

0.02

0.01

0

0.2

0.1

0

V

T

= +12V

= 0V

V

T

= +15V

= –15V

DD

SS

DD

SS

= +25؇C

A

I

(ON)

D

I

(OFF)

I

(ON)

D

I

(OFF)

S

I

(OFF)

S

–0.01

–0.02

–0.03

–0.04

I

(OFF)

D

–0.1

–15

–10

–5

0

5

10

15

0

2

4

6

8

10

12

V

(V ) – Volts

S

V

(V ) – Volts

S

D

Figure 14. Leakage Currents as a Function of V_D(V_S)

Figure 16. Leakage Currents as a Function of V_D(V_S)

–8–

REV. C

ADG428/ADG429

TEST CIRCUITS

I

DS

V1

V

SS

DD

V

SS

DD

S1

S2

S8

D

S

D

+0.8V

I

(OFF)

A

EN

D

GND

V

S

V

S

V

D

R

= V1/I

ON

DS

Test Circuit 1. On Resistance

Test Circuit 3. I_D(OFF)

V

SS

DD

SS

DD

V

SS

V

SS

DD

S1

S8

D

S2

S8

D

I

(OFF)

V

A

S

I

(ON)

A

D

2.4V

+0.8V

EN

GND

V

S

V

S

D

Test Circuit 4. I_D(ON)

Test Circuit 2. I_S(OFF)

V

SS

DD

3V

0V

V

SS

DD

ENABLE

DRIVE – V

50%

A0

A1

A2

IN

S1

S2–S7

V

S1

V

50⍀

IN

ADG428*

t_TRANSITION

S8

D

S8

2.4V

EN

90%

OUTPUT

RS

OUTPUT

WR

1M⍀

GND

35pF

90%

*SIMILAR CONNECTION FOR ADG429

Test Circuit 5. Switching Time of Multiplexer, t_TRANSITION

V

SS

DD

V

SS

3V

0V

DD

A0

A1

A2

ADDRESS

DRIVE – V

S1

S2–S7

V

S

IN

V

50⍀

IN

ADG428*

S8

D

2.4V

EN

OUTPUT

80%

RS

OUTPUT

WR

1k⍀

GND

35pF

t_OPEN

*SIMILAR CONNECTION FOR ADG429

Test Circuit 6. Break-Before-Make Delay, t_OPEN

–9–

REV. C

ADG428/ADG429

V

SS

DD

V

SS

3V

DD

A0

A1

A2

ENABLE DRIVE

50%

S1

S2–S8

V

S

–V

IN

0V

ADG428*

t_ON(EN)

t_OFF(EN)

0.9V

2.4V

RS

OUTPUT

V

O

D

0.9V

O

EN

OUTPUT (V

)

O

1k⍀

35pF

V

50⍀

IN

0V

WR

GND

*SIMILAR CONNECTION FOR ADG429

Test Circuit 7. Enable Delay, t_ON(EN), t_OFF(EN)

V

SS

DD

3V

WR

V

SS

DD

50%

A0

A1

A2

S1

S2–S8

V

S

0V

ADG428*

2.4V

EN

t_ON(WR)

OUTPUT

V

O

RS

D

WR

OUTPUT

1k⍀

35pF

0.2V

O

GND

V

WR

RS

0V

*SIMILAR CONNECTION FOR ADG429

Test Circuit 8. Write Turn-On Time, t_ON(WR)

V

SS

DD

3V

0V

V

SS

DD

A0

RS

50%

S1

S2–S8

V

S

A1

A2

ADG428*

t_OFF(RS)

2.4V

EN

OUTPUT

D

V

O

RS

0.8V

O

1k⍀

35pF

OUTPUT

GND

WR

V

IN

0V

*SIMILAR CONNECTION FOR ADG429

Test Circuit 9. Reset Turn-Off Time, t_OFF(RS)

–10–

REV. C

ADG428/ADG429

V

SS

DD

V

SS

3V

DD

A0

A1

A2

2.4V

RS

EN

ADG428*

S

D

V

OUT

⌬V

V

OUT

R

S

V

S

C

L

Q

= C

؋

⌬V

OUT

EN

INJ

L

10nF

V

GND

WR

IN

*SIMILAR CONNECTION FOR ADG429

Test Circuit 10. Charge Injection

V

SS

V

SS

DD

V

SS

V

SS

DD

A0

A1

A2

EN

2.4V

A0

A1

A2

2.4V

RS

ADG428

S1

S2

D

S1

V

OUT

D

OUT

1k⍀

S8

V

S

EN

0V

S8

V

S

GND

WR

GND

WR

Test Circuit 12. Crosstalk

Test Circuit 11. OFF Isolation

REV. C

–11–

ADG428/ADG429

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Cerdip (Q-18)

PLCC (P-20A)

0.180 (4.57)

18

10

0.165 (4.19)

0.048 (1.21)

0.310 (7.87)

0.056 (1.42)

0.042 (1.07)

0.220 (5.59)

0.025 (0.63)

1

9

0.015 (0.38)

0.048 (1.21)

0.042 (1.07)

0.320 (8.13)

0.290 (7.37)

PIN 1

0.840 (21.34) MAX

3

19

18

0.021 (0.53)

0.013 (0.33)

0.060 (1.52)

0.015 (0.38)

4

8

PIN 1

0.050

(1.27)

BSC

IDENTIFIER

0.330 (8.38)

0.290 (7.37)

0.200 (5.08)

MAX

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

0.150

(3.81)

MIN

0.015 (0.381)

0.008 (0.204)

14

13

0.200 (5.08)

0.125 (3.18)

9

0.020

(0.50)

R

0.040 (1.01)

0.025 (0.64)

0.022 (0.58)

0.014 (0.36)

SEATING

PLANE

0.356 (9.04)

0.350 (8.89)

0.100

(2.54)

BSC

0.070 (1.78)

0.030 (0.76)

SQ

0.110 (2.79)

0.085 (2.16)

0.395 (10.02)

0.385 (9.78)

SQ

Plastic DIP (N-18)

SOIC (R-18)

0.910 (23.12)

0.890 (22.61)

0.4625 (11.75)

0.4469 (11.35)

18

10

9

0.260 (6.61)

0.240 (6.10)

18

10

1

0.306 (7.78)

0.294 (7.47)

PIN 1

0.180

(4.48)

MAX

0.140 (3.56)

0.120 (3.05)

1

9

0.175 (4.45)

0.120 (3.05)

0.120 (0.305)

0.008 (0.203)

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

SEATING

PLANE

0.065 (1.66)

0.020 (0.508) 0.105 (2.67)

x 45°

0.0098 (0.25)

0.095 (2.42) 0.045 (1.15)

0.015 (0.381)

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0118 (0.30)

0.0040 (0.10)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

0.0138 (0.35)

–12–

REV. C


型号：	ADG429
厂家：	ADI
描述：	LC2MOS Latchable 4-/8-Channel High Performance Analog Multiplexers LC2MOS可锁存4- / 8通道高性能模拟多路复用器复用器
文件：	总12页 (文件大小：161K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADG429 [ADI]

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