ADG431TQ [ADI]

LC2MOS Precision Quad SPST Switches; LC2MOS精密四通道SPST开关


型号：	ADG431TQ
厂家：	ADI
描述：	LC2MOS Precision Quad SPST Switches LC2MOS精密四通道SPST开关复用器开关复用器或开关信号电路输出元件
文件：	总8页 (文件大小：123K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LC²MOS

Precision Quad SPST Switches

ADG431/ADG432/ADG433

FUNCTIONAL BLOCK DIAGRAMS

FEATURES

44 V Supply Maximum Ratings

؎15 V Analog Signal Range

Low On Resistance (<24 ⍀)

Ultralow Power Dissipation (3.9 ␮W)

Low Leakage (<0.25 nA)

Fast Switching Times

t_ON<165 ns

t_OFF<130 ns

Break-Before-Make Switching Action

TTL/CMOS Compatible

Plug-in Replacement for DG411/DG412/DG413

IN1

IN2

IN3

IN4

IN1

IN2

IN3

IN4

ADG431

ADG432

APPLICATIONS

IN1

Audio and Video Switching

Automatic Test Equipment

Precision Data Acquisition

Battery Powered Systems

Sample Hold Systems

Communication Systems

IN2

IN3

IN4

ADG433

GENERAL DESCRIPTION

SWITCHES SHOWN FOR A LOGIC "1" INPUT

The ADG431, ADG432 and ADG433 are monolithic CMOS

devices comprising four independently selectable switches. They

are designed on an enhanced LC²MOS process which provides

low power dissipation yet gives high switching speed and low on

resistance.

PRODUCT HIGHLIGHTS

1. Extended Signal Range

The ADG431, ADG432 and ADG433 are fabricated on an

enhanced LC²MOS process giving an increased signal range

which extends fully to the supply rails.

The on resistance profile is very flat over the full analog input

range ensuring excellent linearity and low distortion when

switching audio signals. Fast switching speed coupled with high

signal bandwidth also make the parts suitable for video signal

switching. CMOS construction ensures ultralow power dissipa-

tion making the parts ideally suited for portable and battery

powered instruments.

2. Ultralow Power Dissipation

3. Low R_ON

4. Break-Before-Make Switching

This prevents channel shorting when the switches are config-

ured as a multiplexer.

The ADG431, ADG432 and ADG433 contain four indepen-

dent SPST switches. The ADG431 and ADG432 differ only in

that the digital control logic is inverted. The ADG431 switches

are turned on with a logic low on the appropriate control input,

while a logic high is required for the ADG432. The ADG433

has two switches with digital control logic similar to that of the

ADG431 while the logic is inverted on the other two switches.

5. Single Supply Operation

For applications where the analog signal is unipolar, the

ADG431, ADG432 and ADG433 can be operated from a

single rail power supply. The parts are fully specified with a

single +12 V power supply and will remain functional with

single supplies as low as +5 V.

Each switch conducts equally well in both directions when ON

and has an input signal range which extends to the supplies. In

the OFF condition, signal levels up to the supplies are blocked.

All switches exhibit break before make switching action for use

in multiplexer applications. Inherent in the design is low charge

injection for minimum transients when switching the digital inputs.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADG431/ADG432/ADG433–SPECIFICATIONS¹

(V = +15 V ؎ 10%, V = –15 V ؎ 10%, V = +5 V ؎ 10%, GND = O V, unless otherwise noted)

Dual Supply

B Versions

T Versions

–55؇C to

–40؇C to

Parameter

+25؇C +85؇C

+25؇C +125؇C

Units

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

R_ON

_DDto V_SS

V_DDto V_SS

0.5

Ω typ

Ω max

% typ

%/°C typ

% typ

V_D= ±8.5 V, I_S= –10 mA;

V_DD= +13.5 V, V_SS= –13.5 V

0.5

R_ONvs. V_D(V_S)

R_ONDrift

R_ONMatch

V_D= 0 V, I_S= –10 mA

LEAKAGE CURRENTS

Source OFF Leakage I_S(OFF)

V_DD= +16.5 V, V_SS= –16.5 V

V_D= ±15.5 V, V_S= ϯ15.5 V;

Test Circuit 2

V_D= ±15.5 V, V_S= ϯ15.5 V;

Test Circuit 2

V_D= V_S= ±15.5 V;

Test Circuit 3

±0.05

±0.25 ±2

±0.05

±0.25 ±2

±0.1

±0.35 ±3

±0.05

±0.25 ±15

±0.05

±0.25 ±15

±0.1

±0.35 ±17

nA typ

nA max

nA typ

nA max

nA typ

nA max

Drain OFF Leakage I_D(OFF)

Channel ON Leakage I_D, I_S(ON)

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.4

0.8

2.4

0.8

V min

V max

I_INLor I_INH

0.005

µA typ

µA max

pF typ

V_IN= V_INLor V_INH

±0.02

C_INDigital Input Capacitance

DYNAMIC CHARACTERISTICS²

t_ON

V_DD= +15 V, V_SS= –15 V

R_L= 300 Ω, C_L= 35 pF;

V_S= ±10 V; Test Circuit 4

R_L= 300 Ω, C_L= 35 pF;

V_S= ±10 V; Test Circuit 4

R_L= 300 Ω, C_L= 35 pF;

V_S1= V_S2= +10 V;

ns typ

ns max

ns typ

ns max

ns typ

165

130

175

145

t_OFF

Break-Before-Make Time Delay, t_D25

(ADG433 Only)

Test Circuit 5

V_S= 0 V, R_S= 0 Ω, C_L= 10 nF;

Test Circuit 6

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 7

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 8

Charge Injection

pC typ

dB typ

OFF Isolation

Channel-to-Channel Crosstalk

C_S(OFF)

C_D(OFF)

C_D, C_S(ON)

pF typ

f = 1 MHz

POWER REQUIREMENTS

_DD= +16.5 V, V_SS= –16.5 V

Digital Inputs = 0 V or 5 V

I_DD

I_SS

I_L

0.0001

0.1

0.0001

0.1

0.0001

0.1

0.0001

0.1

0.0001

0.1

0.0001

0.1

µA typ

µA max

µA typ

µA max

µA typ

µA max

µW max

0.2

7.7

0.2

7.7

Power Dissipation

NOTES

¹Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

REV. B

ADG431/ADG432/ADG433

(V_DD= +12 V ؎ 10%, V_SS= O V, V_L= +5 V ؎ 10%, GND = O V, unless otherwise noted)

Single Supply

B Versions

–40؇C to

T Versions

–55؇C to

Parameter

+25؇C +85؇C

+25؇C +125؇C

Units

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

R_ON

0 V to V_DD

Ω typ

Ω max

% typ

%/°C typ

% typ

0 < V_D< 8.5 V, I_S= –10 mA;

V_DD= +10.8 V

0.5

R_ONvs. V_D(V_S)

R_ONDrift

R_ONMatch

V_D= 0 V, I_S= –10 mA

_DD= +13.2 V

LEAKAGE CURRENTS

Source OFF Leakage I_S(OFF)

±0.04

±0.25 ±2

±0.04

±0.25 ±2

±0.01

±0.3

±0.04

±0.25 ±15

±0.04

±0.25 ±15

±0.01

±0.3

nA typ

nA max

nA typ

nA max

nA typ

nA max

V_D= 12.2/1 V, V_S= 1/12.2 V;

Test Circuit 2

V_D= 12.2/1 V, V_S= 1/12.2 V;

Test Circuit 2

V_D= V_S= +12.2 V/+1 V;

Test Circuit 3

Drain OFF Leakage I_D(OFF)

Channel ON Leakage I_D, Is (ON)

±3

±17

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.4

0.8

2.4

0.8

V min

V max

I_INLor I_INH

0.005

µA typ

µA max

pF typ

V_IN= V_INLor V_INH

±0.01

C_INDigital Input Capacitance

DYNAMIC CHARACTERISTICS²

t_ON

V_DD= +12 V, V_SS= 0 V

R_L= 300 Ω, C_L= 35 pF;

V_S= +8 V; Test Circuit 4

R_L= 300 Ω, C_L= 35 pF;

V_S= +8 V; Test Circuit 4

R_L= 300 Ω, C_L= 35 pF;

V_S1= V_S2= +10 V;

Test Circuit 5

165

ns typ

ns max

ns typ

ns max

ns typ

240

115

240

115

t_OFF

Break-Before-Make Time Delay, t_D25

(ADG433 Only)

Charge Injection

pC typ

dB typ

V_S= 0 V, R_S= 0 Ω, C_L= 10 nF;

Test Circuit 6

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 7

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 8

OFF Isolation

Channel-to-Channel Crosstalk

C_S(OFF)

C_D(OFF)

C_D, C_S(ON)

pF typ

f = 1 MHz

POWER REQUIREMENTS

V_DD= +13.2 V

Digital Inputs = 0 V or 5 V

I_DD

I_L

0.0001

0.03

0.0001

0.03

0.0001

0.03

0.0001

0.03

µA typ

µA max

µA typ

µA max

µW max

0.1

1.9

0.1

1.9

V_L= +5.25 V

Power Dissipation

NOTES

¹Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

Truth Table (ADG431/ADG432)

Truth Table (ADG433)

Switch 1, 4

ADG431 In

ADG432 In

Switch Condition

Logic

Switch 2, 3

OFF

REV. B

–3–

ADG431/ADG432/ADG433

ABSOLUTE MAXIMUM RATINGS

(T_A= +25°C unless otherwise noted)

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 76°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C

Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W

Lead Temperature, Soldering

V_DDto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

V_SSto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V

V_Lto GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Analog, Digital Inputs². . . . . . . . . . V_SS– 2 V to V_DD+ 2 V or

30 mA, Whichever Occurs First

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

(Pulsed at 1 ms, 10% Duty Cycle max)

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability. Only one absolute

maximum rating may be applied at any one time.

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW

²Overvoltages at IN, S or D will be clamped by internal diodes. Current should be

limited to the maximum ratings given.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, perma-

nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

PIN CONFIGURATION

(DIP/SOIC)

Model¹

Temperature Range

Package Options²

ADG431BN

ADG431BR

ADG431TQ

ADG431ABR

ADG432BN

ADG432BR

ADG432TQ

ADG432ABR

–40°C to +85°C

–55°C to +125°C

–40°C to +85°C

–55°C to +125°C

–40°C to +85°C

N-16

IN1

IN2

R-16A

Q-16

ADG431

ADG432

R-16A³

ADG433 13

TOP VIEW

N-16

GND

R-16A

Q-16

(Not to Scale)

R-16A³

IN3

ADG433BN

ADG433BR

ADG433ABR

–40°C to +85°C

N-16

IN4

R-16A

R-16A³

NOTES

¹To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers.

²N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.

³Trench isolated, latch-up proof parts. See Trench Isolation section.

TERMINOLOGY

C_S(OFF)

V_DD

V_SS

Most positive power supply potential.

Most negative power supply potential in dual

supplies. In single supply applications, it may be

connected to GND.

Logic power supply (+5 V).

Ground (0 V) reference.

“OFF” switch source capacitance.

“OFF” switch drain capacitance.

“ON” switch capacitance.

C_D(OFF)

C_D, C_S(ON)

C_IN

Input Capacitance to ground of a digital input.

Delay between applying the digital control input

and the output switching on.

Delay between applying the digital control input

and the output switching off.

“OFF” time or “ON” time measured between the

90% points of both switches, when switching

from one address state to another.

A measure of unwanted signal which is coupled

through from one channel to another as a result

of parasitic capacitance.

V_L

GND

t_ON

Source terminal. May be an input or output.

Drain terminal. May be an input or output.

Logic control input.

t_OFF

t_D

R_ON

Ohmic resistance between D and S.

R_ONvs. V_D(V_S) The variation in R_ONdue to a change in the ana-

log input voltage with a constant load current.

Crosstalk

R_ONDrift

R_ONMatch

I_S(OFF)

I_D(OFF)

I_D, I_S(ON)

V_D(V_S)

Change in R_ONvs. temperature.

Difference between the R_ONof any two switches.

Source leakage current with the switch “OFF.”

Drain leakage current with the switch “OFF.”

Channel leakage current with the switch “ON.”

Analog voltage on terminals D, S.

Off Isolation

A measure of unwanted signal coupling through an

“OFF” switch.

A measure of the glitch impulse transferred from the

digital input to the analog output during switching.

Charge

Injection

–4–

REV. B

ADG431/ADG432/ADG433

Typical Performance Graphs

= +25؇C

= +5V

= +25؇C

= +5V

= 0V

= +5V

= –5V

= +10V

= 0V

= +12V

= 0V

= +10V

= –10V

= +12V

= –12V

= +15V

= 0V

= +15V

= –15V

–20

–10

OR V – DRAIN OR SOURCE VOLTAGE – V

Figure 1. On Resistance as a Function of V_D(V_S) Dual

Supplies

Figure 4. On Resistance as a Function of V_D(V_S) Single

Supply

100mA

= +15V

= –15V

= +5V

4 SW

1 SW

= +15V

= –15V

= +5V

10mA

1mA

I+, I–

100␮A

10␮A

+125؇C

+85؇C

+25؇C

1␮A

100nA

100

10k

100k

10M

–20

–10

FREQUENCY – Hz

OR V – DRAIN OR SOURCE VOLTAGE – V

Figure 2. On Resistance as a Function of

V_D(V_S) for Different Temperatures

Figure 5. Supply Current vs. Input Switching Frequency

0.04

= +15V

= –15V

= +15V

= –15V

= +5V

= +25؇C

= +5V

(ON)

0.02

0.1

= ؎15V

I (OFF)

(OFF)

0.00

–0.02

–0.04

(OFF)

0.01

0.001

(ON)

100

120

140

–20

–10

TEMPERATURE – ؇C

OR V – DRAIN OR SOURCE VOLTAGE – V

Figure 3. Leakage Currents as a Function of Temperature

Figure 6. Leakage Currents as a Function of V_D(V_S)

REV. B

–5–

ADG431/ADG432/ADG433

120

= +15V

= –15V

= +5V

P-CHANNEL

N-CHANNEL

100

–

BURIED OXIDE LAYER

SUBSTRATE (BACKGATE)

Figure 9. Trench Isolation

APPLICATION

Figure 10 illustrates a precise, fast sample-and-hold circuit. An

AD845 is used as the input buffer while the output operational

amplifier is an AD711. During the track mode, SW1 is closed

and the output V_OUTfollows the input signal V_IN. In the hold

mode, SW1 is opened and the signal is held by the hold capaci-

tor C_H.

100

10k

100k

10M

FREQUENCY – Hz

Figure 7. Off Isolation vs. Frequency

110

Due to switch and capacitor leakage, the voltage on the hold

capacitor will decrease with time. The ADG431/ADG432/

ADG433 minimizes this droop due to its low leakage specifica-

tions. The droop rate is further minimized by the use of a poly-

styrene hold capacitor. The droop rate for the circuit shown is

typically 30 µV/µs.

= +15V

= –15V

= +5V

100

A second switch SW2, which operates in parallel with SW1, is

included in this circuit to reduce pedestal error. Since both

switches will be at the same potential, they will have a differen-

tial effect on the op amp AD711 which will minimize charge

injection effects. Pedestal error is also reduced by the compensa-

tion network R_Cand C_C. This compensation network also

reduces the hold time glitch while optimizing the acquisition

time. Using the illustrated op amps and component values, the

pedestal error has a maximum value of 5 mV over the ±10 V

input range. Both the acquisition and settling times are 850 ns.

100

10k

100k

10M

FREQUENCY – Hz

Figure 8. Crosstalk vs. Frequency

TRENCH ISOLATION

+15V

+5V

2200pF

In the ADG431A, ADG432A and ADG433A, an insulating

oxide layer (trench) is placed between the NMOS and PMOS

transistors of each CMOS switch. Parasitic junctions, which

occur between the transistors in junction isolated switches, are

eliminated, the result being a completely latch-up proof switch.

+15V

AD711

–15V

SW2

SW1

+15V

OUT

1000pF

75⍀

AD845

2200pF

In junction isolation, the N and P wells of the PMOS and

NMOS transistors from a diode that is reverse-biased under

normal operation. However, during overvoltage conditions, this

diode becomes forward biased. A silicon-controlled rectifier

(SCR) type circuit is formed by the two transistors causing a

significant amplification of the current which, in turn, leads to

latch up. With trench isolation, this diode is removed, the result

being a latch-up proof switch.

–15V

ADG431

ADG432

ADG433

–15V

Figure 10. Fast, Accurate Sample-and-Hold

–6–

REV. B

ADG431/ADG432/ADG433

Test Circuits

(ON)

(OFF)

= V1/I

Test Circuit 3. On Leakage

Test Circuit 1. On Resistance

Test Circuit 2. Off Leakage

+15V

0.1␮F

+5V

0.1␮F

50%

ADG431

OUT

ADG432

35pF

300⍀

90%

OUT

GND

0.1␮F

–15V

t_ON

t_OFF

Test Circuit 4. Switching Times

+15V

+5V

0.1␮F

50%

OUT1

90%

OUT1

35pF

OUT2

300⍀

35pF

IN1, IN2

300⍀

90%

GND

OUT2

t_D

0.1␮F

–15V

Test Circuit 5. Break-Before-Make Time Delay

+15V

+5V

OUT

10nF

OUT

⌬V

OUT

GND

= C

⌬V

L OUT

INJ

–15V

Test Circuit 6. Charge Injection

REV. B

–7–

ADG431/ADG432/ADG433

+15V

0.1␮F

+5V

+15V

+5V

0.1␮F

50⍀

OUT

IN1

IN2

50⍀

OUT

GND

50⍀

CHANNEL TO CHANNEL

CROSSTALK = 20

LOG V /V

0.1␮F

–15V

0.1␮F

–15V

OUT

Test Circuit 7. Off Isolation

Test Circuit 8. Channel-to-Channel Crosstalk

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Cerdip

(Q-16)

16-Lead SOIC

(R-16A)

0.005 (0.13) MIN

0.080 (2.03) MAX

0.3937 (10.00)

0.3859 (9.80)

0.310 (7.87)

0.1574 (4.00)

0.1497 (3.80)

0.220 (5.59)

0.2440 (6.20)

0.2284 (5.80)

0.320 (8.13)

0.290 (7.37)

PIN 1

0.840 (21.34) MAX

0.060 (1.52)

0.015 (0.38)

0.0688 (1.75)

0.0532 (1.35)

PIN 1

0.0196 (0.50)

0.0099 (0.25)

x 45؇

0.200 (5.08)

MAX

0.0098 (0.25)

0.0040 (0.10)

0.150

(3.81)

MIN

SEATING

PLANE

0.200 (5.08)

0.125 (3.18)

8؇

0؇

0.015 (0.38)

0.008 (0.20)

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.023 (0.58)

0.014 (0.36)

0.100

(2.54)

BSC

0.070 (1.78)

0.030 (0.76)

SEATING

PLANE

15°

0°

0.0500 (1.27)

0.0160 (0.41)

0.0099 (0.25)

0.0075 (0.19)

16-Lead Plastic DIP (Narrow)

(N-16)

0.840 (21.34)

0.745 (18.92)

0.280 (7.11)

0.240 (6.10)

0.325 (8.26)

0.195 (4.95)

0.115 (2.93)

0.300 (7.62)

PIN 1

0.060 (1.52)

0.015 (0.38)

0.210 (5.33)

MAX

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

0.070 (1.77) SEATING

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

PLANE

0.045 (1.15)

–8–

REV. B

ADG431TQ [ADI]

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SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E