ADG442BNZ [ADI]

LC2MOS Quad SPST Switch;


型号：	ADG442BNZ
厂家：	ADI
描述：	LC2MOS Quad SPST Switch 开关
文件：	总9页 (文件大小：326K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LC²MOS Quad SPST Switches

ADG441/ADG442/ADG444

FEATURES

44 V Supply Maximum Ratings

FUNCTIONAL BLOCK DIAGRAMS

_SSto V_DDAnalog Signal Range

Low On Resistance (< 70 Ω)

Low ∆R_ON(9 Ω max)

Low R_ONMatch (3 Ω max)

Low Power Dissipation

Fast Switching Times

t_ON< 110 ns

IN1

IN2

IN3

IN4

IN1

IN2

IN3

IN4

ADG441

ADG444

ADG442

t_OFF< 60 ns

Low Leakage Currents ( 3 nA max)

Low Charge Injection (6 pC max)

Break-Before-Make Switching Action

Latch-Up Proof

Plug-In Upgrade for

DG201A/ADG201A, DG202A/ADG202A,

DG211/ADG211A

SWITCHES SHOWN FOR A LOGIC "1" INPUT

Plug in Replacement for DG441/DG442/DG444

APPLICATIONS

Each switch conducts equally well in both directions when ON

and has an input signal range that extends to the power sup-

plies. In the OFF condition, signal levels up to the supplies are

blocked. All switches exhibit break-before-make switching action

for use in multiplexer applications. Inherent in the design is low

charge injection for minimum transients when switching the

digital inputs.

Audio and Video Switching

Automatic Test Equipment

Precision Data Acquisition

Battery Powered Systems

Sample Hold Systems

Communication Systems

GENERAL DESCRIPTION

The ADG441, ADG442 and ADG444 are monolithic CMOS

devices comprising four independently selectable switches. They

are designed on an enhanced LC²MOS process that provides

low power dissipation yet gives high switching speed and low on

resistance.

PRODUCT HIGHLIGHTS

1. Extended Signal Range

The ADG441/ADG442/ADG444 are fabricated on an en-

hanced LC²MOS, trench-isolated process, giving an in-

creased signal range that extends to the supply rails.

The on resistance profile is very flat over the full analog input

range ensuring good linearity and low distortion when switching

audio signals. High switching speed also makes the parts suit-

able for video signal switching. CMOS construction ensures

ultralow power dissipation making the parts ideally suited for

portable and battery powered instruments.

2. Low Power Dissipation

3. Low R_ON

4. Trench Isolation Guards Against Latch Up

A dielectric trench separates the P and N channel transistors

thereby preventing latch up even under severe overvoltage

conditions.

The ADG441, ADG442 and ADG444 contain four indepen-

dent SPST switches. Each switch of the ADG441 and ADG444

turns on when a logic low is applied to the appropriate control

input. The ADG442 switches are turned on with a logic high on

the appropriate control input. The ADG441 and ADG444

switches differ in that the ADG444 requires a 5 V logic power

supply which is applied to the V_Lpin. The ADG441 and

ADG442 do not have a V_Lpin, the logic power supply being

generated internally by an on-chip voltage generator.

5. Break-Before-Make Switching

This prevents channel shorting when the switches are config-

ured as a multiplexer.

6. Single Supply Operation

For applications where the analog signal is unipolar, the

ADG441/ADG442/ADG444 can be operated from a single

rail power supply. The parts are fully specified with a single

+12 V power supply.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

ADG441/ADG442/ADG444–SPECIFICATIONS¹

Dual Supply ^(V_DD= +15 V ± 10%, V_SS= –15 V ± 10%, V_L= +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted)

B Version

T Version

–55°C to

–40°C to

+85°C

Parameter

+25°C

+125°C

Units

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

R_ON

V_SSto V_DD

Ω typ

Ω max

Ω typ

Ω max

Ω typ

Ω max

V_D= ±8.5 V, I_S= –10 mA

V_DD= +13.5 V, V_SS= –13.5 V

–8.5 V ≤ V_D≤ +8.5 V

∆R_ON

R_ONMatch

V_D= 0 V, I_S= –10 mA

LEAKAGE CURRENTS

Source OFF Leakage I_S(OFF)

V_DD= +16.5 V, V_SS= –16.5 V

V_D= ±15.5 V, V_S= ϯ15.5 V;

Test Circuit 2

V_D= ±15.5 V, V_S= ϯ15.5 V;

Test Circuit 2

V_S= V_D= ±15.5 V;

Test Circuit 3

±0.01

±0.5

±0.01

±0.5

±0.08

±0.5

±0.01

±0.5

±0.01

±0.5

±0.08

±0.5

nA typ

nA max

nA typ

nA max

nA typ

nA max

±3

±20

±40

Drain OFF Leakage I_D(OFF)

Channel ON Leakage I_D, I_S(ON)

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.4

0.8

2.4

0.8

V min

V max

I_INLor I_INH

±0.00001

±0.5

±0.00001

±0.5

µA typ

µA max

V_IN= V_INLor V_INH

DYNAMIC CHARACTERISTICS²

t_ON

110

ns typ

ns max

ns typ

ns max

ns typ

pC typ

pC max

R_L= 1 kΩ, C_L= 35 pF;

V_S= ±10 V; Test Circuit 4

R_L= 1 kΩ, C_L= 35 pF;

V_S= ±10 V; Test Circuit 4

R_L= 1 kΩ, C_L= 35 pF;

V_S= 0 V, R_S= 0 Ω, C_L= 1 nF;

V_DD= +15 V, V_SS= –15 V;

Test Circuit 5

170

t_OFF

t_OPEN

Charge Injection

OFF Isolation

dB typ

R_L= 50 Ω, C_L= 5 pF;

f = 1 MHz; Test Circuit 6

R_L= 50 Ω, C_L= 5 pF;

f = 1 MHz; Test Circuit 7

f = 1 MHz

Channel-to-Channel Crosstalk

100

C_S(OFF)

C_D(OFF)

C_D, C_S(ON)

pF typ

POWER REQUIREMENTS

I_DD

_DD= +16.5 V, V_SS= –16.5 V

Digital Inputs = 0 V or 5 V

ADG441/ADG442

ADG444

µA max

µA typ

0.001

2.5

µA max

µA typ

µA max

µA typ

I_SS

0.0001

0.001

0.0001

0.001

I_L(ADG444 Only)

V_L= +5.5 V

µA max

NOTES

¹Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

REV. 0

ADG441/ADG442/ADG444

Single Supply

(V_DD= +12 V ± 10%, V_SS= 0 V, V_L= +5 V ± 10% (ADG444), GND = 0 V, unless otherwise noted)

B Version

–40°C to

T Version

–55°C to

Parameter

+25°C

+85°C

+25°C

+125°C

Units

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

R_ON

0 to V_DD

110

Ω typ

Ω max

Ω typ

Ω max

Ω typ

Ω max

V_D= +3 V, +8 V, I_S= –10 mA;

V_DD= +10.8 V

+3 V ≤ V_D≤ +8 V

130

∆R_ON

R_ONMatch

V_D= 6 V, I_S= –10 mA

LEAKAGE CURRENT

Source OFF Leakage I_S(OFF)

V_DD= +13.2 V

V_D= 12.2 V/1 V, V_S= 1 V/12.2 V;

Test Circuit 2

V_D= 12.2 V/1 V, V_S= 1 V/12.2 V;

Test Circuit 2

V_S= V_D= 12.2 V/1 V;

Test Circuit 3

±0.01

±0.5

±0.01

±0.5

±0.08

±0.5

±0.01

±0.5

±0.01

±0.5

±0.08

±0.5

nA typ

nA max

nA typ

nA max

nA typ

nA max

±3

±20

±40

Drain OFF Leakage I_D(OFF)

Channel ON Leakage I_D, I_S(ON)

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.4

0.8

2.4

0.8

V min

V max

I_INLor I_INH

±0.00001

±0.5

±0.00001

±0.5

µA typ

µA max

V_IN= V_INLor V_INH

DYNAMIC CHARACTERISTICS²

t_ON

105

150

105

150

ns typ

ns max

ns typ

ns max

ns typ

pC typ

pC max

R_L= 1 kΩ, C_L= 35 pF;

V_S= +8 V; Test Circuit 4

R_L= 1 kΩ, C_L= 35 pF;

V_S= +8 V; Test Circuit 4

R_L= 1 kΩ, C_L= 35 pF;

V_S= 6 V, R_S= 0 Ω, C_L= 1 nF;

V_DD= +12 V, V_SS= 0 V;

Test Circuit 5

220

100

220

100

t_OFF

t_OPEN

Charge Injection

OFF Isolation

dB typ

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 6

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 7

Channel-to-Channel Crosstalk

100

C_S(OFF)

C_D(OFF)

C_D, C_S(ON)

pF typ

f = 1 MHz

POWER REQUIREMENTS

I_DD

V_DD= +13.2 V

Digital Inputs = 0 V or 5 V

ADG441/ADG442

ADG444

µA max

µA typ

µA max

µA typ

µA max

0.001

2.5

I_L(ADG444 Only)

NOTES

V_L= +5.5 V

¹Temperature ranges are as follows: B Versions: –40°C to +85°C; T Versions: –55°C to +125°C.

²Guaranteed by design, not subject to production test.

ORDERING GUIDE

Temperature Range

Specifications subject to change without notice.

Model¹

Package Option²

Table I. Truth Table

ADG441BN

ADG441BR

ADG441TQ

–40°C to +85°C

–55°C to +125°C

N-16

R-16A

Q-16

ADG441/ADG444

ADG442

Switch

Condition

OFF

ADG442BN

ADG442BR

–40°C to +85°C

N-16

R-16A

ADG444BN

ADG444BR

–40°C to +85°C

N-16

R-16A

OTES

¹To order MIL-STD-883, Class B processed parts, add /883B to T grade part

numbers.

²N = Plastic DIP, R = 0.15" Small Outline IC (SOIC), Q = Cerdip.

REV. 0

–3–

ADG441/ADG442/ADG444

ABSOLUTE MAXIMUM RATINGS¹

TERMINOLOGY

(T_A= +25°C unless otherwise noted)

V_DD

V_SS

Most Positive Power Supply Potential.

V_DDto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V

V_SSto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V

V_Lto GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Analog, Digital Inputs². . . . . . . . . . . . V_SS– 2 V to V_DD+ 2 V

or 30 mA, Whichever Occurs First

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

(Pulsed at 1 ms, 10% Duty Cycle Max)

Most Negative Power Supply Potential in dual

supplies. In single supply applications, it may be

connected to ground.

V_L

Logic Power Supply (+5 V).

GND

Ground (0 V) Reference.

Source Terminal. May be an input or output.

Drain Terminal. May be an input or output.

Logic Control Input.

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . . –40°C to +85°C

Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . +300°C

Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 177°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 77°C/W

Lead Temperature, Soldering

R_ON

Ohmic resistance between D and S.

Difference between the R_ONof any two channels.

Source leakage current with the switch “OFF.”

Drain leakage current with the switch “OFF.”

Channel leakage current with the switch “ON.”

Analog voltage on terminals D, S.

R_ONMatch

I_S(OFF)

I_D(OFF)

I_D, I_S(ON)

V_D(V_S)

C_S(OFF)

C_D(OFF)

“OFF” Switch Source Capacitance.

“OFF” Switch Drain Capacitance.

C_D, C_S(ON) “ON” Switch Capacitance.

t_ON

Delay between applying the digital control

input and the output switching on.

Delay between applying the digital control

input and the output switching off.

Break-Before-Make Delay when switches are

configured as a multiplexer.

A measure of unwanted signal which is coupled

through from one channel to another as a result

of parasitic capacitance.

t_OFF

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

t_OPEN

Crosstalk

NOTES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability. Only

one absolute maximum rating may be applied at any one time.

²Overvoltages at IN, S or D will be clamped by internal diodes. Current should be

limited to the maximum ratings given.

Off Isolation A measure of unwanted signal coupling through

an “OFF” switch.

Charge

A measure of the glitch impulse transferred from

the digital input to the analog output during

switching.

Injection

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although these devices feature proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ADG441/ADG442 PIN CONFIGURATION (DIP/SOIC)

ADG444 PIN CONFIGURATION (DIP/SOIC)

IN1

16 IN2

15 D2

14 S2

13 V_DD

12 V_L

11 S3

10 D3

IN1

16 IN2

15 D2

ADG441 14 S2

ADG442

ADG444

V_SS

GND

13 V

GND

TOP VIEW

(Not to Scale)

TOP VIEW

(Not to Scale)

12 NC

11 S3

10 D3

IN4

IN3

IN4

IN3

NC = NO CONNECT

–4–

REV. 0

ADG441/ADG442/ADG444

TRENCH ISOLATION

NMOS

PMOS

In the ADG441, ADG442 and ADG444, an insulating oxide

layer (trench) is placed between the NMOS and the PMOS

transistors of each CMOS switch. Parasitic junctions, which oc-

cur between the transistors in junction isolated switches, are

eliminated, the result being a completely latch-up proof switch.

LOCOS

In junction isolation, the N and P wells of the PMOS and

NMOS transistors form a diode that is reverse-biased under

normal operation. However, during overvoltage conditions, this

diode becomes forward biased. A silicon-controlled rectifier

(SCR) type circuit is formed by the two transistors causing a sig-

nificant amplification of the current which, in turn, leads to

latch up. With trench isolation, this diode is removed, the result

being a latch-up proof switch.

P-WELL

N-WELL

TRENCH

Trench isolation also leads to lower leakage currents. The

ADG441, ADG442 and ADG444 have a leakage current

of 0.5 nA as compared with a leakage current of several

nanoamperes in non-trench isolated switches. Leakage current is

an important parameter in sample-and-hold circuits, this current

being responsible for the discharge of the holding capacitor with

time causing droop. The ADG441/ADG442/ADG444’s low

leakage current, along with its fast switching speeds, make it

suitable for fast and accurate sample-and-hold circuits.

BURIED OXIDE LAYER

SUBSTRATE (BACK GATE)

Figure 1. Trench Isolation

Typical Performance Characteristics

170

150

130

110

100

= +5V

= 0V

= +25°C

= +5V

= –5V

= +25°C

= +12V

= 0V

= +12V

= –12V

= +10V

= 0V

= +10V

= –10V

= +15V

= 0V

= +15V

= –15V

–15

–10

–5

(V ) – Volts

) – Volts

Figure 2. R_ONas a Function of V_D(V_S): Dual Supply

Figure 3. R_ONas a Function of V_D(V_S): Single Supply

REV. 0

–5–

ADG441/ADG442/ADG444

100

120

100

V_DD= +12V

_SS= 0V

= +15V

= –15V

+125°C

+85°C

+25°C

+85°C

+25°C

–15

–10

–5

_D(V_S) – Volts

(V ) – Volts

Figure 4. R_ONas a Function of V_D(V_S) for Different

Temperatures

Figure 7. R_ONas a Function of V_D(V_S) for Different

Temperatures

0.010

0.02

V_DD= +12V

V_DD= +15V

V_SS= 0V

V_SS= –15V

I_D(OFF)

T_A= +25 C

I_D(ON)

T_A= +25 C

0.005

0.000

0.01

I_S(OFF)

I_D(ON)

0.00

I_S(OFF)

I_D(OFF)

–0.005

–0.010

–0.01

–0.02

–15

–10

–5

V_S, V_D– Volts

Figure 5. Leakage Currents as a Function of V_S(V_D)

Figure 8. Leakage Currents as a Function of V_S(V_D)

120

= +15V

= –15V

= 1nF

110

100

CROSSTALK

= +12V

= 0V

= +15V

= –15V

OFF ISOLATION

–10

–20

–15 –12

–9

–6

–3

10k

100k

10M

– Volts

FREQUENCY – Hz

Figure 6. Crosstalk and Off Isolation vs. Frequency

Figure 9. Charge Injection vs. Source Voltage

–6–

REV. 0

ADG441/ADG442/ADG444

120

100

160

140

120

100

= +8V

V_IN= +8V

t_ON

t_OFF

±10

±12

±14

±16

±18

±20

SUPPLY VOLTAGE – Volts

Figure 10. Switching Time vs. Bipolar Supply

Figure 11. Switching Time vs. Single Supply

Test Circuits

I_DS

(ON)

(OFF)

V_S

R_ON= V₁/I_DS

Test Circuit 2. Off Leakage

Test Circuit 1. On Resistance

Test Circuit 3. On Leakage

+15V

+5V

0.1µF

50%

ADG441/ADG444

OUT

1kΩ

35pF

ADG442

GND

90%

OUT

0.1µF

–15V

t_ON

t_OFF

Test Circuit 4. Switching Times

REV. 0

–7–

ADG441/ADG442/ADG444

+15V

+5V

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic DIP (N-16)

OUT

1nF

0.25 0.31

(6.35) (7.87)

PIN 1

GND

0.87 (22.1) MAX

0.035

–15V

0.18

(4.57)

MAX

(0.89)

0.125

(3.18)

MIN

0.011

(0.28)

0.18 (4.57)

0.3 (7.62)

SEATING

PLANE

0.018 (0.46)

0.033 (0.84)

0.1 (2.54)

BSC

OUT

∆V

OUT

Small Outline IC (R-16A)

= C × ∆V

L OUT

INJ

Test Circuit 5. Charge Injection

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

+15V

+5V

0.1µF

0.0196 (0.50)

0.0099 (0.25)

0.3937 (10.00)

0.3859 (9.80)

× 45°

OUT

0° – 8°

0.0688 (1.75)

0.0532 (1.35)

50Ω

0.0098 (0.25)

0.0040 (0.10)

0.0099 (0.25)

0.0075 (0.19)

0.0500 (1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0500 (1.27)

0.0160 (0.41)

GND

SEATING

PLANE

0.1µF

–15V

Cerdip (Q-16)

Test Circuit 6. Off Isolation

0.310 (7.87)

PIN 1

0.220 (5.59)

+15V

+5V

0.1µF

0.320 (8.13)

0.290 (7.37)

0.840 (21.34) MAX

0.060 (1.52)

0.015 (0.38)

0.200

(5.08)

MAX

50Ω

0.150

(3.81)

MIN

0.015 (0.381)

0.008 (0.204)

SEATING

PLANE

IN1

0.070 (1.78)

0.30 (0.76)

0.022 (0.558)

0.014 (0.356)

0.100 (2.54)

BSC

IN2

OUT

GND

50Ω

0.1µF

–15V

CHANNEL-TO-CHANNEL CROSSTALK = 20 × LOG V /V

OUT

Test Circuit 7. Channel-to-Channel Crosstalk

–8–

REV. 0

ADG441/ADG442/ADG444

FOR CATALOG

ORDERING GUIDE

Temperature Range

Model¹

Package Option²

ADG441BN

ADG441BR

ADG441TQ

–40°C to +85°C

–55°C to +125°C

N-16

R-16A

Q-16

ADG442BN

ADG442BR

ADG444BN

ADG444BR

–40°C to +85°C

N-16

R-16A

N-16

R-16A

NOTES

¹To order MIL-STD-883, Class B processed parts, add /883B to T grade part

numbers.

²N = Plastic DIP, R = 0.15" Small Outline IC (SOIC), Q = Cerdip. For outline

information see Package Information section.

REV. 0

–9–

ADG442BNZ [ADI]

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