ADG442BRZ_技术文档

LC²MOS Quad SPST Switches

ADG441/ADG442/ADG444

FUNCTIONAL BLOCK DIAGRAM

FEATURES

S1

44 V supply maximum ratings

V_SSto V_DDanalog signal range

Low on resistance (<70 Ω)

Low ∆R_ON(9 Ω max)

Low R_ONmatch (3 Ω max)

Low power dissipation

Fast switching times

IN1

IN2

IN3

IN4

IN1

IN2

IN3

IN4

D1

S2

D1

S2

ADG441

ADG444

D2

S3

D2

S3

ADG442

D3

S4

D3

S4

t_ON< 110 ns

t_OFF< 60 ns

D4

Low leakage currents (3 nA max)

Low charge injection (6 pC max)

Break-before-make switching action

Latch-up proof A grade

Plug-in upgrade for DG201A/ADG201A, DG202A/ADG202A,

DG211/ADG211A

Plug-in replacement for DG441/DG442/DG444

SWITCHES SHOWN FOR A LOGIC 1 INPUT

Figure 1.

differ in that the ADG444 requires a 5 V logic power supply

that is applied to the V_Lpin. The ADG441 and ADG442 do not

have a V_Lpin, the logic power supply is generated internally by

an on-chip voltage generator.

Each switch conducts equally well in both directions when ON

and has an input signal range that extends to the power

supplies. In the OFF condition, signal levels up to the supplies

are blocked. All switches exhibit break-before-make switching

action for use in multiplexer applications. Inherent in the

design is the low charge injection for minimum transients when

switching the digital inputs.

APPLICATIONS

Audio and video switching

Automatic test equipment

Precision data acquisition

Battery-powered systems

Sample-and-hold systems

Communication systems

PRODUCT HIGHLIGHTS

GENERAL DESCRIPTION

1. Extended signal range. The ADG441A/ADG442A/

ADG444A are fabricated on an enhanced LC²MOS, trench-

isolated process, giving an increased signal range that

extends to the supply rails.

The ADG441, ADG442, and ADG444 are monolithic CMOS

devices that comprise of four independently selectable switches.

They are designed on an enhanced LC²MOS process that

provides low power dissipation yet gives high switching speed

and low on resistance.

2. Low power dissipation.

3. Low R_ON

.

The on resistance profile is very flat over the full analog input

range, which ensures good linearity and low distortion when

switching audio signals. High switching speed also makes the

parts suitable for video signal switching. CMOS construction

ensures ultralow power dissipation, making the parts ideally

suited for portable and battery-powered instruments. The

ADG441, ADG442, and ADG444 contain four independent

SPST switches. Each switch of the ADG441 and ADG444 turns

on when a logic low is applied to the appropriate control input.

The ADG442 switches are turned on with logic high on the

appropriate control input. The ADG441 and ADG444 switches

4. Trench isolation guards against latch-up for A grade parts. A

dielectric trench separates the P and N channel transistors

thereby preventing latch-up even under severe overvoltage

conditions.

5. Break-before-make switching. This prevents channel

shorting when the switches are configured as a multiplexer.

6. Single-supply operation. For applications where the analog

signal is unipolar, the ADG441/ADG442/ADG444 can be

operated from a single-rail power supply. The parts are fully

specified with a single 12 V power supply.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADG441/ADG442/ADG444

TABLE OF CONTENTS

Specifications..................................................................................... 3

Dual Supply ................................................................................... 3

Single Supply ................................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Test Circuits........................................................................................9

Terminology .................................................................................... 11

Trench Isolation .............................................................................. 12

Outline Dimensions....................................................................... 13

Ordering Guide .......................................................................... 14

REVISION HISTORY

5/05—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Format .............................................................Universal

Deleted CERDIP Package and T Grade ..........................Universal

Changes to Features and Product Highlights ............................... 1

Changes to Test Conditions in Table 2 .......................................... 4

Changes to Figure 11........................................................................ 8

Changes to Trench Isolation Section ........................................... 12

Updated Outline Dimensions....................................................... 13

Changes to Ordering Guide .......................................................... 14

4/94–Revision 0: Initial Version

Rev. A | Page 2 of 16

ADG441/ADG442/ADG444

SPECIFICATIONS

DUAL SUPPLY¹

V_DD= +15 V 1ꢀ0, V_SS= −15 V 1ꢀ0, V_L= +5 V 1ꢀ0 ꢁADG444), GND = ꢀ V, unless otherwise noted.

Table 1.

B Version

Parameter

+25°C

−40°C to +85°C

Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

R_ON

V_SSto V_DD

V

40

70

Ω typ

Ω max

Ω typ

Ω max

Ω typ

Ω max

V_D= ±±.ꢀ Vꢁ I_S= −10 mA

V_DD= +13.ꢀ Vꢁ V_SS= −13.ꢀ V

−±.ꢀ V ≤ V_D≤ +±.ꢀ V

±ꢀ

4

9

1

3

∆R_ON

R_ONMatch

V_D= 0 Vꢁ I_S= −10 mA

LEAKAGE CURRENTS

V_DD= +16.ꢀ Vꢁ V_SS= −16.ꢀ V

Source OFF Leakage I_S(OFF)

±0.01

nA typ

V_D= ±1ꢀ.ꢀ Vꢁ V_S= ∓1ꢀ.ꢀ V

±0.ꢀ

±0.01

±3

nA max

nA typ

See Figure 1ꢀ

Drain OFF Leakage I_D(OFF)

V_D= ±1ꢀ.ꢀ Vꢁ V_S= ∓1ꢀ.ꢀ V

See Figure 1ꢀ

V_S= V_D= ±1ꢀ.ꢀ V

See Figure 16

±0.ꢀ

±0.0±

±0.ꢀ

±3

nA max

nA typ

nA max

Channel ON Leakage I_Dꢁ I_S(ON)

DIGITAL INPUTS

Input High Voltageꢁ V_INH

Input Low Voltageꢁ V_INL

Input Current

2.4

0.±

V min

V max

I_INLor I_INH

±0.00001

±0.ꢀ

µA typ

µA max

V_IN= V_INLor V_INH

DYNAMIC CHARACTERISTICS²

t_ON

±ꢀ

110

4ꢀ

60

30

1

ns typ

ns max

ns typ

ns max

ns typ

pC typ

pC max

dB typ

pF typ

R_L= 1 kΩꢁ C_L= 3ꢀ pF;

V_S= ±10 V; see Figure 17

R_L= 1 kΩꢁ C_L= 3ꢀ pF;

V_S= ±10 V; see Figure 17

R_L= 1 kΩꢁ C_L= 3ꢀ pF;

V_S= 0 Vꢁ R_S= 0 Ωꢁ C_L= 1 nF;

V_DD= +1ꢀ Vꢁ V_SS= –1ꢀ V; see Figure 1±

R_L= ꢀ0 Ωꢁ C_L= ꢀ pF; f = 1 MHz; see Figure 19

R_L= ꢀ0 Ωꢁ C_L= ꢀ pF; f= 1 MHz; see Figure 20

f = 1 MHz

170

±0

t_OFF

t_OPEN

Charge Injection

6

OFF Isolation

Channel-to-Channel Crosstalk

C_S(OFF)

C_D(OFF)

C_Dꢁ C_S(ON)

60

100

4

16

f = 1 MHz

POWER REQUIREMENTS

I_DD

V_DD= +16.ꢀ Vꢁ V_SS= −16.ꢀ V

Digital Inputs = 0 V or ꢀ V

ADG441/ADG442

ADG444

±0

µA max

µA typ

µA max

µA typ

µA max

µA typ

µA max

0.001

1

0.0001

1

0.001

1

2.ꢀ

I_SS

I_L(ADG444 Only)

V_L= ꢀ.ꢀ V

¹Temperature range is: B Version: −40°C to +±ꢀ°C.

²Guaranteed by designꢁ not subject to production test.

Rev. A | Page 3 of 16

ADG441/ADG442/ADG444

SINGLE SUPPLY¹

V_DD= +12 V 1ꢀ0, V_SS= ꢀ V, V_L= +5 V 1ꢀ0 ꢁADG444), GND = ꢀ V, unless otherwise noted.

Table 2.

B Version

Parameter

+25°C

−40°C to +85°C

Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

R_ON

0 to V_DD

V

70

110

Ω typ

Ω max

Ω typ

Ω max

Ω typ

Ω max

V_D= +3 Vꢁ +± Vꢁ I_S= −ꢀ mA

V_DD= 10.± V

3 V ≤ V_D≤ ± V

130

4

9

1

3

∆R_ON

R_ONMatch

V_D= +6 Vꢁ I_S= −ꢀ mA

LEAKAGE CURRENT

V_DD= 13.2 V

Source OFF Leakage I_S(OFF)

±0.01

±0.ꢀ

±0.01

±0.ꢀ

±0.0±

±0.ꢀ

nA typ

nA max

nA typ

nA max

nA typ

nA max

V_D= 12.2 V/1 Vꢁ V_S= 1 V/12.2 V

See Figure 1ꢀ

V_D= 12.2 V/1 Vꢁ V_S= 1 V/12.2 V

See Figure 1ꢀ

V_S= V_D= 12.2 V/1 V

Figure 16

±3

Drain OFF Leakage I_D(OFF)

Channel ON Leakage I_Dꢁ I_S(ON)

DIGITAL INPUTS

Input High Voltageꢁ V_INH

Input Low Voltageꢁ V_INL

Input Current

2.4

0.±

V min

V max

I_INLor I_INH

±0.00001

±0.ꢀ

µA typ

µA max

V_IN= V_INLor V_INH

DYNAMIC CHARACTERISTICS²

t_ON

10ꢀ

1ꢀ0

40

60

ꢀ0

2

ns typ

ns max

ns typ

ns max

ns typ

pC typ

pC max

dB typ

pF typ

R_L= 1 kΩꢁ C_L= 3ꢀ pF

V_S= ± V; Figure 17

R_L= 1 kΩꢁ C_L= 3ꢀ pF

V_S= ± V; Figure 17

R_L= 1 kΩꢁ C_L= 3ꢀ pF

V_S= 6 Vꢁ R_S= 0 Ωꢁ C_L= 1 nF

V_DD= 12 Vꢁ V_SS= 0 V; see Figure 1±

R_L= ꢀ0 Ωꢁ C_L= ꢀ pFꢁ f = 1 MHz; see Figure 19

R_L= ꢀ0 Ωꢁ C_L= ꢀ pFꢁ f = 1 MHz; see Figure 20

f = 1 MHz

220

100

t_OFF

t_OPEN

Charge Injection

6

OFF Isolation

Channel-to-Channel Crosstalk

C_S(OFF)

C_D(OFF)

C_Dꢁ C_S(ON)

60

100

7

10

16

f = 1 MHz

POWER REQUIREMENTS

I_DD

V_DD= 13.2 V

Digital Inputs = 0 V or ꢀ V

ADG441/ADG442

ADG444

±0

µA max

µA typ

µA max

µA typ

µA max

0.001

1

0.001

1

2.ꢀ

I_L(ADG444 Only)

V_L= ꢀ.ꢀ V

¹Temperature range is: B Version: −40°C to +±ꢀ°C.

²Guaranteed by designꢁ not subject to production test.

Rev. A | Page 4 of 16

ADG441/ADG442/ADG444

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C unless otherwise noted.

Table 3.

Parameter

Rating

V_DDto V_SS

44 V

V_DDto GND

V_SSto GND

V_Lto GND

−0.3 V to +2ꢀ V

+0.3 V to −2ꢀ V

−0.3 V to V_DD+ 0.3 V

Analogꢁ Digital Inputs

Continuous Currentꢁ S or D

Peak Currentꢁ S or D (Pulsed at 1 msꢁ 10% Duty Cycle Max)

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

Junction Temperature

Lead Temperatureꢁ Soldering (10 sec)

Plastic Packageꢁ Power Dissipation

θ_JAꢁ Thermal Impedance

Lead Temperatureꢁ Soldering (10 sec)

SOIC Packageꢁ Power Dissipation

θ_JAꢁ Thermal Impedance

Lead Temperatureꢁ Soldering

Vapor Phase (60 sec)

V_SS− 2 V to V_DD+ 2 V or 30 mAꢁ Whichever Occurs First

30 mA

100 mA

−40°C to +±ꢀ°C

−6ꢀ°C to +1ꢀ0°C

1ꢀ0°C

300°C

470 mW

177°C/W

260°C

600 mW

77°C/W

21ꢀ°C

220°C

Infrared (1ꢀ sec)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum

rating may be applied at any one time.

Table 4. Truth Table

ADG441/ADG444 IN

ADG442 IN

Switch Condition

0

1

0

ON

OFF

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitryꢁ permanent damage may occur on devices subjected to high energy

electrostatic discharges. Thereforeꢁ proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page ꢀ of 16

ADG441/ADG442/ADG444

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

IN1

D1

S1

1

2

3

4

5

6

7

8

16 IN2

15 D2

14 S2

IN1

D1

S1

1

2

3

4

5

6

7

8

16 IN2

15 D2

14 S2

ADG441

ADG442

TOP VIEW

(Not to Scale)

ADG444

V

13

V

13

12

V

SS

DD

SS

DD

L

TOP VIEW

(Not to Scale)

GND

12 NC

11 S3

10 D3

GND

S4

D4

S4

D4

11 S3

10 D3

IN4

9

IN3

IN4

9 IN3

NC = NO CONNECT

Figure 3. ADG444 (DIP/SOIC)

Figure 2. ADG441/ADG442 (DIP/SOIC)

Table 5. ADG441/ADG442 Pin Function Descriptions

Table 6. ADG444 Pin Function Descriptions

Pin No.

Mnemonic Description

Pin No.

Mnemonic Description

1ꢁ ±ꢁ 9ꢁ 16

IN1 to IN4 Logic Control Input.

1ꢁ ±ꢁ 9ꢁ 16

IN1 to IN4 Logic Control Input.

2ꢁ 7ꢁ 10ꢁ 1ꢀ D1 to D4

Drain Terminal. May be

an input or output.

2ꢁ 7ꢁ 10ꢁ 1ꢀ D1 to D4

Drain Terminal. May be

an input or output.

3ꢁ 6ꢁ 11ꢁ 14 S1 to S4

Source Terminal. May be

an input or output.

3ꢁ 6ꢁ 11ꢁ 14 S1 to S4

Source Terminal. May be

an input or output.

4

V_SS

Most Negative Power Supply

Potential in Dual Supplies. In

single-supply applicationsꢁ

it may be connected to ground.

4

V_SS

Most Negative Power Supply

Potential in Dual Supplies. In

single-supply applicationsꢁ

it may be connected to ground.

ꢀ

12

13

GND

NC

V_DD

Ground (0 V) Reference.

No Connect.

Most Positive Power Supply Potential.

ꢀ

12

13

GND

V_L

V_DD

Ground (0 V) Reference.

Logic Power Supply (ꢀ V).

Most Positive Power Supply Potential.

Rev. A | Page 6 of 16

ADG441/ADG442/ADG444

TYPICAL PERFORMANCE CHARACTERISTICS

100

0.02

0.01

0

V

= +5V

= –5V

V

= +15V

= –15V

= 25°C

T

= 25°C

DD

SS

A

SS

T

A

I

(OFF)

D

80

60

40

20

V

= +12V

= –12V

DD

SS

I (ON)

D

V

= +10V

= –10V

DD

I

(OFF)

SS

S

–0.01

–0.02

V

= +15V

= –15V

DD

SS

–15

–10

–5

0

5

10

15

–15

–10

–5

0

5

10

15

V

(V ) (V)

V (V ) (V)

S D

D

S

Figure 4. R_ONas a Function of V_D(V_S): Dual Supply

Figure 7. Leakage Currents as a Function of V_S(V_D)

170

150

130

110

90

120

V

= 5V

= 0V

V

= +15V

= –15V

T

= 25°C

DD

SS

DD

A

SS

110

100

90

CROSSTALK

V

= 10V

= 0V

V

= 12V

= 0V

DD

V

DD

SS

80

70

OFF ISOLATION

70

50

V

= 15V

= 0V

60

DD

SS

30

50

1k

10

10k

100k

1M

10M

0

3

6

9

12

15

V

(V ) (V)

FREQUENCY (Hz)

D

S

Figure 5. R_ONas a Function of V_D(V_S): Single Supply

Figure 8. Crosstalk and Off Isolation vs. Frequency

100

80

60

40

20

120

100

80

V

= +15V

= –15V

DD

V

= 12V

= 0V

DD

SS

125°C

85°C

25°C

60

85°C

40

25°C

20

–15

–10

–5

0

5

10

15

0

2

4

6

8

10

12

V

(V ) (V)

S

V

(V ) (V)

S

D

Figure 6. R_ONas a Function of V_D(V_S) for Different Temperatures

Figure 9. R_ONas a Function of V_D(V_S) for Different Temperatures

Rev. A | Page 7 of 16

ADG441/ADG442/ADG444

0.010

120

100

80

V

= 12V

= 0V

= 25°C

DD

SS

V

= 8V

IN

T

A

0.005

I

(ON)

D

t_ON

I

(OFF)

S

0

I

(OFF)

D

–0.005

–0.010

60

t_OFF

40

±10

0

2

4

6

8

10

12

±12

±14

±16

±18

±20

V , V (V)

S

D

SUPPLY VOLTAGE (V)

Figure 10. Leakage Currents as a Function of V_S(V_D)

Figure 12. Switching Time vs. Bipolar Supply

160

140

120

100

80

40

30

V

= 8V

T

= 25°C

IN

A

20

t_ON

10

V

= +15V

= –15V

DD

SS

0

V

= 12V

= 0V

DD

SS

–10

–20

–30

–40

60

t_OFF

40

20

8

10

12

14

16

18

20

–15 –12

–9

–6

–3

0

3

6

9

12

15

SUPPLY VOLTAGE (V)

V

(V)

S

Figure 13. Switching Time vs. Single Supply

Figure 11. Charge Injection vs. Source Voltage

Rev. A | Page ± of 16

ADG441/ADG442/ADG444

TEST CIRCUITS

I

DS

V1

I

(OFF)

A

I

(OFF)

A

I

(ON)

A

S

D

S

D

S

D

S

D

V

D

V

D

S

V

S

R

= V /I

1 DS

ON

Figure 14. On Resistance

Figure 15. Off Leakage

Figure 16. On Leakage

+15V +5V

3V

0.1µF

V

50%

IN

ADG441/ADG444

V

L

DD

S

D

V

OUT

3V

R

1kΩ

C

L

35pF

L

V

S

V

50%

IN

ADG442

IN

90%

GND

V

SS

V

OUT

0.1µF

–15V

t_ON

t_OFF

Figure 17. Switching Times

+15V +5V

3V

V

L

DD

R

S

D

V

OUT

IN

C

L

V

S

1nF

IN

V

∆V

OUT

GND

V

SS

Q

= C × ∆V

L OUT

INJ

–15V

Figure 18. Charge Injection

Rev. A | Page 9 of 16

ADG441/ADG442/ADG444

+15V +5V

0.1µF

V

SS

V

SS

DD

50Ω

S

D

S

D

V

OUT

R

L

50Ω

V

IN1

V

S

V

S

V

IN2

IN

V

NC

OUT

R

50Ω

L

GND

V

GND

V

SS

V

IN

0.1µF

–15V

0.1µF

–15V

CHANNEL-TO-CHANNEL CROSSTALK = 20× LOG |V /V

|

S

OUT

Figure 19. Off Isolation

Figure 20. Channel-to-Channel Crosstalk

Rev. A | Page 10 of 16

ADG441/ADG442/ADG444

TERMINOLOGY

R_ON

t_ON

Ohmic resistance between D and S.

Delay between applying the digital control input and the output

switching on.

R_ONMatch

Difference between the R_ONof any two channels.

t_OFF

Delay between applying the digital control input and the output

switching off.

I_S(OFF)

Source leakage current with the switch OFF.

t_OPEN

I_D(OFF)

Break-before-make delay when switches are configured as a

multiplexer.

Drain leakage current with the switch OFF.

I_D, I_S(ON)

Crosstalk

Channel leakage current with the switch ON.

A measure of unwanted signal which is coupled through from

one channel to another as a result of parasitic capacitance.

V_D(V_S)

Analog voltage on Terminals D, S.

Off Isolation

A measure of unwanted signal coupling through an OFF switch.

C_S(OFF)

OFF switch source capacitance.

Charge Injection

A measure of the glitch impulse transferred from the digital

input to the analog output during switching.

C_D(OFF)

OFF switch drain capacitance.

C_D, C_S(ON)

ON switch capacitance.

Rev. A | Page 11 of 16

ADG441/ADG442/ADG444

TRENCH ISOLATION

NMOS

PMOS

In the ADG441A, ADG442A, and ADG444A, an insulating

oxide layer ꢁtrench) is placed between the NMOS and the

PMOS transistors of each CMOS switch. Parasitic junctions,

which occur between the transistors in junction isolated

switches, are eliminated, and the result is a completely latch-up

proof switch.

LOCO

In junction isolation, the N and P wells of the PMOS and

NMOS transistors form a diode that is reverse-biased under

normal operation. However, during overvoltage conditions, this

diode becomes forward-biased. A silicon-controlled rectifier

ꢁSCR) type circuit is formed by the two transistors causing a

significant amplification of the current which, in turn, leads to

latch-up. With trench isolation, this diode is removed, and the

result is a latch-up proof switch.

P-WELL

N-WELL

TRENCH

BURIED OXIDE LAYER

SUBSTRATE (BACK GATE)

Figure 21. Trench Isolation

Rev. A | Page 12 of 16

ADG441/ADG442/ADG444

OUTLINE DIMENSIONS

0.785 (19.94)

0.765 (19.43)

0.745 (18.92)

0.295 (7.49)

0.285 (7.24)

0.275 (6.99)

16

1

9

8

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.100 (2.54)

BSC

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

MIN

0.180 (4.57)

MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

SEATING

PLANE

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

COMPLIANT TO JEDEC STANDARDS MO-095AC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 22. 16-Lead Plastic Dual In-Line Package [PDIP]

(N-16)

Dimensions shown in inches and (millimeters)

10.00 (0.3937)

9.80 (0.3858)

16

1

9

8

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

1.75 (0.0689)

1.35 (0.0531)

1.27 (0.0500)

BSC

0.50 (0.0197)

0.25 (0.0098)

× 45°

0.25 (0.0098)

0.10 (0.0039)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

SEATING

PLANE

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.25 (0.0098)

0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012AC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 23. 16-Lead Standard Small Outline Package [SOIC]

(R-16)

Dimensions shown in millimeters and (inches)

Rev. A | Page 13 of 16

ADG441/ADG442/ADG444

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADG441BN

ADG441BR

ADG441BR-REEL

ADG441BRZ¹

−40°C to +±ꢀ°C

16-Lead Plastic Dual In-Line Package (PDIP)

16-Lead Standard Small Outline Package (SOIC)

DIE

N-16

R-16

ADG441BRZ-REEL¹

ADG441BCHIPS

ADG441ABCHIPS²

ADG441ABN²

DIE

−40°C to +±ꢀ°C

16-Lead Plastic Dual In-Line Package (PDIP)

16-Lead Standard Small Outline Package (SOIC)

16-Lead Plastic Dual In-Line Package (PDIP)

16-Lead Standard Small Outline Package (SOIC)

16-Lead Plastic Dual In-Line Package (PDIP)

16-Lead Standard Small Outline Package (SOIC)

16-Lead Plastic Dual In-Line Package (PDIP)

16-Lead Standard Small Outline Package (SOIC)

16-Lead Plastic Dual In-Line Package (PDIP)

16-Lead Standard Small Outline Package (SOIC)

N-16

R-16

N-16

R-16

N-16

R-16

N-16

R-16

N-16

R-16

ADG441ABR²

ADG441ABR-REEL²

ADG441ABRZ-REEL^{1ꢁ 2}

ADG442BN

ADG442BR

ADG442BR-REEL

ADG442BRZ¹

ADG442BRZ-REEL¹

ADG442ABN²

ADG442ABR²

ADG442ABR-REEL²

ADG442ABRZ^{1ꢁ 2}

ADG442ABRZ-REEL^{1ꢁ 2}

ADG444BN

ADG444BR

ADG444BR-REEL

ADG444BRZ¹

ADG444BRZ-REEL¹

ADG444ABN²

ADG444ABR²

ADG444ABR-REEL²

ADG444ABRZ^{1ꢁ 2}

ADG444ABRZ-REEL^{1ꢁ 2}

¹Z = Pb-free part.

²A = Trench isolated.

Rev. A | Page 14 of 16

ADG441/ADG442/ADG444

NOTES

Rev. A | Page 1ꢀ of 16

ADG441/ADG442/ADG444

NOTES

registered trademarks are the property of their respective owners.

C00396–0–5/05(A)

Rev. A | Page 16 of 16


型号：	ADG442BRZ
厂家：	ADI
描述：	LC2MOS Quad SPST Switches LC2MOS QUAD SPST开关复用器开关复用器或开关信号电路光电二极管 PC
文件：	总16页 (文件大小：394K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADG442BRZ [ADI]

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