ADG442_15 [ADI]
LC MOS Quad SPST Switches;
| 型号： | ADG442_15 |
| 厂家： | 
ADI |
| 描述： | LC MOS Quad SPST Switches |
| 文件： | 总16页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC2MOS Quad SPST Switches
Data Sheet
ADG441/ADG442/ADG444
FEATURES
FUNCTIONAL BLOCK DIAGRAM
S1
S1
44 V supply maximum ratings
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
V
SS to VDD analog signal range
D1
S2
D1
S2
Low on resistance (<70 Ω)
Low ΔRON (9 Ω max)
Low RON match (3 Ω max)
Low power dissipation
Fast switching times
ADG441
ADG444
D2
S3
D2
S3
ADG442
D3
S4
D3
S4
t
t
ON < 110 ns
OFF < 60 ns
D4
D4
Low leakage currents (3 nA max)
Low charge injection (6 pC max)
Break-before-make switching action
Latch-up proof A grade
Plug-in upgrade for DG201A/ADG201A, DG202A/ADG202A,
DG211/ADG211A
Plug-in replacement for DG441/DG442/DG444
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
Each switch conducts equally well in both directions when ON
and has an input signal range that extends to the power
supplies. In the OFF condition, signal levels up to the supplies
are blocked. All switches exhibit break-before-make switching
action for use in multiplexer applications. Inherent in the
design is the low charge injection for minimum transients when
switching the digital inputs.
APPLICATIONS
Audio and video switching
Automatic test equipment
Precision data acquisition
Battery-powered systems
Sample-and-hold systems
Communication systems
PRODUCT HIGHLIGHTS
1. Extended signal range. The ADG441A/ADG442A/
ADG444A are fabricated on an enhanced LC2MOS,
trench-isolated process, giving an increased signal range
that extends to the supply rails.
GENERAL DESCRIPTION
2. Low power dissipation.
The ADG441, ADG442, and ADG444 are monolithic CMOS
devices that comprise of four independently selectable switches.
They are designed on an enhanced LC2MOS process that
provides low power dissipation yet gives high switching speed
and low on resistance.
3. Low RON
.
4. Trench isolation guards against latch-up for A grade parts.
A dielectric trench separates the P and N channel
transistors thereby preventing latch-up even under severe
overvoltage conditions.
5. Break-before-make switching. This prevents channel
shorting when the switches are configured as a multiplexer.
6. Single-supply operation. For applications where the analog
signal is unipolar, the ADG441/ADG442/ADG444 can be
operated from a single-rail power supply. The parts are
fully specified with a single 12 V power supply.
The on resistance profile is very flat over the full analog input
range, which ensures good linearity and low distortion when
switching audio signals. High switching speed also makes the
parts suitable for video signal switching. CMOS construction
ensures ultralow power dissipation, making the parts ideally
suited for portable and battery-powered instruments. The
ADG441, ADG442, and ADG444 contain four independent
SPST switches. Each switch of the ADG441 and ADG444 turns
on when a logic low is applied to the appropriate control input.
The ADG442 switches are turned on with logic high on the
appropriate control input. The ADG441 and ADG444 switches
differ in that the ADG444 requires a 5 V logic power supply
that is applied to the VL pin. The ADG441 and ADG442 do not
have a VL pin, the logic power supply is generated internally by
an on-chip voltage generator.
Rev. B
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Tel: 781.329.4700 ©1994–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADG441/ADG442/ADG444
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Test Circuits........................................................................................9
Terminology.................................................................................... 11
Trench Isolation.............................................................................. 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
REVISION HISTORY
5/14—Rev. A to Rev. B
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 14
5/05—Rev. 0 to Rev. A
Changes to Format .............................................................Universal
Deleted CERDIP Package and T Grade ..........................Universal
Changes to Features and Product Highlights ............................... 1
Changes to Test Conditions in Table 2 .......................................... 4
Changes to Figure 11........................................................................ 8
Changes to Trench Isolation Section ........................................... 12
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 14
4/94–Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADG441/ADG442/ADG444
SPECIFICATIONS
DUAL SUPPLY1
VDD = +15 V 10%, VSS = −15 V 10%, VL = +5 V 10% (ADG444), GND = 0 V, unless otherwise noted.
Table 1.
B Version
Parameter
+25°C
−40°C to +85°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
VSS to VDD
V
40
70
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VD = 8.5 V, IS = −10 mA
VDD = +13.5 V, VSS = −13.5 V
−8.5 V ≤ VD ≤ +8.5 V
85
4
9
1
3
∆RON
RON Match
VD = 0 V, IS = −10 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source OFF Leakage IS (OFF)
0.01
nA typ
VD = 15.5 V, VS = ∓15.5 V
0.5
0.01
3
nA max
nA typ
See Figure 15
Drain OFF Leakage ID (OFF)
VD = 15.5 V, VS = ∓15.5 V
See Figure 15
VS = VD = 15.5 V
See Figure 16
0.5
0.08
0.5
3
3
nA max
nA typ
nA max
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.00001
0.5
µA typ
µA max
VIN = VINL or VINH
DYNAMIC CHARACTERISTICS2
tON
85
110
45
60
30
1
ns typ
ns max
ns typ
ns max
ns typ
pC typ
pC max
dB typ
dB typ
pF typ
pF typ
pF typ
RL = 1 kΩ, CL = 35 pF;
VS = 10 V; see Figure 17
RL = 1 kΩ, CL = 35 pF;
VS = 10 V; see Figure 17
RL = 1 kΩ, CL = 35 pF;
VS = 0 V, RS = 0 Ω, CL = 1 nF;
VDD = +15 V, VSS = –15 V; see Figure 18
RL = 50 Ω, CL = 5 pF; f = 1 MHz; see Figure 19
RL = 50 Ω, CL = 5 pF; f= 1 MHz; see Figure 20
f = 1 MHz
170
80
tOFF
tOPEN
Charge Injection
6
OFF Isolation
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
CD, CS (ON)
60
100
4
4
16
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital Inputs = 0 V or 5 V
ADG441/ADG442
ADG444
80
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
0.001
1
0.0001
1
0.001
1
2.5
2.5
2.5
ISS
IL (ADG444 Only)
VL = 5.5 V
1 Temperature range is: B Version: −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 3 of 16
ADG441/ADG442/ADG444
Data Sheet
SINGLE SUPPLY1
VDD = +12 V 10%, VSS = 0 V, V L = +5 V 10% (ADG444), GND = 0 V, unless otherwise noted.
Table 2.
B Version
Parameter
+25°C
−40°C to +85°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
RON
0 to VDD
V
70
110
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VD = +3 V, +8 V, IS = −5 mA
VDD = 10.8 V
3 V ≤ VD ≤ 8 V
130
4
9
1
3
∆RON
RON Match
VD = +6 V, IS = −5 mA
LEAKAGE CURRENT
VDD = 13.2 V
Source OFF Leakage IS (OFF)
0.01
0.5
0.01
0.5
0.08
0.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 12.2 V/1 V, VS = 1 V/12.2 V
See Figure 15
VD = 12.2 V/1 V, VS = 1 V/12.2 V
See Figure 15
VS = VD = 12.2 V/1 V
Figure 16
3
3
3
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.00001
0.5
µA typ
µA max
VIN = VINL or VINH
DYNAMIC CHARACTERISTICS2
tON
105
150
40
60
50
2
ns typ
ns max
ns typ
ns max
ns typ
pC typ
pC max
dB typ
dB typ
pF typ
pF typ
pF typ
RL = 1 kΩ, CL = 35 pF
VS = 8 V; Figure 17
RL = 1 kΩ, CL = 35 pF
VS = 8 V; Figure 17
RL = 1 kΩ, CL = 35 pF
VS = 6 V, RS = 0 Ω, CL = 1 nF
VDD = 12 V, VSS = 0 V; see Figure 18
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
220
100
tOFF
tOPEN
Charge Injection
6
OFF Isolation
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
CD, CS (ON)
60
100
7
10
16
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 13.2 V
Digital Inputs = 0 V or 5 V
ADG441/ADG442
ADG444
80
µA max
µA typ
µA max
µA typ
µA max
0.001
1
0.001
1
2.5
2.5
IL (ADG444 Only)
VL = 5.5 V
1 Temperature range is: B Version: −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 16
Data Sheet
ADG441/ADG442/ADG444
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to VSS
44 V
VDD to GND
VSS to GND
VL to GND
−0.3 V to +25 V
+0.3 V to −25 V
−0.3 V to VDD + 0.3 V
Table 4. Truth Table
ADG441/ADG444 IN
0
1
Analog, Digital Inputs
VSS − 2 V to VDD + 2 V
or 30 mA, Whichever
Occurs First
30 mA
100 mA
ADG442 IN
Switch Condition
1
0
ON
OFF
Continuous Current, S or D
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
Lead Temperature, Soldering (10 sec)
Plastic Package, Power Dissipation
θJA, Thermal Impedance
Lead Temperature, Soldering (10 sec)
SOIC Package, Power Dissipation
θJA, Thermal Impedance
300°C
470 mW
177°C/W
260°C
600 mW
77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
Rev. B | Page 5 of 16
ADG441/ADG442/ADG444
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN1
D1
S1
1
2
3
4
5
6
7
8
16 IN2
15 D2
14 S2
ADG441
ADG442
TOP VIEW
(Not to Scale)
V
13 V
DD
SS
GND
12 NC
11 S3
10 D3
S4
D4
IN4
9 IN3
NC = NO CONNECT
Figure 2. ADG441/ADG442 (DIP/SOIC)
Table 5. ADG441/ADG442 Pin Function Descriptions
Pin No.
1, 8, 9, 16
2, 7, 10, 15
3, 6, 11, 14
4
Mnemonic
IN1 to IN4
D1 to D4
S1 to S4
VSS
Description
Logic Control Input.
Drain Terminal. May be an input or output.
Source Terminal. May be an input or output.
Most Negative Power Supply Potential in Dual Supplies. In single-supply applications, it may be connected
to ground.
5
12
13
GND
NC
VDD
Ground (0 V) Reference.
No Connect.
Most Positive Power Supply Potential.
IN1
D1
S1
1
2
3
4
5
6
7
8
16 IN2
15 D2
14 S2
ADG444
V
13
12
V
V
SS
DD
TOP VIEW
(Not to Scale)
GND
L
S4
D4
11 S3
10 D3
IN4
9 IN3
Figure 3. ADG444 (DIP/SOIC)
Table 6. ADG444 Pin Function Descriptions
Pin No.
1, 8, 9, 16
2, 7, 10, 15
3, 6, 11, 14
4
Mnemonic
IN1 to IN4
D1 to D4
S1 to S4
VSS
Description
Logic Control Input.
Drain Terminal. May be an input or output.
Source Terminal. May be an input or output.
Most Negative Power Supply Potential in Dual Supplies. In single-supply applications, it may be connected
to ground.
5
12
13
GND
VL
VDD
Ground (0 V) Reference.
Logic Power Supply (5 V).
Most Positive Power Supply Potential.
Rev. B | Page 6 of 16
Data Sheet
ADG441/ADG442/ADG444
TYPICAL PERFORMANCE CHARACTERISTICS
100
0.02
0.01
0
V
V
= +5V
= –5V
V
V
= +15V
= –15V
= 25°C
T
= 25°C
DD
DD
A
SS
SS
T
A
I
(OFF)
D
80
60
40
20
V
V
= +12V
= –12V
DD
SS
I (ON)
D
V
V
= +10V
= –10V
DD
I
(OFF)
SS
S
–0.01
V
V
= +15V
= –15V
DD
SS
–0.02
–15
–10
–5
0
5
10
15
–15
–10
–5
0
5
10
15
V
(V ) (V)
V (V ) (V)
S D
D
S
Figure 4. RON as a Function of VD (VS): Dual Supply
Figure 7. Leakage Currents as a Function of VS (VD)
170
150
130
110
90
120
V
V
= 5V
= 0V
V
V
= +15V
= –15V
T
= 25°C
DD
SS
DD
A
SS
110
100
90
CROSSTALK
V
= 10V
= 0V
V
= 12V
= 0V
DD
V
DD
SS
V
SS
80
70
OFF ISOLATION
70
50
V
V
= 15V
= 0V
60
DD
SS
30
10
50
1k
0
3
6
9
12
15
10k
100k
1M
10M
V
(V ) (V)
FREQUENCY (Hz)
D
S
Figure 5. RON as a Function of VD (VS): Single Supply
Figure 8. Crosstalk and Off Isolation vs. Frequency
100
80
60
40
20
120
100
80
V
V
= +15V
= –15V
V
V
= 12V
= 0V
DD
DD
SS
SS
125°C
125°C
85°C
25°C
60
85°C
40
25°C
20
–15
–10
–5
0
5
10
15
0
2
4
6
8
10
12
V
(V ) (V)
V (V ) (V)
D S
D
S
Figure 6. RON as a Function of VD (VS) for Different Temperatures
Figure 9. RON as a Function of VD (VS) for Different Temperatures
Rev. B | Page 7 of 16
ADG441/ADG442/ADG444
Data Sheet
0.010
120
100
80
V
V
= 12V
= 0V
= 25°C
DD
SS
V
= 8V
IN
T
A
0.005
I
(ON)
D
tON
I
(OFF)
S
0
I
(OFF)
D
–0.005
–0.010
60
tOFF
40
±10
0
2
4
6
8
10
12
±12
±14
±16
±18
±20
V , V (V)
S
D
SUPPLY VOLTAGE (V)
Figure 10. Leakage Currents as a Function of VS (VD)
Figure 12. Switching Time vs. Bipolar Supply
40
30
160
140
120
100
80
T
= 25°C
V
= 8V
IN
A
20
tON
10
V
V
= +15V
= –15V
DD
SS
0
V
V
= 12V
= 0V
DD
SS
–10
–20
–30
–40
60
tOFF
40
20
–15 –12
–9
–6
–3
0
3
6
9
12
15
8
10
12
14
16
18
20
V
(V)
SUPPLY VOLTAGE (V)
S
Figure 11. Charge Injection vs. Source Voltage
Figure 13. Switching Time vs. Single Supply
Rev. B | Page 8 of 16
Data Sheet
ADG441/ADG442/ADG444
TEST CIRCUITS
I
DS
I
(OFF)
A
I
(OFF)
A
I
(ON)
A
S
D
D
V1
S
D
S
D
V
V
D
V
V
D
S
S
S
D
V
S
R
= V /I
1 DS
ON
Figure 14. On Resistance
Figure 15. Off Leakage
Figure 16. On Leakage
+15V +5V
3V
0.1F
0.1F
V
50%
50%
50%
IN
ADG441/ADG444
V
V
L
DD
S
D
V
OUT
3V
R
1k
C
35pF
L
L
V
S
V
50%
IN
ADG442
IN
90%
90%
GND
V
SS
V
OUT
0.1F
–15V
tON
tOFF
Figure 17. Switching Times
+15V +5V
3V
V
V
L
DD
R
S
S
D
V
V
OUT
IN
C
L
V
S
1nF
IN
V
V
OUT
OUT
GND
V
SS
Q
= C × V
L OUT
INJ
–15V
Figure 18. Charge Injection
Rev. B | Page 9 of 16
ADG441/ADG442/ADG444
Data Sheet
+15V
+5V
+15V
+5V
0.1F
0.1F
0.1F
0.1F
V
V
V
V
DD
SS
DD
SS
50
S
D
S
D
V
OUT
R
L
50
V
IN1
V
S
V
S
V
IN2
IN
V
NC
OUT
R
50
L
GND
V
GND
V
SS
SS
V
IN
0.1F
–15V
0.1F
–15V
CHANNEL-TO-CHANNEL CROSSTALK = 20× LOG |V /V
|
OUT
S
Figure 19. Off Isolation
Figure 20. Channel-to-Channel Crosstalk
Rev. B | Page 10 of 16
Data Sheet
ADG441/ADG442/ADG444
TERMINOLOGY
tON
RON
Delay between applying the digital control input and the output
switching on.
Ohmic resistance between D and S.
RON Match
tOFF
Difference between the RON of any two channels.
Delay between applying the digital control input and the output
switching off.
IS (OFF)
Source leakage current with the switch OFF.
tOPEN
ID (OFF)
Break-before-make delay when switches are configured as a
multiplexer.
Drain leakage current with the switch OFF.
ID, IS (ON)
Crosstalk
Channel leakage current with the switch ON.
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
VD (VS)
Analog voltage on Terminals D, S.
Off Isolation
CS (OFF)
A measure of unwanted signal coupling through an OFF switch.
OFF switch source capacitance.
Charge Injection
CD (OFF)
OFF switch drain capacitance.
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD, CS (ON)
ON switch capacitance.
Rev. B | Page 11 of 16
ADG441/ADG442/ADG444
Data Sheet
TRENCH ISOLATION
NMOS
PMOS
In the ADG441A, ADG442A, and ADG444A, an insulating
oxide layer (trench) is placed between the NMOS and the
PMOS transistors of each CMOS switch. Parasitic junctions,
which occur between the transistors in junction isolated
switches, are eliminated, and the result is a completely latch-up
proof switch.
LOCO
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward-biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER
SUBSTRATE (BACK GATE)
Figure 21. Trench Isolation
Rev. B | Page 12 of 16
Data Sheet
ADG441/ADG442/ADG444
OUTLINE DIMENSIONS
0.775
0.755
0.735
9
8
16
1
0.280
0.250
0.240
PIN 1
INDICATOR
TOP VIEW
SIDE VIEW
0.325
0.310
0.300
0.100
BSC
0.195
0.130
0.115
0.210
MAX
0.015
0.015
GAUGE
PLANE
0.150
0.130
0.115
MIN
END VIEW
0.012
SEATING
PLANE
0.021
0.010
0.008
0.022
0.430
MAX
0.018
0.015
0.016
0.011
0.070
0.060
0.055
0.045
0.039
0.030
COMPLIANT TO JEDEC STANDARDS MS-001-BB
Figure 22. 16-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-16)
Dimensions shown in inches
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 23. 16-Lead Standard Small Outline Package [SOIC_N]
(R-16)
Dimensions shown in millimeters and (inches)
Rev. B | Page 13 of 16
ADG441/ADG442/ADG444
Data Sheet
ORDERING GUIDE
Model1, 2
Temperature Range
Package Description
Package Option
ADG441BNZ
ADG441BR
ADG441BR-REEL
ADG441BRZ
ADG441BRZ-REEL
ADG441ABCHIPS
ADG441ABR-REEL
ADG441ABRZ-REEL
ADG442BNZ
ADG442BRZ
ADG442BRZ-REEL
ADG444BNZ
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
DIE
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Plastic Dual In-Line Package [PDIP]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
N-16
R-16
R-16
R-16
R-16
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
R-16
R-16
N-16
R-16
R-16
N-16
R-16
R-16
R-16
R-16
ADG444BR
ADG444BR-REEL
ADG444BRZ
ADG444BRZ-REEL
1 Z = RoHS Compliant Part.
2 A = Trench isolated.
Rev. B | Page 14 of 16
Data Sheet
NOTES
ADG441/ADG442/ADG444
Rev. B | Page 15 of 16
ADG441/ADG442/ADG444
NOTES
Data Sheet
©1994–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00396-0-5/14(B)
Rev. B | Page 16 of 16
相关型号：
ADG444ABN
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDIP16, PLASTIC, MO-095AC, DIP-16, Multiplexer or Switch
ADI
ADG444ABR-REEL
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16, MS-012AC, SOIC-16, Multiplexer or Switch
ADI
ADG444ABRZ-REEL
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO16, LEAD FREE, MS-012AC, SOIC-16, Multiplexer or Switch
ADI
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