ADG465 [ADI]
Single Channel Protector in an SOT-23 Package; 单通道保护器采用SOT -23封装
| 型号： | ADG465 |
| 厂家： | 
ADI |
| 描述： | Single Channel Protector in an SOT-23 Package |
| 文件： | 总8页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single Channel Protector
in an SOT-23 Package
a
ADG465
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fault and Overvoltage Protection up to ؎40 V
Signal Paths Open Circuit with Power Off
Signal Path Resistance of RON with Power On
44 V Supply Maximum Ratings
V
V
SS
DD
V
V
D1
S1
V
VIN
OUT
V
Low On Resistance 80 ⍀ Typ
ADG465
IN
V
OUT
1 nA Max Path Current Leakage @ +25؇C
Low Power Dissipation 0.8 W Typ
Latchup-Proof Construction
V
DD
V
DD
APPLICATIONS
ATE Equipment
OUTPUT CLAMPED
@ V – 1.5V
DD
Sensitive Measurement Equipment
Hot-Insertion Rack Systems
ADC Input Channel Protection
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG465 is a single channel protector in an SOT-23 pack-
age. The channel protector is placed in series with the signal
path, and will protect sensitive components from voltage tran-
sience in the signal path whether or not the power supplies are
present. Because the channel protection works regardless of the
presence of the supplies, the channel protectors are ideal for use
in applications where correct power sequencing cannot always
be guaranteed to protect analog inputs (e.g., hot-insertion rack
systems). This is discussed further, and some example circuits
are given, in the Applications section of this data sheet.
1. Fault Protection.
The ADG465 can withstand continuous voltage inputs from
–40 V to +40 V. When a fault occurs due to the power sup-
plies being turned off, or due to an overvoltage being applied
to the ADG465, the output is clamped. When power is turned
off, current is limited to the nanoampere level.
2. Low Power Dissipation.
3. Low RON 80 Ω typ.
4. Trench Isolation Latchup-Proof Construction.
A dielectric trench separates the p- and n-channel MOSFETs
thereby preventing latchup.
A channel protector consists of an n-channel MOSFET, a
p-channel MOSFET and an n-channel MOSFET, connected in
series. The channel protector behaves like a series resistor dur-
ing normal operation, i.e., (VSS + 2 V) < VIN < (VDD – 1.5 V).
When a channel’s analog input exceeds the power supplies
(including VDD and VSS = 0 V), one of the MOSFETs will
switch off, clamping the output to either VSS + 2 V or VDD – 1.5 V.
Circuitry and signal source protection is provided in the event of
an overvoltage or power loss. The channel protectors can with-
stand overvoltage inputs from –40 V to +40 V. See the Circuit
Information section of this data sheet.
The ADG465 can operate from both bipolar and unipolar
supplies. The channels are normally on when power is con-
nected, and open circuit when power is disconnected. With
power supplies of ±15 V, the on-resistance of the ADG465 is
80 Ω typ, with a leakage current of ±1 nA max. When power
is disconnected, the input leakage current is approximately
±5 nA typ.
The ADG465 is available in a 6-lead plastic surface mount
SOT-23 package, and an 8-lead µSOIC package.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
ADG465–SPECIFICATIONS
Dual Supply1 (VDD = +15 V, VSS = –15 V, GND = 0 V, unless otherwise noted)
Parameter
+25؇C
B
Units
Test Conditions/Comments
FAULT PROTECTED CHANNEL
Fault-Free Analog Signal Range2
VSS + 1.2
VDD – 0.8
V min
V max
Ω typ
Ω max
Ω max
Output Open Circuit
–10 V ≤ VS ≤ +10 V, IS = 1 mA
–5 V ≤ VS ≤ +5 V
RON
80
95
4
115
5
∆RON
LEAKAGE CURRENTS
Channel Output Leakage, IS(ON)
(Without Fault Condition)
VS = VD = ±10 V
±0.1
±1
±1
±5
nA typ
nA max
Channel Input Leakage, ID(ON)
(With Fault Condition)
VS = ±25 V
VD = Open Circuit
±0.2
±2
±0.4
±5
nA typ
nA max
Channel Input Leakage, ID(OFF)
(With Power Off and Fault)
VDD = 0 V, VSS = 0 V
VS = ±35 V
VD = Open Circuit
±0.5
±2
±2
±10
nA typ
nA max
Channel Input Leakage, ID(OFF)
(With Power Off and Output S/C)
VDD = 0 V, VSS = 0 V
VS = ±35 V, VD = 0 V
±0.005
±0.015
±0.1
±0.5
µA typ
µA max
POWER REQUIREMENTS
IDD
±0.05
±0.5
±0.05
±0.5
0
µA typ
µA max
µA typ
µA max
V min
±5
ISS
±5
0
VDD/VSS
±20
±20
V max
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. A
–2–
ADG465
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
PIN CONFIGURATIONS
(RT-6)
(RM-8)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
VS, VD, Analog Input Overvoltage with Power ON2
. . . . . . . . . . . . . . . . . . . . . . . . . VSS – 20 V to VDD + 20 V
VS, VD, Analog Input Overvoltage with Power OFF2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –35 V to +35 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . .20 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .40 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
V
1
2
3
6
5
4
V
DD
D1
1
8
NC
V
NC
ADG465
TOP VIEW
(Not to Scale)
ADG465
TOP VIEW
(Not to Scale)
NC
NC
V
2
3
4
7
6
5
DD
D1
V
V
V
SS
V
SS
S1
S1
NC
NC
NC = NO CONNECT
NC = NO CONNECT
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SOT-23 Package
PIN FUNCTION DESCRIPTIONS
Pin
Pin
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 230°C/W
µSOIC Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . 205°C/W
Lead Temperature, Soldering
RT-6 RM-8 Pin Description
1
7
VD1, this is one terminal of the channel protec-
tor. The channel protector is bidirectional so this
terminal may be used as an input or an output.
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
2
3
1, 4
6
NC, this is a no connect pin.
VSS, Negative Power Supply (0 V to –20 V).
The clamping point for a negative overvoltage is
also defined by VSS, see Overvoltage Protection
section.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
4
3
VS1, this is one terminal of the channel protec-
tor. The channel protector is bidirectional so this
terminal may be used as an output or an input.
2Overvoltages at S or D will be clamped by the channel protector, see Circuit
Information section of the data sheet.
5
6
5, 8
2
NC, this is a no connect pin.
VDD, Positive Power Supply (0 V to 20 V). The
clamping point for a positive overvoltage is also
defined by VDD, see Overvoltage Protection
section.
ORDERING GUIDE
Package Descriptions
Model
Temperature Range
Brand
Package Options
ADG465BRT
ADG465BRM
–40°C to +85°C
–40°C to +85°C
6-Lead Plastic Surface Mount SOT-23
8-Lead µSOIC
S1B
S1B
RT-6
RM-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG465 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
ADG465—Typical Performance Characteristics
140
TEMP = +25؇C
POSITIVE OVERVOLTAGE ON INPUT
130
R
C
= 100k⍀
= 100pF
LOAD
LOAD
–5V TO +15V
STEP INPUT
120
110
V
V
= +10V
= –10V
DD
SS
15
V
V
= +5V
= –5V
DD
SS
100
90
10
5
V
V
= +10V
= –10V
DD
SS
80
70
60
50
V
V
= +16.5V
= –16.5V
CHANNEL PROTECTOR
OUTPUT
DD
SS
0
–5
–10
–5
0
5
10
Ch1 5.00V Ch2
5.00V
M50.0ns Ch1
500mV
V
, V – Volts
D
S
Figure 1. On Resistance as a Function of VDD and VD
(Input Voltage)
Figure 3. Positive Overvoltage Transience Response
125
NEGATIVE OVERVOLTAGE ON INPUT
R
C
= 100k⍀
= 100pF
= +10V
= –10V
LOAD
V
V
= +15V
= –15V
DD
SS
LOAD
115
105
95
5
0
V
V
DD
SS
CHANNEL PROTECTOR
OUTPUT
–5
+125؇C
+80؇C
85
75
65
55
45
–10
–15
+25؇C
5V TO –15V
STEP INPUT
–10
–5
0
5
10
Ch1 5.00V
Ch2
5.00V
M50.0ns Ch1
500mV
V
, V – Volts
D
S
Figure 2. On Resistance as a Function of Temperature
and VD (Input Voltage)
Figure 4. Negative Overvoltage Transience Response
R
= 100k⍀
10V TO +10V INPUT
LOAD
V
V
= +5V
= –5V
DD
SS
20V
10
V
= 4.5V
CLAMP
OUTPUT
20
V
= 4V
CLAMP
Ch1
5.00V Ch2
5.00V
M100ns
Ch1
500mV
Figure 5. Overvoltage Ramp
REV. A
–4–
ADG465
CIRCUIT INFORMATION
VSS – VTP where VTP is the threshold voltage of the PMOS
device (2 V typ). If the input voltage exceeds these threshold
voltages, the output of the channel protector (no load) is
clamped at these threshold voltages. However, the channel
protector output will clamp at a voltage inside these thresholds
if the output is loaded. For example, with an output load of
1 kΩ, VDD = 15 V and a positive overvoltage. The output will
clamp at VDD – VTN – ∆V = 15 V – 1.5 V – 0.6 V = 12.9 V
where ∆V is due to I. R voltage drops across the channels of the
MOS devices (see Figure 8). As can be seen from Figure 8, the
current during fault condition is determined by the load on the
output (i.e., VCLAMP/RL). However, if the supplies are off, the
fault current is limited to the nanoampere level.
Figure 6 below shows a simplified schematic of a channel pro-
tector circuit. The circuit is comprised of four MOS transis-
tors—two NMOS and two PMOS. One of the PMOS devices
does not lie directly in the signal path, but is used to connect the
source of the second PMOS device to its backgate. This has the
effect of lowering the threshold voltage and increasing the
input signal range of the channel for normal operation. The
source and backgate of the NMOS devices are connected for the
same reason. During normal operation the channel protectors
have a resistance of 80 Ω typ. The channel protectors are very
low power devices; even under fault conditions the supply cur-
rent is limited to sub-microampere levels. All transistors are
dielectrically isolated from each other using a trench isolation
method. This makes it impossible to latch up the channel pro-
tectors. For an explanation, see Trench Isolation section.
Figures 7, 9 and 10 show the operating conditions of the signal
path transistors during various fault conditions. Figure 7 shows
how the channel protectors operate when a positive overvoltage
is applied to the channel protector.
V
– V *
TN
DD
(+13.5V)
V
SS
PMOS
PMOS
POSITIVE
OVERVOLTAGE
(+20V)
NMOS
PMOS
NMOS
NMOS
NMOS
NON-
SATURATED
NON-
SATURATED
SATURATED
V
(+15V)
V
(–15V)
V
(+15V)
DD
SS
DD
V
V
V
DD
DD
SS
*V = NMOS THRESHOLD VOLTAGE (+1.5V)
TN
Figure 6. The Channel Protector Circuit
Overvoltage Protection
Figure 7. Positive Overvoltage on the Channel Protector
The first NMOS transistor goes into a saturated mode of opera-
tion as the voltage on its Drain exceeds the Gate voltage (VDD) –
the threshold voltage (VTN). This situation is shown in Figure 8.
The potential at the source of the NMOS device is equal to VDD
–VTN. The other MOS devices are in a nonsaturated mode of
operation.
When a fault condition occurs on the input of a channel pro-
tector, the voltage on the input has exceeded some threshold
voltage set by the supply rail voltages. The threshold voltages
are related to the supply rails as follows: for a positive overvolt-
age, the threshold voltage is given by VDD – VT where VTN is the
threshold voltage of the NMOS transistor (1.5 V typ). In the
case of a negative overvoltage the threshold voltage is given by
V
V
V
S
⌬V
D
G
(+13.5V)
(+20V)
(V = +15V)
DD
NMOS
PMOS
NONSATURATED
OPERATION
+
+
+
N
N
N
R
OVERVOLTAGE
OPERATION
(SATURATED)
V
EFFECTIVE
SPACE CHARGE
REGION
L
CLAMP
N-CHANNEL
I
OUT
(V – V = 13.5V)
–
G
T
V
= 1.5V
P
T
Figure 8. Positive Overvoltage Operation on the Channel Protector
REV. A
–5–
ADG465
When a negative overvoltage is applied to the channel protector
circuit, the PMOS transistor enters a saturated mode of operation
as the drain voltage exceeds VSS – VTP. See Figure 9 below. As in
the case of the positive overvoltage, the other MOS devices are
nonsaturated.
TRENCH ISOLATION
The MOS devices that make up the channel protector are
isolated from each other by an oxide layer (trench) (see Figure
11). When the NMOS and PMOS devices are not electrically
isolated from each other, there exists the possibility of “latchup”
caused by parasitic junctions between CMOS transistors. Latchup
is caused when P-N junctions that are normally reverse biased,
become forward biased, causing large currents to flow. This can
be destructive.
NEGATIVE
OVERVOLTAGE
(–20V)
V
– V *
TP
SS
(–13V)
NEGATIVE
OVERVOLTAGE
(–20V)
NMOS
PMOS
NMOS
CMOS devices are normally isolated from each other by
Junction Isolation. In Junction Isolation, the N and P wells of the
CMOS transistors form a diode that is reverse biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A Silicon-Controlled Rectifier
(SCR) type circuit is formed by the two transistors, causing a
significant amplification of the current that, in turn, leads to
latchup. With Trench Isolation, this diode is removed; the result
is a latchup-proof circuit.
NON-
SATURATED
NON-
SATURATED
SATURATED
V
(+15V)
V
(–15V)
V
(+15V)
DD
DD
SS
*V = PMOS THRESHOLD VOLTAGE (+2V)
TP
Figure 9. Negative Overvoltage on the Channel Protector
The channel protector is also functional when the supply rails
are down (e.g., power failure) or momentarily unconnected
(e.g., rack system). This is where the channel protector has an
advantage over more conventional protection methods such as
diode clamping (see Applications Information). When VDD and
V
V
G
G
V
V
V
V
D
S
D
S
V
SS equal 0 V, all transistors are off and the current is limited to
P-CHANNEL
N-CHANNEL
T
R
E
N
C
H
T
R
E
N
C
H
T
R
E
N
C
H
+
+
+
+
N
P
P
N
microampere levels (see Figure 10).
–
–
P
N
(0V)
BURIED OXIDE LAYER
POSITIVE OR
NEGATIVE
SUBSTRATE (BACKGATE)
NMOS
PMOS
NMOS
OVERVOLTAGE
OFF
(0V)
OFF
(0V)
OFF
(0V)
Figure 11. Trench Isolation
V
V
V
DD
DD
SS
Figure 10. Channel Protector Supplies Equal to Zero Volts
REV. A
–6–
ADG465
APPLICATIONS INFORMATION
channel protectors. In this way, the outputs of the channel
protectors are clamped well below VDD and VSS until the
capacitors are charged. The diodes ensure that the supplies on
the channel protector never exceed the supply rails of the board
when it is being disconnected. Again, this ensures that signals
on the inputs of the CMOS devices never exceed the supplies.
Overvoltage and Power Supply Sequencing Protection
The ADG465 is ideal for use in applications where input over-
voltage protection is required and correct power supply sequencing
cannot always be guaranteed. The overvoltage protection en-
sures that the output voltage of the channel protector will not
exceed the threshold voltages set by the supplies (see Circuit
Information section) when there is an overvoltage on the input.
When the input voltage does not exceed these threshold volt-
ages, the channel protector behaves like a series resistor (80 Ω
typ). The resistance of the channel protector does vary slightly
with operating conditions (see Typical Performance Graphs).
High Voltage Surge Suppression
The ADG465 are not intended for use in high voltage applica-
tions such as surge suppression. The ADG465 has breakdown
voltages of VSS – 20 V and VDD + 20 V on the inputs when the
power supplies are connected. When the power supplies are
disconnected, the breakdown voltages on the input of the chan-
nel protector are ±35 V. In applications where inputs are likely
to be subject to overvoltages exceeding the breakdown voltages
quoted for the channel protectors, transient voltage suppressors
(TVSs) should be used. These devices are commonly used to
protect vulnerable circuits from electric overstress such as that
caused by electrostatic discharge, inductive load switching and
induced lightning. However, TVSs can have a substantial
standby (leakage) current (300 µA typ) at the reverse standoff
voltage. The reverse standoff voltage of a TVS is the normal
peak operating voltage of the circuit. In addition, TVSs offer no
protection against latchup of sensitive CMOS devices when the
power supplies are off. To provide the best leakage current
specification and circuit protection, the best solution is to use a
channel protector in conjunction with a TVS.
The power sequencing protection is afforded by the fact that
when the supplies to the channel protector are not connected,
the channel protector becomes a high resistance device. Under
this condition all transistors in the channel protector are off and
the only currents that flow are leakage currents, which are at the
µA level.
EDGE
CONNECTOR
V
DD
+5V
V
SS
–5V
Figure 13 shows an input protection scheme that uses both a
TVS and channel protector. The TVS is selected with a reverse
standoff voltage much greater than the operating voltage of the
circuit (TVSs with higher breakdown voltages tend to have
better standby leakage current specifications), but inside
the breakdown voltage of the channel protector. This circuit
protects the circuitry whether or not the power supplies are
present.
ANALOG IN
–2.5V TO +2.5V
ADC
ADG465
LOGIC
CONTROL
LOGIC
LOGIC
GND
V
= –5V
V
= +5V
SS
DD
Figure 12. Overvoltage and Power Supply Sequencing
Protection
ADG465
Figure 12 shows a typical application requiring overvoltage and
power supply sequencing protection. The application shows a
Hot-Insertion rack system. This involves plugging a circuit
board or module into a live rack via an edge connector. In this
type of application it is not possible to guarantee correct power
supply sequencing. Correct power supply sequencing means that
the power supplies should be connected prior to any external
signals. Incorrect power sequencing can cause a CMOS device
to “latch up,” see Trench Isolation section. This is true of most
CMOS devices, regardless of the functionality. RC networks
are used on the supplies of the channel protector (Figure 12)
to ensure that the rest of the circuitry is powered up before the
ADC
TVSs
BREAKDOWN
VOLTAGE = 20V
Figure 13. High Voltage Protection
REV. A
–7–
ADG465
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead Plastic Surface Mount SOT-23 Package
(RT-6)
0.122 (3.10)
0.106 (2.70)
6
1
5
2
4
3
0.071 (1.80)
0.059 (1.50)
0.118 (3.00)
0.098 (2.50)
PIN 1
0.037 (0.95) BSC
0.075 (1.90)
BSC
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
10؇
0؇
0.020 (0.50)
0.010 (0.25)
0.022 (0.55)
0.014 (0.35)
0.006 (0.15)
0.000 (0.00)
SEATING
PLANE
0.009 (0.23)
0.003 (0.08)
8-Lead SOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
5
4
8
1
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33°
27°
0.018 (0.46)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
SEATING
PLANE
0.008 (0.20)
–8–
REV. A
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