ADG466BR [ADI]

Triple and Octal Channel Protectors; 三人间和八通道保护器


型号：	ADG466BR
厂家：	ADI
描述：	Triple and Octal Channel Protectors 三人间和八通道保护器晶体小信号场效应晶体管开关光电二极管
文件：	总10页 (文件大小：235K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Triple and Octal

Channel Protectors

ADG466/ADG467

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Fault and Overvoltage Protection up to ؎40 V

Signal Paths Open Circuit with Power Off

Signal Path Resistance of R_ONwith Power On

44 V Supply Maximum Ratings

Low On Resistance

ADG466/ADG467 60 ⍀ typ

1 nA Max Path Current Leakage @ +25؇C

Low R_ONMatch (5 ⍀ max)

ADG466

Low Power Dissipation 0.8 ␮W typ

Latch-Up Proof Construction

APPLICATIONS

ATE Equipment

V_IN

OUT

ADG467

OUT

Sensitive Measurement Equipment

Hot-Insertion Rack Systems

OUTPUT CLAMPED

GENERAL DESCRIPTION

@ V – 1.5V

The ADG466 and ADG467 are triple and octal channel pro-

tectors, respectively. The channel protector is placed in series

with the signal path. The channel protector will protect sensitive

components from voltage transience in the signal path whether

the power supplies are present or not. Because the channel

protection works whether the supplies are present or not, the

channel protectors are ideal for use in applications where

correct power sequencing can’t always be guaranteed (e.g., hot-

insertion rack systems) to protect analog inputs. This is dis-

cussed further, and some example circuits are given in the

Applications section of this data sheet.

ADG467 is 60 Ω typ with a leakage current of ±1 nA max.

When power is disconnected, the input leakage current is ap-

proximately ±5 nA typ.

The ADG466 is available in 8-lead DIP, SOIC and µSOIC

packages. The ADG467 is available in an 18-lead SOIC package

and a 20-lead SSOP package.

Each channel protector has an independent operation and con-

sists of an n-channel MOSFET, a p-channel MOSFET and an

n-channel MOSFET, connected in series. The channel protec-

tor behaves just like a series resistor during normal operation,

i.e., (V_SS+ 2 V) < V_IN< (V_DD– 1.5 V). When a channel’s ana-

PRODUCT HIGHLIGHTS

1. Fault Protection.

The ADG466 and ADG467 can withstand continuous volt-

age inputs from –40 V to +40 V. When a fault occurs due to

the power supplies being turned off or due to an overvoltage

being applied to the ADG466 and ADG467, the output is

clamped. When power is turned off, current is limited to the

microampere level.

log input exceeds the power supplies (including V_DDand V_SS

0 V), one of the MOSFETs will switch off, clamping the output

to either V_SS+ 2 V or V_DD– 1.5 V. Circuitry and signal source

protection is provided in the event of an overvoltage or power

loss. The channel protectors can withstand overvoltage inputs

from –40 V to +40 V. See the Circuit Information section of

this data sheet.

2. Low Power Dissipation.

3. Low R_ON

ADG466/ADG467 60 Ω typ.

The ADG466 and ADG467 can operate off both bipolar and

unipolar supplies. The channels are normally on when power is

connected and open circuit when power is disconnected. With

power supplies of ±15 V, the on-resistance of the ADG466 and

4. Trench Isolation Latch-Up Proof Construction.

A dielectric trench separates the p- and n-channel MOSFETs

thereby preventing latch-up.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

ADG466/ADG467–SPECIFICATIONS

Dual Supply¹

(V_DD= +15 V, V_SS= –15 V, GND = 0 V, unless otherwise noted)

ADG466

ADG467

+25؇C

Parameter

+25؇C

B¹

Units

Test Conditions/Comments

FAULT PROTECTED CHANNEL

Fault-Free Analog Signal Range²

V_SS+ 1.2

V_DD– 0.8

V_SS+ 1.2

V_DD– 0.8

V min

V max

Ω typ

Ω max

Output Open Circuit

R_ON

–10 V ≤ V_S≤ +10 V, I_S= 1 mA

∆R_ON

R_ONMatch

–5 V ≤ V_S≤ +5 V

V_S= ±10 V, I_S= 1 mA

LEAKAGE CURRENTS

Channel Output Leakage, I_S(ON)

(without Fault Condition)

V_S= V_D= ±10 V

±0.1

±1

±5

±0.04

±1

±0.2

±5

nA typ

nA max

Channel Input Leakage, I_D(ON)

(with Fault Condition)

V_S= ±25 V

V_D= Open Circuit

±0.2

±2

±0.4

±5

±0.2

±2

±0.4

±5

nA typ

nA max

Channel Input Leakage, I_D(OFF)

(with Power Off and Fault)

V_DD= 0 V, V_SS= 0 V

V_S= ±35 V,

V_D= Open Circuit

V_DD= 0 V, V_SS= 0 V

V_S= ±35 V, V_D= 0 V

±0.5

±1

±2

±5

±0.5

±2

±10

nA typ

nA max

Channel Input Leakage, I_D(OFF)

(with Power Off and Output S/C) ±0.005 ±0.1

±0.015 ±0.5

±0.006 ±0.16

±0.015 ±0.5

µA typ

µA max

POWER REQUIREMENTS

I_DD

±0.05

±0.5

±0.05

±0.5

±0.05

µA typ

µA max

µA typ

µA max

V min

±8

±0.5

±0.05

±0.5

±8

I_SS

±8

V_DD/V_SS

±20

V max

NOTES

¹Temperature range is as follows: B Version: –40°C to +85°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

REV. A

ADG466/ADG467

PIN CONFIGURATIONS

ABSOLUTE MAXIMUM RATINGS¹

(T_A= +25°C unless otherwise noted)

8-Lead

V_DDto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V

V_S, V_D, Analog Input Overvoltage with Power ON²

. . . . . . . . . . . . . . . . . . . . . . . . . . . .V_SS– 20 V to V_DD+ 20 V

V_S, V_D, Analog Input Overvoltage with Power OFF²

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–35 V to +35 V

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA

(Pulsed at 1 ms, 10% Duty Cycle Max)

DIP, SOIC

and ␮SOIC

18-Lead

SOIC

ADG466

TOP VIEW

(Not to Scale)

ADG467

TOP VIEW 14

(Not to Scale)

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Plastic DIP Package

13 S5

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W

Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C

SOIC Package

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W

Lead Temperature, Soldering

20-Lead

SSOP

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

µSOIC Package

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

SSOP Package

θ_JA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W

Lead Temperature, Soldering

20 NC

ADG467

TOP VIEW

(Not to Scale)

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NC 10

NC = NO CONNECT

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability. Only one absolute maxi-

mum rating may be applied at any one time.

²Overvoltages at S or D will be clamped by the channel protector, see Circuit

Information section of the data sheet.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Options

ADG466BN

ADG466BR

ADG466BRM

–40°C to +85°C

8-Lead Plastic DIP

8-Lead Small Outline Package

8-Lead Micro Small Outline Package

N-8

SO-8

RM-8

ADG467BR

ADG467BRS

–40°C to +85°C

18-Lead Small Outline Package

20-Lead Shrink Small Outline Package RS-20

R-18

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADG466/ADG467 features proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

–3–

ADG466/ADG467–Typical Performance Characteristics

ADG466

POSITIVE OVERVOLTAGE

ON INPUT

LOAD

= 100k⍀

–5V TO +15V STEP INPUT

= 100pF

LOAD

= +10V

= –10V

15V

10V

, V =؎5V

DD SS

, V =؎15V

DD SS

, V =؎10V

DD SS

, V =؎13.5V

DD SS

CHANNEL PROTECTOR

OUTPUT

–5V

؎16.5V

–10

–5

Ch1 5.00V

Ch2

5.00V

M50.0ns Ch1

500mV

– Volts

Figure 1. On Resistance as a Function of V_DDand V_D

(Input Voltage)

Figure 4. Positive Overvoltage Transience Response

= +15V

= –15V

NEGATIVE OVERVOLTAGE

ON INPUT

= 100k⍀

= 100pF

= +10V

= –10V

LOAD

CHANNEL PROTECTOR

OUTPUT

125؇C

85؇C

–5V

–10V

–15V

25؇C

5V TO –15V STEP INPUT

–40؇C

–10

–5

Ch1 5.00V

Ch2

5.00V

M50.0ns Ch1

500mV

– Volts

Figure 2. On Resistance as a Function of Temperature

and V_D(Input Voltage)

Figure 5. Negative Overvoltage Transience Response

ADG467

105

=100k⍀

=+5V

=–5V

LOAD

10V TO +10 V INPUT

20V

؎5V

=4.5V

CLAMP

؎15V

OUTPUT

؎13.5V

؎10V

=4V

CLAMP

؎16.5V

–10

–5

Ch1

5.00V

Ch2 5.00V

M100␮s Ch1

500mV

– Volts

Figure 6. Overvoltage Ramp

Figure 3. On Resistance as a Function of V_DDand V_D

(Input Voltage)

REV. A

–4–

ADG466/ADG467

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–10

–12

–14

–16

–18

–20

–22

–24

–26

–28

–30

100k

10M

40M

30M

10k

10M

FREQUENCY – Hz

Figure 7. Frequency Response (Magnitude) of the ADG467,

Figure 10. Off Isolation of the ADG467, V_DD/V_SS= 0 V and

V_DD/V_SS= ±15 V and Input Signal Level of ±100 mV

Input Signal Level of ±100 mV

TEK RUN: 5.00GS/s ET SAMPLE

105.359

82.859

60.359

37.859

15.359

–7.141

–29.641

–52.161

–76.641

–97.161

11.8ns

12.2ns

100

10k

100k

10M

CH1 2.00V CH2

2.00V

M 10.0ns CH1

2.2V

FREQUENCY – Hz

Figure 8. Frequency Response (Phase) of the ADG467,

Figure 11. Propagation Delay Through ADG467, V_DD/V_SS=

_DD/V_SS= ±15 V and Input Signal Level of ±100 mV

±15 V, Channel 1 Input and Channel 2 Output

–10

–14

–18

–22

–26

–30

–36

–38

–42

–46

–50

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

100k

10M

40M

10k

40M

100k

10M

FREQUENCY – Hz

Figure 9. Crosstalk Between Adjacent Channels of the

ADG467, V_DD/V_SS= ±15 V and Input Signal Level of ±100 mV

Figure 12. Frequency Response (Magnitude) of the ADG466,

V_DD/V_SS= ±15 V and Input Signal Level of ±100 mV

REV. A

–5–

ADG466/ADG467

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

105.3

82.8

60.3

37.8

15.3

–7.1

–29.6

–52.1

–76.6

–92.1

40M

10k

100k

10M

100

10k

100k

10M

FREQUENCY – Hz

Figure 15. Off Isolation of the ADG466, V_DD/V_SS= 0 V and

Input Signal Level of ±100 mV

Figure 13. Frequency Response (Phase) of the ADG466, V_DD

V_SS= ±15 V and Input Signal Level of ±100 mV

TEK RUN: 2.5GS/s ET SAMPLE

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

22.0ns

18.0ns

40M

CH1 1.00V CH2

1.00V

M 20.0ns CH1

760V

10k

100k

10M

FREQUENCY – Hz

Figure 14. Crosstalk Between Adjacent Channels of the

Figure 16. Propagation Delay Through ADG466, V_DD/V_SS=

ADG466, V_DD/V_SS= ±15 V and Input Signal Level of ±100 mV

±15 V, Channel 1 Input and Channel 2 Output

REV. A

–6–

ADG466/ADG467

CIRCUIT INFORMATION

case of a negative overvoltage the threshold voltage is given by

Figure 17 below shows a simplified schematic of a channel

protector circuit. The circuit is made up of four MOS transis-

tors—two NMOS and two PMOS. One of the PMOS devices

does not lie directly in the signal path but is used to connect the

source of the second PMOS device to its backgate. This has the

effect of lowering the threshold voltage and so increasing the

input signal range of the channel for normal operation. The

source and backgate of the NMOS devices are connected for the

same reason. During normal operation the channel protectors

have a resistance of 60 Ω typ. The channel protectors are very

low power devices, and even under fault conditions the supply

current is limited to sub microampere levels. All transistors are

dielectrically isolated from each other using a trench isolation

method. This makes it impossible to latch up the channel

protectors. For an explanation, see Trench Isolation section.

V_SS– V_TPwhere V_TPis the threshold voltage of the PMOS de-

vice (2 V typ). If the input voltage exceeds these threshold volt-

ages, the output of the channel protector (no load) is clamped at

these threshold voltages. However, the channel protector output

will clamp at a voltage that is inside these thresholds if the out-

put is loaded. For example with an output load of 1 kΩ, V_DD

15 V and a positive overvoltage. The output will clamp at V_DD

–

V_TN– ∆V = 15 V – 1.5 V – 0.6 V = 12.9 V where ∆V is due to I

× R voltage drop across the channels of the MOS devices (see

Figure 19). As can be seen from Figure 19, the current during

fault condition is determined by the load on the output (i.e.,

V_CLAMP/R_L). However, if the supplies are off, the fault current is

limited to the nano-ampere level.

Figures 18, 20 and 21 show the operating conditions of the

signal path transistors during various fault conditions. Figure 18

shows how the channel protectors operate when a positive over-

voltage is applied to the channel protector.

– V

(+13.5V)

PMOS

NMOS

PMOS

NMOS

POSITIVE

OVERVOLTAGE

(+20V)

NMOS

NON-

SATURATED

NON-

SATURATED

PMOS

(+15V)

(–15V)

(+15V)

*V = NMOS THRESHOLD VOLTAGE (+1.5V)

Figure 17. The Channel Protector Circuit

Overvoltage Protection

Figure 18. Positive Overvoltage on the Channel Protector

The first NMOS transistor goes into a saturated mode of opera-

tion as the voltage on its Drain exceeds the Gate voltage (V_DD) –

the threshold voltage (V_TN). This situation is shown in Figure

19. The potential at the source of the NMOS device is equal to

V_DD– V_TN. The other MOS devices are in a nonsaturated mode of

operations.

When a fault condition occurs on the input of a channel protec-

tor, the voltage on the input has exceeded some threshold volt-

age set by the supply rail voltages. The threshold voltages are

related to the supply rails as follows. For a positive overvoltage,

the threshold voltage is given by V_DD– V_Twhere V_TNis the

threshold voltage of the NMOS transistor (1.5 V typ). In the

⌬V

(V =15V)

(+20V)

(+13.5V)

NMOS

PMOS

N CHANNEL

CLAMP

NONSATURATED

OPERATION

EFFECTIVE

SPACE CHARGE

REGION

OVERVOLTAGE

OPERATION

(SATURATED)

(V – V = 13.5V)

OUT

–

= 1.5V

Figure 19. Positive Overvoltages Operation of the Channel Protector

REV. A

–7–

ADG466/ADG467

TRENCH ISOLATION

When a negative overvoltage is applied to the channel protector

circuit, the PMOS transistor enters a saturated mode of opera-

tion as the drain voltage exceeds V_SS– V_TP. See Figure 20 be-

low. As in the case of the positive overvoltage, the other MOS

devices are nonsaturated.

The MOS devices that make up the channel protector are iso-

lated from each other by an oxide layer (trench) (see Figure 22).

When the NMOS and PMOS devices are not electrically iso-

lated from each other, there exists the possibility of “latch-up”

caused by parasitic junctions between CMOS transistors. Latch-

up is caused when P-N junctions that are normally reverse bi-

ased become forward biased, causing large currents to flow,

which can be destructive.

NEGATIVE

OVERVOLTAGE

(–20V)

– V

(–13V)

NMOS

PMOS

NMOS

NEGATIVE

OVERVOLTAGE

(–20V)

CMOS devices are normally isolated from each other by Junc-

tion Isolation. In Junction Isolation, the N and P wells of the

CMOS transistors form a diode that is reverse-biased under

normal operation. However, during overvoltage conditions, this

diode becomes forward biased. A Silicon-Controlled Rectifier

(SCR) type circuit is formed by the two transistors causing a

significant amplification of the current that, in turn, leads to

latch-up. With Trench Isolation, this diode is removed; the

result is a latch-up proof circuit.

SATURATED

(+15V) (–15V)

NON-

SATURATED

NON-

SATURATED

(+15V)

*V = PMOS THRESHOLD VOLTAGE (–2V)

Figure 20. Negative Overvoltage on the Channel Protector

The channel protector is also functional when the supply rails

are down (e.g., power failure) or momentarily unconnected

(e.g., rack system). This is where the channel protector has an

advantage over more conventional protection methods such as

diode clamping (see Applications Information). When V_DDand

V_SSequal 0 V, all transistors are off and the current is limited to

subnano-ampere levels (see Figure 21).

P-CHANNEL

N-CHANNEL

–

(0V)

–

NMOS

PMOS

NMOS

POSITIVE OR

NEGATIVE

OVERVOLTAGE

BURIED OXIDE LAYER

SUBSTRATE (BACKGATE)

OFF

(0V)

Figure 22. Trench Isolation

Figure 21. Channel Protector Supplies Equal to Zero Volts

REV. A

–8–

ADG466/ADG467

APPLICATIONS INFORMATION

Again this ensures that signals on the inputs of the CMOS de-

vices never exceed the supplies.

Overvoltage and Power Supply Sequencing Protection

The ADG466 and ADG467 are ideal for use in applications

where input overvoltage protection is required and correct

power supply sequencing cannot always be guaranteed. The

overvoltage protection ensures that the output voltage of the

channel protector will not exceed the threshold voltages set by

the supplies (see Circuit Information) when there is an overvolt-

age on the input. When the input voltage does not exceed these

threshold voltages, the channel protector behaves like a series

resistor (60 Ω typ). The resistance of the channel protector does

vary slightly with operating conditions (see Typical Performance

Graphs).

High Voltage Surge Suppression

The ADG466 and ADG467 are not intended for use in high

voltage applications like surge suppression. The ADG466

and ADG467 have breakdown voltages of V_SS– 20 V and

V_DD+ 20 V on the inputs when the power supplies are con-

nected. When the power supplies are disconnected, the break-

down voltages on the input of the channel protector are ±35 V.

In applications where inputs are likely to be subject to overvolt-

ages exceeding the breakdown voltages quoted for the channel

protectors, transient voltage suppressors (TVSs) should be used.

These devices are commonly used to protect vulnerable circuits

from electric overstress such as that caused by electrostatic

discharge, inductive load switching and induced lightning. How-

ever, TVSs can have a substantial standby (leakage) current

(300 µA typ) at the reverse standoff voltage. The reverse standoff

voltage of a TVS is the normal peak operating voltage of the

circuit. Also TVS offer no protection against latch-up of sensitive

CMOS devices when the power supplies are off. The best solution

is to use a channel protector in conjunction with a TVS to provide

the best leakage current specification and circuit protection.

The power sequencing protection is afforded by the fact that

when the supplies to the channel protector are not connected,

the channel protector becomes a high resistance device. Under

this condition all transistors in the channel protector are off and

the only currents that flow are leakage currents, which are at the

µA level.

EDGE

CONNECTOR

+5V

= +5V

= –5V

–5V

ADC

ANALOG IN

–2.5V TO +2.5V

ADC

ADG466

LOGIC

CONTROL

LOGIC

TVSs

BREAKDOWN

VOLTAGE = 20V

ADG466

GND

Figure 24. High Voltage Protection

Figure 24 shows an input protection scheme that uses both a

TVS and channel protector. The TVS is selected with a reverse

standoff voltage that is much greater than operating voltage of

the circuit (TVSs with higher breakdown voltages tend to have

better standby leakage current specifications) but is inside the

breakdown voltage of the channel protector. This circuit pro-

tects the circuitry whether the power supplies are present

or not.

Figure 23. Overvoltage and Power Supply Sequencing

Protection

Figure 23 shows a typical application that requires overvoltage

and power supply sequencing protection. The application shows

a Hot-Insertion rack system. This involves plugging a circuit

board or module into a live rack via an edge connector. In this

type of application it is not possible to guarantee correct power

supply sequencing. Correct power supply sequencing means

that the power supplies should be connected before any external

signals. Incorrect power sequencing can cause a CMOS device

to “latch up.” This is true of most CMOS devices regardless of

the functionality. RC networks are used on the supplies of the

channel protector (Figure 23) to ensure that the rest of the

circuitry is powered up before the channel protectors. In this

way, the outputs of the channel protectors are clamped well

below V_DDand V_SSuntil the capacitors are charged. The diodes

ensure that the supplies on the channel protector never exceed

the supply rails of the board when it is being disconnected.

REV. A

–9–

ADG466/ADG467

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead Plastic DIP (N-8)

8-Lead Small Outline IC (SO-8)

0.1968 (5.00)

0.1890 (4.80)

0.430 (10.92)

0.348 (8.84)

0.280 (7.11)

0.240 (6.10)

0.1574 (4.00)

0.1497 (3.80)

0.2440 (6.20)

0.2284 (5.80)

0.325 (8.25)

0.300 (7.62)

0.060 (1.52)

0.015 (0.38)

PIN 1

0.0688 (1.75)

0.0532 (1.35)

0.0196 (0.50)

0.0099 (0.25)

0.195 (4.95)

0.115 (2.93)

x 45°

0.210 (5.33)

MAX

0.0098 (0.25)

0.0040 (0.10)

0.130

(3.30)

MIN

0.160 (4.06)

0.115 (2.93)

0.015 (0.381)

0.008 (0.204)

8°

0°

SEATING

PLANE

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.100

(2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.77)

0.045 (1.15)

SEATING

PLANE

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

18-Lead Small Outline IC (R-18)

20-Lead Shrink Small Outline Package (RS-20)

0.295 (7.50)

0.271 (6.90)

0.4625 (11.75)

0.4469 (11.35)

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

0.0098 (0.25)

x 45°

0.07 (1.78)

0.078 (1.98)

PIN 1

0.066 (1.67)

0.068 (1.73)

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0118 (0.30)

0.0040 (0.10)

0.037 (0.94)

8°

0°

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

0.0256

(0.65)

BSC

0.0138 (0.35)

0.022 (0.559)

0.008 (0.203)

0.002 (0.050)

SEATING

PLANE

0.009 (0.229)

0.005 (0.127)

8-Lead Micro Small Outline IC (RM-8)

0.122 (3.10)

0.114 (2.90)

0.199 (5.05)

0.187 (4.75)

0.122 (3.10)

0.114 (2.90)

PIN 1

0.0256 (0.65) BSC

0.120 (3.05)

0.112 (2.84)

0.120 (3.05)

0.112 (2.84)

0.043 (1.09)

0.037 (0.94)

0.006 (0.15)

0.002 (0.05)

33°

27°

0.018 (0.46)

0.011 (0.28)

0.003 (0.08)

0.028 (0.71)

0.016 (0.41)

SEATING

PLANE

0.008 (0.20)

REV. A

–10–

ADG466BR [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E