ADG509FBNZ [ADI]
8-Channel/4-Channel Fault-Protected Analog Multiplexers; 8通道/ 4通道故障保护模拟多路复用器
| 型号： | ADG509FBNZ |
| 厂家： | 
ADI |
| 描述： | 8-Channel/4-Channel Fault-Protected Analog Multiplexers |
| 文件： | 总20页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel/4-Channel
Fault-Protected Analog Multiplexers
ADG508F/ADG509F
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs
Latch-up proof construction
ADG508F
S1
Low on resistance (270 Ω typical)
Fast switching times
D
t
t
ON: 230 ns maximum
OFF: 130 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V)
Break-before-make construction
S8
1 OF 8
DECODER
TTL and CMOS compatible inputs
A0 A1 A2 EN
APPLICATIONS
Figure 1.
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions
ADG509F
S1A
GENERAL DESCRIPTION
DA
S4A
The ADG508F and ADG509F are CMOS analog multi-
plexers, with the ADG508F comprising eight single channels
and the ADG509F comprising four differential channels. These
multiplexers provide fault protection. Using a series n-channel,
p-channel, n-channel MOSFET structure, both device and signal
source protection is provided in the event of an overvoltage or
power loss. The multiplexer can withstand continuous overvolt-
age inputs from −40 V to +55 V. During fault conditions with
power supplies off, the multiplexer input (or output) appears as
an open circuit and only a few nanoamperes of leakage current
will flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
S1B
S4B
DB
1 OF 4
DECODER
A1
A0
EN
Figure 2.
PRODUCT HIGHLIGHTS
1. Fault protection. The ADG508F/ADG509F can withstand
continuous voltage inputs from −40 V to +55 V. When a
fault occurs due to the power supplies being turned off, all
the channels are turned off and only a leakage current of a
few nanoamperes flows.
The ADG508F switches one of eight inputs to a common output
as determined by the 3-bit binary address lines A0, A1, and A2.
The ADG509F switches one of four differential inputs to a
common differential output as determined by the 2-bit binary
address lines A0 and A1. An EN input on each device is used
to enable or disable the device. When disabled, all channels are
switched off.
2. On channel saturates while fault exists.
3. Low RON
.
4. Fast switching times.
5. Break-before-make switching. Switches are guaranteed
break-before-make so that input signals are protected
against momentary shorting.
6. Trench isolation eliminates latch-up. A dielectric trench
separates the p and n-channel MOSFETs thereby
preventing latch-up.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2011 Analog Devices, Inc. All rights reserved.
ADG508F/ADG509F
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................8
Terminology.................................................................................... 10
Theory of Operation ...................................................................... 11
Test Circuits..................................................................................... 12
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply................................................................................... 3
Truth Tables................................................................................... 4
REVISION HISTORY
7/11—Rev. E to Rev. F
Deleted ADG528F..............................................................Universal
Changes to Features Section and General Description Section. 1
Changes to Specifications Section.................................................. 3
Deleted Timing Diagrams Section................................................. 4
Changes to Table 4............................................................................ 5
Added Table 5.................................................................................... 6
Added Table 6.................................................................................... 7
Replaced Typical Performance Characteristics Section .............. 8
Changes to Terminology Section.................................................. 10
Changes to Figure 27 and Figure 28............................................. 13
Changes to Figure 31...................................................................... 14
Changes to Theory of Operation Section.................................... 11
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 17
7/09—Rev. D: Rev. E
Updated Format..................................................................Universal
Added TSSOP .....................................................................Universal
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01—Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table...................................................... 2
Max Ratings Changed...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12
Rev. F | Page 2 of 20
ADG508F/ADG509F
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
B Version
Parameter
+25°C
−40°C to +85°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS + 1.4
VDD − 1.4
VSS + 2.2
VDD – 2.2
270
V typ
V typ
V typ
V typ
Ω typ
Ω max
Output open circuit
Output loaded, 1 mA
RON
350
390
−10 V ≤ VS ≤ +10 V, IS = 1 mA;
VDD = +15 V 10ꢀ, VSS = −15 V 10ꢀ
See Figure 21
RON Drift
On-Resistance Match Between
Channels, ∆RON
0.6
3
ꢀ/°C typ
ꢀ max
VS = 0 V, IS = 1 mA
VS = 10 V, IS = −1 mA
LEAKAGE CURRENTS
Source Off Leakage IS (Off)
0.02
1
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = 10 V, VS = +10 V;
See Figure 22
VD = 10 V, VS = +10 V;
See Figure 23
50
0.04
1
1
0.04
1
1
Drain Off Leakage ID (Off)
ADG508F
ADG509F
Channel On Leakage ID, IS (On)
ADG508F
ADG509F
60
30
VS = VD = 10 V;
See Figure 24
60
30
FAULT
Source Leakage Current IS (Fault)
(With Overvoltage)
Drain Leakage Current ID (Fault)
(With Overvoltage)
0.02
nA typ
μA max
nA typ
μA max
VS = +55 V or −40 V, VD = 0 V, see Figure 25
VS = 25 V, VD = +10 V, see Figure 23
2
5
2
2
Source Leakage Current IS (Fault)
(Power Supplies Off)
1
2
nA typ
μA max
VS = 25 V, VD = VEN = A0, A1, A2 = 0 V
See Figure 26
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS1
tTRANSITION
2.4
0.8
1
V min
V max
μA max
pF typ
VIN = 0 or VDD
5
175
220
90
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
RL = 1 MΩ, CL = 35 pF;
VS1 = 10 V, VS8 = +10 V; see Figure 27
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; see Figure 28
RL = 1 kΩ, CL = 35 pF;
300
40
tOPEN
60
tON (EN)
tOFF (EN)
180
230
100
130
300
150
VS = 5 V; see Figure 29
RL = 1 kΩ, CL = 35 pF
tSETT, Settling Time
0.1ꢀ
0.01ꢀ
ns max
μs typ
μs typ
VS = 5 V; see Figure 29
RL = 1 kΩ, CL = 35 pF;
VS = 5 V
1
2.5
Rev. F | Page 3 of 20
ADG508F/ADG509F
B Version
Parameter
+25°C
15
93
−40°C to +85°C
Unit
Test Conditions/Comments
Charge Injection
Off Isolation
pC typ
dB typ
VS = 0 V, RS = 0 Ω, CL= 1 nF; see Figure 30
RL = 1 kΩ, CL = 15 pF, f = 100 kHz; VS = 7 V rms;
see Figure 31
CS (Off)
3
pF typ
CD (Off)
ADG508F
ADG509F
22
12
pF typ
pF typ
POWER REQUIREMENTS
IDD
ISS
0.05
0.1
0.2
1
mA max
ꢁA max
VIN = 0 V or 5 V
1 Guaranteed by design, not subject to production test.
TRUTH TABLES
Table 2. ADG508F Truth Table1
A2
X
0
0
0
0
1
1
1
A1
X
0
0
1
1
0
0
1
A0
X
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
On Switch
None
1
2
3
4
5
6
7
8
1
1
1
1
1 X = don’t care.
Table 3. ADG509F Truth Table1
A1
A0
EN
0
On Switch Pair
X
X
None
0
0
1
1
0
1
0
1
1
1
1
1
1
2
3
4
1 X = don’t care.
Rev. F | Page 4 of 20
ADG508F/ADG509F
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TA = 25°C unless otherwise noted.
Table 4.
Parameter
Rating
VDD to VSS
48 V
VDD to GND
VSS to GND
−0.3 V to +48 V
+0.3 V to −48 V
Digital Input, EN, Ax
−0.3 V to VDD + 0.3 V or
20 mA, whichever occurs first
VS, Analog Input Overvoltage with
Power On (VDD = +15 V, VSS = −15 V)
VS, Analog Input Overvoltage with
Power Off (VDD = 0 V, VSS = 0 V)
Continuous Current, S or D
Peak Current, S or D
(Pulsed at 1 ms, 10ꢀ Duty Cycle Max)
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
TSSOP
VSS − 25 V to VDD + 40 V
−40 V to +55 V
20 mA
ESD CAUTION
40 mA
−40°C to +85°C
−65°C to +150°C
150°C
θJA, Thermal Impedance
Plastic DIP Package
θJA, Thermal Impedance
16-Lead
112°C/W
117°C/W
SOIC Package
θJA, Thermal Impedance
Narrow Body
Wide Body
77°C/W
75°C/W
Rev. F | Page 5 of 20
ADG508F/ADG509F
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A0
EN
1
2
3
4
5
6
7
8
16 A1
15 A2
V
14 GND
SS
ADG508F
TOP VIEW
(Not to Scale)
S1
13
V
DD
S2
S3
S4
D
12 S5
11 S6
10 S7
9
S8
Figure 3. ADG508F Pin Configuration
Table 5. ADG508F Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
A0
EN
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3
VSS
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Rev. F | Page 6 of 20
ADG508F/ADG509F
A0
EN
1
2
3
4
5
6
7
8
16 A1
15 GND
V
14
V
DD
SS
ADG509F
TOP VIEW
(Not to Scale)
S1A
13 S1B
12 S2B
11 S3B
10 S4B
S2A
S3A
S4A
DA
9
DB
Figure 4. ADG509F Pin Configuration
Table 6. ADG509F Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
A0
EN
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3
VSS
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
S1A
S2A
S3A
S4A
DA
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Drain Terminal A. This pin can be an input or an output.
Drain Terminal B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Most Positive Power Supply Potential.
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
Ground (0 V) Reference.
Logic Control Input.
Rev. F | Page 7 of 20
ADG508F/ADG509F
TYPICAL PERFORMANCE CHARACTERISTICS
2000
2000
1750
1500
1250
1000
750
T
= 25°C
A
V
V
= +15V
= –15V
DD
SS
1750
1500
1250
1000
750
500
250
0
V
= +5V
= –5V
DD
SS
T
T
T
T
= 125°C
= 105°C
= 85°C
= 25°C
V
A
A
A
A
V
V
= +10V
= –10V
DD
SS
V
V
= +15V
= –15V
DD
SS
500
250
0
–15
–10
–5
0
5
10
15
–15
–10
–5
0
5
10
15
V
, V (V)
S
V
, V (V)
S
D
D
Figure 5. On Resistance as a Function of VD (VS)
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures
1m
100µ
10µ
1µ
1m
100µ
V
V
V
= 0V
= 0V
= 0V
DD
V
V
V
= +15V
= –15V
= 0V
DD
SS
SS
10µ
1µ
D
D
OPERATING RANGE
100n
10n
1n
100n
10n
1n
OPERATING RANGE
100p
10p
1p
100p
10p
1p
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
V
SOURCE VOLTAGE (V)
V
SOURCE VOLTAGE (V)
S
S
Figure 6. Source Input Leakage Current as a Function of VS (Power Supplies
Off) During Overvoltage Conditions
Figure 9. Source Input Leakage Current as a Function of VS (Power Supplies
On) During Overvoltage Conditions
0.3
1m
V
V
V
T
= +15V
= –15V
DD
SS
100µ
V
V
V
= +15V
= –15V
= 0V
DD
0.2
0.1
(V ) = ±10V
SS
S
D
10µ
1µ
= 25°C
D
A
100n
10n
1n
I
(OFF)
D
0.0
I
(OFF)
S
–0.1
–0.2
–0.3
OPERATING RANGE
100p
10p
1p
I
, I (ON)
S
D
–14
–10
–6
–2
2
6
10
14
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
V , V (V)
V
SOURCE VOLTAGE (V)
S
D
S
Figure 10. Leakage Currents as a Function of VD (VS)
Figure 7. Drain Output Leakage Current as a Function of VS (Power Supplies
On) During Overvoltage Conditions
Rev. F | Page 8 of 20
ADG508F/ADG509F
0
–20
100
10
T
V
V
= 25°C
A
= +15V
= –15V
DD
SS
V
V
V
V
= +15V
= –15V
= +10V
= –10V
DD
SS
D
S
–40
I
(OFF)
D
–60
1
I
(ON)
D
–80
I
(OFF)
0.1
0.01
S
–100
–120
1k
10k
100k
1M
10M
100M
1G
25
35
45
55
65
75
85
95
105 115 125
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 11. Leakage Currents as a Function of Temperature
Figure 14. Off Isolation vs. Frequency, 15 V Dual Supply
40
260
T
V
V
= 25°C
= +15V
A
35
30
25
20
15
10
5
DD
240
220
200
180
160
140
120
100
= –15V
SS
tTRANSITION
tON (EN)
DRAIN OFF
tOFF (EN)
SOURCE OFF
0
–15
–10
–5
0
5
10
15
10
11
12
13
14
15
V
(V)
POWER SUPPLY (V)
S
Figure 12. Switching Time vs. Dual Power Supply
Figure 15. Capacitance vs. Source Voltage
30
20
300
250
200
150
100
50
V
V
T
= +15V
V
V
= +15V
= –15V
DD
DD
SS
= –15V
SS
= 25°C
A
tON (EN)
10
tTRANSITION
0
–10
–20
–30
tOFF (EN)
0
–40
–15
–10
–5
0
5
10
15
–20
0
20
40
60
80
100
120
V
(V)
S
TEMPERATURE (°C)
Figure 16. Charge Injection vs. Source Voltage
Figure 13. Switching Time vs. Temperature
Rev. F | Page 9 of 20
ADG508F/ADG509F
TERMINOLOGY
CD (Off)
VDD
Channel output capacitance for off condition.
Most positive power supply potential.
CIN
VSS
Digital input capacitance.
Most negative power supply potential.
t
ON (EN)
GND
Delay time between the 50% and 90% points of the digital input
and switch on condition.
Ground (0 V) reference.
RON
t
OFF (EN)
Ohmic resistance between D and S.
Delay time between the 50% and 90% points of the digital input
and switch off condition.
RON Drift
Percentage change in RON when temperature changes by one
degree Celsius.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from
one address state to another.
ΔRON
ΔRON represents the difference between the RON of any two
channels as a percentage of the maximum RON of those two
channels.
tOPEN
Off time measured between 80% points of both switches when
switching from one address state to another.
IS (Off)
Source leakage current when the switch is off.
VINL
ID (Off)
Maximum input voltage for Logic 0.
Drain leakage current when the switch is off.
VINH
ID, IS (On)
Minimum input voltage for Logic 1.
Channel leakage current when the switch is on.
I
INL (IINH)
IS (Fault—Power Supplies On)
Source leakage current when exposed to an overvoltage
condition.
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling through an off channel.
ID (Fault—Power Supplies On)
Drain leakage current when exposed to an overvoltage
condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IS (Fault—Power Supplies Off)
Source leakage current with power supplies off.
IDD
Positive supply current.
VD (VS)
ISS
Analog Voltage on Terminals D, S.
Negative supply current.
CS (Off)
Channel input capacitance for off condition.
Rev. F | Page 10 of 20
ADG508F/ADG509F
THEORY OF OPERATION
The ADG508F/ADG509F multiplexers are capable of withstand-
ing overvoltages from −40 V to +55 V, irrespective of whether the
power supplies are present or not. Each channel of the multiplexer
consists of an n-channel MOSFET, a p-channel MOSFET, and an
n-channel MOSFET, connected in series. When the analog input
exceeds the power supplies, one of the MOSFETs will saturate
limiting the current. The current during a fault condition is
determined by the load on the output. Figure 17 illustrates
the channel architecture that enables these multiplexers to
withstand continuous overvoltages.
During fault conditions (power supplies off), the leakage
current into and out of the ADG508F/ADG509F is limited to
a few microamps. This protects the multiplexer and succeeding
circuitry from over stresses as well as protecting the signal
sources which drive the multiplexer. Also, the other channels
of the multiplexer will be undisturbed by the overvoltage and
will continue to operate normally.
Q1
Q2
Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET
SATURATES
When an analog input of VSS + 2.2 V to VDD − 2.2 V (output
loaded, 1 mA) is applied to the ADG508F/ADG509F, the
multiplexer behaves as a standard multiplexer, with spec-
ifications similar to a standard multiplexer, for example,
the on-resistance is 390 Ω maximum. However, when an
overvoltage is applied to the device, one of the three
MOSFETs saturate.
V
V
SS
DD
Figure 17. +55 V Overvoltage Input to the On Channel
Q1
Q2
Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET
IS ON
p-CHANNEL
MOSFET
SATURATES
Figure 17 to Figure 20 show the conditions of the three MOSFETs
for the various overvoltage situations. When the analog input
applied to an on channel approaches the positive power supply
line, the n-channel MOSFET saturates because the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more nega-
tive than VSS is applied to the multiplexer, the p-channel
MOSFET will saturate because the analog input is more
negative than the difference between VSS and the p-channel
threshold voltage (VTP). Because VTN is nominally 1.4 V and
V
V
DD
SS
Figure 18. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
Q1
Q2
Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
Figure 19. +55 V Overvoltage with Power Off
VTP −1.4 V, the analog input range to the multiplexer is limited
to VSS + 1.4 V to VDD – 1.4 V (output open circuit) when a
15 V power supply is used.
Q1
Q2
Q3
–40V
OVERVOLTAGE
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will remain off when an overvoltage occurs.
n-CHANNEL
MOSFET IS
ON
p-CHANNEL
MOSFET IS
OFF
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off because the gate to source voltage applied to this
MOSFET is negative.
Figure 20. −40 V Overvoltage with Power Off
Rev. F | Page 11 of 20
ADG508F/ADG509F
TEST CIRCUITS
I
DS
V1
I
(ON)
A
D
D
S
S
D
NC
V
S
V
D
NC = NO CONNECT
R
= V /I
1 DS
ON
Figure 24. ID (On)
Figure 21. On Resistance
V
V
V
V
DD
DD
SS
SS
V
V
V
V
DD
DD
SS
I
(OFF)
A
S
SS
S1
S2
S1
S2
A
D
D
V
S8
S
S8
EN
0.8V
EN
0.8V
V
D
V
V
D
S
Figure 22. IS (Off)
Figure 25. Input Leakage Current (with Overvoltage)
0V
0V
V
V
V
V
DD
DD
SS
SS
V
V
SS
DD
0V
A2
A
V
S
S1
A1ADG508F
S1
S2
I
(OFF)
A
A0
D
D
S8
D
EN
S8
V
D
EN
0.8V
GND
V
S
Figure 23. ID (Off)
Figure 26. Input Leakage Current (with Power Supplies Off)
Rev. F | Page 12 of 20
ADG508F/ADG509F
V
V
V
V
DD
SS
SS
3V
DD
A2
V
V
S1
S2 TO S7
ADDRESS
DRIVE (V
S1
S8
50%
50%
A1
A0
)
V
50Ω
IN
IN
ADG508F*S8
2.4V
EN
D
V
OUT
R
1MΩ
C
L
35pF
90%
L
GND
V
OUT
90%
*SIMILAR CONNECTION FOR ADG509F.
tTRANSITION
tTRANSITION
Figure 27. Switching Time of Multiplexer, tTRANSITION
V
V
V
V
DD
SS
3V
ADDRESS
SS
DRIVE (V
)
DD
IN
A2
V
S1
S2 TO S7
S
A1
V
50Ω
IN
A0
ADG508F*S8
D
V
OUT
80%
2.4V
EN
GND
V
80%
OUT
R
1kΩ
C
L
35pF
L
tOPEN
*
SIMILAR CONNECTION FOR ADG509F.
Figure 28. Break-Before-Make Delay, tOPEN
V
V
V
V
DD
SS
SS
3V
ENABLE
50%
50%
DRIVE (V
)
DD
IN
A2
V
S1
S2 TO S8
S
0V
A1
A0
ADG508F*
V
OUT
0.9V
OUT
D
V
OUT
EN
GND
OUTPUT
0V
R
1kΩ
C
L
35pF
L
V
50Ω
IN
0.1V
OUT
tOFF (EN)
tON (EN)
*SIMILAR CONNECTION FOR ADG509F.
Figure 29. Enable Delay, tON (EN), tOFF (EN)
Rev. F | Page 13 of 20
ADG508F/ADG509F
V
V
V
V
DD
DD
SS
3V
SS
A2
LOGIC
INPUT (V
)
A1
A0
S
IN
ADG508F*
0V
R
S
D
V
OUT
EN
C
1nF
V
L
S
∆V
V
OUT
OUT
GND
V
IN
Q
= C × ∆V
OUT
INJ
L
*SIMILAR CONNECTION FOR ADG509F.
Figure 30. Charge Injection
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
SS
DD
NC
50Ω
SA
SB
50Ω
IN
V
S
D
V
OUT
V
IN
R
L
50Ω
GND
V
V
OUT
OFF ISOLATION = 20 log
S
Figure 31. Off Isolation
Rev. F | Page 14 of 20
ADG508F/ADG509F
OUTLINE DIMENSIONS
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
16
1
9
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 32. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
0.50 (0.0197)
0.25 (0.0098)
45°
BSC
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 33. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
Rev. F | Page 15 of 20
ADG508F/ADG509F
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0
.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 34. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. F | Page 16 of 20
ADG508F/ADG509F
ORDERING GUIDE
Model1
ADG508FBNZ
ADG508FBRN
ADG508FBRNZ
ADG508FBRNZ–REEL7
ADG508FBRWZ
ADG508FBRWZ-REEL
ADG508FBRUZ
ADG508FBRUZ-REEL7
ADG509FBNZ
ADG509FBRN
ADG509FBRNZ
ADG509FBRNZ–REEL7
ADG509FBRWZ
ADG509FBRWZ-REEL
ADG509FBRUZ
ADG509FBRUZ-REEL7
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead PDIP
Package Option
N-16
R-16
R-16
R-16
RW-16
RW-16
RU-16
RU-16
N-16
R-16
R-16
R-16
RW-16
RW-16
RU-16
RU-16
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead TSSOP
16-Lead TSSOP
16-Lead PDIP
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_N
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead TSSOP
16-Lead TSSOP
1 Z = RoHS Compliant Part.
Rev. F | Page 17 of 20
ADG508F/ADG509F
NOTES
Rev. F | Page 18 of 20
ADG508F/ADG509F
NOTES
Rev. F | Page 19 of 20
ADG508F/ADG509F
NOTES
©2001–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00035-0-7/11(F)
Rev. F | Page 20 of 20
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