ADG509FBRN-REEL7 [ADI]
IC DUAL 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, MS-012AC, SOIC-16, Multiplexer or Switch;
| 型号： | ADG509FBRN-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC DUAL 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, MS-012AC, SOIC-16, Multiplexer or Switch 光电二极管 |
| 文件： | 总12页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4/8 Channel Fault-Protected
Analog Multiplexers
a
ADG508F/ADG509F/ADG528F*
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Low On Resistance (300 ⍀ Typ)
Fast Switching Times
tON 250 ns Max
ADG508F/ADG528F
ADG509F
tOFF 250 ns Max
S1
S1A
S4A
Low Power Dissipation (3.3 mW Max)
Fault and Overvoltage Protection (–40 V to +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped within Power
Supplies if an Overvoltage Occurs
Latch-Up Proof Construction
Break before Make Construction
TTL and CMOS Compatible Inputs
DA
DB
D
S1B
S4B
S8
WR
RS
ADG528F
ONLY
1 OF 8
DECODER
1 OF 4
DECODER
APPLICATIONS
Existing Multiplexer Applications (Both Fault-Protected
and Nonfault-Protected)
A0 A1 A2 EN
A1
A0
EN
New Designs Requiring Multiplexer Functions
2. ON channel turns off while fault exists.
3. Low RON.
GENERAL DESCRIPTION
The ADG508F, ADG509F, and ADG528F are CMOS analog
multiplexers, the ADG508F and ADG528F comprising eight
single channels and the ADG509F comprising four differential
channels. These multiplexers provide fault protection. Using a
series n-channel, p-channel, n-channel MOSFET structure,
both device and signal source protection is provided in the event
of an overvoltage or power loss. The multiplexer can withstand
continuous overvoltage inputs from –40 V to +55 V. During
fault conditions, the multiplexer input (or output) appears as an
open circuit and only a few nanoamperes of leakage current will
flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
4. Fast Switching Times.
5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p and n-channel MOSFETs
thereby preventing latch-up.
ORDERING GUIDE
Model
Temperature Range
Package Option*
The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1, and A2. The ADG509F switches one of four differen-
tial inputs to a common differential output as determined by the
2-bit binary address lines A0 and A1. The ADG528F has on-chip
address and control latches that facilitate microprocessor inter-
facing. An EN input on each device is used to enable or disable
the device. When disabled, all channels are switched OFF.
ADG508FBN
ADG508FBRN
ADG508FBRW
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16N
R-16W
ADG509FBN
ADG509FBRN
ADG509FBRW
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16N
R-16W
ADG528FBN
ADG528FBP
–40°C to +85°C
–40°C to +85°C
N-18
P-20A
PRODUCT HIGHLIGHTS
1. Fault Protection.
*N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); RN = 0.15" Small
Outline IC (SOIC), RW = 0.3" Small Outline IC (SOIC).
The ADG508F/ADG509F/ADG528F can withstand con-
tinuous voltage inputs from –40 V to +55 V. When a fault
occurs due to the power supplies being turned off, all the
channels are turned off and only a leakage current of a few
nanoamperes flows.
*Patent Pending.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: www.analog.com
© Analog Devices, Inc., 2001
ADG508F/ADG509F/ADG528F–SPECIFICATIONS
Dual Supply
(VDD = +15 V ؎ 10%, VSS = –15 V ؎ 10%, GND = 0 V, unless otherwise noted)
B Version
–40؇C to
+85؇C
Parameter
+25؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS + 3
VDD – 1.5
350
V min
V max
Ω typ
RON
300
–10 V < VS < +10 V, IS = 1 mA;
VDD = +15 V 10%, VSS = –15 V 10%
–10 V < VS < +10 V, IS = 1 mA;
VDD = +15 V 5%, VSS = –15 V 5%
VS = 0 V, IS = 1 mA
400
Ω max
RON Drift
RON Match
0.6
5
%/°C typ
% max
VS = 0 V, IS = 1 mA
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
0.02
1
0.04
1
1
0.04
1
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD
Test Circuit 2
VD 10 V, VS = ϯ10 V;
Test Circuit 3
= 10 V, VS = ϯ10 V;
50
Drain OFF Leakage ID (OFF)
ADG508F/ADG528F
ADG509F
Channel ON Leakage ID, IS (ON)
ADG508F/ADG528F
ADG509F
=
60
30
VS = VD = 10 V;
Test Circuit 4
60
30
1
FAULT
Output Leakage Current
(With Overvoltage)
Input Leakage Current
(With Overvoltage)
Input Leakage Current
(With Power Supplies OFF)
0.02
2
0.005
2
0.001
2
nA typ
µA max
µA typ
µA max
µA typ
µA max
VS = 33 V, VD = 0 V, Test Circuit 3
2
VS = 25 V, VD = ϯ10 V, Test Circuit 5
VS = 25 V, VD = VEN = A0, A1, A2 = 0 V
Test Circuit 6
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance
2.4
0.8
1
V min
V max
µA max
pF typ
VIN = 0 or VDD
5
DYNAMIC CHARACTERISTICS1
tTRANSITION
200
300
50
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
RL = 1 MΩ, CL = 35 pF;
400
10
VS1 = 10 V, VS8 = ϯ10 V; Test Circuit 7
tOPEN
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; Test Circuit 8
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; Test Circuit 9
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; Test Circuit 9
25
tON (EN, WR)
tOFF (EN, RS)
200
250
200
250
400
400
tSETT, Settling Time
0.1%
0.01%
1
2.5
µs typ
µs typ
RL = 1 kΩ, CL = 35 pF;
VS = 5 V
ADG528F Only
tW, Write Pulsewidth
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulsewidth
Charge Injection
100
120
100
10
ns min
ns min
ns min
ns min
pC typ
dB typ
dB min
pF typ
100
4
VS = 0 V, RS = 0 Ω, CL= 1 nF; Test Circuit 12
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 7 V rms; Test Circuit 13
OFF Isolation
68
50
5
CS (OFF)
CD (OFF)
ADG508F/ADG528F
ADG509F
50
25
pF typ
pF typ
POWER REQUIREMENTS
IDD
ISS
0.1
0.1
0.2
0.1
mA max
mA max
VIN = 0 V or 5 V
NOTES
1Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. D
ADG508F/ADG509F/ADG528F
Table I. ADG508F Truth Table
Table II. ADG509F Truth Table
A2
A1
A0
EN
ON Switch
A1
A0
EN
ON Switch Pair
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
NONE
1
2
3
4
5
6
7
8
1
2
3
4
X = Don’t Care
X = Don’t Care
Table III. ADG528F Truth Table
A2
A1
A0
EN
WR
RS
ON Switch
X
X
X
0
0
0
0
1
1
1
X
X
X
0
0
1
1
0
0
1
X
X
X
0
1
0
1
0
1
0
X
X
0
1
1
1
1
1
1
1
1
g
X
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
Retains Previous Switch Condition
NONE (Address and Enable Latches Cleared)
NONE
1
2
3
4
5
6
7
8
1
1
1
X = Don’t Care
TIMING DIAGRAMS (ADG528F)
3V
3V
RS
50%
50%
50%
WR
50%
0V
V
0V
tW
tRS
tOFF (RS)
tS
tH
O
3V
0V
0.8V
O
SWITCH
OUTPUT
2V
A0, A1, A2
EN
0.8V
0V
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turn-
off Time, tOFF (RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tR = tF = 20 ns.
REV. D
–3–
ADG508F/ADG509F/ADG528F
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
ADG508F/ADG509F PIN CONFIGURATIONS
DIP/SOIC
DIP/SOIC
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
DD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
VEN, VA Digital Input . . . . . . . – 0.3 V to VDD + 2 V or 20 mA,
Whichever Occurs First
1
2
16 A1
15 A2
A0
EN
1
2
16 A1
A0
EN
15 GND
V
3
4
5
6
7
8
14 GND
V
3
4
5
6
7
8
14 V
DD
SS
SS
VS, Analog Input Overvoltage with Power ON . . . . . VSS – 25 V
ADG508F
ADG509F
S1
13
12 S5
V
S1A
13 S1B
12 S2B
11 S3B
10 S4B
DD
to VDD + 40 V
TOP VIEW
TOP VIEW
S2
S3
S4
D
S2A
S3A
S4A
DA
(Not to Scale)
(Not to Scale)
VS, Analog Input Overvoltage with Power OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 V to +55 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
11
S6
10 S7
S8
9
9
DB
(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic Package
ADG528F PIN CONFIGURATIONS
DIP
PLCC
θJA, Thermal Impedance
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117°C
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C
SOIC Package
1
18
RS
WR
3
2
1
20 19
A0
EN
2
17 A1
18
4
5
6
7
8
EN
A2
3
4
5
6
7
8
9
16 A2
θJA, Thermal Impedance
17
16
15
14
V
GND
V
15 GND
SS
ADG528F
SS
ADG528F
Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77°C/W
Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
S1
TOP VIEW
V
S1
TOP VIEW
14 V
DD
DD
(Not to Scale)
(Not to Scale)
S2
S3
S5
S6
S2
13 S5
12 S6
11 S7
10 S8
S3
S4
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
PLCC Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
9
10 11 12 13
D
NC = NO CONNECT
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG508F/ADG509F/ADG528F features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–4–
ADG508F/ADG509F/ADG528F
TERMINOLOGY
Typical Performance Characteristics
VDD
VSS
Most Positive Power Supply Potential.
2000
Most Negative Power Supply Potential.
Ground (0 V) Reference.
T
= 25؇C
A
1750
1500
1250
1000
750
500
250
0
GND
RON
Ohmic Resistance between D and S.
RON Drift
Change in RON when temperature changes
by one degree Celsius.
V
V
= +5V
= –5V
DD
SS
R
ON Match
Difference between the RON of any two channels.
Source leakage current when the switch is off.
Drain leakage current when the switch is off.
Channel leakage current when the switch is on.
Analog Voltage on Terminals D, S.
IS (OFF)
V
V
= +10V
= –10V
DD
SS
ID (OFF)
ID, IS (ON)
V
DD
V
SS
= +15V
= –15V
V
D (VS)
–15
–10
–5
0
5
10
15
CS (OFF)
CD (OFF)
Channel input capacitance for “OFF” condition.
Channel output capacitance for “OFF” condition.
V
D
(V ) – V
S
TPC 1. On Resistance as a Function of VD (VS)
CD, CS (ON) “ON” Switch Capacitance.
CIN
Digital Input Capacitance.
1m
t
ON (EN)
Delay time between the 50% and 90% points of
the digital input and switch “ON” condition.
V
V
V
= 0V
= 0V
= 0V
100
10
1
DD
SS
t
OFF (EN)
Delay time between the 50% and 90% points of
the digital input and switch “OFF” condition.
D
tTRANSITION
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
100n
10n
1n
OPERATING RANGE
tOPEN
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
100p
10p
1p
VINL
VINH
Maximum input voltage for Logic “0”.
Minimum input voltage for Logic “1”.
Input current of the digital input.
–50 –40 –30 –20 –10
0
10
20
30 40
50
60
V
IN
– INPUT VOLTAGE – V
TPC 2. Input Leakage Current as a Function of VS
(Power Supplies OFF) During Overvoltage Conditions
I
INL (IINH)
Off Isolation
A measure of unwanted signal coupling
through an “OFF” channel.
Charge
Injection
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
1m
V
V
V
= +15V
= –15V
= 0V
DD
100
10
1
SS
D
IDD
ISS
Positive Supply Current.
Negative Supply Current.
100n
10n
1n
OPERATING RANGE
100p
10p
1p
–50 –40 –30 –20 –10
0
10
20
30 40 50
60
V
IN
– INPUT VOLTAGE – V
TPC 3. Output Leakage Current as a Function of VS
(Power Supplies ON) During Overvoltage Conditions
REV. D
–5–
ADG508F/ADG509F/ADG528F
100
10
2000
1750
V
V
= +15V
= –15V
= +10V
= –10V
DD
V
V
= +15V
= –15V
DD
SS
SS
1500
1250
1000
750
500
250
0
V
V
D
S
I
D
(OFF)
1
I
S
(OFF)
125 C
85 C
0.1
I
D
(ON)
25 C
0.01
25
35
45
55
65
75
85
95
105 115 125
–15
–10
–5
0
5
10
15
TEMPERATURE – ؇C
V
D
(V ) – V
S
TPC 4. On Resistance as a Function of VD (VS) for
Different Temperatures
TPC 7. Leakage Currents as a Function of Temperature
1m
260
V
= 2V
IN
V
V
V
= +15V
= –15V
= 0V
100
10
1
DD
240
220
200
180
160
140
120
100
SS
D
tON (EN)
100n
10n
1n
tTRANSITION
OPERATING RANGE
100p
10p
1p
tOFF (EN)
–50 –40 –30 –20 –10
0
10
20 30
40 50
60
10
11
12
V
13
– V
14
15
V
IN
– INPUT VOLTAGE – V
SUPPLY
TPC 5. Input Leakage Current as a Function of VS
(Power Supplies ON) During Overvoltage Conditions
TPC 8. Switching Time vs. Power Supply
0.3
280
260
240
220
200
180
160
140
120
100
V
V
V
= +15V
= –15V
= +5V
DD
V
V
= +15V
= –15V
= 25؇C
DD
SS
0.2
0.1
SS
tON (EN)
IN
T
A
I
S
(OFF)
I
(OFF)
D
tTRANSITION
0.0
I
(ON)
D
–0.1
–0.2
tOFF (EN)
105
–14
–10
–6
–2
2
6
10
14
25
45
65
85
125
V , V – V
TEMPERATURE – ؇C
S
D
TPC 6. Leakage Currents as a Function of VD (VS)
TPC 9. Switching Time vs. Temperature
REV. D
–6–
ADG508F/ADG509F/ADG528F
THEORY OF OPERATION
threshold voltage (VTN). When a voltage more negative than VSS
is applied to the multiplexer, the p-channel MOSFET will turn
off since the analog input is more negative than the difference
between VSS and the p-channel threshold voltage (VTP). Since
VTN is nominally 1.5 V and VTP is typically 3 V, the analog
input range to the multiplexer is limited to –12 V to +13.5 V
when a 15 V power supply is used.
The ADG508F/ADG509F/ADG528F multiplexers are capable
of withstanding overvoltages from –40 V to +55 V, irrespective
of whether the power supplies are present or not. Each channel of
the multiplexer consists of an n-channel MOSFET, a p-channel
MOSFET, and an n-channel MOSFET, connected in series.
When the analog input exceeds the power supplies, one of the
MOSFETs will switch off, limiting the current to submicroamp
levels, thereby preventing the overvoltage from damaging any
circuitry following the multiplexer. Figure 3 illustrates the channel
architecture that enables these multiplexers to withstand
continuous overvoltages.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the
series will remain off since the gate to source voltage applied to
this MOSFET is negative.
When an analog input of VSS + 3 V to VDD – 1.5 V is applied to
the ADG508F/ADG509F/ADG528F, the multiplexer behaves
as a standard multiplexer, with specifications similar to a stan-
dard multiplexer, for example, the on-resistance is 400 Ω
maximum. However, when an overvoltage is applied to the
device, one of the three MOSFETs will turn off.
During fault conditions, the leakage current into and out of the
ADG508F/ADG509F/ADG528F is limited to a few microamps.
This protects the multiplexer and succeeding circuitry from
over stresses as well as protecting the signal sources which
drive the multiplexer. Also, the other channels of the multi-
plexer will be undisturbed by the overvoltage and will continue
to operate normally.
Figures 3 to 6 show the conditions of the three MOSFETs for
the various overvoltage situations. When the analog input applied
to an ON channel approaches the positive power supply line, the
n-channel MOSFET turns OFF since the voltage on the analog
input exceeds the difference between VDD and the n-channel
Q1
Q2
Q3
+55V
OVERVOLTAGE
Q1
Q2
Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
n-CHANNEL
MOSFET IS
OFF
V
V
SS
DD
Figure 5. +55 V Overvoltage with Power OFF
Figure 3. +55 V Overvoltage Input to the ON Channel
Q1
Q2
Q3
–40V
OVERVOLTAGE
Q1
Q2
Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
n-CHANNEL
MOSFET IS
ON
p-CHANNEL
MOSFET IS
OFF
p-CHANNEL
MOSFET IS
OFF
V
V
DD
SS
Figure 6. –40 V Overvoltage with Power OFF
Figure 4. –40 V Overvoltage on an OFF Channel with
Multiplexer Power ON
REV. D
–7–
ADG508F/ADG509F/ADG528F
Test Circuits
I
V
DD
V
V
DS
SS
V
DD
SS
I
D
(ON)
A
D
S1
S2
S8
V1
V
D
D
S
2.4V
EN
V
S
V
S
R
ON
= V /I
1 DS
Test Circuit 4. ID (ON)
Test Circuit 1. On Resistance
V
DD
V
SS
V
DD
V
SS
V
V
DD
SS
S1
S2
S8
A
D
V
V
SS
DD
I
S
(OFF)
A
S1
S2
S8
V
D
EN
0.8V
D
V
S
V
S
0.8V
EN
V
D
Test Circuit 5. Input Leakage Current
(with Overvoltage)
Test Circuit 2. IS (OFF)
0V
0V
V
V
DD
SS
V
V
DD
SS
0V
A2
A1
A0
EN
RS
A
V
S
S1
ADG528F
*
S8
V
V
DD
SS
S1
S2
S8
I
D
(OFF)
A
D
D
WR
GND
V
D
0.8V
EN
V
S
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 6. Input Leakage Current
(with Power Supplies OFF)
Test Circuit 3. ID (OFF)
V
V
V
V
DD
SS
3V
ADDRESS
SS
DD
50%
50%
DRIVE (V
)
IN
A2
V
S1
S1
A1
A0
V
IN
50⍀
S2–S7
V
S8
S8
ADG528F
*
2.4V
EN
90%
D
V
OUT
RS
C
35pF
R
1M⍀
L
V
OUT
L
GND
WR
90%
tTRANSITION
tTRANSITION
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 7. Switching Time of Multiplexer, tTRANSITION
REV. D
–8–
ADG508F/ADG509F/ADG528F
V
DD
V
SS
3V
ADDRESS
V
V
SS
DD
DRIVE (V
)
IN
A2
A1
A0
V
C
S1
S2–S7
S
V
IN
50⍀
ADG528F
*
S8
RS
D
V
OUT
2.4V
EN
80%
V
80%
R
1k⍀
OUT
L
L
GND
WR
35pF
tOPEN
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 8. Break-Before-Make Delay, tOPEN
V
V
V
V
SS
DD
3V
ENABLE
SS
DD
50%
50%
DRIVE (V
)
IN
A2
S1
S2–S8
V
S
A1
A0
0V
tOFF (EN)
ADG528F
*
RS
2.4V
V
O
0.9V
0.9V
O
O
EN
D
V
OUT
C
35pF
R
1k⍀
L
OUTPUT
L
V
IN
50⍀
WR
GND
0V
tON (EN)
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 9. Enable Delay, tON (EN), tOFF (EN)
V
V
V
V
SS
DD
3V
WR
DD
SS
50%
A2
V
S1
S2–S8
ADG528F
S
A1
A0
0V
tON (WR)
2.4V
EN
RS
WR
V
O
D
V
OUT
C
35pF
R
L
OUTPUT
0V
L
GND
1k⍀
0.2V
V
RS
V
WR
O
Test Circuit 10. Write Turn-On Time, tON (WR)
REV. D
–9–
ADG508F/ADG509F/ADG528F
V
V
DD
SS
3V
RS
0V
V
SS
V
A2
DD
50%
50%
V
S1
S2–S8
ADG528F
S
A1
A0
tRS
tOFF (RS)
EN
2.4V
IN
V
O
D
V
OUT
RS
0.8V
O
C
35pF
R
1k⍀
L
SWITCH
OUTPUT
L
GND
WR
V
0V
Test Circuit 11. Reset Turn-Off Time, tOFF (RS)
V
V
V
V
SS
DD
DD
3V
SS
A2
LOGIC
INPUT (V
RS
2.4V
C
)
A1
IN
ADG528F
*
A0
S
0V
R
S
S
D
V
OUT
EN
L
V
1nF
V
⌬V
OUT
OUT
GND
WR
V
IN
Q
= C x ⌬V
L OUT
INJ
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 12. Charge Injection
V
DD
V
DD
S1
S8
A2
A1
A0
V
IN
ADG528F
*
RS
2.4V
D
V
OUT
EN
R
L
V
SS
GND WR
1k⍀
V
SS
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 13. OFF Isolation
REV. D
–10–
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic (N-16)
16-Lead SOIC (R-16N)
(Narrow Body)
0.840 (21.34)
0.745 (18.92)
0.3937 (10.00)
0.3859 (9.80)
16
9
8
0.280 (7.11)
0.240 (6.10)
1
9
16
0.325 (8.25)
0.300 (7.62)
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
1
8
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
PIN 1
MAX
0.160 (4.06)
0.115 (2.93)
0.0688 (1.75)
0.0532 (1.35)
0.130
(3.30)
MIN
0.050 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25)
؋
45؇ 0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
8؇
0؇
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
0.0500 (1.27)
0.0160 (0.41)
0.0099 (0.25)
0.0075 (0.19)
16-Lead SOIC (R-16W)
(Wide Body)
0.4133 (10.50)
0.3977 (10.00)
16
9
8
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.050 (1.27)
BSC
؋
45؇ 8؇
0؇
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
REV. D
–11–
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18-Lead Plastic (N-18)
20-Lead PLCC (P-20A)
0.180 (4.57)
0.165 (4.19)
0.925 (23.49)
0.845 (21.47)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
18
1
10
9
0.280 (7.11)
0.240 (6.10)
0.048 (1.21)
0.042 (1.07)
3
19
0.325 (8.25)
0.300 (7.62)
0.021 (0.53)
0.013 (0.33)
0.195 (4.95)
0.115 (2.93)
4
8
18
PIN 1
0.050
(1.27)
BSC
IDENTIFIER
PIN 1
0.330 (8.38)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
TOP VIEW
(PINS DOWN)
0.032 (0.81)
0.026 (0.66)
0.210
(5.33)
MAX
14
13
0.130
(3.30)
MIN
9
0.160 (4.06)
0.115 (2.93)
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.356 (9.04)
SQ
0.350 (8.89)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.110 (2.79)
0.085 (2.16)
0.395 (10.02)
0.385 (9.78)
SQ
ADG508F/ADG509F/ADG528F–Revision History
Location
Page
Data Sheet changed from REV. C to REV. D.
Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MAX RATINGS changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted 16-Lead Cerdip from Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Deleted 18-Lead Cerdip from Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REV. D
–12–
相关型号：
ADG509FBRW-REEL
IC 4-CHANNEL, DIFFERENTIAL MULTIPLEXER, PDSO16, MS-013AA, SOIC-16, Multiplexer or Switch
ADI
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