ADG5412F [ADI]
Fault Protection and Detection, 10 ohm RON, Quad SPST Switches;
| 型号： | ADG5412F |
| 厂家： | 
ADI |
| 描述： | Fault Protection and Detection, 10 ohm RON, Quad SPST Switches |
| 文件： | 总28页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Fault Protection and Detection,
10 Ω RON, Quad SPST Switches
ADG5412F/ADG5413F
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Low on resistance: 10 Ω
ADG5412F
D1
D2
D3
D4
S1
S2
S3
S4
On-resistance flatness of 0.5 Ω
5.5 kV human body model (HBM) ESD rating
Latch-up immune under any circumstance
Known state without digital inputs present
FAULT
DETECTION
+ SWITCH
DRIVER
FF
V
SS to VDD analog signal range
5 V to 22 V dual supply operation
8 V to 44 V single-supply operation
Fully specified at 15 V, 20 V, +12 V, and +36 V
IN1 IN2 IN3 IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1. ADG5412F
APPLICATIONS
ADG5413F
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
D1
D2
D3
D4
S1
S2
S3
S4
Automatic test equipment
Communication systems
Relay replacement
FAULT
DETECTION
+ SWITCH
DRIVER
FF
IN1 IN2 IN3 IN4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 2. ADG5413F
GENERAL DESCRIPTION
The ADG5412F and ADG5413F contain four independently
controlled single-pole/single-throw (SPST) switches. The
ADG5412F has four switches that turn on with Logic 1 inputs.
The ADG5413F has two switches that turn on and two switches
that turn off with Logic 1 inputs. Each switch conducts equally
well in both directions when on, and each switch has an input
signal range that extends to the supplies. The digital inputs are
compatible with 3 V logic inputs over the full operating supply
range.
The low on resistance of these switches, combined with
on-resistance flatness over a significant portion of the signal
range make them an ideal solution for data acquisition and gain
switching applications where excellent linearity and low
distortion are critical.
PRODUCT HIGHLIGHTS
1. Source pins are protected against voltages greater than the
supply rails, up to −55 V and +55 V.
2. Source pins are protected against voltages between −55 V
and +55 V in an unpowered state.
3. Overvoltage detection with digital output indicates
operating state of switches.
4. Trench isolation guards against latch-up.
5. Optimized for low on resistance and on-resistance flatness.
6. The ADG5412F/ADG5413F can be operated from a dual
supply of 5 V up to 22 V or a single power supply of 8 V
up to 44 V.
When no power supplies are present, the switch remains in the off
condition, and the switch inputs are high impedance. Under
normal operating conditions, if the analog input signal levels on
any Sx pin exceed VDD or VSS by a threshold voltage, VT, the
switch turns off. Input signal levels up to +55 V or −55 V relative to
ground are blocked, in both the powered and unpowered
condition.
Rev. B
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ADG5412F/ADG5413F
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 19
Terminology.................................................................................... 23
Theory of Operation ...................................................................... 25
Switch Architecture.................................................................... 25
Fault Protection .......................................................................... 26
Applications Information .............................................................. 27
Power Supply Rails ..................................................................... 27
Power Supply Sequencing Protection...................................... 27
Signal Range................................................................................ 27
Low Impedance Channel Protection....................................... 27
High Voltage Surge Suppression .............................................. 27
Intelligent Fault Detection ........................................................ 27
Large Voltage, High Frequency Signals................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
20 V Dual Supply ....................................................................... 5
12 V Single Supply........................................................................ 7
36 V Single Supply........................................................................ 9
Continuous Current per Channel, Sx or Dx........................... 11
Absolute Maximum Ratings.......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 14
REVISION HISTORY
1/16—Rev. A to Rev. B
Changes to Table 6.......................................................................... 12
Added Figure 4, Renumbered Sequentially ................................ 13
Changes to Table 7.......................................................................... 13
Changes to Figure 19...................................................................... 16
Changes to Figure 35...................................................................... 19
Changes to Figure 50...................................................................... 25
Changes to Applications Information Section ........................... 27
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide.......................................................... 28
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 7
Changes to Table 4............................................................................ 9
Changes to Switch Architecture Section ..................................... 25
3/15—Rev. 0 to Rev. A
Added 16-Lead LFCSP.......................................................Universal
Changes to Drain Leakage Current, ID/With Overvoltage
Parameter, Table 3............................................................................. 7
Changes to Drain Leakage Current, ID/With Overvoltage
Parameter, Table 4............................................................................. 9
7/14—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
ADG5412F/ADG5413F
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
−40°C to −40°C to
Parameter
+25°C
+85°C
+125°C
VDD to VSS
16.5
16
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 13.5 V, VSS = −13.5 V, see Figure 32
VS = 10 V, IS = −10 mA
VS = 9 V, IS = −10 mA
V
10
11.2
9.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
14
10.7
13.5
0.6
0.5
1.1
0.5
On-Resistance Match Between Channels, ∆RON 0.05
VS = 10 V, IS = −10 mA
VS = 9 V, IS = −10 mA
0.5
0.05
0.35
0.6
0.9
0.1
0.4
0.7
0.7
0.5
On-Resistance Flatness, RFLAT(ON)
VS = 10 V, IS = −10 mA
VS = 9 V, IS = −10 mA
1.1
0.5
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
See Figure 28
VDD = 16.5 V, VSS = −16.5 V
VS = 10 V, VD = ∓10 V, see Figure 33
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
1.5
0.1
1.5
0.3
1.5
5.0
5.0
2.0
21
18
4.5
Drain Off Leakage, ID (Off)
VS = 10 V, VD = ∓10 V, see Figure 33
Channel On Leakage, ID (On), IS (On)
VS = VD = 10 V, see Figure 34
FAULT
Source Leakage Current, IS
With Overvoltage
78
40
µA typ
µA typ
VDD = 16.5 V, VSS = 16.5 V, GND = 0 V, VS =
55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or floating,
GND = 0 V, INx = 0 V or floating, VS =
55 V, see Figure 38
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
2.0
nA typ
VDD = 16.5 V, VSS = 16.5 V, GND = 0 V, VS =
55 V, see Figure 37
8.0
10
15
49
nA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = 55 V,
INx = 0 V, see Figure 38
30
10
50
10
100
10
nA max
µA typ
VDD = floating, VSS = floating, GND = 0 V,
VS = 55 V, INx = 0 V, see Figure 38
DIGITAL INPUTS/OUTPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
5.0
2.0
0.8
V max
Rev. B | Page 3 of 28
ADG5412F/ADG5413F
Data Sheet
−40°C to −40°C to
Parameter
+25°C
+85°C
+125°C
Unit
Test Conditions/Comments
DYNAMIC CHARACTERISTICS1
tON
400
495
410
510
285
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
525
545
550
555
tOFF
Break-Before-Make Time Delay, tD
(ADG5413F Only)
185
630
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
dB typ
% typ
VS1 = VS2 = 10 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
460
585
720
930
85
615
RL = 1 kΩ, CL = 2 pF, see Figure 42
1050
1100
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
60
600
−680
−70
−90
0.0015
CL = 10 pF, RPULLUP = 1 kΩ, see Figure 45
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to
20 kHz, see Figure 40
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−3 dB Bandwidth
Insertion Loss
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
270
−0.72
13
12
24
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 39
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 16.5 V, VSS = −16.5 V, GND = 0 V,
digital inputs = 0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
1.8
5
22
VDD/VSS
GND = 0 V
GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
Rev. B | Page 4 of 28
Data Sheet
ADG5412F/ADG5413F
20 V DUAL SUPPLY
VDD = 20 V 10%, VSS = −20 V 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
−40°C to
+85°C
−40°C to
+125°C
Parameter
+25°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 18 V, VSS = −18 V, see Figure 32
VDD to VSS
16.5
16.5
0.5
V
10
11.5
9.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
VS = 15 V, IS = −10 mA
VS = 13.5 V, IS = −10 mA
VS = 15 V, IS = −10 mA
VS = 13.5 V, IS = −10 mA
VS = 15 V, IS = −10 mA
VS = 13.5 V, IS = −10 mA
14.5
14
11
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
0.05
0.35
0.05
0.35
1.0
1.4
0.1
0.4
0.7
0.5
0.5
1.5
0.5
0.5
1.5
0.5
Threshold Voltage, VT
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
See Figure 28
VDD = 22 V, VSS = −22 V
VS = 15 V, VD = ∓15 V, see Figure 33
0.1
1.5
0.1
1.5
0.3
1.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
5.0
5.0
2.0
21
18
4.5
Drain Off Leakage, ID (Off)
VS = 15 V, VD = ∓15 V, see Figure 33
Channel On Leakage, ID (On), IS (On)
VS = VD = 15 V, see Figure 34
FAULT
Source Leakage Current, IS
With Overvoltage
78
40
µA typ
µA typ
VDD = 22 V, VSS = −22 V, GND = 0 V,
VS = 55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS = 55 V, see Figure 38
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
5.0
nA typ
VDD = +22 V, VSS = −22 V, GND = 0 V,
VS = 55 V, see Figure 37
1.0
10
1.0
1.0
µA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = 55
V, INx = 0 V, see Figure 38
30
10
50
10
100
10
nA max
µA typ
VDD = floating, VSS = floating, GND =
0 V, VS = 55 V, INx = 0 V, see Figure 38
DIGITAL INPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
5.0
2.0
0.8
V max
Rev. B | Page 5 of 28
ADG5412F/ADG5413F
Data Sheet
−40°C to
+85°C
−40°C to
+125°C
Parameter
DYNAMIC CHARACTERISTICS1
+25°C
Unit
Test Conditions/Comments
tON
400
500
415
515
295
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 47
RL = 300 Ω, CL = 35 pF
530
550
555
565
tOFF
Break-Before-Make Time Delay, tD
(ADG5413F Only)
200
515
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
dB typ
VS1 = VS2 = 10 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
370
480
840
1200
85
500
RL = 1 kΩ, CL = 2 pF, see Figure 42
1400
1700
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see Figure 45
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
60
600
−640
−70
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
−90
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to
20 kHz, see Figure 40
Total Harmonic Distortion Plus Noise, THD + N
0.001
−3 dB Bandwidth
Insertion Loss
270
−0.73
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 39
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
12
11
23
pF typ
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 22 V, VSS = −22 V, digital inputs =
0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
1.8
5
22
VDD/VSS
GND = 0 V
GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
Rev. B | Page 6 of 28
Data Sheet
ADG5412F/ADG5413F
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 10.8 V, VSS = 0 V, see Figure 32
0 V to VDD
37
V
22
24.5
10
11.2
0.05
0.5
0.05
0.5
12.5
14.5
0.6
0.9
0.7
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VS = 3.5 V to 8.5 V, IS = −10 mA
31
14
16.5
0.7
On-Resistance Match Between Channels, ∆RON
On-Resistance Flatness, RFLAT(ON)
0.6
0.6
19
0.7
23
1.1
1.3
Threshold Voltage, VT
LEAKAGE CURRENTS
See Figure 28
VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.1
nA typ
VS = 1 V/10 V, VD = 10 V/1 V, see
Figure 33
1.5
0.1
5.0
21
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V, see
Figure 33
1.5
0.3
1.5
5.0
2.0
18
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/10 V, see Figure 34
4.5
FAULT
Source Leakage Current, IS
With Overvoltage
78
40
µA typ
µA typ
VDD = 13.2 V, VSS = 0 V, GND = 0 V,
VS = 55 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS = 55 V, see Figure 38
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
2.0
nA typ
VDD = 13.2 V, VSS = 0 V,
GND = 0 V, VS = 55 V, see
Figure 37
8.0
10
15
49
nA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V,
VS = 55 V, INx = 0 V, see Figure 38
30
10
50
10
100
10
nA max
µA typ
VDD = floating, VSS = floating, GND
= 0 V, VS = 55 V, INx = 0 V, see
Figure 38
DIGITAL INPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
5.0
2.0
0.8
V max
Rev. B | Page 7 of 28
ADG5412F/ADG5413F
Data Sheet
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
DYNAMIC CHARACTERISTICS1
Unit
Test Conditions/Comments
tON
400
485
375
460
260
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 47
RL = 300 Ω, CL = 35 pF
515
495
540
520
tOFF
Break-Before-Make Time Delay, tD
(ADG5413F Only)
170
720
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
VS1 = VS2 = 8 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
560
660
640
800
85
700
865
RL = 1 kΩ, CL = 2 pF, see Figure 42
960
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see
Figure 45
60
600
Charge Injection, QINJ
−340
−65
pC typ
dB typ
dB typ
% typ
VS = 6 V, RS = 0 Ω, CL = 1 nF, see
Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 36
RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz
to 20 kHz, see Figure 40
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N
−90
0.007
−3 dB Bandwidth
Insertion Loss
270
−0.74
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 39
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
16
15
25
pF typ
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V, VSS = 0 V, digital
inputs = 0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = 55 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
Digital inputs = 5 V
VS = 55 V, VD = 0 V
GND = 0 V
1.8
8
VDD
44
V max
GND = 0 V
1 Guaranteed by design; not subject to production test.
Rev. B | Page 8 of 28
Data Sheet
ADG5412F/ADG5413F
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD = 32.4 V, VSS = 0 V, see Figure 32
0 V to VDD
37
V
22
24.5
10
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
V typ
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VS = 4.5 V to 28 V, IS = −10 mA
31
11
14
16.5
0.7
On-Resistance Match Between Channels, ∆RON 0.05
0.5
0.05
0.35
12.5
14.5
0.1
0.6
0.5
19
0.5
On-Resistance Flatness, RFLAT(ON)
23
0.4
0.7
0.5
0.5
Threshold Voltage, VT
LEAKAGE CURRENTS
See Figure 28
VDD =39.6 V, VSS = 0 V
Source Off Leakage, IS (Off)
0.1
1.5
0.1
1.5
0.3
1.5
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 33
5.0
21
18
4.5
Drain Off Leakage, ID (Off)
VS = 1 V/30 V, VD = 30 V/1 V, see Figure 33
VS = VD = 1 V/30 V, see Figure 34
5.0
2.0
Channel On Leakage, ID (On), IS (On)
FAULT
Source Leakage Current, IS
With Overvoltage
78
40
µA typ
µA typ
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS =
+55 V, −40 V, see Figure 37
VDD = 0 V or floating, VSS = 0 V or
floating, GND = 0 V, INx = 0 V or
floating, VS = +55 V, −40 V, see Figure 38
Power Supplies Grounded or Floating
Drain Leakage Current, ID
With Overvoltage
2.0
nA typ
VDD = 39.6 V, VSS = 0 V,
GND = 0 V, VS = +55 V, −40 V, see
Figure 37
8.0
10
15
49
nA max
nA typ
Power Supplies Grounded
Power Supplies Floating
VDD = 0 V, VSS = 0 V, GND = 0 V, VS = +55
V, −40 V, INx = 0 V, see Figure 38
30
10
50
10
100
10
nA max
µA typ
VDD = floating, VSS = floating, GND =
0 V, VS = +55 V, −40 V, INx = 0 V, see
Figure 38
DIGITAL INPUTS
Input Voltage High, VINH
Input Voltage Low, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
V min
0.7
VIN = VGND or VDD
1.2
Digital Input Capacitance, CIN
Output Voltage High, VOH
Output Voltage Low, VOL
5.0
2.0
0.8
V max
Rev. B | Page 9 of 28
ADG5412F/ADG5413F
Data Sheet
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
DYNAMIC CHARACTERISTICS1
Unit
Test Conditions/Comments
tON
400
490
375
460
285
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 47
RL = 300 Ω, CL = 35 pF
VS = 18 V, see Figure 47
RL = 300 Ω, CL = 35 pF
520
485
545
510
tOFF
Break-Before-Make Time Delay, tD
(ADG5413F Only)
195
375
ns min
ns typ
ns max
ns typ
ns max
ns typ
µs typ
ns typ
pC typ
VS1 = VS2 = 18 V, see Figure 46
RL = 1 kΩ, CL = 2 pF, see Figure 41
Overvoltage Response Time, tRESPONSE
Overvoltage Recovery Time, tRECOVERY
250
350
1500
2000
85
60
600
−610
360
RL = 1 kΩ, CL = 2 pF, see Figure 42
2300
2700
115
85
Interrupt Flag Response Time, tDIGRESP
Interrupt Flag Recovery Time, tDIGREC
CL = 10 pF, see Figure 43
CL = 10 pF, see Figure 44
CL = 10 pF, RPULLUP = 1 kΩ, see Figure 45
VS = 18 V, RS = 0 Ω, CL = 1 nF, see
Figure 48
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 36
RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to
20 kHz, see Figure 40
Charge Injection, QINJ
Off Isolation
−70
−90
dB typ
dB typ
% typ
Channel-to-Channel Crosstalk
Total Harmonic Distortion Plus Noise, THD + N 0.001
−3 dB Bandwidth
Insertion Loss
270
−0.75
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, see Figure 39
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see
Figure 39
CS (Off)
CD (Off)
CD (On), CS (On)
POWER REQUIREMENTS
12
11
23
pF typ
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V, VSS = 0 V, digital inputs =
0 V, 5 V, or VDD
Normal Mode
IDD
0.9
1.2
0.4
0.55
0.5
mA typ
mA max
mA typ
mA max
mA typ
mA max
1.3
0.6
0.7
IGND
ISS
0.65
Fault Mode
IDD
VS = +55 V, −40 V
1.2
1.6
0.8
1.0
0.5
1.0
mA typ
mA max
mA typ
mA max
mA typ
mA max
V min
1.8
1.1
IGND
ISS
1.8
8
44
VDD
GND = 0 V
GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
Rev. B | Page 10 of 28
Data Sheet
ADG5412F/ADG5413F
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
25°C
85°C
125°C
Unit
Test Conditions/Comments
16-LEAD TSSOP
θJA = 112.6°C/W
83
64
59
48
39
29
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
16-LEAD LFCSP
θJA = 30.4°C/W
152
118
99
80
61
52
mA max
mA max
VS = VSS + 4.5 V to VDD − 4.5 V
VS = VSS to VDD
Rev. B | Page 11 of 28
ADG5412F/ADG5413F
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Sx Pins
Sx to VDD or VSS
VS to VD
Dx Pins1
Rating
48 V
−0.3 V to +48 V
−48 V to +0.3 V
−55 V to +55 V
80 V
Only one absolute maximum rating can be applied at any
one time.
80 V
VSS − 0.7 V to VDD + 0.7 V or
30 mA, whichever occurs first
ESD CAUTION
Digital Inputs
GND − 0.7 V to +48 V or
30 mA, whichever occurs first
Peak Current, Sx or Dx Pins
288 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current, Sx or Dx Pins Data2 + 15%
Digital Output
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
−40°C to +125°C
−65°C to +150°C
150°C
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer Board)
16-Lead LFCSP (4-Layer Board)
112.6°C/W
30.4°C/W
Reflow Soldering Peak
Temperature, Pb-Free
As per JEDEC J-STD-020
ESD (HBM: ANSI/ESD STM5.1-2007)
I/O Port to Supplies
I/O Port to I/O Port
5.5 kV
5.5 kV
5.5 kV
All Other Pins
1 Overvoltages at the Dx pins are clamped by internal diodes. Limit current to
the maximum ratings given.
2 See Table 5.
Rev. B | Page 12 of 28
Data Sheet
ADG5412F/ADG5413F
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
D1
S1
IN2
D2
S2
V
S1
1
2
3
4
12 S2
11
ADG5412F/
ADG5413F
TOP VIEW
(Not to Scale)
V
V
V
SS
DD
ADG5412F/
SS
DD
ADG5413F
GND
FF
S3
D3
IN3
10
9
GND
FF
S3
TOP VIEW
(Not to Scale)
S4
D4
S4
IN4
NOTES:
1. THE EXPOSED PAD IS INTERNALLY CONNECTED. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE CONNECTED TO THE LOWEST
SUPPLY VOLTAGE, V
.
SS
Figure 4. LFCSP Pin Configuration
Figure 3. TSSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1
2
3
4
5
6
7
8
15
16
1
2
3
4
5
6
7
IN1
D1
S1
VSS
GND
S4
D4
IN4
IN3
D3
S3
Logic Control Input.
Drain Terminal. This pin can be an input or an output.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Logic Control Input.
Logic Control Input.
Drain Terminal. This pin can be an input or an output.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
9
10
11
12
8
9
10
FF
Fault Flag Digital Output. This pin has a high output when the device is in normal operation or a low
when a fault condition occurs on any of the Sx inputs.
13
14
15
16
11
12
13
14
EP
VDD
S2
D2
IN2
Exposed
Pad
Most Positive Power Supply Potential.
Overvoltage Protected Source Terminal. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Logic Control Input.
The exposed pad is internally connected. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be connected to the lowest supply voltage, VSS.
Table 8. ADG5412F Truth Table
INx
Switch Condition (S1 to S4)
1
0
On
Off
Table 9. ADG5413F Truth Table
Switch Condition
INx
0
S1, S4
Off
S2, S3
On
1
On
Off
Rev. B | Page 13 of 28
ADG5412F/ADG5413F
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
25
40
35
30
25
20
15
10
5
V
V
= +22V
= –22V
V
V
= +15V
= –15V
DD
SS
T
= 25°C
DD
A
SS
V
V
= +20V
= –20V
DD
SS
20
15
10
5
V
V
= +16.5V
= –16.5V
DD
SS
V
V
= +18V
= –18V
DD
SS
V
V
= +13.5V
= –13.5V
DD
SS
+125°C
+85°C
+25°C
–40°C
V
V
= +15V
= –15V
DD
SS
0
0
–25 –20 –15 –10
–5
0
5
10
15
20
25
–15 –12
–9
–6
–3
0
3
6
9
12
15
V , V (V)
V , V (V)
S D
S
D
Figure 5. RON as a Function of VS,VD (Dual Supply)
Figure 8. RON as a Function of VS,VD for Different Temperatures,
15 V Dual Supply
25
20
15
10
5
40
V
V
= +20V
= –20V
T
= 25°C
DD
A
SS
35
30
25
20
15
10
5
V
V
= 12V
= 0V
DD
SS
V
V
= 10.8V
= 0V
DD
SS
+125°C
+85°C
V
V
= 13.2V
= 0V
DD
SS
+25°C
–40°C
0
0
–20
0
2
4
6
8
10
12
14
–15
–10
–5
0
5
10
15
20
V , V (V)
V , V (V)
S
D
S
D
Figure 9. RON as a Function of VS,VD for Different Temperatures,
20 V Dual Supply
Figure 6. RON as a Function of VS,VD (12 V Single Supply)
40
25
20
15
10
5
V
V
= 12V
DD
T
= 25°C
A
= 0V
SS
35
30
25
20
15
10
5
V
V
= 36V
= 0V
DD
SS
V
V
= 32.4V
= 0V
DD
SS
+125°C
+85°C
+25°C
–40°C
V
V
= 39.6V
= 0V
DD
SS
0
0
0
2
4
6
8
10
12
0
5
10
15
20
V , V (V)
25
30
35
40
V , V (V)
S
D
S
D
Figure 10. RON as a Function of VS,VD for Different Temperatures,
12 V Single Supply
Figure 7. RON as a Function of VS,VD (36 V Single Supply)
Rev. B | Page 14 of 28
Data Sheet
ADG5412F/ADG5413F
40
35
30
25
20
15
10
5
1
0
V
V
= 36V
DD
= 0V
SS
V
V
V
= 12V
= 0V
DD
SS
–1
–2
–3
–4
–5
= 1V/10V
BIAS
+125°C
+85°C
+25°C
–40°C
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
D
I
S
D
I , I (ON) + +
I , I (ON) – –
S
D
S
D
0
0
4
8
12
16
20
24
28
32
36
0
20
40
60
80
100
120
V , V (V)
S
D
TEMPERATURE (°C)
Figure 11. RON as a Function of VS,VD for Different Temperatures,
36 V Single Supply
Figure 14. Leakage Current vs. Temperature, 12 V Single Supply
2
2
0
V
V
V
= +15V
= –15V
DD
SS
1
0
= +10V/–10V
BIAS
V
V
V
= 36V
= 0V
DD
SS
–1
–2
–3
–4
–5
–6
–7
–8
–2
–4
= 1V/30V
BIAS
–6
–8
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
S
D
S
D
D
D
S
I , I (ON) + +
I , I (ON) – –
I , I (ON) + +
I , I (ON) – –
S
D
S
D
S
D
S
D
–10
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature, 15 V Dual Supply
Figure 15. Leakage Current vs. Temperature, 36 V Single Supply
2
0
5
V
V
= +15V
= –15V
DD
SS
0
–5
V
V
V
= +20V
= –20V
DD
SS
–2
–4
= +15V/–15V
BIAS
–10
–15
–20
–6
V
V
V
V
= –30V
= –55V
= +30V
= +55V
–8
S
S
S
S
I
I
(OFF) + –
(OFF) – +
I
I
(OFF) + –
(OFF) – +
S
D
S
D
I , I (ON) + +
I , I (ON) – –
S
D
S
D
–10
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Leakage Current vs. Temperature, 20 V Dual Supply
Figure 16. Overvoltage Leakage Current vs. Temperature, 15 V Dual Supply
Rev. B | Page 15 of 28
ADG5412F/ADG5413F
Data Sheet
5
0
–20
V
V
= +15V
= –15V
= 25°C
V
V
= +20V
= –20V
DD
DD
SS
SS
T
A
0
–5
–40
–10
–15
–20
–25
–60
–80
V
V
V
V
= –30V
= –55V
= +30V
= +55V
S
S
S
S
–100
–120
0
20
40
60
80
100
120
1k
10k
100k
1M
10M
100M
1G
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 17. Overvoltage Leakage Current vs. Temperature, 20 V Dual Supply
Figure 20. Off Isolation vs. Frequency, 15 V Dual Supply
2
0
–20
V
V
= +15V
= –15V
= 25°C
V
V
= 12V
= 0V
DD
DD
SS
SS
0
–2
T
A
–4
–40
–6
–60
–8
–10
–12
–14
–16
–80
V
V
V
V
= –30V
= –55V
= +30V
= +55V
S
S
S
S
–100
–120
0
20
40
60
80
100
120
10k
100k
1M
10M
100M
1G
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 18. Overvoltage Leakage Current vs. Temperature, 12 V Single Supply
Figure 21. Crosstalk vs. Frequency, 15 V Dual Supply
2
100
0
V
V
= 36V
= 0V
DD
SS
T
= 25°C
A
0
–2
–100
–200
–300
–400
–500
–600
–700
–800
V
V
= 12V
= 0V
DD
SS
–4
–6
–8
V
V
= 36V
= 0V
DD
SS
–10
–12
–14
V
V
V
V
= –38V
= –40V
= +38V
= +55V
S
S
S
S
0
20
40
60
80
100
120
0
5
10
15
20
(V)
25
30
35
40
TEMPERATURE (°C)
V
S
Figure 19. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
Figure 22. Charge Injection vs. Source Voltage (VS), Single Supply
Rev. B | Page 16 of 28
Data Sheet
ADG5412F/ADG5413F
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
100
V
V
= +15V
= –15V
= 25°C
DD
SS
T
= 25°C
A
0
–100
–200
–300
–400
–500
–600
–700
–800
T
A
V
V
= +15V
= –15V
DD
SS
V
V
= +20V
= –20V
DD
SS
10k
100k
1M
10M
100M
1G
–20
–15
–10
–5
0
5
10
15
20
FREQUENCY (Hz)
V
(V)
S
Figure 26. Bandwidth vs. Frequency
Figure 23. Charge Injection vs. Source Voltage (VS), Dual Supply
480
460
440
420
400
380
360
340
320
0
V
V
T
= +15V
= –15V
= 25°C
tON (+12V)
tON (±20V)
tOFF (±15V)
tON (+36V)
tOFF (+12V)
tOFF (±20V)
tON (±15V)
tOFF (+36V)
DD
SS
–20
–40
A
WITH DECOUPLING CAPACITORS
–60
–80
–100
–120
–140
–40
–20
0
20
40
60
80
100
120
10k
100k
1M
10M
100M
1G
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 27. tON, tOFF Times vs. Temperature
Figure 24. ACPSRR vs. Frequency, 15 V Dual Supply
0.020
0.015
0.010
0.005
0
0.9
0.8
0.7
0.6
0.5
LOAD = 10kΩ
T
= 25°C
A
V
= 12V, V = 0V, V = 6V p-p
SS S
DD
V
= 15V, V = –15V, V = 15V p-p
SS S
DD
V
= 20V, V = –20V, V = 20V p-p
SS S
DD
V
= 36V, V = 0V, V = 18V p-p
SS S
DD
0
5000
10000
FREQUENCY (Hz)
15000
20000
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 28. Threshold Voltage (VT) vs. Temperature
Figure 25. THD + N vs. Frequency, 15 V Dual Supply
Rev. B | Page 17 of 28
ADG5412F/ADG5413F
Data Sheet
24
20
16
12
8
T
T
V
V
= 25°C
A
SOURCE
= +10V
= –10V
DD
SS
V
DD
DISTORTIONLESS
OPERATING
REGION
2
DRAIN
4
0
CH1 5.00V CH2 5.00V
CH3 5.00V
M400ns
–10.00ns
A
CH2
10.1V
1
10
FREQUENCY (MHz)
100
T
Figure 29. Drain Output Response to Positive Overvoltage
Figure 31. Large Voltage Signal Tracking vs. Frequency
DRAIN
1
V
SS
SOURCE
CH2 –14.7V
CH1 5.00V CH2 5.00V
CH3 5.00V
M400ns
–10.00ns
A
T
Figure 30. Drain Output Response to Negative Overvoltage
Rev. B | Page 18 of 28
Data Sheet
ADG5412F/ADG5413F
TEST CIRCUITS
I
I
D
S
V
Sx
Dx
A
A
R
10kΩ
L
|V | > |V | OR |V |
SS
Sx
Dx
S
DD
I
DS
V
S
R
= V/I
DS
ON
Figure 32. On Resistance
Figure 37. Switch Overvoltage Leakage
I
(OFF)
A
I
(OFF)
A
V
= V = GND = 0V
SS
S
D
DD
Sx
Dx
I
I
D
S
Sx
Dx
A
A
V
V
D
S
R
10kΩ
L
V
S
Figure 33. Off Leakage
Figure 38. Switch Unpowered Leakage
I
(ON)
A
D
Sx
Dx
NC
V
D
NC = NO CONNECT
Figure 34. On Leakage
V
V
V
V
DD
SS
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
V
V
DD
SS
DD
SS
Sx
Dx
Sx
50Ω
50Ω
INx
INx
IN
V
S
V
S
Dx
V
V
OUT
OUT
V
V
IN
R
R
L
L
50Ω
50Ω
GND
GND
V
WITH SWITCH
V
OUT
OUT
INSERTION LOSS = 20 log
OFF ISOLATION = 20 log
V
S
V
WITHOUT SWITCH
OUT
Figure 35. Off Isolation
Figure 39. Bandwidth
V
V
V
V
SS
DD
SS
DD
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
AUDIO
PRECISION
V
V
V
V
DD
SS
DD
SS
V
OUT
R
S
S1
R
L
Sx
50Ω
V
V p-p
INx
IN
S
Dx
R
L
50Ω
S2
Dx
V
OUT
V
R
10kΩ
V
L
S
GND
GND
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 36. Channel-to-Channel Crosstalk
Figure 40. THD + N
Rev. B | Page 19 of 28
ADG5412F/ADG5413F
Data Sheet
V
V
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
DD
SS
SOURCE
VOLTAGE
V
S1
D1
D
(V )
S
C *
L
2pF
R
L
V
S
1kΩ
0V
ADG5412F/
ADG5413F
tRESPONSE
V
– 0.9V
DD
S2 TO S4
GND
OUTPUT
(V
)
D
0V
*INCLUDES TRACK CAPACITANCE
Figure 41. Overvoltage Response Time, tRESPONSE
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
V
DD
SS
SOURCE
VOLTAGE
V
D
S1
D1
(V )
S
C *
L
2pF
R
L
1kΩ
V
S
0V
ADG5412F/
ADG5413F
tRECOVERY
S2 TO S4
GND
OUTPUT
(V
)
D
1V
0V
*INCLUDES TRACK CAPACITANCE
Figure 42. Overvoltage Recovery Time, tRECOVERY
V
V
DD
SS
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
V
DD
SOURCE
VOLTAGE
S1
D1
S2 TO S4
(V )
S
V
S
0V
ADG5412F/
ADG5413F
tDIGRESP
FF
C *
L
12pF
OUTPUT
(V
)
GND
FF
0.1V
OUT
0V
*INCLUDES TRACK CAPACITANCE
Figure 43. Interrupt Flag Response Time, tDIGRESP
Rev. B | Page 20 of 28
Data Sheet
ADG5412F/ADG5413F
V
V
V
V
DD
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
SS
SOURCE
S1
D1
S2 TO S4
VOLTAGE
(V )
V
S
S
0V
ADG5412F/
ADG5413F
FF
tDIGREC
C *
L
12pF
0.9V
OUT
OUTPUT
GND
(V
)
FF
0V
*INCLUDES TRACK CAPACITANCE
Figure 44. Interrupt Flag Recovery Time, tDIGREC
V
V
DD
SS
0.1µF
0.1µF
V
+ 0.5V
DD
V
V
DD
SS
SOURCE
S1
D1
S2 TO S4
VOLTAGE
(V )
S
V
S
5V
0V
R
1kΩ
ADG5412F/
ADG5413F
PULLUP
tDIGREC
OUTPUT
FF
5V
C *
L
12pF
3V
OUTPUT
GND
(V
)
FF
0V
*INCLUDES TRACK CAPACITANCE
Figure 45. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
V
V
DD
SS
V
0.1µF
0.1µF
IN
50%
50%
0V
0V
V
S1
V
SS
D1
90%
DD
90%
V
V
OUT1
OUT2
V
V
S1
OUT1
C
35pF
R
300Ω
L
L
S2
D2
V
V
S2
OUT2
C
R
300Ω
L
L
90%
90%
35pF
IN1,
IN2
0V
ADG5413F
GND
tD
tD
Figure 46. Break-Before-Make Time Delay, tD
V
V
DD
SS
0.1µF
0.1µF
ADG5412F/
ADG5413F
V
50%
50%
IN
V
V
SS
DD
V
L
OUT
Sx
Dx
R
300Ω
C
L
V
S
35pF
INx
90%
V
OUT
10%
GND
tOFF
tON
Figure 47. Switching Times, tON and tOFF
Rev. B | Page 21 of 28
ADG5412F/ADG5413F
Data Sheet
V
V
V
DD
SS
0.1µF
0.1µF
ADG5412F/
ADG5413F
V
DD
SS
V
IN
V
R
S
OUT
Sx
Dx
OFF
ON
C
1nF
L
V
S
INx
V
OUT
ΔV
OUT
Q
= C × ΔV
L
OUT
INJ
GND
Figure 48. Charge Injection, QINJ
Rev. B | Page 22 of 28
Data Sheet
ADG5412F/ADG5413F
TERMINOLOGY
IDD
tOFF
OFF represents the delay between applying the digital control
I
DD represents the positive supply current.
t
input and the output switching off (see Figure 47).
ISS
I
SS represents the negative supply current.
tD
tD represents the off time measured between the 90% point of
both switches when switching from one address state to
another.
VD, VS
VD and VS represent the analog voltage on the Dx pins and the
Sx pins, respectively.
tDIGRESP
RON
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to voltage on the source pin exceeding
the supply voltage by 0.5 V.
R
ON represents the ohmic resistance between the Dx pins and
the Sx pins.
∆RON
tDIGREC
∆RON represents the difference between the RON of any two
channels.
tDIGREC is the time required for the FF pin to return high,
measured with respect to voltage on the Sx pin falling below the
supply voltage plus 0.5 V.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 90% of the supply voltage.
IS (Off)
IS (Off) is the source leakage current with the switch off.
tRECOVERY
ID (Off)
tRECOVERY represents the delay between an overvoltage on the Sx
ID (Off) is the drain leakage current with the switch off.
pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 10% of the supply voltage.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
VINL
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
INL and IINH represent the low and high input currents of the
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
V
I
I
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
On Response
On response is the frequency response of the on switch.
CD (On), CS (On)
Insertion Loss
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
CIN
C
IN is the digital input capacitance.
tON
tON represents the delay between applying the digital control
input and the output switching on (see Figure 47).
Rev. B | Page 23 of 28
ADG5412F/ADG5413F
Data Sheet
AC Power Supply Rejection Ratio (ACPSRR)
VT
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
VT is the voltage threshold at which the overvoltage protection
circuitry engages. See Figure 28.
Rev. B | Page 24 of 28
Data Sheet
ADG5412F/ADG5413F
THEORY OF OPERATION
During overvoltage conditions, the leakage current into and out
of the source pins is limited to tens of microamperes and only
nanoamperes for the drain pins. This limit protects the switch
and connected circuitry from overstresses as well as restricting
the current drawn from the signal source. When an overvoltage
event occurs, the channels undisturbed by the overvoltage input
continue to operate normally without additional crosstalk.
SWITCH ARCHITECTURE
Each channel of the ADG5412F/ADG5413F consists of a parallel
pair of N-channel diffused metal-oxide semiconductor (NDMOS)
and P-channel DMOS (PDMOS) transistors. This construction
provides excellent performance across the signal range. The
ADG5412F/ADG5413F channels operate as standard switches
when input signals with a voltage between VSS and VDD are applied.
For example, the on resistance is 10 Ω typically and the appropriate
control pin, INx, controls the opening or closing of the switch.
ESD Performance
The ADG5412F/ADG5413F have an ESD rating of 5.5 kV for
the human body model (HBM).
Additional internal circuitry enables the switch to detect over-
voltage inputs by comparing the voltage on the source pin with
The drain pins have ESD protection diodes to the rails and the
voltage at these pins must not exceed supply voltage. The source
pins have specialized ESD protection that allow the signal voltage
to reach 55 V regardless of supply voltage level. See Figure 49
for switch channel overview.
V
DD and VSS. A signal is considered overvoltage if it exceeds the
supply voltages by the voltage threshold, VT. The threshold voltage
is typically 0.7 V, but can range from 0.8 V at −40°C down to 0.6
V at +125°C. See Figure 28 to see the change in VT with
operating temperature.
Trench Isolation
The maximum voltage that can be applied to any source input is
+55 V or −55 V. When the device is powered using the single
supply of 25 V or greater, the maximum signal level reduces
from −55 V to −40 V at VDD = 40 V to remain within the 80 V
maximum rating. Construction of the process allows the channel to
withstand 80 V across the switch when it is opened. These over-
voltage limits apply whether the power supplies are present or not.
In the ADG5412F and ADG5413F, an insulating oxide layer
(trench) is placed between the NDMOS and the PDMOS
transistors of each switch. Parasitic junctions, which occur
between the transistors in junction-isolated switches, are
eliminated, and the result is a switch that is latch-up immune
under all circumstances. These devices pass a JESD78D latch-
up test of 500 mA for 1 sec, which is the harshest test in the
specification.
V
DD
ESD
PROTECTION
ESD
NDMOS
PDMOS
DIODE
Sx
Dx
ESD
DIODE
FAULT
DETECTOR
SWITCH
DRIVER
V
SS
AND
INx
Figure 49. Switch Channel and Control Function
P-WELL
N-WELL
When an overvoltage condition is detected on a source pin, the
switch is automatically opened regardless of the digital logic
state, INx. The source and drain pins both become high impedance
and ensure that no current flows through the switch. In Figure 29,
the voltage on the drain pin can be seen to follow the voltage on
the source pin until the switch has turned off completely and the
drain voltage discharges through the load. The maximum voltage
on the drain is limited by the internal ESD diodes and the rate at
which the output voltage discharges is dependent on the load at the
pin. The ADG5412BF/ADG5413BF are pin-compatible devices
that are overvoltage protected on both the source and drain pins.
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 50. Trench Isolation
Rev. B | Page 25 of 28
ADG5412F/ADG5413F
Data Sheet
+22V 0V
–22V
FAULT PROTECTION
When the voltages at the source inputs exceed VDD or VSS by VT,
the switch turns off or, if the device is unpowered, the switch
remains off. The switch input remains high impedance regardless
of the digital input state or the load resistance and the output
acts as a virtual open circuit. Signal levels up to +55 V and
−55 V are blocked in both the powered and unpowered condition
as long as the 80 V limitation between the source and supply
pins is met.
V
GND
V
SS
DD
ADG5413F
S1
S2
S3
S4
D1
D2
D3
D4
+22V
‒55V
+55V
FAULT
DETECTION
+ SWITCH
DRIVER
Power-On Protection
FF
0V
The following three conditions must be satisfied for the switch
to be in the on condition:
5V
IN1 IN2 IN3 IN4
•
•
•
VDD to VSS ≥ 8 V
Input signal is between VSS − VT and VDD + VT
Digital logic control input, INx, is turned on
Figure 51. ADG5413F in Multiplexer Configuration under Overvoltage
Conditions
Power-Off Protection
When the switch is turned on, signal levels up to the supply rails
are passed.
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The switch responds to an analog input that exceeds VDD or VSS
by a threshold voltage, VT, by turning off. The absolute input
voltage limits are −55 V and +55 V, while maintaining an 80 V
limit between the source pin and the supply rails. The switch
remains off until the voltage at the source pin returns to
between VDD and VSS.
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to 55 V
are blocked in the unpowered condition.
The fault response time (tRESPONSE) when powered by 15 V dual
supply is typically 460 ns and the fault recovery time (tRECOVERY) is
720 ns. These vary with supply voltages and output load conditions.
Digital Input Protection
The ADG5412F and the ADG5413F can tolerate digital input
signals being present on the device without power. When the
device is unpowered, the switch is guaranteed to be in the off
state, regardless of the state of the digital logic signals.
Exceeding 55 V on any source input may damage the ESD
protection circuitry on the device.
The maximum stress across the switch channel is 80 V,
therefore, the user must pay close attention to this limit if using the
device in a multiplexed configuration and one channel is on while
another channel is in a fault condition.
The digital inputs are protected against positive faults up to
44 V. The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are
present on the digital inputs.
For example, consider the case where the device is set up in a
multiplexer configuration as shown in Figure 51.
Overvoltage Interrupt Flag
•
•
VDD/VSS = 22 V, S1 = 22 V, all switches are on
D1 is externally multiplexed with D2; therefore, D1 and
D2 = 22 V
The voltages on the source inputs of the ADG5412F and the
ADG5413F are continuously monitored and the state of the
switch is indicated by an active low digital output pin, FF.
•
•
S2 has a −55 V fault and S3 has a+55 V fault
The voltage between S2 and D1 or between S2 and D2 =
+22 V − (−55 V) = +77 V
The voltage on the FF pin indicates if any of the source input
pins are experiencing a fault condition. The output of the FF pin
is a nominal 3 V when all source pins are within normal
operating range. If any source pin voltage exceeds the supply
voltage by VT, the FF output reduces to below 0.8 V.
•
The voltage between S3 and D3 = 55 V− 0 V = 55 V
These calculations are all within device specifications: 55 V
maximum fault on source inputs and a maximum of 80 V
across the off switch channel.
Rev. B | Page 26 of 28
Data Sheet
ADG5412F/ADG5413F
APPLICATIONS INFORMATION
The overvoltage protected family of switches and multiplexers
provide a robust solution for instrumentation, industrial,
aerospace, and other harsh environments where overvoltage
signals can be present and the system must remain operational
both during and after the overvoltage has occurred.
The ADG5412F/ADG5413F enable the designer to remove
these resistors and retain the precision performance without
compromising the protection of the circuit.
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5412F/ADG5413F are not intended for use in very
high voltage applications. The maximum operating voltage of
the transistor is 80 V. In applications where the inputs are likely
to be subject to overvoltages exceeding the breakdown voltage,
use transient voltage suppressors (TVSs) or similar.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required.
The ADG5412F and the ADG5413F can operate with bipolar
supplies between 5 V and 22 V. The supplies on VDD and VSS
need not be symmetrical but the VDD to VSS range must not
exceed 44 V. The ADG5412F and the ADG5413F can also
operate with single supplies between 8 V and 44 V with VSS
connected to GND.
INTELLIGENT FAULT DETECTION
The ADG5412F/ADG5413F digital output pin, FF, can interface
with a microprocessor or control system and be used as an
interrupt flag. This feature provides real-time diagnostic
information on the state of the device and the system to which it
connects.
These devices are fully specified at 15 V, 20 V, +12 V, and
+36 V supply ranges.
The control system can use the digital interrupt to start a
variety of actions, such as
POWER SUPPLY SEQUENCING PROTECTION
The switch channel remains open when the device is unpowered
and signals from −55 V to +55 V can be applied without damaging
the device. Only when the supplies are connected, a suitable
digital control signal is placed on the INx pin, and the signal is
within normal operating range does the switch channel close.
Placing the ADG5412F/ADG5413F between external connectors
and sensitive components offers protection in systems where a
signal is presented to the source pins before the supply voltages
are available.
•
•
•
Initiating investigation into the source of the overvoltage fault
Shutting down critical systems in response to the overvoltage
Data recorders marking data during these events as
unreliable or out of specification
For systems that are sensitive during a start-up sequence, the
active low operation of the flag allows the system to ensure that
the ADG5412F/ADG5413F are powered on and that all input
voltages are within normal operating range before initiating
operation.
SIGNAL RANGE
The FF pin is a weak pull-up, which allows the signals to be
combined into a single interrupt for larger modules that contain
multiple devices.
The ADG5412F/ADG5413F switches have overvoltage detection
circuitry on their inputs that compares the voltage levels at the
source terminals with VDD and VSS. To protect downstream
circuitry from overvoltages, supply the ADG5412F/ADG5413F
with voltages that match the intended signal range. The low
on-resistance switch allows signals up to the supply rails to be
passed with very little distortion. A signal that exceeds the supply
rail by the threshold voltage is then blocked. This signal block
offers protection to both the device and any downstream circuitry.
The recovery time, tDIGREC, can be decreased from a typical 60 µs
to 600 ns by using a 1 kΩ pull-up resistor.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 31 illustrates the voltage range and frequencies that the
ADG5412F/ADG5413F can reliably convey. For signals that
extend across the full signal range from VSS to VDD, keep the
frequency below 3 MHz. If the required frequency is greater
than 3 MHz, decrease the signal range appropriately to ensure
signal integrity.
LOW IMPEDANCE CHANNEL PROTECTION
The ADG5412F/ADG5413F can be used as protective elements
in signal chains that are sensitive to both channel impedance
and overvoltage signals. Traditionally, series resistors are used
to limit the current during an overvoltage condition to protect
susceptible components.
These series resistors affect the performance of the signal chain
and reduce the precision that can be reached. A compromise
must be reached on the value of the series resistance that is high
enough to sufficiently protect sensitive components but low
enough that the precision performance of the signal chain is not
sacrificed.
Rev. B | Page 27 of 28
ADG5412F/ADG5413F
OUTLINE DIMENSIONS
Data Sheet
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 53.16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RU-16
RU-16
ADG5412FBRUZ
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
ADG5412FBRUZ-RL7
ADG5412FBCPZ-RL7
EVAL-ADG5412FEBZ
ADG5413FBRUZ
ADG5413FBRUZ-RL7
ADG5413FBCPZ-RL7
CP-16-17
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
RU-16
RU-16
CP-16-17
1 Z = RoHS Compliant Part.
©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12472-0-1/16(B)
Rev. B | Page 28 of 28
相关型号：
ADG5413BFBRUZ
Bidirectional Fault Protection and Detection, 10 Ω RON, Quad SPST Switches, 2 x NO, 2 x NC
ADI
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