ADG601BRTZ-REEL [ADI]
Low on resistance, 2.5 OHM maximum; 低导通电阻2.5欧姆最大
| 型号： | ADG601BRTZ-REEL |
| 厂家： | 
ADI |
| 描述： | Low on resistance, 2.5 OHM maximum |
| 文件： | 总12页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 Ω, CMOS, ± ± ꢀV/± ꢀ
SPST Switches
ADG601VADG602
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Low on resistance, 2.5 Ω maximum
<0.65 Ω on-resistance flatness
S
D
S
D
Dual 2.7 V to 5.5 V or single +2.7 V to +5.5 V supplies
Rail-to-rail input signal range
Tiny, 6-lead SOT-23; 8-lead MSOP; and 820 μm × 2255 μm die
Low power consumption
IN
IN
ADG601
ADG602
NOTES
1. SWITCHES SHOWN FOR A LOGIC 0 INPUT.
TTL-/CMOS-compatible inputs
Figure 1.
APPLICATIONS
Automatic test equipment
Power routing
Communication systems
Data acquisition systems
Sample-and-hold systems
Avionics
Table 1. Truth Table
ADG601 IN
ADG602 IN
Switch Condition
0
1
1
0
Off
On
Relay replacement
Battery-powered systems
well in both directions when the device is on, with the input
signal range extending to the supply rails.
GENERAL DESCRIPTION
The ADG601/ADG602 are monolithic, CMOS single-pole
single-throw (SPST) switches with on resistance typically less
than 2.5 Ω. The low on-resistance flatness makes the
ADG601/ADG602 ideally suited to many applications,
particularly those requiring low distortion. These switches are
ideal replacements for mechanical relays because they are more
reliable, have lower power requirements, and are available in
much smaller package sizes.
The switches are available in tiny, 6-lead SOT-23; 8-lead MSOP;
and 820 μm × 2255 μm die.
PRODUCT HIGHLIGHTS
1. Low on resistance (2 Ω typical)
2. Dual 2.ꢀ ꢁ to 5.5 ꢁ or single +2.ꢀ ꢁ to +5.5 ꢁ supplies
3. Tiny, 6-lead SOT-23; 8-lead MSOP; and 820 μm × 2255 μm die
4. Rail-to-rail input signal range
The ADG601 is a normally open (NO) switch, and the ADG602
is a normally closed (NC) switch. Each switch conducts equally
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2001–2007 Analog Devices, Inc. All rights reserved.
ADG601VADG602
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configurations and Function Descriptions............................6
Typical Performance Characteristics ..............................................ꢀ
Terminology.......................................................................................9
Test Circuits..................................................................................... 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply................................................................................... 3
Single Supply................................................................................. 4
REVISION HISTORY
Updated Outline Dimensions........................................................11
Changes to Ordering Guide...........................................................11
3/07—Rev. B to Rev. C
Added Die Package.............................................................Universal
Changes to Specifications.................................................................3
Added Figure 4 and Table 6..............................................................6
Changes to Ordering Guide .......................................................... 11
6/03—Rev. 0 to Rev. A
Changes to Specifications.................................................................2
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions..........................................................8
3/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to 6-Lead SOT-23 (RJ-6) Pin Configuration .................6
Added Pin Function Descriptions Table ........................................6
Changes to Figure 19.........................................................................9
Rev. C | Page 2 of 12
ADG601VADG602
SPECIFICATIONS
DUAL SUPPLY
ꢁDD = 5 ꢁ 10%, ꢁSS = –5 ꢁ 10%, GND = 0 ꢁ, unless otherwise noted.
Table 2.
B Version1
Parameter
+25°C
−40°C to +85°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS to VDD
V
VDD = +4.5 V, VSS = –4.5 V
On Resistance (RON
)
2
Ω typ
Ω max
Ω typ
Ω max
VS = 4.5 V, IDS = −10 mA; see Figure 15
2.5
0.35
0.6
5.5
0.4
0.65
On-Resistance Flatness (RFLAT (ON)
)
VS = 3.3 V, IDS = −10 mA
LEAKAGE CURRENTS
VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off)
0.01
0.25
0.01
0.25
0.01
0.25
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = +4.5 V/−4.5 V, VD = −4.5 V/+4.5 V; see Figure 16
1
1
1
Drain Off Leakage, ID (Off)
VS = +4.5 V/−4.5 V, VD = −4.5 V/+4.5 V; see Figure 16
VS = VD = +4.5 V or −4.5 V; see Figure 17
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.4
0.8
V min
V max
μA typ
μA max
pF typ
0.005
2
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
80
120
45
ns typ
ns max
ns typ
ns max
pC typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 3.3 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS = 3.3 V; see Figure 18
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
155
90
tOFF
75
Charge Injection
Off Isolation
Bandwidth −3 dB
CS (Off)
CD (Off)
CD, CS (On)
250
−60
180
50
50
145
MHz typ RL = 50 Ω, CL = 5 pF; see Figure 21
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or 5.5 V
0.001
0.001
μA typ
μA max
μA typ
μA max
1.0
1.0
ISS
Digital inputs = 0 V or 5.5 V
1 Temperature range for B version is −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
Rev. C | Page 3 of 12
ADG601VADG602
SINGLE SUPPLY
ꢁDD = 5 ꢁ 10%, ꢁSS = 0 ꢁ, GND = 0 ꢁ, unless otherwise noted.
Table 3.
B Version1
Parameter
+25°C
−40°C to +85°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
VDD = 4.5 V
On Resistance (RON
)
3.5
5
0.2
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to 4.5 V, IDS = −10 mA; see Figure 15
8
0.2
0.6
On-Resistance Flatness (RFLAT (ON)
)
VS = 1.5 V to 3.3 V, IDS = –10 mA
LEAKAGE CURRENTS
VDD = 5.5 V
Source Off Leakage, IS (Off)
0.01
0.25
0.01
0.25
0.01
0.25
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 4.5 V/1 V, VD = 1 V/4.5 V; see Figure 16
1
1
1
Drain Off Leakage, ID (Off)
VS = 4.5 V/1 V, VD = 1 V/4.5 V; see Figure 16
VS = VD = 4.5 V or 1 V; see Figure 17
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.4
0.8
V min
V max
μA typ
μA max
pF typ
0.005
2
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
tON
110
220
50
80
20
−60
180
50
50
145
ns typ
ns max
ns typ
ns max
pC typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 3.3 V; see Figure 18
RL = 300 Ω, CL = 35 pF
VS = 3.3 V; see Figure 18
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
RL = 50 Ω, CL = 5 pF; see Figure 21
f = 1 MHz
280
110
tOFF
Charge Injection
Off Isolation
Bandwidth –3 dB
CS (Off)
CD (Off)
CD, CS (On)
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
0.001
μA typ
1.0
μA max
1 Temperature range for B version is −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 12
ADG601VADG602
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
13 V
−0.3 V to +6.5 V
+0.3 V to –6.5 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V or
30 mA (whichever
occurs first)
Only one absolute maximum rating may be applied at a time.
Continuous Current, S or D
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 200 mA
Operating Temperature Range
100 mA
ESD CAUTION
Industrial (B Version)
−40°C to +85°C
Storage Temperature Range
Junction Temperature
−65°C to +150°C
150°C
Thermal Resistance
MSOP
θJA
θJC
206°C/W
44°C/W
SOT-23
θJA
θJC
229.6°C/W
91.99°C/W
300°C
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature
220°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. C | Page 5 of 12
ADG601VADG602
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
14
13
3
4
12
5
PIN 1
11
10
PIN 1
V
1
2
3
6
5
4
IN
D
NC
NC
1
2
3
4
8
7
6
5
S
INDICATOR
DD
6
7
INDICATOR
GND
IN
ADG601/
ADG602
ADG601/
ADG602
9
8
S
D
TOP VIEW
TOP VIEW
V
V
(Not to Scale)
(Not to Scale)
DD
SS
TOP VIEW
(Not to Scale)
V
GND
SS
NC = NO CONNECT
Figure 2. 6-Lead SOT-23 (RJ-6)
Figure 3. 8-Lead MSOP (RM-8)
Figure 4. Die (820 μm × 2255 μm)
Table 5. Pin Function Descriptions
Pin No.
6-Lead SOT-23 8-Lead MSOP
Mnemonic
Description
1
2
3
4
5
6
4
8
5
7
1
6
VDD
S
VSS
GND
D
Most Positive Power Supply Potential.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Drain Terminal. Can be an input or output.
Logic Control Input.
IN
N/A
2, 3
NC
No Connect.
Table 6. Die Pad Coordinates1
Die Pad
Coordinates
Y (μm)
Die Pad No.
Mnemonic
Description
X (μm)
−265
−265
−265
−265
−265
−265
−265
−265
+265
+265
+265
+265
+265
+265
1
+754
+525
+241
+141
−191
−409
−549
−787
−767
−429
−289
+189
+521
+661
NC
D
D
No Connect.
2
3
4
5
6
7
8
9
Drain Terminal. Can be an input or output.2
Drain Terminal. Can be an input or output.2
Drain Terminal. Can be an input or output.2
No Connect.
D
NC
NC
NC
VDD
VSS
IN
GND
S
S
No Connect.
No Connect.
Most Positive Power Supply Potential.
Most Negative Power Supply Potential.
Logic Control Input.
10
11
12
13
14
Ground (0 V) Reference.
Source Terminal. Can be an input or output.3
Source Terminal. Can be an input or output.3
Source Terminal. Can be an input or output.
NC
1 Measured from the center of the die.
2 Bond the D pads together to a single point to preserve the on resistance and current handling capability. The common point acts as the drain pin of the switch.
3 Bond the S pads together to a single point to preserve the on resistance and current handling capability. The common point acts as the source pin of the switch.
Rev. C | Page 6 of 12
ADG601VADG602
TYPICAL PERFORMANCE CHARACTERISTICS
5
4
3
2
1
0
5
T
= 25°C
A
+85°C
4
3
2
1
0
±2.5V
±3V
±3.3V
±4.5V
+25°C
–40°C
±5V
3
V
V
= 5V
= 0V
DD
SS
0
0.5
1.0
1.5
2.0
V
2.5
3.0
3.5
4.0
4.5
5.0
–5
–4
–3
–2
–1
0
1
2
4
5
5.0
5
, V (V)
V
, V (V)
S
D
S
D
Figure 8. On Resistance vs. VD, VS for Different Temperatures (Single Supply)
Figure 5. On Resistance vs. VD, VS (Dual Supply)
10
0.5
V
V
V
V
= +5V
= –5V
DD
SS
V
= 2.7V
9
8
7
6
5
4
3
2
1
0
0.4
0.3
DD
= ±4.5V
D
S
±
=
4.5V
V
= 3.0V
DD
0.2
I
, I (ON)
S
D
0.1
0
V
= 4.5V
DD
V
= 3.3V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
I
(OFF)
D
I
(OFF)
S
V
= 5.0V
4.0
DD
T
V
= 25°C
A
= 0V
SS
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.5
0
10
20
30
40
50
60
70
80 85
V
, V (V)
TEMPERATURE (°C)
D
S
Figure 6. On Resistance vs. VD, VS (Single Supply)
Figure 9. Leakage Currents vs. Temperature (Dual Supply)
5
0.5
V
V
V
V
= 5V
= 0V
V
V
= +5V
= –5V
DD
SS
DD
SS
0.4
0.3
0.2
0.1
0
= 4.5V/1V
= 1V/4.5V
D
S
4
3
2
1
0
I
, I (ON)
S
D
+85°C
+25°C
–0.1
–0.2
–0.3
–0.4
–0.5
I
(OFF)
D
I
(OFF)
S
–40°C
–5
–4
–3
–2
–1
0
1
2
3
4
0
10
20
30
40
50
60
70
80 85
V
, V (V)
S
TEMPERATURE (°C)
D
Figure 7. On Resistance vs. VD, VS for Different Temperatures (Dual Supply)
Figure 10. Leakage Currents vs. Temperature (Single Supply)
Rev. C | Page 7 of 12
ADG601VADG602
500
450
400
350
0
–10
–20
–30
–40
–50
–60
–70
–80
T
= 25°C
A
V
V
= +5V
= –5V
DD
SS
300
250
200
150
100
50
V
V
= +5V
DD
SS
= 0V
V
V
= +5V
= –5V
DD
SS
T
= 25°C
A
0
–5
–4
–3
–2
–1
V
0
(V)
1
2
3
4
5
0.2
1
10
FREQUENCY (MHz)
100
S
Figure 11. Charge Injection vs. Source Voltage
Figure 13. Off Isolation vs. Frequency
0
180
160
140
120
100
80
–2
–4
V
V
= +5V
= 0V
DD
SS
V
V
= +5V
= –5V
DD
SS
tON
–6
–8
60
tOFF
40
V
V
= +5V
= –5V
= 25°C
V
V
= +5V
= –5V
–10
–12
DD
SS
DD
SS
V
V
= +5V
= 0V
DD
SS
20
T
A
0
–40
0.2
1
10
100
400
–20
0
20
40
60
80
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 14. On Response vs. Frequency
Figure 12. tON/tOFF Times vs. Temperature
Rev. C | Page 8 of 12
ADG601VADG602
TERMINOLOGY
VDD
VINL
Most positive power supply potential.
Maximum input voltage for Logic 0.
VSS
VINH
Most negative power supply potential.
Minimum input voltage for Logic 1.
IDD
IINL (IINH)
Positive supply current.
Input current of the digital input.
ISS
CS (Off)
Negative supply current.
Off switch source capacitance. Measured with reference to ground.
GND
CD (Off)
Ground (0 ꢁ) reference.
Off switch drain capacitance. Measured with reference to ground.
S
CD, CS (On)
Source terminal. Can be an input or an output.
On switch capacitance. Measured with reference to ground.
D
CIN
Drain terminal. Can be an input or an output.
Digital input capacitance.
IN
tON
Logic control input.
Delay between applying the digital control input and the output
switching on.
VD, VS
Analog voltage on Terminal D and Terminal S.
tOFF
Delay between applying the digital control input and the output
switching off.
RON
Ohmic resistance between Terminal D and Terminal S.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum values of on resistance as measured over the specified
analog signal range.
Off Isolation
A measure of unwanted signal coupling through an off switch.
IS (Off)
Source leakage current with the switch off.
On Response
Frequency response of the on switch.
ID (Off)
Drain leakage current with the switch off.
Insertion Loss
Loss due to the on resistance of the switch.
ID, IS (On)
Channel leakage current with the switch on.
Rev. C | Page 9 of 12
ADG601VADG602
TEST CIRCUITS
I
DS
V1
I
(ON)
A
D
I
(OFF)
A
I
(OFF)
A
S
D
S
D
S
D
S
D
NC
V
D
V
R
= V1/I
V
V
D
S
ON
DS
S
NC = NO CONNECT
Figure 15. On Resistance
Figure 16. Off Leakage
Figure 17. On Leakage
V
V
SS
DD
0.1µF
0.1µF
ADG601
50%
50%
50%
50%
V
V
DD
SS
V
IN
V
L
V
IN
OUT
S
D
ADG602
R
C
L
V
S
300Ω
35pF
IN
90%
90%
V
OUT
GND
tON
tOFF
Figure 18. Switching Times
V
V
SS
DD
V
V
SS
DD
R
V
V
IN ADG601
S
ON
OFF
S
D
V
OUT
C
1nF
L
V
S
IN
IN ADG602
GND
V
ΔV
OUT
OUT
Q
= C × ΔV
L OUT
INJ
Figure 19. Charge Injection
V
V
V
V
SS
DD
SS
DD
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
V
V
SS
DD
SS
DD
S
S
50Ω
50Ω
50Ω
IN
IN
V
V
S
S
D
D
V
V
OUT
OUT
V
V
IN
IN
R
R
L
L
50Ω
50Ω
GND
GND
V
V
WITH SWITCH
OUT
OUT
V WITHOUT SWITCH
S
OFF ISOLATION = 20 log
INSERTION LOSS = 20 log
V
S
Figure 20. Off Isolation
Figure 21. Bandwidth
Rev. C | Page 10 of 12
ADG601VADG602
OUTLINE DIMENSIONS
3.20
3.00
2.80
2.90 BSC
6
1
5
2
4
3
8
1
5
4
5.15
4.90
4.65
2.80 BSC
1.60 BSC
3.20
3.00
2.80
PIN 1
INDICATOR
0.95 BSC
PIN 1
1.90
BSC
0.65 BSC
1.30
1.15
0.90
0.95
0.85
0.75
1.10 MAX
1.45 MAX
0.22
0.08
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
10°
4°
0°
0.60
0.45
0.30
0.50
0.30
0.15 MAX
SEATING
PLANE
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-178-AB
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 23. 6-Lead Small Outline Transistor Package [SOT-23]
Figure 22. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
(RJ-6)
Dimensions shown in millimeters
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
Branding1
ADG601BRT-REEL
ADG601BRT-REEL7
ADG601BRTZ-REEL2
ADG601BRTZ-REEL72
ADG601BRM
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
Die
RJ-6
RJ-6
RJ-6
RJ-6
RM-8
RM-8
STB
STB
STB#
STB#
STB
STB
STB
S1G
S1G
S1G
ADG601BRM-REEL
ADG601BRM-REEL7
ADG601BRMZ2
ADG601BRMZ-REEL2
ADG601BRMZ-REEL72
ADG601CSURF
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
RM-8
RM-8
RM-8
RM-8
ADG602BRT-REEL
ADG602BRT-REEL7
ADG602BRTZ-REEL2
ADG602BRTZ-REEL72
ADG602BRM
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
RJ-6
SUB
SUB
S18
S18
SUB
SUB
SUB
S18
S18
RJ-6
RJ-6
RJ-6
RM-8
RM-8
RM-8
RM-8
RM-8
ADG602BRM-REEL
ADG602BRM-REEL7
ADG602BRMZ2
ADG602BRMZ-REEL72
1 Branding on SOT-23 and MSOP is limited to three characters due to space constraints.
2 Z = RoHS Compliant Part, # denotes RoHS compliant product, may be top or bottom marked.
Rev. C | Page 11 of 12
ADG601VADG602
NOTES
©2001–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02619-0-3/07(C)
Rev. C | Page 12 of 12
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