ADG659YCP-REEL7 [ADI]
+3 V/+5 V/【5 V CMOS 4- and 8-Channel Analog Multiplexers; 3 V / + 5 V / 【 5 V CMOS 4和8通道模拟多路复用器
| 型号： | ADG659YCP-REEL7 |
| 厂家： | 
ADI |
| 描述： | +3 V/+5 V/【5 V CMOS 4- and 8-Channel Analog Multiplexers |
| 文件： | 总20页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
+3 V/+5 V/ 5 V ꢀCMO ꢁ4 ꢂan ꢃ4ꢀꢄꢂaaꢅe
Aaꢂeog Cuetipeꢅxꢅrs
ADG65ꢃ/ADG659
demultiplexers and have an input range that extends to the
supplies. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching
channels. All digital inputs have 0.8 V to 2.4 V logic thresholds,
ensuring TTL/CMOS logic compatibility when using single
+5 V or dual 5 V supplies.
FEATURES
2 ꢀ to 6 ꢀ dual supply
2 ꢀ to 12 ꢀ single supply
Automotive temperature range −40°C to +125°C
<0.1 nA leakage currents
45 Ω on resistance over full signal range
Rail-to-rail switching operation
Single 8-to-1 multiplexer ADG658
Differential 4-to-1 multiplexer ADG659
16-lead LFCSP/TSSOP/QSOP packages
Typical power consumption <0.1 µW
TTL/CMOS compatible inputs
The ADG658 and ADG659 are available in 16-lead TSSOP/
QSOP packages and 16-lead 4 mm × 4 mm LFCSP packages.
PRODUCT HIGHLIGHTS
1. Single- and dual-supply operation.
Package upgrades to 74HC4051/74HC4052 and
MAX4051/MAX4052/MAX4581/MAX4582
The ADG658 and ADG659 offer high performance and are
fully specified and guaranteed with 5 V, +5 V, and +3 V
supply rails.
APPLICATIONS
2. Automotive temperature range −40°C to +125°C.
3. Low power consumption, typically <0.1 µW.
Automotive applications
Automatic test equipment
Data acquisition systems
Battery-powered systems
Communication systems
Audio and video signal routing
Relay replacement
4. 16-lead 4 mm × 4 mm LFCSP packages, 16-lead TSSOP
package and 16-lead QSOP package.
FUNCTIONAL BLOCK DIAGRAM
Sample-and-hold systems
Industrial control systems
ADG659
ADG658
GENERAL DESCRIPTION
S1
S1A
S4A
DA
DB
The ADG658 and ADG659 are low voltage, CMOS analog
multiplexers comprised of eight single channels and four
differential channels, respectively. The ADG658 switches one of
eight inputs (S1–S8) to a common output, D, as determined by
the 3-bit binary address lines A0, A1, and A2. The ADG659
switches one of four differential inputs to a common differential
output, as determined by the 2-bit binary address lines A0 and
D
S1B
S4B
S8
1 OF 8
DECODER
1 OF 4
DECODER
EN
A1. An
input on both devices is used to enable or disable
the device. When disabled, all channels are switched off.
A0 A1 A2 EN
A0
A1
EN
These parts are designed on an enhanced process that provides
lower power dissipation yet gives high switching speeds. These
parts can operate equally well as either multiplexers or
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADG65ꢃ/ADG659
TABLE MF ꢀMNTENTO
Specifications: Dual Supply............................................................. 3
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Test Circuits ................................................................................ 16
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 20
Specifications: Single Supply 5V..................................................... 5
Specifications: Single Supply 2.7 to 3.6 V...................................... 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
REꢀISION HISTORY
7/04—Data Sheet Changed from Rev. 0 to Rev. A
Updated Format.............................................................. Universal
Added QSOP Package Outline ..................................................20
Changes to Ordering Guide .......................................................20
3/03—Rev. 0: Initial Version
Rev. A | Page 2 of 20
ADG65ꢃ/ADG659
OPEꢀIFIꢀATIMNO: DUAL OUPPLY
VDD = +5 V ꢀ0%, VSS = −5 V ꢀ0%, GND = 0 V, unless otherwise noted.ꢀ
Table ꢀ.
B ꢀersion
Y ꢀersion
−40°C
−40°C
Parameter
+25°C
to +85°C
to+125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS to VDD
100
V
VDD = +4.5 V, VSS = −4.5 V
VS = 4.5 V, IS = 1 mA;
Test Circuit 1
On Resistance (RON
)
45
75
1.3
3
10
16
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
90
3.2
17
On Resistance Match between
Channels (∆RON
)
3.5
VS = 3.5 V, IS = 1 mA
VDD = +5 V, VSS = −5 V;
VS = 3 V, IS = 1 mA
On Resistance Flatness (RFLAT(ON)
)
18
LEAKAGE CURRENTS
VDD = +5.5 V, VSS = −5.5 V
Source OFF Leakage IS (OFF)
0.005
0.2
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = 4.5 V, VS = m 4.5 V;
Test Circuit 2
5
Drain OFF Leakage ID (OFF)
ADG658
ADG659
Channel ON Leakage ID, IS (ON)
ADG658
ADG659
0.005
0.2
0.1
0.005
0.2
0.1
VD = 4.5 V, VS = m 4.5 V;
Test Circuit 3
5
2.5
VD = VS = 4.5 V; Test Circuit 4
5
2.5
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
2
µA typ
µA max
pF typ
VIN = VINL or VINH
1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANS
80
115
80
115
30
45
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
% typ
RL = 300 Ω, CL = 35 pF
VS = 3 V; Test Circuit 5
140
140
50
165
165
55
tON (EN)
tOFF (EN)
RL = 300 Ω, CL = 35 pF
VS = 3 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS = 3 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V; Test Circuit 6
VS = 0 V, RS = 0 Ω,
CL = 1 nF; Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 9
RL = 600 Ω, 2 V p-p, f = 20 Hz to 20 kHz
Break-Before-Make Time Delay, tBBM
Charge Injection
50
10
2
4
Off Isolation
Total Harmonic Distortion, THD + N
−90
0.025
Channel-to-Channel Crosstalk
(ADG659)
−90
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 11
−3 dB Bandwidth
ADG658
ADG659
210
400
4
MHz typ RL = 50 Ω, CL = 5 pF;
MHz typ Test Circuit 10
CS (OFF)
pF typ
f = 1 MHz
CD (OFF)
ADG658
ADG659
23
12
pF typ
pF typ
f = 1 MHz
f = 1 MHz
Rev. A | Page 3 of 20
ADG65ꢃ/ADG659
B ꢀersion
−40°C
Y ꢀersion
−40°C
Parameter
CD, CS (ON)
ADG658
+25°C
to +85°C
to+125°C Unit
Test Conditions/Comments
28
16
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG659
POWER REQUIREMENTS
IDD
VDD = +5.5 V, VSS = −5.5 V
Digital Inputs = 0 V or 5.5 V
0.01
0.01
µA typ
µA max
µA typ
µA max
1
1
ISS
Digital Inputs = 0 V or 5.5 V
1 Temperature range is as follows: B Version: −40°C to +85°C. Y Version: −40°C to +125°C.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 20
ADG65ꢃ/ADG659
OPEꢀIFIꢀATIMNO: OINGLE OUPPLY 5V
VDD = 5 V ꢀ0%, VSS = 0 V, GND = 0 V, unless otherwise noted.ꢀ
Table 2.
B ꢀersion Y ꢀersion
−40°C
−40°C
Parameter
+25°C
to +85°C
to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 to VDD
200
V
VDD = 4.5 V, VSS = 0 V
VS = 0 V to 4.5 V, IS = 1 mA;
Test Circuit 1
On Resistance (RON
)
85
150
4.5
8
Ω typ
Ω max
Ω typ
Ω max
Ω typ
160
On Resistance Match between
Channels (∆RON
VS = 3.5 V, IS = 1 mA
)
9
14
10
16
On Resistance Flatness (RFLAT(ON)
)
13
VDD = 5 V, VSS = 0 V
VS = 1.5 V to 4 V, IS = 1 mA
LEAKAGE CURRENTS
VDD = 5.5 V
Source OFF Leakage IS (OFF)
0.005
0.2
0.005
0.2
0.1
0.005
0.2
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VS = 1 V/4.5 V, VD = 4.5 V/1 V;
Test Circuit 2
VS = 1 V/4.5 V, VD = 4.5 V/1 V;
Test Circuit 3
5
Drain OFF Leakage ID (OFF)
ADG658
ADG659
Channel ON Leakage ID, IS (ON)
ADG658
ADG659
5
2.5
VS = VD = 1 V or 4.5 V, Test Circuit 4
5
2.5
0.1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
2
µA typ
µA max
pF typ
VIN = VINL or VINH
1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANS
120
200
120
190
35
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 3 V; Test Circuit 5
RL = 300 Ω, CL = 35 pF
270
245
60
300
280
70
tON (EN)
tOFF (EN)
VS = 3 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF
50
100
VS = 3 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V; Test Circuit 6
VS = 2.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 9
RL = 50 Ω, CL = 5 pF; f = 1 MHz;
Test Circuit 11
Break-Before-Make Time Delay, tBBM
Charge Injection
10
0.5
1
−90
−90
Off Isolation
Channel-to-Channel Crosstalk
(ADG659)
−3 dB Bandwidth
ADG658
ADG659
180
330
5
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF;
Test Circuit 10
f = 1 MHz
CS (OFF)
CD (OFF)
ADG658
ADG659
29
15
pF typ
pF typ
f = 1 MHz
f = 1 MHz
Rev. A | Page 5 of 20
ADG65ꢃ/ADG659
CD, CS (ON)
ADG658
ADG659
30
16
pF typ
pF typ
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
0.01
µA typ
1
µA max
1 Temperature range is as follows: B Version: −40°C to +85°C. Y Version: −40°C to +125°C.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 6 of 20
ADG65ꢃ/ADG659
OPEꢀIFIꢀATIMNO: OINGLE OUPPLY 2.7 TM 3.6 V
VDD = 2.7 to 3.6 V, VSS = 0 V, GND = 0 V, unless otherwise noted.ꢀ
Table 3.
B ꢀersion Y ꢀersion
−40°C
−40°C
Parameter
+25°C
to +85°C
to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 to VDD
400
V
VDD = 2.7 V, VSS = 0 V
VS = 0 V to 2.7 V, IS = 0.1 mA;
Test Circuit 1
On Resistance (RON
)
185
300
2
Ω typ
Ω max
Ω typ
Ω max
350
6
On Resistance Match between
Channels (∆RON
VS = 1.5 V, IS = 0.1 mA
4.5
7
)
LEAKAGE CURRENTS
VDD = 3.3 V
Source OFF Leakage IS (OFF)
0.005
0.2
0.005
0.2
0.1
0.005
0.2
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VS = 1 V/3 V, VD = 3 V/1 V;
Test Circuit 2
VS = 1 V/3 V, VD = 3 V/1 V;
Test Circuit 3
5
Drain OFF Leakage ID (OFF)
ADG658
ADG659
Channel ON Leakage ID, IS (ON)
ADG658
ADG659
5
2.5
VS = VD = 1 V or 3 V, Test Circuit 4
5
2.5
0.1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.5
V min
V max
IINL or IINH
0.005
2
µA typ
µA max
pF typ
VIN = VINL or VINH
1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANS
200
370
230
370
50
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 1.5 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF
440
440
90
490
490
110
10
tON (EN)
VS = 1.5 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF
tOFF (EN)
80
200
VS = 1.5 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; Test Circuit 6
VS = 1.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 9
RL = 50 Ω, CL = 5 pF; f = 1 MHz;
Test Circuit 11
Break-Before-Make Time Delay, tBBM
Charge Injection
1
2
−90
−90
Off Isolation
Channel-to-Channel Crosstalk
(ADG659)
−3 dB Bandwidth
ADG658
ADG659
160
300
5
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF;
Test Circuit 10
f = 1 MHz
CS (OFF)
CD (OFF)
ADG658
ADG659
29
15
pF typ
pF typ
f = 1 MHz
f = 1 MHz
CD, CS (ON)
ADG658
ADG659
30
16
pF typ
pF typ
f = 1 MHz
f = 1 MHz
Rev. A | Page 7 of 20
ADG65ꢃ/ADG659
B ꢀersion Y ꢀersion
−40°C
−40°C
Parameter
+25°C
to +85°C
to +125°C Unit
Test Conditions/Comments
VDD = 3.6 V
Digital Inputs = 0 V or 3.6 V
POWER REQUIREMENTS
IDD
0.01
µA typ
µA max
1
1 Temperature range is as follows: B Version: −40°C to +85°C. Y Version: −40°C to +125°C.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 8 of 20
ADG65ꢃ/ADG659
ABOMLUTE CAXICUC RATINGO
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameters
Ratings
VDD to VSS
13 V
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
−0.3 V to +13 V
+0.3 V to −6.5 V
VSS −0.3 V to VDD +0.3 V
GND −0.3 V to VDD +0.3
V or 10 mA, whichever
occurs first
Peak Current, S or D
40 mA
(Pulsed at 1 ms, 10% duty cycle max)
Continuous Current, S or D
Operating Temperature Range
Automotive (Y Version)
Industrial (B Version)
Storage Temperature Range
Junction Temperature
20 mA
−40°C to +125°C
−40°C to +85°C
−65°C to +150°C
150°C
θJA Thermal Impedance, 16-Lead
QSOP
104°C/W
θJA Thermal Impedance, 16-Lead
TSSOP
150.4°C/W
θJA Thermal Impedance (4-Layer
Board),
16-Lead LFCSP
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD
70°C/W
215°C
220°C
5.5 kV
1
EN
Over voltages at AX, , S, or D are clamped by internal diodes. Current
should be limited to the maximum ratings.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 9 of 20
ADG65ꢃ/ADG659
Table 5. ADG658 Truth Table
A2
A1
A0
EN
Switch Condition
X1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
NONE
1
2
3
4
5
6
7
8
1 X = Don’t Care
Table 6. ADG659 Truth Table
A1
A0
EN
On Switch Pair
X1
0
0
1
X
0
1
0
1
1
0
0
0
0
NONE
1
2
3
4
1
1 X = Don’t Care
Rev. A | Page 10 of 20
ADG65ꢃ/ADG659
PIN ꢀMNFIGURATIMN AND FUNꢀTIMN DEOꢀRIPTIMNO
1
1
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
S5
S7
D
V
S1B
S3B
DB
V
DD
DD
2
3
4
5
6
7
8
2
3
4
5
6
7
8
S3
S2
S1
S4
A0
A1
A2
S3A
S2A
DA
ADG658
TOP VIEW
(Not to Scale)
ADG659
TOP VIEW
(Not to Scale)
S8
S6
S4B
S2B
S1A
S4A
A0
EN
EN
V
V
SS
SS
GND
GND
A1
Figure 2. 16-Lead TSSOP/QSOP
16 15 14 13
16 15 14 13
1
2
3
4
12
1
2
3
4
12
S2A
D
S8
S6
S2
DB
S4B
S2B
ADG658
TOPVIEW
(Not to Scale)
ADG659
TOPVIEW
(Not to Scale)
11 S1
10 S4
11 DA
10 S1A
A0
S4A
9
9
EN
EN
5
6
7
8
5
6
7
8
EXPOSED PAD FLOATING
Figure 3. 4 mm x 4 mm LFCSP
Table 7. Functional Descriptions
Parameter
Description
VDD
VSS
IDD
ISS
Most Positive Power Supply Potential.
Most Negative Power Supply Potential.
Positive Supply Current.
Negative Supply Current.
GND
S
D
Ground (0 V) Reference.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input.
AX
EN
Active Low Digital Input. When high, device is disabled and all switches are OFF. When low, AXlogic inputs determine ON
switch.
VD (VS)
RON
Analog Voltage on Terminals D, S.
Ohmic Resistance between D and S.
On Resistance Match between Any Two Channels, i.e., RONmax − RONmin.
∆RON
RFLAT(ON)
Flatness is defined as the difference between the maximum and minimum value of ON Resistance as measured over the
specified analog signal range.
IS (OFF)
ID (OFF)
ID, IS (ON)
VINL
Source Leakage Current with the Switch OFF.
Drain Leakage Current with the Switch OFF.
Channel Leakage Current with the Switch ON.
Maximum Input Voltage for Logic 0.
VINH
Minimum Input Voltage for Logic 1.
IINL (IINH
)
Input Current of the Digital Input.
CS (OFF)
CD (OFF)
OFF Switch Source Capacitance. Measured with reference to ground.
OFF Switch Drain Capacitance. Measured with reference to ground.
Rev. A | Page 11 of 20
ADG65ꢃ/ADG659
Parameter
Description
CD, CS (ON)
ON Switch Capacitance. Measured with reference to ground.
CIN
Digital Input Capacitance.
tON
tOFF
tBBM
Delay between Applying the Digital Control Input and the Output Switching ON. See Test Circuit 7.
Delay between Applying the Digital Control Input and the Output Switching OFF.
ON Time. Measured between 80% points of both switches when switching from one address state to another.
Measure of the Glitch Impulse Transferred from the Digital Input to the Analog Output during Switching.
Charge
Injection
Off Isolation
Crosstalk
Bandwidth
On Response
Insertion Loss
Measure of Unwanted Signal Coupling through an OFF Switch.
Measure of Unwanted Signal Coupled through from One Channel to Another as a Result of Parasitic Capacitance.
The Frequency at which the Output is Attenuated by 3 dB.
The Frequency Response of the ON Switch.
The Loss Due to the ON Resistance of the Switch.
Rev. A | Page 12 of 20
ADG65ꢃ/ADG659
TYPIꢀAL PERFMRCANꢀE ꢀHARAꢀTERIOTIꢀO
100
T
= 25°C
A
140
120
100
80
90
80
70
60
50
40
30
20
10
0
+125°C
V
, V = ±2.7V
DD SS
+85°C
V
, V = ±3V
DD SS
+25°C
–40°C
60
V
, V = ±5.5V
DD SS
V
, V = ±4.5V
DD SS
40
V
, V = ±5V
DD SS
20
V
V
= 5V
= 0V
DD
SS
0
0
0.5
1.0
1.5
2.0
2.5
, V (V)
3.0
3.5
4.0
4.5
5.0
–5.5
–3.5
–1.5
0.5
2.5
4.5
V
D
S
V
, V (V)
S
D
Figure 7. On Resistance vs. VD (VS) for Different Temperatures (Single Supply)
Figure 4. On Resistance vs. VD (VS) for Dual Supply
300
250
200
150
100
50
T
= 25°C
A
V
= 2.7V
+85°C
DD
250
+125°C
200
150
V
= 3V
DD
V
= 3.3V
DD
+25°C
V
= 4.5V
DD
100
V
= 5V
–40°C
DD
V
= 5.5V
DD
50
V
V
= 3V
= 0V
DD
SS
V
= 12V
4
V
= 10V
8
DD
DD
0
0
0
2
6
10
12
0
0.5
1.0
1.5
V , V (V)
D
2.0
2.5
3.0
V
, V (V)
D
S
S
Figure 5. On Resistance vs. VD (VS) for Single Supply
Figure 8. On Resistance vs. VD (VS) for Different Temperatures (Single Supply)
100
90
80
70
60
50
40
30
20
10
0
1.5
V
V
V
V
= 5V
= –5V
= ±4V
= ±4V
DD
SS
1.0
0.5
D
S
I
(OFF)
+125°C
S
+85°C
+25°C
0
I
(OFF)
D
–0.5
–1.0
–1.5
–2.0
–2.5
I , I (ON)
–40°C
S
D
V
V
= +5V
= –5V
DD
SS
–5
–4
–3
–2
–1
0
1
2
3
4
5
0
20
40
60
80
100
120
V
, V (V)
S
TEMPERATURE (°C)
D
Figure 9. Leakage Current vs. Temperature (Dual Supply)
Figure 6. On Resistance vs. VD (VS) for Different Temperatures (Dual Supply)
Rev. A | Page 13 of 20
ADG65ꢃ/ADG659
350
300
250
200
150
100
50
1.5
V
V
V
V
= +5V
= 0V
V
= 0V
DD
SS
SS
1.0
0.5
V
= 3V
= ±4V
DD
D
S
±
I
(OFF)
S
=
1V
0
I
(OFF)
V
= 5V
= 3V
D
DD
–0.5
–1.0
–1.5
–2.0
–2.5
tON
I , I (ON)
S
D
V
DD
V
V
V
V
= +3V
= 0V
DD
SS
= ±2.4V
D
S
±
tOFF
V
= 5V
=
1V
DD
0
–40
0
20
40
60
80
100
120
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Leakage Current vs. Temperature (Single Supply)
Figure 13. tON/tOFF Times vs. Temperature (Single Supply)
14
0
TA = 25°C
–1
–2
12
10
8
–3
–4
–5
–6
6
–7
–8
4
–9
2
V
V
= +5V
= –5V
–10
–11
–12
–13
–14
–15
DD
SS
0
V
V
= +5V
= –5V
DD
SS
V
V
= +5V
= 0V
DD
SS
–2
T
= 25°C
A
–4
–5
–4
–3
–2
–1
0
1
2
3
4
5
100k
1M
10M
100M
V
(V)
FREQUENCY (Hz)
S
Figure 14. ON Response vs. Frequency (ADG658)
Figure 11. Charge Injection vs. Source Voltage
0
140
120
100
80
V
V
= +5V
= –5V
DD
SS
–2
–4
–6
tON
–8
–10
–12
–14
–16
–18
–20
–22
–24
60
tOFF
40
V
V
= +5V
= –5V
DD
20
SS
T
= 25°C
A
0
100k
1M
10M
100M
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 15. ON Response vs. Frequency (ADG659)
Figure 12. tON/tOFF Times vs. Temperature (Dual Supply)
Rev. A | Page 14 of 20
ADG65ꢃ/ADG659
0
10000
1000
100
10
V
= 0V
SS
V
V
= +5V
= –5V
= 25°C
DD
SS
–20
T
A
V
= 12V
DD
–40
–60
V
= 5V
DD
1
–80
V
= 3V
DD
0.1
–100
–120
0.01
0
2
4
6
V(EN) (V)
8
10
12
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 19. VDD Current vs. Logic Level
Figure 16. OFF Isolation vs. Frequency
3.0
0
V
V
= –5V
= +5V
= 25°C
DD
SS
–10
–20
T
A
2.5
2.0
1.5
1.0
0.5
0
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
2
4
6
8
10
12
100k
1M
10M
100M
V
(V)
DD
FREQUENCY (Hz)
Figure 17. Crosstalk vs. Frequency
Figure 20. Logic Threshold Voltage vs. Supply Voltage
100
10
600Ω
IN AND OUT
V
V
= +5V
= –5V
= 25°C
DD
SS
T
A
1
0.1
0.01
20
50
100
200
500
1k
2k
5k
10k
20k
FREQUENCY (Hz)
Figure 18. THD + Noise
Rev. A | Page 15 of 20
ADG65ꢃ/ADG659
TEOT ꢀIRꢀUITO
I
V
V
SS
DS
DD
V
V
SS
DD
V1
S1
S2
S8
I
(OFF)
A
D
D
V
O
D
S
EN
V
S
GND
LOGIC 1
V
S
Figure 23. Test Circuit 3. ID (OFF)
R
= V /I
1
ON
DS
Figure 21. Test Circuit 1. ON Resistance
V
V
V
V
DD
SS
DD
SS
V
V
SS
DD
I
(ON)
A
S1
S8
D
D
V
V
SS
DD
I
(OFF)
A
S
V
S1
S2
S8
D
EN
V
D
S
V
GND
S
LOGIC 1
EN
V
D
GND
Figure 24. Test Circuit 4. ID (ON)
Figure 22. Test Circuit 2. IS (OFF)
V
V
SS
DD
3V
0V
ADDRESS
DRIVE (V
V
V
DD
SS
S1
50%
50%
)
IN
A2
V
S1
V
A1
A0
IN
50Ω
S2–S7
V
S8
S8
V
ADG658*
GND
S1
90%
V
D
OUT
EN
R
L
300Ω
C
35pF
V
L
OUT
90%
V
S8
* SIMILAR CONNECTION FOR ADG659
tTRANSITION
tTRANSITION
Figure 25. Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
Rev. A | Page 16 of 20
ADG65ꢃ/ADG659
V
V
V
V
DD
DD
SS
3V
0V
ADDRESS
DRIVE (V
SS
)
IN
A2
V
S1
S
V
A1
A0
IN
50Ω
S2–S7
S8
ADG658*
GND
V
D
OUT
EN
80%
80%
R
C
V
OUT
L
L
300Ω
35pF
tBBM
* SIMILAR CONNECTION FOR ADG659
Figure 26. Test Circuit 6. Break-Before-Make Delay, tBBM
V
V
SS
DD
3V
ENABLE
DRIVE (V
V
V
SS
DD
50%
50%
)
A2
A1
A0
IN
V
S1
S
0V
S2–S8
tOFF (EN)
0.9V
ADG658*
GND
V
O
0.9V
O
O
V
D
OUT
EN
C
35pF
R
300Ω
OUTPUT
L
L
V
IN
50Ω
0V
tON (EN)
* SIMILAR CONNECTION FOR ADG659
EN
), tOFF
EN
)
Figure 27. Test Circuit 7. Enable Delay, tON
(
(
V
V
SS
DD
A2 V
DD
V
SS
3V
A1
A0
S
LOGIC INPUT
ADG658*
(V
)
IN
R
S
S
D
0V
V
OUT
C
1nF
V
L
EN
V
GND
IN
V
∆V
OUT
OUT
Q
= C × ∆V
L OUT
INJ
* SIMILAR CONNECTION FOR ADG659
Figure 28. Test Circuit 8. Charge Injection
Rev. A | Page 17 of 20
ADG65ꢃ/ADG659
V
V
V
V
V
DD
SS
0.1µF
DD
SS
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
SS
V
DD
DD
SS
A2
A1
A0
A2
50Ω
50Ω
A1
A0
S
S
50Ω
V
V
S
S
D
D
V
V
OUT
OUT
LOGIC 1
EN
EN
R
R
L
L
50Ω
50Ω
GND
GND
V
OUT
V
WITH SWITCH
OUT
OFF ISOLATION = 20 LOG
V
INSERTION LOSS = 20 LOG
S
V
WITHOUT SWITCH
OUT
Figure 29. Test Circuit 9. Off Isolation
Figure 30. Test Circuit 10. Bandwidth
V
V
V
V
DD
DD
SS
SS
0.1µF
0.1µF
A1
A0
NETWORK
ANALYZER
EN
ADG659
GND
NETWORK
ANALYZER
50Ω
DA
DB
S1A
V
OUT
S1B
DB
R
L
50Ω
50Ω
V
S
DA
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG
V
S
Figure 31. Test Circuit 11. Channel-to-Channel Crosstalk
Rev. A | Page 18 of 20
ADG65ꢃ/ADG659
MUTLINE DICENOIMNO
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 32. 16-Lead Thin Shrink Small Outline Package [TSSOP]
( RU-16)
Dimensions shown in millimeters
4.0
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
13
16
12
1
0.65 BSC
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
TOP
VIEW
EXPOSED
3.75
BSC SQ
PAD
(BOTTOM VIEW)
0.75
0.60
0.50
4
9
8
5
0.25 MIN
1.95 BSC
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.35
0.28
0.25
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
Figure 33. 16-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-16-4)
Dimensions shown in millimeters
Rev. A | Page 19 of 20
ADG65ꢃ/ADG659
0.193
BSC
16
1
9
8
0.154
BSC
0.236
BSC
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AB
Figure 34. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG658YRU
ADG658YRU-REEL7
ADG658YCP
ADG658YCP-REEL7
ADG658YRQ
ADG658YRQ-REEL
ADG658YRQ-REEL7
ADG659YRU
ADG659YRU-REEL7
ADG659YCP
ADG659YCP-REEL7
ADG659YCPZ1
ADG659YCPZ-REEL71
Temperature Range
Package Description
Package Option
RU-16
RU-16
CP-16
CP-16
RQ-16
RQ-16
RQ-16
RU-16
RU-16
CP-16
CP-16
CP-16
CP-16
RQ-16
RQ-16
RQ-16
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Shrink Small Outline Package (QSOP)
Shrink Small Outline Package (QSOP)
Shrink Small Outline Package (QSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Shrink Small Outline Package (QSOP)
Shrink Small Outline Package (QSOP)
Shrink Small Outline Package (QSOP)
ADG659YRQ
ADG659YRQ-REEL
ADG659YRQ-REEL7
1 Z = Pb-free part.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03273-0-7/04(A)
Rev. A | Page 20 of 20
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