ADG714_13 [ADI]
CMOS, Low Voltage Serially Controlled, Octal SPST Switches; CMOS ，低电压串行控制，八通道SPST开关
| 型号： | ADG714_13 |
| 厂家： | 
ADI |
| 描述： | CMOS, Low Voltage Serially Controlled, Octal SPST Switches |
| 文件： | 总16页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, Low Voltage
Serially Controlled, Octal SPST Switches
a
ADG714/ADG715
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface
ADG715 I2C™-Compatible Interface
2.7 V to 5.5 V Single Supply
ꢀ2.5 V Dual Supply
ADG715
ADG714
D1
D2
D3
D4
D5
D6
D7
D8
S1
S2
S3
S4
S5
S6
S7
S8
D1
D2
D3
D4
D5
D6
D7
D8
S1
S2
S3
S4
S5
S6
S7
S8
2.5 ꢁ On Resistance
0.6 ꢁ On Resistance Flatness
100 pA Leakage Currents
Octal SPST
Power-On Reset
Fast Switching Times
TTL/CMOS-Compatible
Small TSSOP Package
INTERFACE
LOGIC
INPUT SHIFT
REGISTER
DOUT
RESET
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
SDA SCL A0 A1
SCLK DIN SYNC RESET
Audio and Video Switching
On power-up of these devices, all switches are in the OFF con-
dition, and the internal registers contain all zeros.
GENERAL DESCRIPTION
The ADG714/ADG715 are CMOS, octal SPST (single-pole,
single-throw) switches controlled via either a 2- or 3-wire serial
interface. On resistance is closely matched between switches and
very flat over the full signal range. Each switch conducts equally
well in both directions and the input signal range extends to the
supplies. Data is written to these devices in the form of 8 bits,
each bit corresponding to one channel.
Low power consumption and operating supply range of 2.7 V to
5.5 V make this part ideal for many applications. These parts
may also be supplied from a dual 2.5 V supply. The ADG714
and ADG715 are available in a small 24-lead TSSOP package.
PRODUCT HIGHLIGHTS
1. 2- or 3-wire serial interface
The ADG714 uses a 3-wire serial interface that is compatible
with SPI , QSPI, and MICROWIRE and most DSP interface
standards. The output of the shift register DOUT enables a
number of these parts to be daisy chained.
2. Single/dual supply operation. The ADG714 and ADG715
are fully specified and guaranteed with 3 V, 5 V, and 2.5 V
supply rails.
The ADG715 uses a 2-wire serial interface that is compatible
with the I2C interface standard. The ADG715 has four hard wired
addresses, selectable from two external address pins (A0 and A1).
This allows the 2 LSBs of the 7-bit slave address to be set by
the user. A maximum of four of these devices may be connected
to the bus.
3. Low on resistance, typically 2.5 Ω
4. Low leakage
5. Power-on reset
6. Small 24-lead TSSOP package
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
I2C is a trademark of Philips Corporation.
C
REV.
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reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
781/461-3113
www.analog.com
2013
© Analog Devices, Inc.,
Fax:
ADG714/ADG715–SPECIFICATIONS1
(VDD = 5 V ꢀ 10%, VSS = 0 V, GND = 0 V unless otherwise noted.)
B Version
–40ꢂC
Parameter
+25ꢂC
to +85ꢂC
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
2.5
4.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IS = 10 mA
5
0.4
0.8
On Resistance Match Between Channels (ΔRON
)
VS = 0 V to VDD, IS = 10 mA
VS = 0 V to VDD, IS = 10 mA
On Resistance Flatness (RFLAT(ON)
)
0.6
1.2
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = 5.5 V
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V
VD = VS = 1 V, or 4.5 V
0.3
0.3
0.3
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1)
Input High Voltage, VINH
Input Low Voltage, VINL
2.4
0.8
V min
V max
μA typ
μA max
pF typ
Input Current, IINL or IINH
0.005
3
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance2
DIGITAL OUTPUT ADG714 DOUT2
Output Low Voltage
COUT Digital Output Capacitance
0.4
V max
pF typ
ISINK = 6 mA
4
DIGITAL INPUTS (SCL, SDA)2
Input High Voltage, VINH
0.7 VDD
V min
V
DD + 0.3 V max
Input Low Voltage, VINL
–0.3
0.3 VDD
V min
V max
μA typ
μA max
V min
pF typ
I
IN, Input Leakage Current
HYST, Input Hysteresis
0.005
VIN = 0 V to VDD
1
V
0.05 VDD
6
CIN, Input Capacitance
LOGIC OUTPUT (SDA)2
VOL, Output Low Voltage
0.4
0.6
V max
V max
ISINK = 3 mA
ISINK = 6 mA
DYNAMIC CHARACTERISTICS2
tON ADG714
20
95
8
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
VS = 3 V, RL = 300 Ω, CL = 35 pF
VS = 3 V, RL = 300 Ω, CL = 35 pF
VS = 3 V, RL = 300 Ω, CL = 35 pF
VS = 3 V, RL = 300 Ω, CL = 35 pF
VS = 3 V, RL = 300 Ω, CL = 35 pF
32
tON ADG715
tOFF ADG714
140
15
t
OFF ADG715
85
8
130
1
ns max
ns typ
Break-Before-Make Time Delay, tD
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
Charge Injection
Off Isolation
3
VS = 2 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF
–60
–80
–70
–90
155
11
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
C
D (OFF)
11
22
CD, CS (ON)
POWER REQUIREMENTS
IDD
V
DD = 5.5 V
10
μA typ
μA max
Digital Inputs = 0 V or 5.5 V
20
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
C
REV.
–2–
ADG714/ADG715
SPECIFICATIONS1
(VDD = 3 V ꢀ10%, VSS = 0 V, GND = 0 V unless otherwise noted.)
B Version
–40ꢂC
to +85ꢂC
Parameter
+25ꢂC
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
6
11
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = 10 mA
VS = 0 V to VDD, IS = 10 mA
VS = 0 V to VDD, IS = 10 mA
12
On Resistance Match Between Channels (ΔRON
)
0.4
1.2
3.5
On Resistance Flatness (RFLAT(ON)
)
LEAKAGE CURRENTS
VDD = 3.3 V
Source OFF Leakage IS (OFF)
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V
0.3
0.3
0.3
Drain OFF Leakage ID (OFF)
VS = 1 V/3 V, VD = 3 V/1 V
VS = VD = 1 V, or 3 V
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS (SCLK, DIN, SYNC, A0, A1)
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.005
3
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance2
DIGITAL OUTPUT ADG714 DOUT2
Output Low Voltage
COUT Digital Output Capacitance
0.4
V max
pF typ
ISINK = 6 mA
4
DIGITAL INPUTS (SCL, SDA)2
Input High Voltage, VINH
0.7 VDD
V min
VDD + 0.3 V max
Input Low Voltage, VINL
IIN, Input Leakage Current
–0.3
0.3 VDD
V min
V max
μA typ
μA max
V min
pF typ
0.005
VIN = 0 V to VDD
1
VHYST, Input Hysteresis
CIN, Input Capacitance
0.05 VDD
6
LOGIC OUTPUT (SDA)2
VOL, Output Low Voltage
0.4
0.6
V max
V max
ISINK = 3 mA
ISINK = 6 mA
DYNAMIC CHARACTERISTICS2
tON ADG714
35
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
VS = 2 V, RL = 300 Ω, CL = 35 pF
VS = 2 V, RL = 300 Ω, CL = 35 pF
VS = 2 V, RL = 300 Ω, CL = 35 pF
VS = 2 V, RL = 300 Ω, CL = 35 pF
VS = 2 V, RL = 300 Ω, CL = 35 pF
65
t
ON ADG715
130
11
200
20
tOFF ADG714
tOFF ADG715
115
8
180
1
ns max
ns typ
Break-Before-Make Time Delay, tD
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
Charge Injection
Off Isolation
2
VS = 1.5 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF
–60
–80
–70
–90
155
11
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
CD (OFF)
CD, CS (ON)
11
22
POWER REQUIREMENTS
IDD
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
10
μA typ
μA max
20
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
C
REV.
–3–
ADG714/ADG715–SPECIFICATIONS1
(VDD = +2.5 V ꢀ10% VSS = −2.5 V ꢀ10% ꢁGD = 1 V unless otherwise noted.)
DUAL SUPPLY
B Version
–40ꢂC
to +85ꢂC
Parameter
+25ꢂC
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS to VDD
V
On Resistance (RON
)
2.5
4.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to VDD, IDS = 10 mA
VS = VSS to VDD, IDS = 10 mA
VS = VSS to VDD, IDS = 10 mA
5
0.4
0.8
On Resistance Match Between Channels (ΔRON
)
On Resistance Flatness (RFLAT(ON)
)
0.6
1
LEAKAGE CURRENTS
VDD = +2.75 V, VSS = –2.75 V
Source OFF Leakage IS (OFF)
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V
0.3
0.3
0.3
Drain OFF Leakage ID (OFF)
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V
VS = VD = +2.25 V/–1.25 V
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
1.7
0.7
V min
V max
μA typ
μA max
pF typ
0.005
3
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance2
DIGITAL OUTPUT ADG714 DOUT2
Output Low Voltage
0.4
V max
pF typ
ISINK = 6 mA
COUT Digital Output Capacitance
4
DIGITAL INPUTS (SCL, SDA)2
Input High Voltage, VINH
0.7 VDD
V min
VDD + 0.3 V max
Input Low Voltage, VINL
IIN, Input Leakage Current
–0.3
0.3 VDD
V min
V max
μA typ
μA max
V min
pF typ
0.005
VIN = 0 V to VDD
1
VHYST, Input Hysteresis
CIN, Input Capacitance
0.05 VDD
6
LOGIC OUTPUT (SDA)2
VOL, Output Low Voltage
0.4
0.6
V max
V max
ISINK = 3 mA
ISINK = 6 mA
DYNAMIC CHARACTERISTICS2
tON ADG714
20
133
8
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
VS = 1.5 V, RL = 300 Ω, CL = 35 pF
32
tON ADG715
200
18
tOFF ADG714
tOFF ADG715
124
8
190
1
ns max
ns typ
Break-Before-Make Time Delay, tD
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
Charge Injection
Off Isolation
3
VS = 0 V, RS = 0 Ω, CL = 1 nF
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz
RL = 50 Ω, CL = 5 pF
–60
–80
–70
–90
155
11
Channel-to-Channel Crosstalk
–3 dB Bandwidth
CS (OFF)
CD (OFF)
CD, CS (ON)
11
22
POWER REQUIREMENTS
IDD
VDD = +2.75 V, VSS = –2.75 V
Digital Inputs = 0 V or
VDD
15
15
μA typ
μA max
μA typ
μA max
25
25
ISS
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
C
REV.
–4–
ADG714/ADG715
ADG714 TIMING CHARACTERISTICS1, 2(VDD = 2.7 V to 5.5 V. All specifications –40ꢂC to +85ꢂC unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
30
33
13
13
0
5
4.5
0
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Rising Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SCLK Rising Edge to DOUT Valid
t83
33
20
t9
NOTES
1See Figure 1.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3CL = 20 pF, RL = 1 kΩ.
Specifications subject to change without notice.
t1
SCLK
t3
t8
t2
t7
t4
SYNC
t6
t5
DB7
t9
DB0
DIN
*
*
*
*
*
DB7
DB6
DB2
DB1
DB0
DOUT
*
DATA FROM PREVIOUS WRITE CYCLE
Figure 1. 3-Wire Serial Interface Timing Diagram
C
REV.
–5–
ADG714/ADG715
ADG715 TIMING CHARACTERISTICS1
(VDD = 2.7 V to 5.5 V. All specifications –40ꢂC to +85ꢂC unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCL
t1
t2
t3
t4
400
2.5
0.6
1.3
0.6
100
0.9
0
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
SCL Clock Frequency
SCL Cycle Time
tHIGH, SCL High Time
tLOW, SCL Low Time
tHD, STA, Start/Repeated Start Condition Hold Time
tSU, DAT, Data Setup Time
tHD, DAT, Data Hold Time
t52
t6
t7
t8
t9
0.6
0.6
1.3
tSU, STA, Setup Time for Repeated Start
tSU, STO, Stop Condition Setup Time
tBUF, Bus Free Time Between a STOP Condition and
a Start Condition
t10
300
20 + 0.1Cb
250
300
0.1Cb
ns max
ns min
ns max
ns max
ns min
pF max
ns max
tR, Rise Time of Both SCL and SDA When Receiving
3
t11
t11
tF, Fall Time of SDA When Receiving
tF, Fall Time of SDA When Transmitting
3
Cb4
tSP
400
50
Capacitive Load for Each Bus Line
Pulsewidth of Spike Suppressed
NOTES
1See Figure 2.
2A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
3Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD
4Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
.
Specifications subject to change without notice.
SDA
t9
t3
t4
t11
t10
SCL
t2
t4
t8
t5
t7
t1
t6
START
CONDITION
REPEATED
STOP
CONDITION
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
C
REV.
–6–
ADG714/ADG715
ABSOLUTE MAXIMUM RATINGS1
TSSOP Package
(TA = 25°C unless otherwise noted.)
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 128°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 42°C/W
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs2 . . . . . . . . . . . . . . . . . VSS –0.3 V to VDD +0.3 V
or 30 mA, Whichever Occurs First
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
Infrared Reflow (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 235°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Digital Inputs2 . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
or 30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
2Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG714/ADG715 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
24-Lead TSSOP
1
2
24
23
22
21
20
19
18
17
16
15
SCLK
1
2
24
23
22
21
20
19
18
17
16
15
14
13
SCL
A0
SYNC
RESET
DOUT
V
V
RESET
DD
DD
3
3
A1
SDA
GND
S1
DIN
GND
S1
4
4
V
V
SS
SS
5
5
S8
D8
S7
D7
S6
D6
S8
D8
S7
D7
S6
D6
S5
D5
ADG715
TOP VIEW
(Not to Scale)
ADG714
TOP VIEW
(Not to Scale)
6
6
D1
D1
7
7
S2
S2
8
8
D2
D2
9
9
S3
S3
10
11
12
10
11
12
D3
D3
14 S5
13 D5
S4
S4
D4
D4
C
REV.
–7–
ADG714/ADG715
ADG714 PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic
1
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. These devices can accommodate serial input rates of up to 30 MHz.
2
3
VDD
DIN
Positive Analog Supply Voltage.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial
clock input.
4
GND
Sx
Ground Reference
Source. May be an input or output.
5, 7, 9, 11, 14,
16, 18, 20
6, 8, 10, 12, 13, Dx
15, 17, 19
Drain. May be an input or output.
21
22
VSS
DOUT
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
Serial Data Output. This allows a number a parts to be daisy chained. Data is clocked out of
the input shift register on the rising edge of SCLK. DOUT is an open-drain output that should be
pulled to the supply with an external pull-up resistor.
23
24
RESET
SYNC
Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled.
Data is transferred on the falling edges of the following clocks. Taking SYNC high updates the
switches.
ADG715 PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic
1
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit
input shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire
serial interface.
2
3
VDD
SDA
Positive Analog Supply Voltage
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 8-bit input
shift register during the write cycle and used to readback one byte of data during the read cycle. It
is a bidirectional open-drain data line which should be pulled to the supply with an external pull-
up resistor.
4
GND
Sx
Ground Reference
Source. May be an input or output.
5, 7, 9, 11, 14,
16, 18, 20
6, 8, 10, 12, 13, Dx
15, 17, 19
Drain. May be an input or output.
21
22
23
24
VSS
Negative Analog Supply Voltage. For single supply operation this should be tied to GND.
Address Input. Sets the second least significant bit of the 7-bit slave address.
Active Low Control Input. Clears the input register and turns all switches to the OFF condition.
Address Input. Sets the least significant bit of the 7-bit slave address.
A1
RESET
A0
C
REV.
–8–
ADG714/ADG715
TERMINOLOGY
VDD
VSS
Most positive power supply potential.
CD, CS (ON) “ON” Switch Capacitance. Measured with ref-
erence to ground.
Most negative power supply in a dual supply
application. In single supply applications, this
should be tied to ground.
Positive Supply Current
Negative Supply Current
CIN
tON
Digital Input Capacitance
Delay time between loading new data to the
shift register and selected switches switching on.
IDD
ISS
GND
S
D
RON
ΔRON
tOFF
Delay time between loading new data to the
shift register and selected switches switching off.
Ground (0 V) Reference
Off Isolation
Crosstalk
A measure of unwanted signal coupling through
an “OFF” switch.
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Ohmic resistance between D and S
On resistance match between any two channels,
i.e., RON max–RON min.
Charge
Injection
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
RFLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on resistance
as measured over the specified analog signal range.
Bandwidth
The frequency at which the output is attenuated
by –3 dBs.
IS (OFF)
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Analog voltage on terminals D and S
On Response The frequency response of the “ON” switch.
Insertion Loss The loss due to the ON resistance of the switch.
Insertion Loss = 20 log10 (VOUT with switch/
I
D (OFF)
ID, IS (ON)
VD (VS)
V
OUT without switch.
CS (OFF)
“OFF” Switch Source Capacitance. Measured
with reference to ground.
VINL
VINH
Maximum input voltage for Logic 0.
Minimum input voltage for Logic 1.
Input current of the digital input.
Positive Supply Current
CD (OFF)
“OFF” Switch Drain Capacitance. Measured
with reference to ground.
I
INL(IINH
)
IDD
C
REV.
–9–
ADG714/ADG715–Typical Performance Characteristics
8
8
7
6
5
V
V
= 3V
= GND
DD
SS
T
V
= 25ꢂC
A
7
6
5
4
= GND
SS
V
= 2.7V
DD
+85ꢂC
–40ꢂC
+25ꢂC
V
= 3.3V
DD
4
3
2
1
0
V
= 4.5V
DD
V
= 5.5V
DD
3
2
1
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
0
V
, V , DRAIN OR SOURCE VOLTAGE – V
V OR V DRAIN OR SOURCE VOLTAGE – V
D S
D
S
TPC 1. On Resistance as a Function of VD (VS) Single
Supply
TPC 4. On Resistance as a Function of VD (VS) for
Different Temperatures; VDD = 3 V
8
8
T
= 25ꢂC
V
= +2.5V
= –2.5V
A
DD
7
V
7
6
5
SS
6
5
4
3
4
3
2
1
V
SS
= +2.25V
= –2.25V
+25ꢂC
DD
V
+85ꢂC
–40ꢂC
2
1
V
SS
= +2.5V
= –2.5V
DD
V
V
= +2.75V
= –2.75V
V
DD
SS
0
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
2.5
–2.7 –2.1 –1.5 –0.9 –0.3
0.3
0.9
1.5
2.1
2.7
V
OR V DRAIN OR SOURCE VOLTAGE – V
V
OR V DRAIN OR SOURCE VOLTAGE – V
S
D
S
D
TPC 2. On Resistance as a Function of VD (VS); Dual
Supply
TPC 5. On Resistance as a Function of VD (VS) for
Different Temperatures; Dual Supply
0.04
8
V
V
= 5V
= GND
= 25ꢂC
DD
V
V
= 5V
= GND
DD
SS
SS
7
6
T
A
0.02
0
I
, I (ON)
D
S
5
4
3
2
+85ꢂC
+25ꢂC
–40ꢂC
I
(OFF)
D
–0.02
–0.04
I (OFF)
S
1
0
0
1
2
D
3
4
5
0
1
2
3
4
5
V
OR V DRAIN OR SOURCE VOLTAGE – V
S
V
OR V – Volts
S
D
TPC 3. On Resistance as a Function of VD (VS) for
Different Temperatures; VDD = 5 V
TPC 6. Leakage Currents as a Function of VD (VS)
C
REV.
–10–
ADG714/ADG715
0.04
0.02
0.1
V
= 3V
= GND
= 25ꢂC
DD
V
V
V
V
= 3V
= GND
= 3V/1V
= 1V/3V
DD
V
SS
SS
T
A
D
S
0.05
I
, I (ON)
D
S
I
, I (ON)
S
D
0
–0.02
–0.04
0
–0.05
–0.1
I (OFF)
D
I
(OFF)
S
I
(OFF)
D
I
(OFF)
S
0
0.5
1.0
1.5
VOLTAGE – V
2.0
2.5
3.0
10
20
30
40
50
60
70
80
TEMPERATURE – ꢂC
TPC 7. Leakage Currents as a Function of VD (VS)
TPC 10. Leakage Currents as a Function of Temperature
0.04
0
V
= +2.5V
= –2.5V
= 25ꢂC
DD
V
= 5V
= 25ꢂC
DD
V
SS
T
A
T
A
–20
–40
0.02
I
(OFF)
D
I
(OFF)
S
0
–0.02
–0.04
–60
I
, I (ON)
D
–80
S
–100
–120
–2
–1
0
1
2
30k
100k
1M
10M
100M
VOLTAGE – V
FREQUENCY – Hz
TPC 8. Leakage Currents as a Function of VD (VS) Dual
Supply
TPC 11. Off Isolation vs. Frequency
0.1
0
–2
–4
–6
V
V
V
V
= +2.75V
= –2.75V
= +2.25V/–1.25V
= –1.25V/+2.25V
V
V
V
V
= +5V
= GND
= 4.5V/1V
= 1V/4.5V
DD
SS
DD
SS
I
, I (ON)
D
S
D
S
D
S
0.05
I
(OFF)
0
–0.05
–0.1
S
I
(OFF)
–8
D
–10
–12
–14
10
20
30
40
50
60
70
80
30k
100k
1M
10M
100M 300M
TEMPERATURE – ꢂC
FREQUENCY – Hz
TPC 9. Leakage Currents as Function of Temperature
TPC 12. On Response vs. Frequency
C
REV.
–11–
ADG714/ADG715
–40
–50
–60
–70
–80
–90
–100
GENERAL DESCRIPTION
V
= 5V
= 25ꢂC
DD
The ADG714 and ADG715 are serially controlled, octal SPST
switches, controlled by either a 2- or 3-wire interface. Each bit
of the 8-bit serial word corresponds to one switch of the part. A
Logic 1 in the particular bit position turns on the switch, while a
Logic 0 turns the switch off. Because each switch is independently
controlled by an individual bit, this provides the option of having
any, all, or none of the switches ON.
T
A
When changing the switch conditions, a new 8-bit word is writ-
ten to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. To minimize glitches on the output
of these switches, the part cleverly compares the state of switches
from the previous write cycle. If the switch is already in the
ON condition, and is required to stay ON, there will be minimal
glitches on the output of the switch.
30k
100k
1M
10M
100M
FREQUENCY – Hz
TPC 13. Crosstalk vs. Frequency
POWER-ON RESET
On power-up of the device, all switches will be in the OFF con-
dition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.
10
5
T
= 25ꢂC
A
V
V
= +3.3V
= GND
DD
SS
SERIAL INTERFACE
3-Wire Serial Interface
The ADG714 has a 3-wire serial interface (SYNC, SCLK, and
DIN), that is compatible with SPI, QSPI, MICROWIRE
interface standards and most DSPs. Figure 1 shows the tim-
ing diagram of a typical write sequence.
0
V
V
= +5V
= GND
V
V
= +2.5V
= –2.5V
DD
SS
DD
SS
–5
–10
Data is written to the 8-bit shift register via DIN under the con-
trol of the SYNC and SCLK signals. Data may be written to
the shift register in more or less than eight bits. In each case
the shift register retains the last eight bits that were written.
–15
–20
–3
–2
–1
0
1
2
3
4
5
VOLTAGE – V
When SYNC goes low, the input shift register is enabled. Data
from DIN is clocked into the shift register on the falling edge of
SCLK. Each bit of the 8-bit word corresponds to one of the eight
switches. Figure 3 shows the contents of the input shift register.
Data appears on the DOUT pin on the rising edge of SCLK
suitable for daisy chaining, delayed of course by eight bits. When
all eight bits have been written into the shift register, the SYNC
line is brought high again. The switches are updated with the
new configuration and the input shift register is disabled. With
SYNC held high, the input shift register is disabled, so further data
or noise on the DIN line will have no effect on the shift register.
TPC 14. Charge Injection vs. Source/Drain Voltage
45
V
= GND
SS
40
35
30
25
20
15
10
5
T
, V = 3V
DD
ON
T
, V = 5V
DD
ON
DB7 (MSB)
DB0 (LSB)
T
, V = 3V
S8 S7 S6 S5 S4 S3 S2 S1
OFF
DD
DATA BITS
Figure 3. Input Shift Register Contents
T
, V = 5V
DD
OFF
0
10
SERIAL INTERFACE
2-Wire Serial Interface
20
30
40
50
60
70
80
TEMPERATURE – ꢂC
The ADG715 is controlled via an I2C-compatible serial bus.
This device is connected to the bus as a slave device (no clock is
generated by the switch).
TPC 15. TON/TOFF Times vs. Temperature for ADG714
The ADG715 has a 7-bit slave address. The five MSBs are 10010
and the two LSBs are determined by the state of the A0 and
A1 pins.
C
REV.
–12–
ADG714/ADG715
The 2-wire serial bus protocol operates as follows:
A repeated write function gives the user flexibility to update the
matrix switch a number of times after addressing the part only
once. During the write cycle, each data byte will update the con-
figuration of the switches. For example, after the matrix switch
has acknowledged its address byte, and received one data byte,
the switches will update after the data byte; if another data byte
is written to the matrix switch while it is still the addressed slave
device, this data byte will also cause a switch configuration update.
Repeat read of the matrix switch is also allowed.
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is the
address byte that consists of the 7-bit slave address followed
by a R/W bit (this bit determines whether data will be read
from or written to the slave device).
The slave whose address corresponds to the transmitted address
responds by pulling the SDA line low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage,
all other devices on the bus remain idle while the selected
device waits for data to be written to or read from its serial
register. If the R/W bit is high, the master will read from the
slave device. However, if the R/W bit is low, the master will
write to the slave device.
Input Shift Register
The input shift register is eight bits wide. Figure 3 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure
2. The 8-bit word consists of eight data bits, each controlling
one switch. MSB (Bit 7) is loaded first.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
Write Operation
When writing to the ADG715, the user must begin with an address
byte and R/W bit, after which the switch will acknowledge that
it is prepared to receive data by pulling SDA low. This address
byte is followed by the 8-bit word. The write operation for the
switch is shown in the Figure 4.
3. When all data bits have been read or written, a STOP con-
dition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition. In read mode, the master will issue a no acknowledge
for the ninth clock pulse (i.e., the SDA line remains high).
The master will then bring the SDA line low before the tenth
clock pulse and then high during the tenth clock pulse to estab-
lish a STOP condition.
READ Operation
When reading data back from the ADG715, the user must begin
with an address byte and R/W bit, after which the switch will
acknowledge that it is prepared to transmit data by pulling SDA
low. The readback operation is a single byte that consists of the
eight data bits in the input register. The read operation for the
part is shown in Figure 5.
See Figure 4 for a graphical explanation of the serial interface.
SCL
A1
SDA
1
0
0
1
0
A0
R/W
S8
S7
S6
S5
S4
S3
S2
S1
STOP
COND
BY
START
COND
BY
ACK
BY
ADG715
ACK
BY
ADG715
DATA BYTE
ADDRESS BYTE
MASTER
MASTER
Figure 4. ADG715 Write Sequence
SCL
A1
SDA
0
0
1
0
A0
R/W
S8
S7
S6
S5
S4
S3
S2
S1
1
START
COND
BY
ACK
BY
ADG715
NO ACK
BY
MASTER
STOP
COND
BY
ADDRESS BYTE
DATA BYTE
MASTER
MASTER
Figure 5. ADG715 Readback Sequence
C
REV.
–13–
ADG714/ADG715
APPLICATIONS
Power Supply Sequencing
Multiple Devices On One Bus
When using CMOS devices, care must be taken to ensure correct
power-supply sequencing. Incorrect power-supply sequencing
can result in the device being subjected to stresses beyond those
maximum ratings listed in the data sheet. Digital and analog inputs
should always be applied after power supplies and ground. In dual
supply applications, if digital or analog inputs may be applied to
the device prior to the VDD and VSS supplies, the addition of a
Schottky diode connected between VSS and GND will ensure
that the device powers on correctly. For single supply operation,
VSS should be tied to GND as close to the device as possible.
Figure 6 shows four ADG715 devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each switch to be written to or
read from independently.
Daisy-Chaining Multiple ADG714s
A number of ADG714 switches may be daisy-chained simply by
using the DOUT pin. Figure 7 shows a typical implementation.
The SYNC pin of all three parts in the example are tied
together. When SYNC is brought low, the input shift registers
of all parts are enabled, data is written to the parts via DIN, and
clocked through the shift registers. When the transfer is complete,
SYNC is brought high and all switches are updated simulta-
neously. Further shift registers may be added in series.
Decoding Multiple ADG714s Using an ADG739
The dual 4-channel ADG739 multiplexer can be used to multiplex
a single chip select line to provide chip selects for up to four
V
DD
R
R
P
P
SDA
SCL
MASTER
V
V
V
DD
DD
DD
SDA
A1
A0
SCL
SDA
A1
A0
SCL
SDA
A1
A0
SCL
SDA
A1
A0
SCL
ADG715
ADG715
ADG715
ADG715
Figure 6. Multiple ADG715s On One Bus
-
V
V
V
DD
DD
DD
R
R
R
SCLK
DIN
SCLK
SCLK
SCLK
ADG714
DIN
ADG714
DIN
ADG714
DIN
DOUT
DOUT
DOUT
TO
OTHER
SERIAL
DEVICES
SYNC
SYNC
SYNC
SYNC
Figure 7. Multiple ADG714 Devices in a Daisy-Chained Configuration
C
REV.
–14–
ADG714/ADG715
VDD
devices on the SPI bus. Figure 8 illustrates the ADG739 and mul-
tiple ADG714s in such a typical configuration. All devices receive
the same serial clock and serial data, but only one device will
receive the SYNC signal at any one time. The ADG739 is a serially
controlled device also. One bit programmable pin of the micro-
controller is used to enable the ADG739 via SYNC2, while
another bit programmable pin is used as the chip select for the
other serial devices, SYNC1. Driving SYNC2 low enables
changes to be made to the addressed serial devices. By bringing
SYNC1 low, the selected serial device hanging from the SPI bus
will be enabled and data will be clocked into its shift register on
the falling edges of SCLK. The convenient design of the matrix
switch allows for different combinations of the four serial
devices to be addressed at any one time. If more devices need
to be addressed via one chip select line, the ADG738 is an 8-
channel device and would allow further expansion of the chip
select scheme. There may be some digital feedthrough from the
digital input lines because SCLK and DIN are permanently
connected to each device. Using a burst clock will minimize the
effects of digital feedthrough on the analog channels.
ADG714
R
R
R
SYNC
DIN
SCLK
VDD
VDD
ADG714
V
SYNC
DD
DIN
SCLK
1/2 of ADG739
DA
S1A
S2A
S3A
S4A
OTHER
SPI
DEVICE
SYNC1
SYNC2
SYNC
DIN
SCLK
DIN
SYNC
SCLK
FROM
ꢃCONTROLLER
VDD
OTHER
SPI
DEVICE
OR DSP
R
SYNC
DIN
DIN
SCLK
SCLK
Figure 8. Addressing Multiple ADG714s Using an
ADG739
C
REV.
–15–
ADG714/ADG715
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 1. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERIGꢁ ꢁUIDE
Modelꢀ
ADG714BRU-REEL
ADG714BRU-REEL7
ADG714BRUZ
ADG714BRUZ-REEL
ADG714BRUZ-REEL7
ADG715BRU
ADG715BRU-REEL
ADG715BRU-REEL7
ADG715BRUZ
Temperature Range
Package Description
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
Package Option
RU-24
RU-24
RU-24
RU-24
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
ADG715BRUZ-REEL
ADG715BRUZ-REEL7
1 Z = RoHS Compliant Part.
REVISIOG HISTORY
1/13—Rev. B to Rev. C
Changes to Dual Supply Table Summary and IDD Test
Conditions/Comments.....................................................................4
Changes to Ordering Guide...........................................................16
11/02—Rev. A to Rev. B
Edits to Features ................................................................................1
Edits to General Description ...........................................................1
Edits to Product Highlights .............................................................1
Edits to Specifications...................................................................3, 4
Edits to TPCs 2 and 5 .....................................................................10
Edits to TPCs 8 and 9 .....................................................................11
Edits to TPCs 14..............................................................................12
Edits to Figure 8...............................................................................15
©21ꢀ3 Analog Devices% Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11143-1-ꢀ/ꢀ3(C)
–16–
REV. C
相关型号：
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