ADG721BRM [ADI]
CMOS Low Voltage 4 ohm Dual SPST Switches; CMOS低电压4欧姆双通道SPST开关
| 型号： | ADG721BRM |
| 厂家： | 
ADI |
| 描述： | CMOS Low Voltage 4 ohm Dual SPST Switches |
| 文件： | 总8页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS
a
Low Voltage 4 ⍀ Dual SPST Switches
ADG721/ADG722/ADG723
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
+1.8 V to +5.5 V Single Supply
4 ⍀ (Max) On Resistance
Low On-Resistance Flatness
–3 dB Bandwidth >200 MHz
Rail-to-Rail Operation
8-Lead SOIC Package
Fast Switching Times
tON 20 ns
ADG722
ADG721
S1
D1
S1
D1
IN1
IN1
D2
S2
D2
S2
IN2
IN2
tOFF 10 ns
Low Power Consumption (<0.1 W)
TTL/CMOS Compatible
ADG723
APPLICATIONS
Battery Powered Systems
Communication Systems
Sample Hold Systems
Audio Signal Routing
Video Switching
S1
D1
IN1
D2
S2
IN2
Mechanical Reed Relay Replacement
SWITCHES SHOWN FOR A LOGIC "0" INPUT
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. +1.8 V to +5.5 V Single Supply Operation. The ADG721,
ADG722 and ADG723 offers high performance, including
low on resistance and fast switching times and is fully speci-
fied and guaranteed with +3 V and +5 V supply rails.
The ADG721, ADG722 and ADG723 are monolithic CMOS
SPST switches. These switches are designed on an advanced
submicron process that provides low power dissipation yet gives
high switching speed, low On resistance and low leakage currents.
2. Very Low RON (4 Ω max at 5 V, 10 Ω max at 3 V). At 1.8 V
operation, RON is typically 40 Ω over the temperature range.
The ADG721, ADG722 and ADG723 are designed to operate
from a single +1.8 V to +5.5 V supply, making them ideal for
use in battery powered instruments and with the new generation
of DACs and ADCs from Analog Devices.
3. Low On-Resistance Flatness.
4. –3 dB Bandwidth >200 MHz.
The ADG721, ADG722 and ADG723 contain two independent
single-pole/single-throw (SPST) switches. The ADG721 and
ADG722 differ only in that both switches are normally open and
normally closed respectively. While in the ADG723, Switch 1 is
normally open and Switch 2 is normally closed.
5. Low Power Dissipation. CMOS construction ensures low
power dissipation.
6. Fast tON/tOFF.
7. 8-Lead µSOIC.
Each switch of the ADG721, ADG722 and ADG723 conducts
equally well in both directions when on. The ADG723 exhibits
break-before-make switching action.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
ADG721/ADG722/ADG723–SPECIFICATIONS1
(VDD = +5 V ؎ 10%, GND = 0 V. All specifications –40؇C to +85؇C, unless otherwise noted.)
B Version
–40؇C to
+85؇C
Parameter
+25؇C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
5
V
On Resistance (RON
)
4
Ω max
VS = 0 V to VDD, IS = –10 mA,
Test Circuit 1
On Resistance Match Between
Channels (∆RON
)
0.3
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IS = –10 mA
VS = 0 V to VDD, IS = –10 mA
1.0
1.5
On-Resistance Flatness (RFLAT(ON)
)
0.85
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = +5.5 V
VS = 4.5 V/1 V, VD = 1 V/4.5 V
Test Circuit 2
VS = 4.5 V/1 V, VD = 1 V/4.5 V
Test Circuit 2
VS = VD = 1 V, or VS = VD = 4.5 V
Test Circuit 3
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
nA typ
nA max
nA typ
nA max
nA typ
nA max
±0.35
±0.35
±0.35
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
µA typ
VIN = VINL or VINH
±0.1
µA max
DYNAMIC CHARACTERISTICS2
tON
14
6
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 3 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
20
10
1
tOFF
VS = 3 V, Test Circuit 4
Break-Before-Make Time Delay, tD
(ADG723 Only)
Charge Injection
7
RL = 300 Ω, CL = 35 pF,
VS1 = VS2 = 3 V, Test Circuit 5
VS = 2 V; RS = 0 Ω, CL = 1 nF,
Test Circuit 6
2
Off Isolation
–60
–80
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Test Circuit 7
Channel-to-Channel Crosstalk
–77
–97
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Test Circuit 8
Bandwidth –3 dB
CS (OFF)
CD (OFF)
200
7
7
MHz typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF, Test Circuit 9
CD, CS (ON)
18
POWER REQUIREMENTS
IDD
VDD = +5.5 V
Digital Inputs = 0 V or 5 V
0.001
µA typ
µA max
1.0
NOTES
1Temperature ranges are as follows: B Version, –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG721/ADG722/ADG723
SPECIFICATIONS1(VDD = +3 V ؎ 10%, GND = 0 V. All specifications –40؇C to +85؇C, unless otherwise noted.)
B Version
–40؇C to
Parameter
+25؇C
+85؇C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
10
V
On Resistance (RON
)
6.5
0.3
Ω typ
Ω max
VS = 0 V to VDD, IS = –10 mA
Test Circuit 1
On Resistance Match Between
Channels (∆RON
)
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = –10 mA
1.0
3.5
On-Resistance Flatness (RFLAT(ON)
)
VS = 0 V to VDD, IS = –10 mA
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = +3.3 V
VS = 3 V/1 V, VD = 1 V/3 V
Test Circuit 2
VS = 3 V/1 V, VD = 1 V/3 V
Test Circuit 2
VS = VD = 1 V, or 3 V
Test Circuit 3
±0.01
±0.25
±0.01
±0.25
±0.01
±0.25
nA typ
nA max
nA typ
nA max
nA typ
nA max
±0.35
±0.35
±0.35
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.4
V min
V max
IINL or IINH
0.005
µA typ
VIN = VINL or VINH
±0.1
µA max
DYNAMIC CHARACTERISTICS2
tON
16
7
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 2 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 2 V, Test Circuit 4
RL = 300 Ω, CL = 35 pF,
VS1 = VS2 = 2 V, Test Circuit 5
VS = 1.5 V; RS = 0 Ω, CL = 1 nF,
Test Circuit 6
24
11
1
tOFF
Break-Before-Make Time Delay, tD
(ADG723 Only)
Charge Injection
7
2
Off Isolation
–60
–80
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Test Circuit 7
Channel-to-Channel Crosstalk
Bandwidth –3 dB
–77
–97
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
Test Circuit 8
RL = 50 Ω, CL = 5 pF,
Test Circuit 9
200
MHz typ
CS (OFF)
CD (OFF)
CD, CS (ON)
7
7
18
pF typ
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = +3.3 V
Digital Inputs = 0 V or 3 V
0.001
µA typ
µA max
1.0
NOTES
1Temperature ranges are as follows: B Version, –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
ADG721/ADG722/ADG723
ABSOLUTE MAXIMUM RATINGS1
TERMINOLOGY
(TA = +25°C unless otherwise noted)
VDD
GND
S
D
IN
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input.
Ohmic resistance between D and S.
On resistance match between any two channels
i.e., RON max – RON min.
Flatness is defined as the difference between the
maximum and minimum value of on resistance as
measured over the specified analog signal range.
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog, Digital Inputs2 . . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
µSOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
RON
∆RON
RFLAT(ON)
IS (OFF)
I
D (OFF)
ID, IS (ON) Channel leakage current with the switch “ON.”
VD (VS)
CS (OFF)
CD (OFF)
Analog voltage on terminals D, S.
“OFF” Switch Source Capacitance.
“OFF” Switch Drain Capacitance.
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one absolute maxi-
mum rating may be applied at any one time.
CD, CS (ON) “ON” Switch Capacitance.
tON
tOFF
tD
Delay between applying the digital control input
and the output switching on.
Delay between applying the digital control input
and the output switching off.
“OFF” time or “ON” time measured between the
90% points of both switches, When switching
from one address state to another. (ADG723 Only)
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Table I. Truth Table (ADG721/ADG722)
Crosstalk
ADG721 In
ADG722 In
Switch Condition
0
1
1
0
OFF
ON
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
Charge
Injection
A measure of the glitch impulse transferred
during switching.
Table II. Truth Table (ADG723)
Switch 1
Logic
Switch 2
PIN CONFIGURATION
0
1
OFF
ON
ON
OFF
8-Lead SOIC (RM-8)
1
2
3
4
8
7
6
5
V
DD
S1
D1
ADG721/
722/723
IN1
D2
S2
IN2
TOP VIEW
(Not to Scale)
GND
ORDERING GUIDE
Model
Temperature Range
Brand*
Package Description
Package Option
ADG721BRM
ADG722BRM
ADG723BRM
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
S6B
S7B
S8B
µSOIC
µSOIC
µSOIC
RM-8
RM-8
RM-8
*Brand = Due to package size limitations, these three characters represent the part number.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG721/ADG722/ADG723 features proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high energy electrostatic discharges. There-
fore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
ADG721/ADG722/ADG723
Typical Performance Characteristics–
1m
6.0
5.5
5.0
T
= +25؇C
A
V
= +5V
DD
V
= +2.7V
DD
100
10
1
4.5
4.0
V
= +4.5V
DD
V
= +3.0V
DD
3.5
3.0
2.5
2.0
V
= +5.0V
DD
100n
10n
1n
1.5
1.0
0.5
0
10
100
1k
10k
100k
1M
10M
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY – Hz
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
Figure 4. Supply Current vs. Input Switching Frequency
Figure 1. On Resistance as a Function of VD (VS) Single
Supplies
6.0
–30
+85؇C
V
= +3V
V
= +3V, +5V
DD
DD
–40
–50
–60
–70
5.0
4.0
3.0
2.0
+25؇C
–40؇C
–80
–90
1.0
0
–100
10k
100k
1M
10M
100M
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY – Hz
V
OR V – DRAIN OR SOURCE VOLTAGE – V
D
S
Figure 2. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = +3 V
Figure 5. Off Isolation vs. Frequency
6.0
–30
–40
V
= +3V, +5V
V
= +5V
DD
DD
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
–50
+25؇C
+85؇C
–40؇C
–60
–70
–80
1.5
1.0
0.5
0
–90
–100
–110
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
10k
100k
1M
10M
100M
FREQUENCY – Hz
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
Figure 3. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = +5 V
Figure 6. Crosstalk vs. Frequency
REV. 0
–5–
ADG721/ADG722/ADG723
–6
V
= +5V
DD
–7
–8
–9
–10
–11
–12
100
1k
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 7. On Response vs. Frequency
Test Circuits
I
DS
V1
I
(OFF)
A
I
(OFF)
A
I
D
(ON)
A
S
D
S
D
S
D
S
D
V
R
= V1/I
V
V
V
V
D
S
ON
DS
S
D
S
Test Circuit 1. On Resistance
Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage
V
DD
0.1F
ADG721
V
V
50%
50%
50%
IN
IN
V
DD
V
L
OUT
S
D
50%
90%
ADG722
R
C
L
V
S
35pF
300⍀
IN
90%
V
OUT
GND
tOFF
tON
Test Circuit 4. Switching Times
V
V
DD
0.1F
V
IN
50%
50%
90%
DD
0V
0V
S1
D1
V
V
S1
OUT1
90%
V
V
OUT1
R
C
L1
35pF
L1
V
OUT2
S2
D2
R
300⍀
V
S2
C
IN1, IN2
L2
300⍀
L2
35pF
V
IN
90%
90%
GND
OUT2
0V
tD
tD
Test Circuit 5. Break-Before-Make Time Delay, tD (ADG723 Only)
–6–
REV. 0
ADG721/ADG722/ADG723
V
DD
SW ON
SW OFF
V
DD
V
R
IN
S
S
D
V
OUT
C
1nF
L
V
S
IN
V
OUT
⌬V
OUT
GND
Q
= C
؋
⌬V INJ
L
OUT
Test Circuit 6. Charge Injection
V
V
DD
DD
V
V
DD
DD
0.1F
0.1F
S
D
S
D
V
OUT
V
OUT
R
50⍀
L
R
50⍀
L
IN
IN
V
V
S
V
IN
V
S
IN
GND
GND
Test Circuit 7. Off Isolation
Test Circuit 9. Bandwidth
V
V
DD
DD
0.1F
50⍀
S
D
D
V
IN1
V
S
V
IN2
S
NC
V
OUT
GND
R
L
50⍀
CHANNEL-TO-CHANNEL
CROSSTALK
= 20
؋
LOG V /V S
OUT
Test Circuit 8. Channel-to-Channel Crosstalk
REV. 0
–7–
ADG721/ADG722/ADG723
APPLICATIONS INFORMATION
Off Isolation
The ADG721/ADG722/ADG723 belongs to Analog Devices’
new family of CMOS switches. This series of general purpose
switches have improved switching times, lower on resistance,
higher bandwidths, low power consumption and low leakage
currents.
Off isolation is a measure of the input signal coupled through an
off switch to the switch output. The capacitance, CDS, couples
the input signal to the output load, when the switch is off as
shown in Figure 9.
C
DS
ADG721/ADG722/ADG723 Supply Voltages
Functionality of the ADG721/ADG722/ADG723 extends from
+1.8 V to +5.5 V single supply, which makes it ideal for battery
powered instruments, where important design parameters are
power efficiency and performance.
S
D
V
OUT
V
IN
R
LOAD
C
C
D
LOAD
It is important to note that the supply voltage effects the input
signal range, the on resistance and the switching times of the
part. By taking a look at the typical performance characteristics
and the specifications, the effects of the power supplies can be
clearly seen.
Figure 9. Off Isolation Is Affected by External Load Resis-
tance and Capacitance
The larger the value of CDS, larger values of feedthrough will be
produced. The typical performance characteristic graph of Fig-
ure 5 illustrates the drop in off isolation as a function of fre-
quency. From dc to roughly 1 MHz, the switch shows better
than –80 dB isolation. Up to frequencies of 10 MHz, the off
isolation remains better than –60 dB. As the frequency increases,
more and more of the input signal is coupled through to the
output. Off isolation can be maximized by choosing a switch
with the smallest CDS as possible. The values of load resistance
and capacitance also affect off isolation, as they contribute to
the coefficients of the poles and zeros in the transfer function of
the switch when open.
For VDD = +1.8 V, on resistance is typically 40 Ω over the tem-
perature range.
On Response vs. Frequency
Figure 8 illustrates the parasitic components that affect the ac
performance of CMOS switches (the switch is shown surrounded
by a box). Additional external capacitances will further degrade
some performance. These capacitances affect feedthrough,
crosstalk and system bandwidth.
C
DS
s(RLOAD CDS
)
S
D
A(s) =
V
OUT
R
s(RLOAD )(CLOAD + CD + CDS ) +1
ON
V
IN
R
LOAD
C
C
D
LOAD
Figure 8. Switch Represented by Equivalent Parasitic
Components
The transfer function that describes the equivalent diagram of
the switch (Figure 8) is of the form (A)s shown below.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
s(RON
CDS ) +1
A(s) = RT
(RM-8)
s(RON CT RT ) +1
0.122 (3.10)
0.114 (2.90)
where:
CT = CLOAD + CD + CDS
RT = RLOAD/(RLOAD + RON
5
4
8
1
)
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
The signal transfer characteristic is dependent on the switch
channel capacitance, CDS. This capacitance creates a frequency
zero in the numerator of the transfer function A(s). Because the
switch on resistance is small, this zero usually occurs at high
frequencies. The bandwidth is a function of the switch output
capacitance combined with CDS and the load capacitance. The
frequency pole corresponding to these capacitances appears in
the denominator of A(s).
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.120 (3.05)
0.112 (2.84)
0.112 (2.84)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33°
27°
0.018 (0.46)
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
0.008 (0.20)
The dominant effect of the output capacitance, CD, causes the
pole breakpoint frequency to occur first. Therefore, in order to
maximize bandwidth a switch must have a low input and
output capacitance and low on resistance. The On Response
vs. Frequency plot for the ADG721/ADG722/ADG723 can
be seen in Figure 7.
–8–
REV. 0
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