ADG738BRUZ [ADI]
CMOS, Low Voltage, 3-Wire Serially-Controlled, Matrix Switches; CMOS ，低压， 3线串行控制，矩阵开关
| 型号： | ADG738BRUZ |
| 厂家： | 
ADI |
| 描述： | CMOS, Low Voltage, 3-Wire Serially-Controlled, Matrix Switches |
| 文件： | 总20页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, Low Voltage, 3-Wire
Serially-Controlled, Matrix Switches
Data Sheet
ADG738/ADG739
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
3-wire serial interface
2.7 V to 5.5 V single supply
2.5 Ω on resistance
ADG738
S1
0.75 Ω on-resistance flatness
100 pA leakage currents
Single 8-to-1 multiplexer ADG738
Dual 4-to-1 multiplexer ADG739
Power-on reset
D
S8
TTL/CMOS-compatible
Qualified for automotive applications
INPUT SHIFT
DOUT
REGISTER
APPLICATIONS
Data acquisition systems
Communication systems
Relay replacement
SCLK DIN SYNC RESET
Figure 1.
Audio and video switching
ADG739
S1A
DA
S4A
S1B
DB
S4B
INPUT SHIFT
DOUT
REGISTER
GENERAL DESCRIPTION
The ADG738 and ADG739 are CMOS analog matrix switches
with a serially-controlled 3-wire interface. The ADG738 is an
8-channel matrix switch, while the ADG739 is a dual 4-channel
matrix switch. On resistance is closely matched between switches
and very flat over the full signal range.
SCLK DIN SYNC
Figure 2.
The ADG738 and ADG739 utilize a 3-wire serial interface
that is compatible with SPI™, QSPI™, MICROWIRE®, and some
DSP interface standards. The output of the input shift register,
DOUT, enables a number of these parts to be daisy-chained.
On power-up, the internal input shift register contains all zeros
and all switches are in the off state.
All channels exhibit break-before-make switching action,
preventing momentary shorting when switching channels.
The ADG738 and ADG739 are available in 16-lead TSSOP
packages.
PRODUCT HIGHLIGHTS
1. 3-Wire Serial Interface.
Each switch conducts equally well in both directions when on,
making these parts suitable for both multiplexing and demulti-
plexing applications. As each switch is turned on or off by a
separate bit, these parts can also be configured as a type of
switch array, where any, all, or none of the eight switches may
be closed at any time. The input signal range extends to the
supply rails.
2. Single Supply Operation. The ADG738/ADG739 are fully
specified and guaranteed with 3 V and 5 V supply rails.
3. Low On Resistance, 2.5 Ω typical.
4. Any configuration of switches may be on or off at any
one time.
5. Guaranteed Break-Before-Make Switching Action.
6. Small 16-lead TSSOP Package.
Rev. A
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Tel: 781.329.4700 ©2000–2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADG738/ADG739
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 15
Power-On Reset.......................................................................... 15
Serial Interface ............................................................................ 15
Microprocessor Interfacing....................................................... 15
ADSP-21xx to ADG738/ADG739 ........................................... 15
8051 Interface to ADG738/ADG739....................................... 16
MC68HC11 Interface to ADG738/ADG739.......................... 16
Applications Information .............................................................. 17
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 12
Terminology .................................................................................... 14
Expand the Number of Selectable Serial Devices Using an
ADG739....................................................................................... 17
Daisy-Chaining Multiple ADG738s ........................................ 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Automotive Products................................................................. 18
REVISION HISTORY
11/12—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features Section............................................................ 1
Added W Version Specifications to Table 1 .................................. 3
Added W Version Specifications to Table 2.................................. 4
Changes to Table 4............................................................................ 6
Changes to Figure 7, Figure 8, and Figure 11 ............................... 9
Changes to Figure 12...................................................................... 10
Deleted Figure 22............................................................................ 12
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 19
4/00—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
ADG738/ADG739
SPECIFICATIONS
VDD = 5 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
B Version
W Version
Parameter
25°C
−40°C to +85°C
−40°C to +105°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
6
V
On Resistance (RON
)
2.5
4.5
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = 10 mA; see Figure 19
VS = 0 V to VDD, IS = 10 mA
5
0.4
On-Resistance Match Between
Channels (∆RON
)
0.8
1.2
1
Ω max
Ω typ
On-Resistance Flatness (RFLAT(ON)
)
0.75
VS = 0 V to VDD, IS = 10 mA
1.5
Ω max
LEAKAGE CURRENTS
VDD = 5.5 V
Source Off Leakage IS (Off)
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V; see Figure 20
0.3
1
0.6
1.3
1.3
Drain Off Leakage ID (Off)
VD = 4.5 V/1 V, VS = 1 V/4.5 V
Channel On Leakage ID, IS (On)
VD = VS = 1 V/4.5 V, see Figure 21
1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.4
0.8
V min
V max
µA typ
µA max
pF typ
0.005
3
VIN = VINL or VINH
0.1
0.4
0.1
CIN, Digital Input Capacitance
DIGITAL OUTPUT
Output Low Voltage
max
ISINK = 6 mA
COUT, Digital Output Capacitance
DYNAMIC CHARACTERISTICS1
tON
4
pF typ
20
10
9
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
RL = 300 Ω, CL = 35 pF, see Figure 22; VS1 = 3 V
RL = 300 Ω, CL = 35 pF, see Figure 22; VS1 = 3 V
32
17
1
35
20
1
tOFF
Break-Before-Make Time Delay, tD
RL = 300 Ω, CL = 35 pF;
VS1 = VS8 = 3 V, see Figure 22
VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 10 MHz
Charge Injection
Off Isolation
3
−55
−75
−55
−75
Channel-to-Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 24
−3 dB Bandwidth
ADG738
ADG739
65
100
13
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, see Figure 25
CS (Off)
CD (Off)
ADG738
ADG739
85
42
pF typ
pF typ
CD, CS (On)
ADG738
ADG739
96
48
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
10
µA typ
20
20
µA max
1 Guaranteed by design, not subject to production test.
Rev. A | Page 3 of 20
ADG738/ADG739
Data Sheet
VDD = 3 V 10%, GND = 0 V, unless otherwise noted.
Table 2.
B Version
W Version
Parameter
25°C
−40°C to +85°C
−40°C to +105°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
16
V
On Resistance (RON
)
6
11
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = 10 mA; see Figure 19
VS = 0 V to VDD, IS = 10 mA
12
0.4
On-Resistance Match Between
Channels (∆RON
)
1.2
1.4
Ω max
Ω typ
On-Resistance Flatness (RFLAT(ON)
LEAKAGE CURRENTS
)
3.5
VS = 0 V to VDD, IS = 10 mA
VDD = 3.3 V
Source Off Leakage IS (Off)
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V; see Figure 20
0.3
1
0.6
1.3
1.3
Drain Off Leakage ID (Off)
VD = 3 V/1 V, VD = 1 V/3 V
Channel On Leakage ID, IS (On)
VD = VS = 3 V/1 V, see Figure 21
1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.4
V min
V max
µA typ
µA max
pF typ
0.005
3
VIN = VINL or VINH
0.1
0.4
0.1
CIN, Digital Input Capacitance
DIGITAL OUTPUT
Output Low Voltage
max
ISINK = 6 mA
COUT, Digital Output Capacitance
DYNAMIC CHARACTERISTICS1
tON
4
pF typ
40
14
12
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
dB typ
dB typ
RL = 300 Ω, CL = 35 pF, see Figure 22; VS1 = 2 V
RL = 300 Ω, CL = 35 pF, see Figure 22; VS1 = 2 V
70
25
1
75
40
1
tOFF
Break-Before-Make Time Delay, tD
RL = 300 Ω, CL = 35 pF;
VS = 2 V, see Figure 22
Charge Injection
Off Isolation
3
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 24
−55
−75
−55
−75
Channel-to-Channel Crosstalk
−3 dB Bandwidth
ADG738
65
MHz typ RL = 50 Ω, CL = 5 pF, see Figure 25
ADG739
CS (Off)
100
13
MHz typ
pF typ
CD (Off)
ADG738
ADG739
85
42
pF typ
pF typ
CD, CS (On)
ADG738
ADG739
96
48
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
10
µA typ
20
20
µA max
1 Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 20
Data Sheet
ADG738/ADG739
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications −40°C to +105°C, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Parameter1, 2
Min
Max
Unit
MHz
ns
ns
ns
Test Conditions/Comments
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
fSCLK
t1
t2
t3
t4
30
33
13
13
0
ns
SYNC to SCLK active edge setup time
Data setup time
t5
5
ns
t6
t7
4.5
0
ns
ns
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SCLK rising edge to DOUT valid
t8
33
20
ns
3
t9
ns min
1 See Figure 3.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 CL = 20 pF, RL = 1 kΩ.
t1
SCLK
t2
t3
t8
t7
t4
SYNC
DIN
t6
t5
DB7
t9
DB0
1
1
DOUT
1
DB7
DB0
DATA FROM LAST WRITE CYCLE.
Figure 3. 3-Wire Serial Interface Timing Diagram
Rev. A | Page 5 of 20
ADG738/ADG739
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD to GND
Analog, Digital Inputs1
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or
30 mA, Whichever
Occurs First
Peak Current, S or D
100 mA
(Pulsed at 1 ms, 10%
Duty Cycle Max)
ESD CAUTION
Continuous Current, Each S
Continuous Current D
ADG739
30 mA
80 mA
ADG738
120 mA
Operating Temperature Range
Industrial (B Version)
Industrial (W Version)
Storage Temperature Range
Junction Temperature
TSSOP Package
−40°C to +85°C
−40°C to +105°C
−65°C to +150°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
150.4°C/W
27.6°C/W
As per JEDEC J-STD-020
1 Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to
the maximum ratings given.
Rev. A | Page 6 of 20
Data Sheet
ADG738/ADG739
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
DOUT
GND
SCLK
RESET
DIN
S1
ADG738
V
DD
TOP VIEW
S2
S5
S6
S7
S8
(Not to Scale)
S3
S4
D
Figure 4. ADG738 Pin Configuration
Table 5. ADG738 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
These devices can accommodate serial input rates of up to 30 MHz.
2
RESET
DIN
S1, S2, S3, S4
D
Active Low Control Input. This pin clears the input register and turns all switches to the off condition.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input.
Source. May be an input or output.
3
4, 5, 6, 7
8
Drain. May be an input or output.
9, 10, 11, 12
S8, S7, S6, S5
VDD
GND
Source. May be an input or output.
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
Ground Reference.
Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of the input shift
register on the rising edge of SCLK. This is an open drain output, which should be pulled to the supply
with an external resistor.
13
14
15
DOUT
16
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low,
it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on the
falling edges of the following clocks. Taking SYNC high updates the switch conditions.
Rev. A | Page 7 of 20
ADG738/ADG739
Data Sheet
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DOUT
GND
SCLK
SYNC
DIN
V
DD
ADG739
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
TOP VIEW
(Not to Scale)
Figure 5. ADG739 Pin Configuration
Table 6. ADG739 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. These devices can accommodate serial input rates of up to 30 MHz.
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is
transferred on the falling edges of the following clocks. Taking SYNC high updates the switch
conditions.
3
DIN
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial
clock input.
4, 5, 6, 7
8, 9
S1A, S2A, S3A, S4A
DA, DB
Source. May be an input or output.
Drain. May be an input or output.
10, 11, 12, 13 S4B, S3B, S2B, S1B
Source. May be an input or output.
14
15
16
VDD
GND
DOUT
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
Ground Reference.
Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of the input
shift register on the rising edge of SCLK. This is an open drain output, which should be pulled to
the supply with an external resistor.
Rev. A | Page 8 of 20
Data Sheet
ADG738/ADG739
TYPICAL PERFORMANCE CHARACTERISTICS
0.12
0.08
0.04
0
8
V
V
A
= 5V
= 0V
DD
SS
T
= 25°C
A
V
= 0V
SS
7
6
5
4
3
2
1
0
T
= 25°C
V
= 2.7V
DD
I
(ON)
D
V
= 3.3V
DD
V
= 4.5V
DD
I
(OFF)
S
V
= 5.5V
DD
–0.04
–0.08
–0.12
I
(OFF)
D
0
1
2
3
4
5
0
1
2
3
4
5
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
V [V ] (V)
D S
D
S
Figure 6. On Resistance as a Function of VD (VS)
Figure 9. Leakage Currents as a Function of VD (VS), VDD = 5 V
8
0.12
0.08
0.04
0
V
V
= 5V
= 0V
DD
SS
V
V
A
= 3V
= 0V
DD
SS
7
6
T
= 25°C
I
(ON)
D
5
4
3
2
1
0
+125°C
+85°C
+25°C
I
(OFF)
S
0.04
0.08
0.12
I (OFF)
D
–40°C
0
1
2
3
4
5
0
0.5
1.0
1.5
[V ] (V)
2.0
2.5
3.0
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
D
S
V
D
S
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
DD = 5 V
Figure 10. Leakage Currents as a Function of VD (VS), VDD = 3 V
V
8
7
0.35
V
V
= 3V
= 0V
V
V
= 5V
= 0V
DD
SS
DD
SS
0.30
0.25
0.20
0.15
0.10
0.05
0
+125°C
6
5
4
3
2
+85°C
–40°C
I
(OFF)
I
(OFF)
D
S
+25°C
I
(ON)
D
1
0
0
20
40
60
80
100
120
0
0.5
1.0
1.5
2.0
2.5
3.0
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
TEMPERATURE (°C)
D
S
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
DD = 3 V
Figure 11. Leakage Currents as a Function of Temperature, VDD = 5 V
V
Rev. A | Page 9 of 20
ADG738/ADG739
Data Sheet
0.35
20
10
T
= 25°C
V
= 3V
A
DD
0.30
0.25
0.20
0.15
0.10
0.05
0
V
V
= 5V
= 0V
DD
SS
0
V
V
= 3V
= 0V
DD
SS
–10
–20
–30
–40
I
(ON)
I
D
(OFF)
D
I
(OFF)
S
0
20
40
60
80
100
120
0
1
2
3
4
5
TEMPERATURE (°C)
VOLTAGE (V)
Figure 12. Leakage Currents as a Function of Temperature, VDD = 3 V
Figure 14. Charge Injection vs. Source Voltage
10m
50
45
40
35
30
25
20
15
10
5
T
= 25°C
A
T
, V = 3V
ON DD
1m
100µ
10µ
1µ
T
, V = 5V
V
= 5V
ON DD
DD
T
, V = 3V
OFF DD
V
= 3V
DD
T
, V = 5V
OFF DD
0
–40
–20
0
20
40
60
80
10k
100k
1M
FREQUENCY (Hz)
10M
100M
TEMPERATURE (°C)
Figure 13. Input Currents vs. Switching Frequency
Figure 15. TON/TOFF Times vs. Temperature
Rev. A | Page 10 of 20
Data Sheet
ADG738/ADG739
0
0
–5
V
A
= 5V
DD
T
= 25°C
ADG738
ADG739
–20
–40
–60
–10
–15
–20
–80
–100
–120
V
A
= 5V
DD
T
= 25°C
30k
100k
1M
10M
100M
30k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 16. Off Isolation vs. Frequency
Figure 18. On Response vs. Frequency
0
V
A
= 5V
DD
T
= 25°C
–20
–40
–60
–80
–100
–120
30k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 17. Crosstalk vs. Frequency
Rev. A | Page 11 of 20
ADG738/ADG739
TEST CIRCUITS
Data Sheet
I
(ON)
A
D
S1
S2
D
NC
V
Sn
S
D
I
DS
V
V
D
D
V
R
= V/I
DS
S
ON
NC = NO CONNECT
Figure 19. On Resistance
Figure 21. IS, ID (On)
I
(OFF)
A
I
(OFF)
A
S
D
S1
Sn
D
A
V
V
D
S
Figure 20. ID (Off), IS (Off)
V
DD
V
DD
SYNC
SYNC
50%
50%
ADG738*
V
S1
S1
S8
S2 THRU S7
S8
V
S1
V
R
V
= V
S8
S1
90%
V
D
80%
OUT
V
80%
V
OUT
OUT
C
GND
L
L
35pF
300Ω
90%
tOPEN
tOFF
tON
*SIMILAR CONNECTION FOR ADG739.
Figure 22. Switching Times and Break-Before-Make Times
SYNC
V
DD
ADG738*
SWITCH ON
R
S
D
SWITCH OFF
∆V
S
OUT
V
OUT
Q
= C × V
L OUT
INJ
C
1nF
L
V
S
INPUT LOGIC
GND
*SIMILAR CONNECTION FOR ADG739.
Figure 23. Charge Injection
Rev. A | Page 12 of 20
Data Sheet
ADG738/ADG739
V
V
DD
DD
S1
S8
VDD
V
S
V
ADG738*
DD
ADG738*
D
V
OUT
50Ω
S1
R
50Ω
D
L
V
OUT
GND
R
50Ω
L
S2
S8
V
S
GND
*SIMILAR CONNECTION FOR ADG739.
S1 IS SWITCHED OFF FOR OFF ISOLATION MEASUREMENTS
AND ON FOR BANDWIDTH MEASUREMENTS
OFF ISOLATION = 20LOG (V
/V )
S
10 OUT
*SIMILAR CONNECTION FOR ADG739.
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG (V
V
WITH SWITCH
OUT
INSERTION LOSS = 20LOG
10
V
WITHOUT SWITCH
/V )
OUT
10
OUT
S
Figure 24. Channel-to-Channel Crosstalk
Figure 25. Off Isolation and Bandwidth
Rev. A | Page 13 of 20
ADG738/ADG739
TERMINOLOGY
Data Sheet
CS (Off)
VDD
Off switch source capacitance. Measured with reference to
ground.
Most positive power supply potential.
IDD
CD (Off)
Positive supply current.
Off switch drain capacitance. Measured with reference to
ground.
GND
Ground (0 V) reference.
CD, CS (On)
S
On switch capacitance. Measured with reference to ground.
Source terminal. May be an input or output.
CIN
D
Digital input capacitance.
Drain terminal. May be an input or output.
tON
VD (VS)
SYNC
SYNC
Delay time between the 50% and 90% points of the
edge and the switch on condition.
rising
rising
Analog voltage on Terminal D, Terminal S.
RON
tOFF
Ohmic resistance between D and S.
Delay time between the 50% and 90% points of the
edge and the switch off condition.
∆RON
On resistance match between any two channels, that is, RONmax
− RONmin.
tD
Off time measured between the 80% points of both switches
when switching from one switch to another.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IS (Off)
Off Isolation
Source leakage current with the switch off.
A measure of unwanted signal coupling through an off switch.
ID (Off)
Crosstalk
Drain leakage current with the switch off.
A measure of unwanted signal which is coupled through from
one channel to another as a result of parasitic capacitance.
ID, IS (On)
Channel leakage current with the switch on.
Bandwidth
VINL
The frequency at which the output is attenuated by 3 dB.
Maximum input voltage for Logic 0.
On Response
The frequency response of the on switch.
VINH
Minimum input voltage for Logic 1.
Insertion Loss
The loss due to the on resistance of the switch.
I
INL (IINH
)
Input current of the digital input.
Rev. A | Page 14 of 20
Data Sheet
ADG738/ADG739
THEORY OF OPERATION
DB0 (LSB)
DB7 (MSB)
S8 S7
The ADG738 and ADG739 are serially controlled, 8-channel
and dual 4-channel matrix switches, respectively. While provid-
ing the normal multiplexing and demultiplexing functions,
these parts also provide the user with more flexibility as to
where their signal may be routed. Each bit of the 8-bit serial
word corresponds to one switch of the part. A Logic 1 in the
particular bit position turns on the switch, while a Logic 0 turns
the switch off. Because each switch is independently controlled
by an individual bit, this provides the option of having any, all,
or none of the switches on. This feature may be particularly
useful in the demultiplexing application where the user may
wish to direct one signal from the drain to a number of outputs
(sources). Take care, however, in the multiplexing situation
where a number of inputs may be shorted together (separated
only by the small on resistance of the switch).
S6
S5
S4
S3
S2
S1
DATA BITS
Figure 26. Input Shift Register Contents
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the ADG738/ADG739 is via
a serial bus that uses a standard protocol compatible with
microcontrollers and DSP processors. The communications
channel is a 3-wire (minimum) interface consisting of a
clock signal, a data signal, and a synchronization signal.
The ADG738/ADG739 requires an 8-bit data word with
data valid on the falling edge of SCLK.
Data from the previous write cycle is available on the DOUT
pin. The following sections illustrate simple 3-wire interfaces
with popular microcontrollers and DSPs.
When changing the switch conditions, a new 8-bit word is
written to the input shift register. Some of the bits may be the
same as the previous write cycle, as the user may not wish to
change the state of some switches. To minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the on condition, and is required to stay on, there will be
minimal glitches on the output of the switch.
ADSP-21xx TO ADG738/ADG739
An interface between the ADG738/ADG739 and the ADSP-
21xx is shown in Figure 27. In the interface example shown,
SPORT0 is used to transfer data to the matrix switch. The
SPORT control register should be configured as follows:
internal clock operation, alternate framing mode; active low
framing signal.
POWER-ON RESET
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the matrix switch. The update of each switch
condition takes place automatically when TFS is taken high.
During device power-up, all switches will be in the off condi-
tion and the internal input shift register is filled with zeros and
remains so until a valid write takes place.
SERIAL INTERFACE
The ADG738 and ADG739 have a 3-wire serial interface
TFS
SYNC
DIN
SYNC
(
, SCLK, and DIN), which is compatible with SPI, QSPI,
ADG738/
ADG739
DT
ADSP-21xx*
MICROWIRE interface standards and most DSPs. Figure 3
shows the timing diagram of a typical write sequence.
SCLK
SCLK
Data is written to the 8-bit input shift register via DIN under
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
the control of the
and SCLK signals. Data may be written
Figure 27. ADSP-21xx to ADG738/ADG739 Interface
to the input shift register in more or less than eight bits. In each
case, the input shift register retains the last eight bits that were
written.
SYNC
When
goes low, the input shift register is enabled. Data
from DIN is clocked into the input shift register on each falling
edge of SCLK. Each bit of the 8-bit word corresponds to one of
the eight switches. Figure 26 shows the contents of the input
shift register. Data appears on the DOUT pin on the rising edge
of SCLK suitable for daisy-chaining, delayed, of course, by eight
bits. When all eight bits have been written into the shift register,
SYNC
the
with the new configuration and the input shift register is
SYNC
line is brought high again. The switches are updated
disabled. With
held high, any further data or noise
on the DIN line has no effect on the shift register.
Rev. A | Page 15 of 20
ADG738/ADG739
Data Sheet
8051 INTERFACE TO ADG738/ADG739
MC68HC11 INTERFACE TO ADG738/ADG739
A serial interface between the ADG738/ADG739 and the 8051
is shown in Figure 28. TXD of the 8051 drives SCLK of the
ADG738/ADG739, while RXD drives the serial data line, DIN.
P3.3 is a bit-programmable pin on the serial port and is used to
Figure 29 shows an example of a serial interface between the
ADG738/ADG739 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the matrix switch, while the
SYNC
MOSI output drives the serial data line, DIN.
from one of the port lines, in this case PC7.
is driven
SYNC
drive
.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user has to ensure that the data in the SBUF
register is arranged correctly as the switch expects MSB first.
PC7
SYNC
ADG738/
ADG739
MC68HC11*
MOSI
SCK
DIN
When data is to be transmitted to the matrix switch, P3.3 is
taken low. Data on RXD is clocked out of the microcontroller
on the rising edge of TXD and is valid on the falling edge. As a
result no glue logic is required between the ADG738/ADG739
and microcontroller interface.
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. MC68HC11 Interface to ADG738/ADG739
The 68HC11 is configured for master mode; MSTR = 1, CPOL
= 0, and CPHA = 1. When data is transferred to the part, PC7 is
taken low, data is transmitted MSB first. Data appearing on the
MOSI output is valid on the falling edge of SCK.
P3.3
SYNC
DIN
ADG738/
ADG739
RXD
80C51/80L51*
If the user wishes to verify the data previously written to the
input shift register, the DOUT line could be connected to MISO
SCLK
TXD
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
of the MC68HC11, and with
low, the input shift register
Figure 28. 8051 Interface to ADG738/ADG739
would clock data out on the rising edges of SCLK.
Rev. A | Page 16 of 20
Data Sheet
ADG738/ADG739
APPLICATIONS INFORMATION
EXPAND THE NUMBER OF SELECTABLE SERIAL
DEVICES USING AN ADG739
ADG739
SYNC
DIN
The dual 4-channel ADG739 multiplexer can be used to
multiplex a single chip select line to provide chip selects for
up to four devices on the SPI bus. Figure 30 illustrates the
ADG739 in such a typical configuration. All devices receive
the same serial clock and serial data, but only one device
SCLK
ADG738
V
DD
SYNC
DIN
1/2 OF
ADG739
SCLK
SYNC
S1A
receives the
serially controlled device also. One bit programmable pin of
SYNC2
signal at any one time. The ADG739 is a
S2A
S3A
S4A
OTHER SPI
DEVICE
DA
the microcontroller is used to enable the ADG739 via
while another bit programmable pin is used as the chip select
,
SYNC1
SYNC
DIN
SYNC1
SYNC2
for the other serial devices,
. Driving
low enables
SCLK
FROM
MICRO-
CONTROLLER
OR DSP
SCLK DIN SYNC
changes to be made to the addressed serial devices. By
SYNC1
OTHER SPI
DEVICE
bringing
low, the selected serial device hanging from
SYNC2
the SPI bus is enabled and data will be clocked into its input
shift register on the falling edges of SCLK. The convenient
design of the matrix switch allows for different combinations of
the four serial devices to be addressed at any one time. If more
devices need to be addressed via one chip select line, the
ADG738 is an 8-channel device and would allow further
expansion of the chip select scheme. There may be some digital
feedthrough from the digital input lines because SCLK and DIN
are permanently connected to each device. Using a burst clock
minimizes the effects of digital feedthrough on the analog
channels.
SYNC
SCLK
DIN
DIN
SCLK
Figure 30. Addressing Multiple Serial Devices Using an ADG739
DAISY-CHAINING MULTIPLE ADG738S
A number of ADG738 matrix switches may be daisy-chained
simply by using the DOUT pin. DOUT is an open-drain output
that should be pulled to the supply with an external resistor.
SYNC
Figure 31 shows a typical implementation. The
pin of
SYNC
all three parts in the example are tied together. When
is brought low, the input shift registers of all parts are enabled,
data is written to the parts via DIN, and clocked through the
SYNC
shift registers. When the transfer is complete,
is brought
high and all switches are updated simultaneously. Further shift
registers may be added in series.
V
DD
R
R
R
SCLK
SCLK
SCLK
DIN
SCLK
DIN
ADG739
ADG739
ADG739
DOUT
DOUT
DOUT
DIN
DIN
TO OTHER
SERIAL DEVICES
SYNC
SYNC
SYNC
SYNC
Figure 31. Multiple ADG739 Devices in a Daisy-Chained Configuration
Rev. A | Page 17 of 20
ADG738/ADG739
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 32. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +105°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
RU-16
RU-16
RU-16
RU-16
ADG738BRU
ADG738BRUZ
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
ADG738BRUZ-REEL
ADG738BRUZ-REEL7
ADG738WBRUZ-REEL
ADG739BRU
ADG739BRU-REEL7
ADG739BRUZ
RU-16
RU-16
RU-16
RU-16
RU-16
ADG739BRUZ-REEL
ADG739BRUZ-REEL7
RU-16
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADG738W model is available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. A | Page 18 of 20
Data Sheet
NOTES
ADG738/ADG739
Rev. A | Page 19 of 20
ADG738/ADG739
NOTES
Data Sheet
©2000–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10758-0-11/12(A)
Rev. A | Page 20 of 20
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