ADG739BRUZ-REEL7 [ADI]
CMOS, Low-Voltage, 3-Wire Serially-Controlled, Matrix Switch;
| 型号： | ADG739BRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | CMOS, Low-Voltage, 3-Wire Serially-Controlled, Matrix Switch 光电二极管 |
| 文件： | 总12页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, Low-Voltage, 3-Wire
Serially-Controlled, Matrix Switches
a
ADG738/ADG739
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
3-Wire Serial Interface
2.7 V to 5.5 V Single Supply
2.5 ⍀ On Resistance
ADG738
ADG739
0.75 ⍀ On-Resistance Flatness
100 pA Leakage Currents
Single 8-to-1 Multiplexer ADG738
Dual 4-to-1 Multiplexer ADG739
Power-On Reset
S1
S1A
S4A
DA
D
TTL/CMOS-Compatible
S1B
S4B
DB
APPLICATIONS
S8
Data Acquisition Systems
Communication Systems
Relay Replacement
INPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
DOUT
DOUT
Audio and Video Switching
SCLK
SYNC
DIN
SCLK DIN SYNC RESET
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG738 and ADG739 are CMOS analog matrix switches
with a serially-controlled 3-wire interface. The ADG738 is an
8-channel matrix switch, while the ADG739 is a dual 4-channel
matrix switch. On resistance is closely matched between switches
and very flat over the full signal range.
1. 3-Wire Serial Interface.
2. Single Supply Operation. The ADG738 and ADG739 are
fully specified and guaranteed with 3 V and 5 V supply rails.
3. Low On Resistance, 2.5 Ω typical.
4. Any configuration of switches may be on or off at any one time.
5. Guaranteed Break-Before-Make Switching Action.
6. Small 16-lead TSSOP Package.
The ADG738 and ADG739 utilize a 3-wire serial interface that
is compatible with SPI™, QSPI™, MICROWIRE™, and some
DSP interface standards. The output of the shift register DOUT
enables a number of these parts to be daisy-chained. On power-up,
the internal shift register contains all zeros and all switches
are in the OFF state.
Each switch conducts equally well in both directions when on,
making these parts suitable for both multiplexing and demulti-
plexing applications. As each switch is turned on or off by a
separate bit, these parts can also be configured as a type of switch
array, where any, all, or none of the eight switches may be closed
at any time. The input signal range extends to the supply rails.
All channels exhibit break-before-make switching action,
preventing momentary shorting when switching channels.
The ADG738 and ADG739 are available in 16-lead TSSOP
packages.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADG738/ADG739–SPECIFICATIONS1
(VDD = 5 V ؎ 10%, GND = 0 V, unless otherwise noted.)
B Version
–40؇C
to +85؇C
Parameter
25؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
2.5
4.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IS = 10 mA
5
0.4
0.8
On-Resistance Match Between
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
0.75
VS = 0 V to VDD, IS = 10 mA
1.2
LEAKAGE CURRENTS
VDD = 5.5 V
Source OFF Leakage IS (OFF)
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 3
VD = VS = 1 V/4.5 V, Test Circuit 4
0.3
1
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.4
0.8
V min
V max
µA typ
µA max
pF typ
0.005
3
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance
DIGITAL OUTPUT
Output Low Voltage
COUT, Digital Output Capacitance
0.4
max
pF typ
ISINK = 6 mA
4
DYNAMIC CHARACTERISTICS2
tON
20
10
9
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5;
32
17
1
VS1 = 3 V
tOFF
RL = 300 Ω, CL = 35 pF, Test Circuit 5;
V
S1 = 3 V
Break-Before-Make Time Delay, tD
Charge Injection
RL = 300 Ω, CL = 35 pF;
VS1 = VS8 = 3 V, Test Circuit 5
VS = 2.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 6
3
Off Isolation
–55
–75
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz;
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk
–55
–75
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz;
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
–3 dB Bandwidth
ADG738
ADG739
65
100
13
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, Test Circuit 8
CS (OFF)
C
D (OFF)
ADG738
ADG739
85
42
pF typ
pF typ
CD, CS (ON)
ADG738
ADG739
96
48
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
10
µA typ
µA max
20
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG738/ADG739
SPECIFICATIONS1
(VDD = 3 V ؎ 10%, GND = 0 V, unless otherwise noted.)
B Version
–40؇C
Parameter
25؇C
to +85؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
6
11
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IS = 10 mA
12
On-Resistance Match Between
0.4
1.2
3.5
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
VS = 0 V to VDD, IS = 10 mA
LEAKAGE CURRENTS
VDD = 3.3 V
Source OFF Leakage IS (OFF)
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VD = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 3
0.3
1
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
VD = VS = 3 V/1 V, Test Circuit 4
1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.4
V min
V max
µA typ
µA max
pF typ
0.005
3
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance
DIGITAL OUTPUT
Output Low Voltage
COUT, Digital Output Capacitance
0.4
max
pF typ
ISINK = 6 mA
4
DYNAMIC CHARACTERISTICS2
tON
40
14
12
3
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5;
70
25
1
VS1 = 2 V
tOFF
RL = 300 Ω, CL = 35 pF, Test Circuit 5;
VS1 = 2 V
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 5
VS = 1.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 6
Break-Before-Make Time Delay, tD
Charge Injection
Off Isolation
–55
–75
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz;
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
Channel-to-Channel Crosstalk
–55
–75
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz;
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
–3 dB Bandwidth
ADG738
ADG739
CS (OFF)
CD (OFF)
ADG738
65
100
13
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, Test Circuit 8
85
42
pF typ
pF typ
ADG739
CD, CS (ON)
ADG738
ADG739
96
48
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
10
µA typ
µA max
20
NOTES
1Temperature ranges are as follows: B Versions: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
ADG738/ADG739
TIMING CHARACTERISTICS1, 2
(VDD = 2.7 V to 5.5 V. All specifications –40؇C to +85؇C, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
fSCLK
t1
t2
t3
t4
t5
t6
t7
30
33
13
13
0
5
4.5
0
33
20
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Frequency
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Active Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SCLK Rising Edge to DOUT Valid
t83
t9
NOTES
1See Figure 1.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3CL = 20 pF, RL = 1 kΩ.
Specifications subject to change without notice.
t1
SCLK
t2
t3
t8
t7
t4
SYNC
t6
t5
DIN
DB7
t9
DB0
1
1
DOUT
DB7
DB0
NOTE
1
DATA FROM LAST WRITE CYCLE
Figure 1. 3-Wire Serial Interface Timing Diagram
–4–
REV. 0
ADG738/ADG739
PIN FUNCTION DESCRIPTIONS
Mnemonic Function
ADG738
ADG739
1
1
SCLK
RESET
DIN
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the
serial clock input. These devices can accommodate serial input rates of up to 30 MHz.
Active low control input that clears the input register and turns all switches to the OFF
condition.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the
serial clock input.
2
3
3
4, 5, 6, 7
8
4, 5, 6, 7
8, 9
Sxx
Dx
Source. May be an input or output.
Drain. May be an input or output.
9, 10, 11, 12 10, 11, 12, 13 Sxx
Source. May be an input or output.
13
14
15
14
15
16
VDD
GND
DOUT
Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V.
Ground Reference.
Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of
the input shift register on the rising edge of SCLK. This is an open drain output which
should be pulled to the supply with an external resistor.
16
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift
register is enabled. Data is transferred on the falling edges of the following clocks.
Taking SYNC high updates the switch conditions.
PIN CONFIGURATIONS
SCLK
16
1
2
3
SYNC
SCLK
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DOUT
GND
RESET
15 DOUT
14 GND
SYNC
DIN
DIN
V
ADG738
DD
ADG739
V
13
12
11
10
9
S1
S2
S3
S4
4
5
6
7
8
S1A
S2A
S3A
S4A
DA
DD
S1B
S2B
S3B
S4B
DB
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
S5
S6
S7
S8
D
ORDERING GUIDE
Package Description
Model
Temperature Range
Package Option
ADG738BRU
ADG739BRU
–40°C to +85°C
–40°C to +85°C
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
RU-16
RU-16
REV. 0
–5–
ADG738/ADG739
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C unless otherwise noted.)
TSSOP Package
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog, Digital Inputs2 . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, Each S . . . . . . . . . . . . . . . . . . . . . 30 mA
Continuous Current D, ADG739 . . . . . . . . . . . . . . . . . 80 mA
Continuous Current D, ADG738 . . . . . . . . . . . . . . . . 120 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6°C/W
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG738/ADG739 feature proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
VDD
IDD
GND
S
Most Positive Power Supply Potential.
Positive Supply Current.
CD, CS (ON) “ON” Switch Capacitance. Measured with refer-
ence to ground.
CIN
tON
Digital Input Capacitance.
Ground (0 V) Reference.
Delay time between the 50% and 90% points
of the SYNC rising edge and the switch “ON”
condition.
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Analog Voltage on Terminals D, S.
Ohmic Resistance between D and S.
D
V
D (VS)
tOFF
Delay time between the 50% and 90% points
of the SYNC rising edge and the switch “OFF”
condition.
RON
∆RON
On Resistance Match Between any Two Chan-
nels, i.e., RONmax – RONmin.
tD
“OFF” time measured between the 80% points of
both switches when switching from one switch to
another.
RFLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on resistance
as measured over the specified analog signal range.
Charge
Injection
A measure of the glitch impulse transferred from
the digital input to the analog output during
switching.
IS (OFF)
Source Leakage Current with the Switch “OFF.”
Drain Leakage Current with the Switch “OFF.”
Channel Leakage Current with the Switch “ON.”
Maximum Input Voltage for Logic “0.”
Minimum Input Voltage for Logic “1.”
Input Current of the Digital Input.
I
D (OFF)
Off Isolation A measure of unwanted signal coupling through
an “OFF” switch.
ID, IS (ON)
VINL
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
VINH
I
INL(IINH
)
Bandwidth
The frequency at which the output is attenuated
by 3 dBs.
CS (OFF)
“OFF” Switch Source Capacitance. Measured
with reference to ground.
On Response The frequency response of the “ON” switch.
C
D (OFF)
“OFF” Switch Drain Capacitance. Measured
with reference to ground.
Insertion
Loss
The loss due to the ON resistance of the switch.
–6–
REV. 0
Typical Performance Characteristics–ADG738/ADG739
8
8
8
7
T
V
= 25؇C
V
V
= 3V
= 0V
V
V
= 5V
= 0V
A
DD
SS
DD
SS
7
7
= 0V
SS
V
= 2.7V
DD
6
5
4
3
6
5
4
6
5
4
3
+85؇C
V
= 3.3V
DD
V
= 4.5V
DD
+25؇C
–40؇C
V
= 5.5V
DD
3
2
+85؇C
2
+25؇C
2
1
–40؇C
1
1
0
0
0
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
V
OR V – DRAIN OR SOURCE VOLTAGE – V
D
S
V
, V , DRAIN OR SOURCE VOLTAGE – V
V
OR V – DRAIN OR SOURCE VOLTAGE – V
S
D
S
D
Figure 2. On Resistance as a Function
of VD (VS)
Figure 3. On Resistance as a Function
of VD (VS) for Different Temperatures
Figure 4. On Resistance as a Function
of VD (VS) for Different Temperatures
0.12
0.35
0.12
V
V
T
= 3V
= 0V
= 25؇C
V
V
= 5V
= 0V
V
V
T
= 5V
= 0V
= 25؇C
DD
DD
SS
DD
SS
SS
0.30
0.25
0.20
0.15
0.10
0.05
0.08
0.04
0.00
0.08
A
A
I
(ON)
D
I
(ON)
D
0.04
0.00
I
(OFF)
D
I
(OFF)
S
I
(OFF)
1.5
–0.04
–0.04
–0.08
–0.12
I
(OFF)
S
D
I
(ON)
D
I
(OFF)
4
D
–0.08
–0.12
0.00
I
(OFF)
65
S
–0.05
0
1
2
3
5
0
0.5
1.0
V
2.0
2.5
3.0
15
25
35
45
55
75
85
V
(V – Volts
S)
(V – Volts
TEMPERATURE – ؇C
D
D
S)
Figure 5. Leakage Currents as a Func-
tion of VD (VS)
Figure 6. Leakage Currents as a Func-
tion of VD (VS)
Figure 7. Leakage Currents as a Func-
tion of Temperature
10m
20
0.35
V
V
= 3V
= 0V
T = 25؇C
A
T
= 25؇C
DD
SS
A
0.30
0.25
0.20
0.15
0.10
0.05
10
V
V
= 5V
= 0V
DD
SS
1m
0
–10
–20
–30
–40
V
= 5V
DD
V
V
= 3V
= 0V
DD
100
SS
V
= 3V
DD
I
(OFF)
D
10
1
0.00
I
(ON)
I
(OFF)
55
D
S
–0.05
15
25
35
45
65
75
85
10k
100k
1M
10M
100M
0
1
2
3
4
5
TEMPERATURE – ؇C
FREQUENCY – Hz
VOLTAGE – Volts
Figure 8. Leakage Currents as a Func-
tion of Temperature
Figure 9. Input Currents vs. Switching
Frequency
Figure 10. Charge Injection vs. Source
Voltage
REV. 0
–7–
ADG738/ADG739
0
–20
–40
0
–20
–40
50
V
T
= 5V
= 25؇C
V
T
= 5V
DD
DD
= 25؇C
T
, V = 3V
ON DD
45
40
35
30
25
20
A
A
T
, V = 5V
ON DD
–60
–80
–60
–80
T
, V = 3V
OFF DD
15
10
5
–100
–120
–100
–120
T
, V = 5V
OFF DD
0
–40
30k 100k
1M
10M
100M
30k 100k
1M
10M
100M
–20
0
20
40
60
80
FREQUENCY – Hz
FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 11. TON /TOFF Times vs.
Temperature
Figure 12. Off Isolation vs. Frequency
Figure 13. Crosstalk vs. Frequency
0
V
= 5V
DD
= 25؇C
T
A
ADG738
ADG739
–5
–10
–15
–20
30k 100k
1M
10M
100M
FREQUENCY – Hz
Figure 14. On Response vs. Frequency
–8–
REV. 0
ADG738/ADG739
MICROPROCESSOR INTERFACING
GENERAL DESCRIPTION
The ADG738 and ADG739 are serially controlled, 8-channel
and dual 4-channel Matrix Switches respectively. While provid-
ing the normal multiplexing and demultiplexing functions, these
parts also provide the user with more flexibility as to where their
signal may be routed. Each bit of the 8-bit serial word corresponds
to one switch of the part. A Logic 1 in the particular bit position
turns on the switch, while a Logic 0 turns the switch off. Because
each switch is independently controlled by an individual bit, this
provides the option of having any, all, or none of the switches ON.
This feature may be particularly useful in the demultiplexing
application where the user may wish to direct one signal from
the drain to a number of outputs (sources). Care must be taken,
however, in the multiplexing situation where a number of inputs
may be shorted together (separated only by the small on resis-
tance of the switch).
Microprocessor interfacing to the ADG738/ADG739 is via a
serial bus that uses standard protocol compatible with micro-
controllers and DSP processors. The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a data
signal, and a synchronization signal. The ADG738/ADG739 requires
an 8-bit data word with data valid on the falling edge of SCLK.
Data from the previous write cycle is available on the DOUT
pin. The following figures illustrate simple 3-wire interfaces
with popular microcontrollers and DSPs.
ADSP-21xx to ADG738/ADG739
An interface between the ADG738/ADG739 and the ADSP-
21xx is shown in Figure 16. In the interface example shown,
SPORT0 is used to transfer data to the Matrix Switch. The
SPORT control register should be configured as follows: internal
Clock operation, alternate framing mode; active low framing signal.
When changing the switch conditions, a new 8-bit word is writ-
ten to the input shift register. Some of the bits may be the same
as the previous write cycle, as the user may not wish to change
the state of some switches. In order to minimize glitches on the
output of these switches, the part cleverly compares the state of
switches from the previous write cycle. If the switch is already
in the ON condition, and is required to stay ON, there will
be minimal glitches on the output of the switch.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required
to interface the DSP to the Matrix Switch. The update of each
switch condition takes place automatically when TFS is taken high.
TFS
DT
SYNC
DIN
ADG738/
ADG739
POWER-ON RESET
ADSP-21xx*
On power-up of the device, all switches will be in the OFF con-
dition and the internal shift register is filled with zeros and will
remain so until a valid write takes place.
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
SERIAL INTERFACE
Figure 16. ADSP-21xx to ADG738/ADG739 Interface
The ADG738 and ADG739 have a 3-wire serial interface
(SYNC, SCLK, and DIN), which is compatible with SPI,
QSPI, MICROWIRE interface standards and most DSPs. Fig-
ure 1 shows the timing diagram of a typical write sequence.
8051 Interface to ADG738/ADG739
A serial interface between the ADG738/ADG739 and the 8051
is shown in Figure 17. TXD of the 8051 drives SCLK of the
ADG738/ADG739, while RXD drives the serial data line, DIN.
P3.3 is a bit-programmable pin on the serial port and is used to
drive SYNC.
Data is written to the 8-bit shift register via DIN under the
control of the SYNC and SCLK signals. Data may be written to
the shift register in more or less than eight bits. In each case
the shift register retains the last eight bits that were written.
The 8051 provides the LSB of its SBUF register as the first bit
in the data stream. The user will have to ensure that the data in
the SBUF register is arranged correctly as the switch expects
MSB first.
When SYNC goes low, the input shift register is enabled. Data
from DIN is clocked into the shift register on each falling edge
of SCLK. Each bit of the 8-bit word corresponds to one of the
eight switches. Figure 15 shows the contents of the input shift
register. Data appears on the DOUT pin on the rising edge of
SCLK suitable for daisy-chaining, delayed, of course, by eight
bits. When all eight bits have been written into the shift register,
the SYNC line is brought high again. The switches are updated
with the new configuration and the input shift register is
disabled. With SYNC held high, any further data or noise on
the DIN line will have no effect on the shift register.
When data is to be transmitted to the Matrix Switch, P3.3 is
taken low. Data on RXD is clocked out of the microcontroller
on the rising edge of TXD and is valid on the falling edge. As a
result no glue logic is required between the ADG738/ADG739
and microcontroller interface.
P3.3
RXD
SYNC
DIN
ADG738/
ADG739
80C51/80L51*
DB0 (LSB)
S2 S1
DB7 (MSB)
S8 S7
SCLK
TXD
S6
S5
S4
S3
DATA BITS
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 15. Input Shift Register Contents
Figure 17. 8051 Interface to ADG738/ADG739
REV. 0
–9–
ADG738/ADG739
MC68HC11 Interface to ADG738/ADG739
allows for different combinations of the four serial devices to
be addressed at any one time. If more devices need to be addressed
via one chip select line, the ADG738 is an 8-channel device and
would allow further expansion of the chip select scheme. There
may be some digital feedthrough from the digital input lines
because SCLK and DIN are permanently connected to each
device. Using a burst clock will minimize the effects of digital
feedthrough on the analog channels.
Figure 18 shows an example of a serial interface between the
ADG738/ADG739 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the Matrix Switch, while the
MOSI output drives the serial data line, DIN. SYNC is driven
from one of the port lines, in this case PC7.
PC7
SYNC
ADG739
ADG738/
ADG739
MC68HC11*
MOSI
SCK
DIN
SYNC
DIN
SCLK
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
V
ADG738
SYNC
DD
Figure 18. MC68HC11 Interface to ADG738/ADG739
1/2 OF ADG739
DIN
The 68HC11 is configured for master mode; MSTR = 1, CPOL
= 0 and CPHA = 1. When data is transferred to the part, PC7 is
taken low, data is transmitted MSB first. Data appearing on the
MOSI output is valid on the falling edge of SCK.
SCLK
S1A
S2A
S3A
OTHER SPI
DEVICE
DA
SYNC1
SYNC
If the user wishes to verify the data previously written to the input
shift register, the DOUT line could be connected to MISO of
the MC68HC11, and with SYNC low, the shift register would
clock data out on the rising edges of SCLK.
DIN
S4A
FROM
CONTROLLER
OR DSP
SCLK
SYNC
SCLK DIN
OTHER SPI
DEVICE
SYNC2
APPLICATIONS
SYNC
Expand the Number of Selectable Serial Devices Using an
ADG739
SCLK
DIN
DIN
SCLK
The dual 4-channel ADG739 multiplexer can be used to multiplex
a single chip select line in order to provide chip selects for up to
four devices on the SPI bus. Figure 19 illustrates the ADG739 in
such a typical configuration. All devices receive the same serial
clock and serial data, but only one device will receive the
SYNC signal at any one time. The ADG739 is a serially controlled
device also. One bit programmable pin of the microcontroller is
used to enable the ADG739 via SYNC2, while another bit
programmable pin is used as the chip select for the other serial
devices, SYNC1. Driving SYNC2 low enables changes to be
made to the addressed serial devices. By bringing SYNC1 low,
the selected serial device hanging from the SPI bus will be enabled
and data will be clocked into its shift register on the falling
edges of SCLK. The convenient design of the matrix switch
Figure 19. Addressing Multiple Serial Devices Using an
ADG739
Daisy-Chaining Multiple ADG738s
A number of ADG738 matrix switches may be daisy-chained
simply by using the DOUT pin. DOUT is an open drain output
that should be pulled to the supply with an external resistor.
Figure 20 shows a typical implementation. The SYNC pin of all
three parts in the example are tied together. When SYNC is
brought low, the input shift registers of all parts are enabled,
data is written to the parts via DIN, and clocked through the
shift registers. When the transfer is complete, SYNC is brought
high and all switches are updated simultaneously. Further shift
registers may be added in series.
V
DD
R
R
R
SCLK
SCLK
SCLK
DIN
SCLK
DIN
ADG739
ADG739
ADG739
DOUT
DOUT
DOUT
DIN
DIN
TO OTHER
SERIAL DEVICES
SYNC
SYNC
SYNC
SYNC
Figure 20. Multiple ADG739 Devices in a Daisy-Chained Configuration
–10–
REV. 0
ADG738/ADG739
TEST CIRCUITS
I
DS
V
DD
V
1
V
DD
I
(OFF)
A
S
S1
S2
S8
V
S
S
D
S
D
V
GND
D
V
R
= V /I
DS
1
ON
Test Circuit 3. IS (OFF)
Test Circuit 1. On Resistance
V
V
DD
DD
V
V
DD
DD
S1
S8
S1
I
(ON)
A
I
(OFF)
A
D
D
S2
S8
D
D
V
V
D
D
GND
GND
V
V
S
S
Test Circuit 2. ID (OFF)
Test Circuit 4. ID (ON)
V
V
DD
DD
SYNC
SYNC
50%
50%
ADG738*
V
S1
S1
S2 THRU S7
S8
V
S1
V
R
S8
V
= V
S8
S1
90%
V
D
80%
OUT
V
80%
V
OUT
OUT
C
35pF
GND
L
L
300⍀
90%
tOPEN
tOFF
tON
* SIMILAR CONNECTION FOR ADG739
Test Circuit 5. Switching Times and Break-Before-Make Times
V
SYNC
DD
ADG738*
SWITCH ON
R
S
D
SWITCH OFF
S
⌬V
OUT
V
OUT
Q
= C x ⌬V
OUT
L
C
INJ
L
V
1nF
S
INPUT LOGIC
GND
* SIMILAR CONNECTION FOR ADG739
Test Circuit 6. Charge Injection
REV. 0
–11–
ADG738/ADG739
V
V
V
V
DD
DD
DD
DD
S1
S8
ADG738*
V
S
50⍀
S1
D
V
ADG738*
OUT
R
50⍀
L
S2
S8
D
V
OUT
R
50⍀
V
L
S
GND
GND
*SIMILAR CONNECTION FOR ADG739
* SIMILAR CONNECTION FOR ADG739
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG (V
S1 IS SWITCHED OFF FOR OFF ISOLATION MEASUREMENTS
AND ON FOR BANDWIDTH MEASUREMENTS
/V )
10 OUT
S
OFF ISOLATION = 20LOG (V
/V )
S
10
OUT
V
WITH SWITCH
OUT
INSERTION LOSS = 20LOG
10
V
WITHOUT SWITCH
OUT
Test Circuit 7. Channel-to-Channel Crosstalk
Test Circuit 8. Off Isolation and Bandwidth
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
0.028 (0.70)
0.020 (0.50)
0.0079 (0.20)
0.0035 (0.090)
SEATING
PLANE
BSC
REV .0
–12–
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