ADG782_15 [ADI]
Quad SPST Switches in Chip Scale Package;
| 型号： | ADG782_15 |
| 厂家： | 
ADI |
| 描述： | Quad SPST Switches in Chip Scale Package |
| 文件： | 总9页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 ꢀ Quad SPST Switches
a
in Chip Scale Package
ADG781/ADG782/ADG783
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
1.8 V to 5.5 V Single Supply
Low On Resistance (2.5 ꢀ Typ)
Low On-Resistance Flatness (0.5 ꢀ)
–3 dB Bandwidth > 200 MHz
Rail-to-Rail Operation
20-Lead 4 mm ꢁ 4 mm Chip Scale Package
Fast Switching Times
tON = 16 ns
tOFF = 10 ns
Typical Power Consumption (< 0.01 ꢂW)
TTL/CMOS Compatible
For Functionally Equivalent Devices in 16-Lead TSSOP
and SOIC Packages, See ADG711/ADG712/ADG713
S1
S1
S1
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
IN1
IN2
IN3
IN4
D1
S2
D1
S2
D1
S2
D2
S3
D2
S3
D2
S3
ADG782
ADG783
ADG781
D3
S4
D3
S4
D3
S4
D4
D4
D4
SWITCHES SHOWN FOR A LOGIC “1” INPUT
APPLICATIONS
Battery Powered Systems
Communication Systems
Sample Hold Systems
Audio Signal Routing
Video Switching
Mechanical Reed Relay Replacement
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. 20-Lead 4 mm ϫ 4 mm Chip Scale Package (CSP).
The ADG781, ADG782, and ADG783 are monolithic CMOS
devices containing four independently selectable switches. These
switches are designed on an advanced submicron process that
provides low power dissipation and high switching speed, low on
resistance, low leakage currents and high bandwidth.
2. 1.8 V to 5.5 V Single Supply Operation. The ADG781,
ADG782, and ADG783 offer high performance and are
fully specified and guaranteed with 3 V and 5 V supply
rails.
They are designed to operate from a single 1.8 V to 5.5 V sup-
ply, making them ideal for use in battery powered instruments
and with the new generation of DACs and ADCs from Analog
Devices. Fast switching times and high bandwidth make the
part suitable for video signal switching.
3. Very Low RON (4.5 Ω max at 5 V, 8 Ω max at 3 V). At supply
voltage of 1.8 V, RON is typically 35 Ω over the temperature
range.
4. Low On-Resistance Flatness.
5. –3 dB Bandwidth >200 MHz.
The ADG781, ADG782, and ADG783 contain four independent
single-pole/single throw (SPST) switches. The ADG781 and
ADG782 differ only in that the digital control logic is inverted.
The ADG781 switches are turned on with a logic low on the
appropriate control input, while a logic high is required to turn
on the switches of the ADG782. The ADG783 contains two
switches whose digital control logic is similar to the ADG781,
while the logic is inverted on the other two switches.
6. Low Power Dissipation. CMOS construction ensures low
power dissipation.
7. Fast tON/tOFF.
8. Break-Before-Make Switching. This prevents channel shorting
when the switches are configured as a multiplexer (ADG783
only).
Each switch conducts equally well in both directions when ON.
The ADG783 exhibits break-before-make switching action.
The ADG781/ADG782/ADG783 are available in 20-lead chip
scale packages.
C
REV.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
781/461-3113
www.analog.com
2013
© Analog Devices, Inc.,
Fax:
(VDD = 5 V ꢃ 10%, GND = 0 V. All specifications
ADG781/ADG782/ADG783–SPECIFICATIONS –40ꢄC to +85ꢄC unless otherwise noted.)
B Version
–40ꢄC to
+85ꢄC
Parameter
+25ꢄC
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
2.5
4
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IS = –10 mA;
Test Circuit 1
VS = 0 V to VDD, IS = –10 mA
4.5
0.05
0.4
On-Resistance Match Between
Channels (ΔRON
)
On-Resistance Flatness (RFLAT(ON)
)
0.5
VS = 0 V to VDD, IS = –10 mA
1.0
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = 5.5 V;
VS = 4.5 V/1 V, VD = 1 V/4.5 V;
Test Circuit 2
VS = 4.5 V/1 V, VD = 1 V/4.5 V;
Test Circuit 2
VS = VD = 1 V, or 4.5 V;
Test Circuit 3
0.01
0.1
0.01
0.1
0.01
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
0.2
0.2
0.2
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
I
INL or IINH
0.005
μA typ
μA max
VIN = VINL or VINH
0.1
DYNAMIC CHARACTERISTICS2
tON
11
6
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF,
VS = 3 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF,
VS = 3 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF,
16
10
1
tOFF
Break-Before-Make Time Delay, tD
(ADG783 Only)
Charge Injection
6
V
S1 = VS2 = 3 V; Test Circuit 5
3
VS = 2 V; RS = 0 Ω, CL = 1 nF;
Test Circuit 6
Off Isolation
–58
–78
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk
–90
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz;
Test Circuit 8
Bandwidth –3 dB
CS (OFF)
200
10
10
MHz typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF; Test Circuit 9
f = 1 MHz
f = 1 MHz
C
D (OFF)
CD, CS (ON)
22
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
0.001
μA typ
μA max
1.0
NOTES
1Temperature ranges are as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
C
–2–
REV.
ADG781/ADG782/ADG783
SPECIFICATIONS1 (VDD = 3 V ꢃ10%, GND = 0 V. All specifications –40ꢄC to +85ꢄC unless otherwise noted.)
B Version
–40ꢄC to
Parameter
+25ꢄC
+85ꢄC
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
5.5
10
V
On Resistance (RON
)
5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IS = –10 mA;
Test Circuit 1
VS = 0 V to VDD, IS = –10 mA
On-Resistance Match Between
0.1
Channels (ΔRON
)
0.5
2.5
On-Resistance Flatness (RFLAT(ON)
)
VS = 0 V to VDD, IS = –10 mA
LEAKAGE CURRENTS
VDD = 3.3 V;
Source OFF Leakage IS (OFF)
0.01
0.1
0.01
0.1
0.01
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = VD = 1 V, or 3 V;
Test Circuit 3
0.2
0.2
0.2
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
0.1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
I
INL or IINH
0.005
μA typ
μA max
VIN = VINL or VINH
0.1
DYNAMIC CHARACTERISTICS2
tON
13
7
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF,
VS = 2 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF,
VS = 2 V; Test Circuit 4
RL = 300 Ω, CL = 35 pF,
20
12
1
tOFF
Break-Before-Make Time Delay, tD
(ADG783 Only)
Charge Injection
7
V
S1 = VS2 = 2 V; Test Circuit 5
3
VS = 1.5 V; RS = 0 Ω, CL = 1 nF;
Test Circuit 6
Off Isolation
–58
–78
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk
–90
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz;
Test Circuit 8
Bandwidth –3 dB
CS (OFF)
200
10
10
MHz typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF; Test Circuit 9
f = 1 MHz
f = 1 MHz
C
D (OFF)
CD, CS (ON)
22
f = 1 MHz
POWER REQUIREMENTS
IDD
V
DD = 3.3 V
0.001
μA typ
μA max
Digital Inputs = 0 V or 3.3 V
1.0
NOTES
1Temperature ranges are as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
C
–3–
REV.
ADG781/ADG782/ADG783
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C unless otherwise noted.)
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
IR Reflow (<20 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 235°C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Analog, Digital Inputs2 . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Chip Scale Package
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 32°C/W
Table I. Truth Table (ADG781/ADG782)
PIN CONFIGURATION
(LFCSP)
ADG781 In
ADG782 In
Switch Condition
0
1
1
0
ON
OFF
15 D2
14 S2
13 V
D1
S1
1
2
3
4
5
ADG781/
ADG782/
ADG783
TOP VIEW
(Not to Scale)
Table II. Truth Table (ADG783)
GND
S4
DD
12 S3
11 D3
Logic
Switch 1, 4
Switch 2, 3
D4
0
1
OFF
ON
ON
OFF
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD TIED TO SUBSTRATE, GND.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG781/ADG782/ADG783 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
C
–4–
REV.
ADG781/ADG782/ADG783
TERMINOLOGY
VDD
Most positive power supply potential.
CD, CS (ON)
“ON” switch capacitance.
tON
Delay between applying the digital control
input and the output switching on.
Delay between applying the digital control
GND
S
D
IN
RON
ΔRON
Ground (0 V) reference.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
Ohmic resistance between D and S.
On-resistance match between any two chan-
nels (i.e., RON max and RON min).
tOFF
input and the output switching off.
tD
“OFF” time or “ON” time measured
between the 90% points of both switches,
when switching from one address state to
another (ADG783 only).
RFLAT(ON)
Flatness is defined as the difference between
the maximum and minimum value of on
resistance as measured over the specified
analog signal range.
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Analog voltage on terminals D, S.
Crosstalk
A measure of unwanted signal that is coupled
through from one channel to another as a
result of parasitic capacitance.
A measure of unwanted signal coupling
through an “OFF” switch.
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
Off Isolation
IS (OFF)
D (OFF)
I
Charge
Injection
ID, IS (ON)
VD (VS)
On Response
On Loss
The frequency response of the “ON” switch.
The loss due to the on resistance of the switch.
CS (OFF)
CD (OFF)
“OFF” switch source capacitance.
“OFF” switch drain capacitance.
Typical Performance Characteristics
6
6
5.5
5
T
= 25ꢄC
5.5
5
V
= 5V
A
DD
V
= 2.7V
DD
4.5
4
4.5
4
+85ꢄC
3.5
3
3.5
3
V
= 4.5V
DD
V
= 3V
+25ꢄC
DD
2.5
2
2.5
2
V
= 5V
DD
1.5
1
1.5
1
–40ꢄC
0.5
0
0.5
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
OR V – DRAIN OR SOURCE VOLTAGE – V
V OR V – DRAIN OR SOURCE VOLTAGE – V
D S
D
S
TPC 1. On Resistance as a Function of VD (VS)
TPC 3. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 5 V
6
10m
V
= 5V
DD
V
= 3V
5.5
5
DD
1m
+85ꢄC
4.5
4
+25ꢄC
100ꢂ
4 SW
3.5
3
10ꢂ
1ꢂ
1 SW
2.5
2
–40ꢄC
100n
1.5
1
10n
1n
0.5
0
100
1k
10k
100k
1M
10M
0
0.5
1
1.5
2
2.5
3
FREQUENCY – Hz
V
OR V – DRAIN OR SOURCE VOLTAGE – V
D
S
TPC 2. On Resistance as a Function of VD (VS) for
Different Temperatures VDD = 3 V
TPC 4. Supply Current vs. Input Switching Frequency
C
REV.
–5–
ADG781/ADG782/ADG783
–30
0
–2
–4
–6
–40
V
= 5V, 3V
DD
–50
–60
V
= 5V
DD
–70
–80
–90
–100
–110
–120
–130
10k
100k
1M
FREQUENCY – Hz
10M
100M
10k
100k
1M
10M
100M
FREQUENCY – Hz
TPC 5. Off Isolation vs. Frequency
TPC 7. On Response vs. Frequency
25
20
15
10
5
–30
–40
T
= 25ꢄC
A
V
= 5V, 3V
DD
–50
–60
–70
V
= 5V
DD
V
= 3V
DD
–80
–90
–100
–110
–120
–130
0
–5
–10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
10k
100k
1M
FREQUENCY – Hz
10M
100M
SOURCE VOLTAGE – V
TPC 8. Charge Injection vs. Source Voltage
TPC 6. Crosstalk vs. Frequency
C1
APPLICATIONS
Figure 1 illustrates a photodetector circuit with programmable
gain. An AD820 is used as the output operational amplifier.
With the resistor values shown in the circuit, and using different
combinations of the switches, gain in the range of 2 to 16 can
be achieved.
R1
33kꢀ
5V
AD820
D1
2.5V
V
OUT
R2
510kꢀ
5V
R4
R5
240kꢀ 240kꢀ
S1
D1
D2
D3
D4
R3
510kꢀ
(LSB) IN1
R6
R7
120kꢀ 120kꢀ
S2
S3
S4
IN2
IN3
R8
120kꢀ
R9
120kꢀ
2.5V
R10
120kꢀ
(MSB) IN4
GND
GAIN RANGE 2 TO 16
Figure 1. Photodetector Circuit with Programmable Gain
C
–6–
REV.
ADG781/ADG782/ADG783
Test Circuits
V
I
(OFF)
A
I
(OFF)
A
I
(ON)
A
S
D
D
S
D
S
D
NC
S
D
V
V
V
D
D
S
I
DS
NC = NO CONNECT
V
R
= V/I
S
ON DS
Test Circuit 1. On Resistance
Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage
V
DD
0.1ꢂF
V
50%
50%
50%
ADG781
ADG782
IN
V
DD
V
IN
50%
90%
D
S
V
OUT
R
300ꢀ
V
C
35pF
IN
L
S
L
V
S
90%
V
OUT
GND
tON
tOFF
Test Circuit 4. Switching Times
V
DD
V
0.1ꢂF
IN
50%
50%
0V
V
DD
90%
90%
V
S1
S2
D1
D2
OUT1
V
V
0V
0V
S1
OUT1
C
35pF
R
300ꢀ
L1
L1
V
V
S2
OUT2
C
35pF
R
300ꢀ
IN1, IN2
L2
L2
90%
90%
V
OUT2
V
ADG783
GND
IN
tD
tD
Test Circuit 5. Break-Before-Make Time Delay, tD
SW ON
SW OFF
V
DD
V
IN
V
DD
R
S
D
S
V
OUT
C
V
L
IN
S
1nF
V
OUT
GND
V
OUT
Q
= C
ꢁ
V
OUT
INJ
L
Test Circuit 6. Charge Injection
V
DD
V
DD
0.1ꢂF
0.1ꢂF
NETWORK
NETWORK
ANALYZER
ANALYZER
V
DD
V
DD
D1
S1
D2
NC
V
OUT
R
L
S
50ꢀ
50ꢀ
50ꢀ
IN
S2
V
S
R
50ꢀ
L
50ꢀ
D
V
V
OUT
IN
IN
V
R
S
L
50ꢀ
GND
GND
CHANNEL-TO-CHANNEL
V
V
V
S
OUT
OUT
OFF ISOLATION = 20 LOG
CROSSTALK = 20 LOG
V
S
Test Circuit 7. Off Isolation
Test Circuit 8. Channel-to-Channel Crosstalk
C
REV.
–7–
ADG781/ADG782/ADG783
V
V
DD
0.1ꢂF
NETWORK
ANALYZER
DD
S
50ꢀ
IN
V
S
D
V
V
OUT
IN
R
L
50ꢀ
GND
V
WITH SWITCH
OUT
WITHOUT SWITCH
INSERTION LOSS = 20 LOG
V
OUT
Test Circuit 9. Bandwidth
C
–8–
REV.
ADG781/ADG782/ADG783
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.30
2.10 SQ
2.00
11
5
6
10
0.65
0.60
0.55
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
Figure 2. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
Package Description
Package Option
CP-20-6
CP-20-6
ADG781BCPZ
ADG781BCPZ-REEL7
ADG782BCPZ
ADG782BCPZ-REEL7
ADG783BCPZ
ADG783BCPZ-REEL
ADG783BCPZ-REEL7
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
CP-20-6
CP-20-6
CP-20-6
CP-20-6
CP-20-6
1 Z = RoHS Compliant Part.
REVISION HISTORY
2/13—Rev. B to Rev. C
Changed Pin 4 from S3 to S4...........................................................4
Changes to Test Circuit 1 .................................................................7
Changes to Ordering Guide.............................................................9
8/12—Rev. A to Rev. B
Updated Outline Dimensions..........................................................9
Changes to Ordering Guide.............................................................9
3/02—Rev. 0 to Rev. A
Edits to Typical Performance Characteristics ........................... 5-6
Changes to OUTLINE DIMENSIONS drawing ...........................8
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02372-0-2/13(C)
REV. C
–9–
相关型号：
SI9130DB
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