ADG783BCP-REEL7 [ADI]
IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, QCC20, 4 X 4 MM, CSP-20, Multiplexer or Switch;
| 型号： | ADG783BCP-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC QUAD 1-CHANNEL, SGL POLE SGL THROW SWITCH, QCC20, 4 X 4 MM, CSP-20, Multiplexer or Switch |
| 文件： | 总10页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
CMOS,
Low Voltage 2.5 ΩQuad SPST Switches
a
Preliminary Technical Data
ADG781/ADG782/ADG783
FEATURES
F U NC T IO NAL B LO C K D IAG RAM S
1.8 V to 5.5 V Single Supply
Low On-Resistance 2.5 Ω
On-Resistance Flatness
-3dB Bandw idth >200MHz
100 pA Leakage Currents
14 ns Sw itching Tim es
20-Lead Chip Scale Package
Low Pow er Consum ption
TTL/ CMOS-Com patible Inputs
S1
S1
S1
IN1
IN2
IN3
IN1
IN2
IN1
IN2
D1
S2
D1
S2
D1
S2
D2
S3
D2
S3
D2
S3
ADG781
ADG782
ADG783
IN3
IN4
IN3
IN4
D3
S4
D3
S4
D3
S4
APPLICATIONS
Battery Pow ered System s
Com m unication System s
Sam ple and Hold System s
Audio SignalRouting
Relay Replacem ent
IN4
D4
D4
D4
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Video Sw itching
G E NE R AL D E S C R IP T IO N
action. T he AD G781/AD G782/AD G783 are available in
20-lead Chip Scale Packages
T he ADG781, ADG782 and ADG783 are monolithic
CMOS devices containing four independently selectable
switches. T hese switches are designed on an advanced
submicron process that provides low power dissipation yet
gives high switching speed, low on resistance, low leakage
currents and high bandwidth.
P R O D U C T H IG H LIG H T S
1. +1.8 V to +5.5 V Single Supply Operation. T he
ADG781, ADG782 and ADG783 offer high perfor
mance and are fully specified and guaranteed with +3V
and +5 V supply rails.
T hey are designed to operate from a single +1.8 V to
+5.5 V supply, making them ideal for use in battery pow-
ered instruments and with the new generation of DACs
and ADCs from Analog Devices. Fast switching times and
high bandwidth make the part suitable for video signal
switching. T he ADG781, ADG782 and ADG783 contain
four independent single-pole/single throw (SPST )
switches. T he ADG781 and ADG782 differ only in that
the digital control logic is inverted. T he ADG781
switches are turned on with a logic low on the appropriate
control input, while a logic high is required to turn on the
switches of the ADG782. T he ADG783 contains two
switches whose digital control logic is similar to the
ADG781, while the logic is inverted on the other two
switches.
2. Very Low RON (4.5 Ω max at +5 V, 8 Ω max at +3 V).
At supply voltage of +1.8 V, RON is typically 35 Ω over
the temperature range.
3. Low On-Resistance Flatness.
4. –3 dB Bandwidth >200 MHz.
5. Fast tON /tOFF
.
6 . Break-Before-M ake Switching.
T his prevents channel shorting when the switches are
configured as a multiplexer (ADG783 only).
Each switch conducts equally well in both directions when
ON . T he AD G783 exhibits break-before-make switching
REV. PrB
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2001
PRELIMINARY TECHNICAL DATA
1(V = 5 V ±10%, GND = 0 V, unless otherwise noted)
DD
ADG781/ADG782/ADG783–SPECIFICATIONS
B Version
–40
to +85
ꢀ
C
P ar am eter
+25
ꢀ
C
ꢀC
Unit
Test Conditions/Com m ents
AN ALO G SWIT C H
Analog Signal Range
0 V to VDD
V
On-Resistance (RON
)
2.5
4
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IDS = 10 mA;
T est Circuit 1
4.5
0.05
0.3
On-Resistance M atch Between
Channels (∆RON
)
VS = 0 V to VDD, IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
On-Resistance Flatness (RFLAT (ON)
)
0.5
1.0
LEAKAG E C U RREN T S
VDD = 5.5 V
Source OFF Leakage IS (OFF)
± 0.01
± 10
± 0.01
± 10
± 0.01
± 10
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
T est Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
T est Circuit 2
± 20
± 20
± 20
D rain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
VD = VS = 1 V, or 4.5 V, T est Circuit 3
D IG IT AL IN PU T S
Input H igh Voltage, VIN H
Input Low Voltage, VIN L
Input Current
2.4
0.8
V min
V max
IIN L or IIN H
0.005
2
µA typ
µA max
pF typ
VIN = VINL or VINH
± 0.1
CIN, Digital Input Capacitance
D YN AM IC C H ARAC T ERIST IC S2
t O N
11
6
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 3 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 3 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF
VS1 =VS2 = 3 V, T est Circuit 5
VS = 2 V, RS = 0 Ω, CL = 1 nF;
T est Circuit 6
16
10
1
tO F F
Break-Before-M ake T ime D elay, tD
Charge Injection
6
± 3
Off Isolation
–58
–78
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 7
C hannel-to-C hannel C rosstalk
–90
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
T est Circuit 8
–3 dB Bandwidth
C S (O F F )
C D (O F F )
200
10
10
MH z typ
pF typ
pF typ
pF typ
RL = 50 Ω, CL = 5 pF, T est Circuit 9
CD , CS (ON )
22
P O WER REQ U IREM EN T S
I D D
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
0.001
µA typ
1.0
µA max
N O T E S
1T emperature range is as follows:
B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Speci•cations subject to change without notice.
REV. PrB
–2 –
PRELIMINARY TECHNICAL DATA
ADG781/ADG782/ADG783
1
SPECIFICATIONS (V = 3 V ± 10%, GND = 0 V, unless otherwise noted)
DD
B Ver sion
–40
ꢀC
P ar am eter
+258C
to +85
ꢀC Unit
Test Conditions/Com m ents
AN ALO G SWIT C H
Analog Signal Range
0 V to VDD
V
On-Resistance (RON
)
5
5.5
8
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IDS = 10 mA;
T est Circuit 1
VS = 0 V to VDD , IDS = 10 mA
On-Resistance M atch Between
Channels (∆RON
0.1
)
0.3
2.5
On-Resistance Flatness (RFLAT (ON )
)
VS = 0 V to VDD , IDS = 10 mA
LEAKAG E C U RREN T S
VDD = 3.3 V
Source OFF Leakage IS (OFF)
± 0.01
± 10
± 0.01
± 10
± 0.01
± 10
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V;
T est Circuit 2
VS = 3 V/1 V, VD = 1 V/3 V;
T est Circuit 2
± 20
± 20
± 20
D rain OFF Leakage ID (OFF)
Channel ON Leakage ID , IS (ON)
VS = VD = 1 V or 3 V, T est Circuit 3
D IG IT AL IN PU T S
Input H igh Voltage, VIN H
Input Low Voltage, VIN L
Input Current
2.0
0.4
V min
V max
IIN L or IIN H
0.005
2
µA typ
µA max
pF typ
VIN = VINL or VINH
± 0.1
CIN , Digital Input Capacitance
D YN AM IC C H ARAC T ERIST IC S2
t O N
13
7
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 2 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF
VS = 2 V, T est Circuit 4
RL = 300 Ω, CL = 35 pF
VS1 =VS2 = 2 V, T est Circuit 5
VS = 1.5 V, RS = 0 Ω, CL = 1 nF;
T est Circuit 6
20
12
1
tO F F
Break-Before-M ake T ime D elay, tD
Charge Injection
7
± 3
Off Isolation
–58
–78
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
T est Circuit 7
C hannel-to-C hannel C rosstalk
–90
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
T est Circuit 8
–3 dB Bandwidth
C S (O F F )
C D (O F F )
200
10
10
MH z typ RL = 50 Ω, CL = 5 pF, T est Circuit 9
pF typ
pF typ
pF typ
CD , C S (ON )
22
P O WER REQ U IREM EN T S
I D D
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
0.001
µA typ
1.0
µA max
N O T E S
1T emperature ranges are as follows:
B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Speci•cations subject to change without notice.
REV. PrB
–3 –
PRELIMINARY TECHNICAL DATA
ADG781/ADG782/ADG783
AB SO LUT E M AXIM UM RAT ING S1
(T A = 25°C unless otherwise noted)
θJC T hermal Impedance . . . . . . . . . . . . . . . . . T BD °C /W
Lead T emperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Analog Inputs2 . . . . . . . . . . VSS – 0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
NOT ES
D igital Inputs2 . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speci•cation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . 100 mA
. . . . . . . . . . . . . . (Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . 30 mA
Operating T emperature Range
Industrial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
CSP Package, Power D issipation . . . . . . . . . . . T BD mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . T BD °C /W
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
C A U T I O N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD G 781/AD G 782/AD G 783 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges.
T herefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
O R D E R ING G U ID E
Model
Tem perature Range
P ackage D escription
P ackage O ption
AD G 781BC P
AD G 782BC P
AD G 783BC P
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Chip Scale Package (CSP)
Chip Scale Package (CSP)
Chip Scale Package (CSP)
C P -20
C P -20
C P -20
P IN C O NF IG U R AT IO NS
Table I. AD G781/AD G782 Tr uth Table
AD G781 In
AD G782 In
Switch Condition
NC IN1 NC IN2 NC
0
1
1
0
O N
O F F
D1
S1
D2
S2
ADG781
ADG782
ADG783
Table II. AD G783 Tr uth Table
VDD
GND
S4
Logic
Switch 1, 4
Switch 2, 3
S3
D3
0
1
O F F
O N
O N
O F F
D4
NC IN4 NC IN3 NC
NC = NO CONNECT
Exposed Pad tied to Substrate, GND
REV. PrB
–4 –
PRELIMINARY TECHNICAL DATA
ADG781/ADG782/ADG783
T E R M I N O L O G Y
V D D
Most positive power supply potential.
Ground (0 V) Reference.
G N D
S
Source T erminal. May be an input or output.
Drain T erminal. May be an input or output.
Logic Control Input.
D
I N
R O N
Ohmic resistance between D and S.
RF L AT (O N )
Flatness is defined as the difference between the maximum and minimum value of on-resistance as mea
sured over the specifed analog signal range.
∆RO N
IS (OFF)
On resistance match between any two channels, i.e RONmax-RONmin.
Source leakage current with the switch “OFF.”
ID (O F F )
Drain leakage current with the switch “OFF.”
ID, IS (ON) Channel leakage current with the switch “ON.”
VD (VS)
Analog voltage on terminals D, S.
C S (O F F )
C D (O F F )
“OFF” switch source capacitance. Measured with reference to ground.
“OFF” switch drain capacitance. M easured with reference to ground.
CD, CS (ON) “ON ” switch capacitance. M easured with reference to ground.
C I N
t O N
tO F F
t D
D igital Input Capacitance.
Delay time between applying the digital control input and the switch turning on.
Delay time between applying the digital control input and the switch turning off.
“OFF” time measured between the 90% points of both switches when switching from one address state to
another (AD G783 only).
Off Isolation A measure of unwanted signal coupling through an “OFF” switch.
C rosstalk
A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic
capacitance.
C harge
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
Injection
Bandwidth
T he frequency at which the output is attenuated by 3 dBs.
On Response T he frequency response of the “ON” switch.
On Loss
VI N L
T he loss due to the ON resistance of the switch.
Maximum input voltage for Logic “0.”
Minimum input voltage for Logic “1.”
Input current of the digital input.
VI N H
IIN L (IIN H
I D D
)
Positive Supply Current.
REV. PrB
–5 –
PRELIMINARY TECHNICAL DATA
Typical Performance Characteristics–
ADG781/ADG782/ADG783
10m
6
V
= +5V
DD
5.5
T
= +25ꢀC
A
1m
5
4.5
4
V
= +2.7V
DD
100ꢂ
4 SW
3.5
3
10ꢂ
1ꢂ
V
= +4.5V
DD
V
= +3V
DD
1 SW
2.5
2
V
= +5V
DD
100n
1.5
1
10n
1n
0.5
0
0
0.5
V
1
1.5
2
2.5
3
3.5
4
4.5
5
100
1k
10k
100k
1M
10M
OR V – DRAIN OR SOURCE VOLTAGE – Volts
D
S
FREQUENCY – Hz
Figure 4. Supply Current vs. Input Switching Frequency
Figure 1. On Resistance as a Function of VD (VS) for Single
Supply
–30
–40
6
V
= +3V
5.5
5
DD
V
= +5V, +3V
DD
+85ꢀC
–50
–60
4.5
4
+25ꢀC
–70
3.5
3
–80
2.5
2
–90
–40ꢀC
–100
–110
–120
–130
1.5
1
0.5
0
0
0.5
1
1.5
23
2.5
10k
100k
1M
FREQUENCY – Hz
10M
100M
V
OR V – DRAIN OR SOURCE VOLTAGE – Volts
S
D
Figure 2. On Resistance as a Function of VD (VS) for Differ-
ent Tem peratures, VDD = 3 V.
Figure 5. Off Isoltaion vs. Frequency
6
–30
5.5
5
V
= +5V
DD
–40
–50
V
= +5V, +3V
DD
4.5
4
–60
+85ꢀC
–70
3.5
3
+25ꢀC
–80
2.5
2
–90
–100
–110
–120
–130
1.5
1
–40ꢀC
0.5
0
0
0.5
V
1
1.5
2
2.5
3
3.5
4
4.5
5
10k
100k
1M
FREQUENCY – Hz
10M
100M
OR V – DRAIN OR SOURCE VOLTAGE – Volts
D
S
Figure 3. On Resistance as a Function of VD (VS) for Differ-
ent Tem peratures, VDD = 5 V.
Figure 6. Crosstalk vs. Frequency
REV. PrB
–6 –
PRELIMINARY TECHNICAL DATA
ADG781/ADG782/ADG783
0
–2
–4
–6
AP P L I C AT I O N S
Figure 9 illustrates a photodetector circuit with program-
mable gain. With the resistor values shown in the circuit
and using different combinations of switches, gains in the
range of 2 to 16 can be achieved.
V
= +5V
DD
C1
R1
33kꢁ
+5V
AD820
D1
10k
100k
1M
10M
100M
V
+2.5V
OUT
FREQUENCY – Hz
R2
510kꢁ
Figure 7. On Response vs. Frequency
+5V
R4
R5
240kꢁ 240kꢁ
S1
D1
D2
D3
D4
25
20
15
10
5
R3
510kꢁ
T
= +25ꢀC
(LSB) IN1
A
R6
R7
120kꢁ 120kꢁ
S2
S3
S4
IN2
IN3
R8
120kꢁ
V
= +5V
R9
120kꢁ
DD
V
= +3V
DD
+2.5V
R10
(MSB) IN4
120kꢁ
GND
0
GAIN RANGE 2 TO 16
–5
–10
Figure 9. Photodetector Circuit with Program m able Gain
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
SOURCE VOLTAGE – Volts
Figure 8. Charge Injection vs. Source Voltage
REV. PrB
–7 –
PRELIMINARY TECHNICAL DATA
ADG781/ADG782/ADG783
Test Circuits
I
DS
V1
I
D
(ON)
A
I
S
(OFF)
A
S
D
S
D
S
D
NC
V
D
V
D
VS
VS
RON = V1/IDS
Test Circuit 1. On Resistance
Test Circuit 2. IS (OFF)
Test Circuit 3. ID (OFF)
VDD
0.1
F
µ
VIN
50%
50%
50%
ADG781
ADG782
VDD
VIN
50%
90%
S
D
VOUT
RL
300
VS
IN
CL
VS
90%
35pF
Ω
VOUT
GND
tON
t OFF
Test Circuit 4. Switching Tim e
V
V
DD
DD
V
IN
0.1
F
50%
50%
µ
0V
0V
90%
90%
V
S1
S2
D1
D2
OUT1
OUT2
V
V
S1
OUT1
R
C
L1
L1
35pF
V
V
300
Ω
S2
OUT2
C
IN1, IN2
R
L2
L2
90%
90%
300
35pF
Ω
V
V
ADG783
GND
0V
IN
t D
tD
Test Circuit 5. Break-Before-Make Delay, tD
V
V
SW ON
SW OFF
DD
V
IN
DD
R
S
D
S
V
OUT
C
1nF
V
S
L
IN
V
OUT
V
OUT
GND
Q
= C ꢃ V
L OUT
INJ
Test Circuit 6. Charge Injection
REV. PrB
–8 –
PRELIMINARY TECHNICAL DATA
ADG781/ADG782/ADG783
V
DD
0.1ꢂF
V
DD
0.1ꢂF
V
DD
S
D
V
DD
V
OUT
S
D
R
50ꢁ
L
V
OUT
IN
R
L
V
IN
V
S
50ꢁ
IN
GND
V
IN
V
S
GND
Test Circuit 7. OFF Isolation
Figure 9. Bandwidth
V
DD
0.1ꢂF
V
DD
50ꢁ
S
S
D
D
V
IN1
V
S
V
IN2
V
NC
OUT
R
50ꢁ
L
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 ꢃ LOG
|
V
/V
|
S
OUT
Test Circuit 8. Channel-to-Channel Crosstalk
REV. PrB
–9 –
PRELIMINARY TECHNICAL DATA
ADG781/ADG782/ADG783
O U T LINE D IM E NS IO NS
D imensions shown in inches and (mm).
20-Lead Chip Scale
(C P - 20)
0.158(4.0)BSC
0.024 (0.6)
0.009(0.24)
0.148(3.75)BSC
20
0.096 (2.45)
0.085 (2.15)
0.024 (0.6)
0.009(0.24)
0.148(3.75)BSC
0.096 (2.45)
0.085 (2.15)
0.158(4.0)BSC
0.03(0.75)
0.014(0.35)
0.02(0.5)BSC
o
0.012(0.3)
0.007(0.18)
12
0.032(0.8)Max
0.026(0.65)Nom
Bottom View
0.039(1.0)Max
0.033(0.85)Nom
0.039(0.05)
0.033(0.01)
0.0(0.0)
0.039(0.2)Ref
–1 0 –
REV. PrB
相关型号：
©2020 ICPDF网 联系我们和版权申明