ADG790 [ADI]
Low Voltage, CMOS Multimedia Switch; 低压， CMOS多媒体开关
| 型号： | ADG790 |
| 厂家： | 
ADI |
| 描述： | Low Voltage, CMOS Multimedia Switch |
| 文件： | 总20页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage, CMOS Multimedia Switch
ADG790
FUNCTIONAL BLOCK DIAGRAM
ADG790
FEATURES
Single-chip audio/video/data switching solution
Wide bandwidth section
Rail-to-rail signal switching capability
Compliant with full speed USB 2.0 signaling (3.6 V p-p)
Compliant with high speed USB 2.0 signaling (400 mV p-p)
Supports USB data rates up to 480 Mbps
550 MHz, 3 dB bandwidth
Low RON: 5.9 Ω typical
Excellent matching between channels
Low distortion section
Low RON: 3.9 Ω typical
230 MHz, 3 dB bandwidth (SPDT)
160 MHz, 3 dB bandwidth (4:1 multiplexers)
Single-supply operation: 1.65 V to 3.6 V
Typical power consumption: <0.1 μW
Pb-free packaging: 30-ball WLCSP (3 mm × 2.5 mm)
WIDE
BANDWIDTH
SECTION
LOW
DISTORTION
SECTION
S5A
S5B
S5C
S5D
D5
S1A
S1B
D1
S6A
S2A
S2B
D2
S6B
S6C
S6D
D6
S3A
S3B
D3
S4A
S4B
D4
APPLICATIONS
DECODER
Cellular phones
PMPs
MP3 players
V
IN1 IN2 IN3 S/D GND
DD
Audio/video/data/USB switching
Figure 1.
GENERAL DESCRIPTION
The ADG790 is a single-chip, CMOS switching solution that
comprises four SPDT switches and two 4:1 multiplexers. The
internal architecture of the device provides two switching
sections, a wide bandwidth section and a low distortion section.
All switches conduct equally well in both directions when on
and block signals up to the supply rails when off. A 4-wire
parallel interface controls the operation of the device and
allows the user to control switches from both sections simul-
taneously. This simplifies the design and provides a cost-effective,
single-chip switching solution for portable devices where
multiple signals share a single port connector. The shutdown
(S/D) pin allows the user to disable all four SPDT switches and
force the 4:1 multiplexers into the S5B and S6B positions,
respectively.
The wide bandwidth section contains three SPDT switches that
exhibit low on resistance with excellent flatness and channel
matching. This, combined with wide bandwidth, makes the
three-SPDT-switch configuration ideal for high frequency
signals, such as full speed (12 Mbps) and high speed (480 Mbps)
USB signals and high resolution video signals.
The ADG790 is packaged in a compact, 30-ball WLCSP (6 × 5
ball array) with a total area of 7.5 mm2 (3 mm × 2.5 mm). This
tiny package size and its low power consumption make the
ADG790 an ideal solution for portable devices.
The low distortion section contains a single SPDT switch and
two 4:1 multiplexers that exhibit very low on resistance and
excellent flatness, making these switches ideal for a wide range
of applications, including low distortion audio applications and
low resolution video (CVBS and S-Video) applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADG790
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 11
Theory of Operation ...................................................................... 13
Wide Bandwidth Section........................................................... 13
Low Distortion Section.............................................................. 13
Control Interface ........................................................................ 13
Evaluation Board ............................................................................ 14
Using the ADG790 Evaluation Board ..................................... 14
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Terminology ...................................................................................... 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG790
SPECIFICATIONS
VDD = 2.7 V to 3.6 V, GND = 0 V, TA = –40°C to +85°C, all switch sections unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance
Symbol
RON
Test Conditions/Comments
Min Typ1
Max Unit
0
VDD
V
VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA (see Figure 18)
Wide bandwidth section2
Low distortion section3
5.9
3.9
8.8
5.5
Ω
Ω
On Resistance Flatness
RFLAT(ON)
VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA (see Figure 18)
Wide bandwidth section2
Low distortion section3
2.0
0.74
3.6
1.6
Ω
Ω
On Resistance Matching
Between Channels4
∆RON
VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA
Wide bandwidth section2
0.52
0.1
0.3
Ω
Ω
Ω
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
LEAKAGE CURRENTS
Source Off Leakage
IS (OFF)
VDD = 3.6 V, VS = 0 V or 3.6 V, VD = 3.6 V or 0 V
(see Figure 19)
10
10
nA
nA
Channel On Leakage
DIGITAL INPUTS (IN1, IN2, IN3, S/D)
Input High Voltage
Input Low Voltage
ID, IS (ON)
VDD = 3.6 V, VS = VD = 0 V or 3.6 V (see Figure 20)
VINH
VINL
2.0
V
V
0.8
Input High/Input Low Current
Digital Input Capacitance
DYNAMIC CHARACTERISTICS5
tON
IINL, IINH
CIN
VIN = VINL or VINH
0.005
0.1 μA
pF
6
tON
tOFF
tD
RL = 50 Ω, CL = 35 pF, VS = VDD/2 or 0 V (see Figure 24)
RL = 50 Ω, CL = 35 pF, VS = VDD/2 or 0 V (see Figure 24)
RL = 50 Ω, CL = 35 pF
20
9
32
15
ns
ns
tOFF
Propagation Delay
Wide bandwidth section2
0.3
0.65
0.4
0.46 ns
0.95 ns
0.65 ns
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
Propagation Delay Skew
tSKEW
RL = 50 Ω, CL = 35 pF
Wide bandwidth section2
20
40
11
ps
ps
ns
Low distortion section3 (4:1 multiplexers)
RL = 50 Ω, CL = 35 pF, VS1 = VS2 = VDD/2 (see Figure 25)
VS = 0 V, RS = 0 Ω, CL = 1 nF (see Figure 26)
Wide bandwidth section2
Break-Before-Make Time Delay
Charge Injection
tBBM
QINJ
5
–0.57
6.2
–74
–77
pC
pC
dB
dB
Low distortion section3
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion
RL = 50 Ω, CL = 5 pF, f = 1 MHz (see Figure 21)
RL = 50 Ω, CL = 5 pF, f = 1 MHz (see Figure 22)
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p
Wide bandwidth section2
THD + N
1.2
0.65
%
%
Low distortion section3
–3 dB Bandwidth
RL = 50 Ω, CL = 5 pF (see Figure 23)
Wide bandwidth section2
550
230
160
MHz
MHz
MHz
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
Differential Gain Error
CCIR330 test signal
Wide bandwidth section2
0.07
0.08
0.18
%
%
%
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
Rev. 0 | Page 3 of 20
ADG790
Parameter
Symbol
Test Conditions/Comments
CCIR330 test signal
Min Typ1
Max Unit
Degrees
Differential Phase Error
Wide bandwidth section2
0.13
0.08
0.19
–90
3.5
11
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
f= 10 kHz, no decoupling capacitors
Wide bandwidth section2
Degrees
Degrees
dB
pF
pF
Power Supply Rejection Ratio
Source Off Capacitance
PSRR
CS (OFF)
Low distortion section3
Drain Off Capacitance
CD (OFF)
Wide bandwidth section2
5.5
14
pF
pF
Low distortion section3 (SPDT)
Source/Drain On Capacitance
CD, CS (ON) Wide bandwidth section2
Low distortion section3 (SPDT)
8.5
19
32
pF
pF
pF
Low distortion section3 (4:1 multiplexers)
POWER REQUIREMENTS
Supply Voltage
Supply Current
VDD
IDD
1.65
0.1
3.6
1
V
μA
VDD = 3.6 V, digital inputs tied to 0 V or 3.6 V
1 All typical values are at TA = 25°C, VDD = 3.3 V.
2 Refers to all switches connected to Pin D1, Pin D2, and Pin D3.
3 Refers to all switches connected to Pin D4 (SPDT), Pin D5, and Pin D6 (4:1 multiplexers).
4 Refers to the on resistance matching between the same channels (SxA and SxB, for example) from different multiplexers for the wide bandwidth section and the 4:1
multiplexers from the low distortion section. For the SPDT switch from the low distortion section, it refers to the matching between the S4A and S4B channels.
5 Guaranteed by design; not subject to production test.
Rev. 0 | Page 4 of 20
ADG790
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Rating
VDD to GND
Analog and Digital Pins1
–0.3 V to +4.6 V
–0.3 V to VDD + 0.3 V or 10 mA,
whichever occurs first
100 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Peak Current, S or D
Continuous Current, S or D
Operating Temperature Range
Storage Temperature Range
Junction Temperature
30 mA
Only one absolute maximum rating can be applied at any one time.
–40°C to +85°C
–65°C to +125°C
150°C
ESD CAUTION
Thermal Impedance (θJA)2
Reflow Soldering (Pb Free)
Peak Temperature
80°C/W
260°C (+0°C/–5°C)
Time at Peak Temperature
As per JEDEC J-STD-20
1 Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to
the maximum ratings given.
2 Measured with the device soldered on a 4-layer board.
Rev. 0 | Page 5 of 20
ADG790
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
1
2
3
4
5
A
B
C
D
E
F
S1A S5A
D1 S5B
D5
S5C S4A
IN1
S5D
D4
S1B GND IN2
V
S4B
DD
S2B GND IN3 GND S3B
D2 S6B S/D S6D D3
S2A S6A S6C S3A
D6
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 2. 30-Ball WLCSP (CB-30-1)
Table 3. Pin Function Descriptions
Ball Name
A1
A2
A3
A4
A5
B1
Mnemonic
S1A
S5A
D5
S5C
S4A
D1
Description
Source Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 4 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Logic Control Input.
B2
B3
S5B
IN1
B4
B5
S5D
D4
S1B
GND
IN2
Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 4 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Most Positive Power Supply Terminal.
Source Terminal for Mux 4 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Ground (0 V) Reference.
Source Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output.
Drain Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Shutdown Logic Control Input.
Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output.
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
F1
F2
F3
F4
VDD
S4B
S2B
GND
IN3
GND
S3B
D2
S6B
S/D
S6D
D3
S2A
S6A
D6
S6C
S3A
F5
Rev. 0 | Page 6 of 20
ADG790
TERMINOLOGY
IDD
tD
Positive supply current.
Signal propagation delay through the switch measured
between the 50% points of the input signal and its corre-
sponding output signal.
VD (VS)
Analog voltage on Terminal D and Terminal S.
tSKEW
RON
Difference in propagation delay between the selected inputs on
the 4:1 multiplexers or any two SPDT switches from the wide
bandwidth section.
Ohmic resistance between Terminal D and Terminal S.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during on-off switching.
ΔRON
On resistance match between any two channels.
Off Isolation
IS (OFF)
A measure of unwanted signal coupling through an off switch.
Source leakage current with the switch off.
Crosstalk
ID, IS (ON)
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Channel leakage current with the switch on.
−3 dB Bandwidth
VINL
The frequency at which the output is attenuated by 3 dB.
Insertion Loss
Maximum input voltage for Logic 0.
VINH
The loss due to the on resistance of the switch.
THD + N
Minimum input voltage for Logic 1.
I
INL (IINH)
The ratio of the harmonic amplitudes plus signal noise to the
fundamental.
Input current of the digital input.
CS (OFF)
Differential Gain Error
Off switch source capacitance. Measured with reference
to ground.
The measure of how much color saturation shift occurs when
the luminance level changes. Both attenuation and amplification
can occur; therefore, the largest amplitude change between any
two levels is specified and expressed in percent.
CD, CS (ON)
On switch capacitance. Measured with reference to ground.
CIN
Differential Phase Error
Digital input capacitance.
The measure of how much hue shift occurs when the luminance
level changes. It can be a negative or a positive value and is
expressed in degrees of subcarrier phase.
tON
Delay time between the 50% and the 90% points of the digital
input and switch on condition.
tOFF
Delay time between the 50% and the 10% points of the digital
input and switch off condition.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to the other.
Rev. 0 | Page 7 of 20
ADG790
TYPICAL PERFORMANCE CHARACTERISTICS
7.5
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
T
I
= 25°C
A
V
= 3.3V
= 10mA
DD
= 10mA
DS
I
DS
7.0
6.5
6.0
5.5
5.0
4.5
4.0
V
= 2.7V
DD
T
= +85°C
A
V
= 3.3V
DD
T
= +25°C
2.5
A
V
= 3.6V
DD
T
= –40°C
1.0
A
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
0
0.5
1.5
2.0
3.0
V
V (V)
S
S
Figure 3. On Resistance vs. Source Voltage,
Wide Bandwidth Section
Figure 6. On Resistance vs. Temperature,
Low Distortion Section
6.5
6.0
5.5
5.0
4.5
4.0
V
= 3.3V
= 10mA
DD
20
18
16
14
12
10
8
I
DS
tOFF
T
= +85°C
A
tON
V
T
R
C
= 3.3V
DD
T
= +25°C
1.0
= 25°C
= 50ꢀ
= 35pF
A
A
6
T
= –40°C
2.5
L
L
A
4
–40
0
0.5
1.5
2.0
3.0
–20
0
20
40
60
80
V
(V)
S
TEMPERATURE (°C)
Figure 4. On Resistance vs. Temperature,
Wide Bandwidth Section
Figure 7. tON/tOFF Times vs. Temperature
T
I
= 25°C
= 10mA
A
–1
V
= 2.7V
DS
4.5
4.0
3.5
3.0
2.5
DD
V
= 3.3V
= 25°C
DD
–3
–5
T
A
WIDE BANDWIDTH SECTION
LOW DISTORTION SECTION
–7
–9
V
= 3.3V
DD
–11
–13
–15
V
= 3.6V
DD
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
0.01
0.1
1
10
100
1000
V
S
FREQUENCY (MHz)
Figure 5. On Resistance vs. Source Voltage,
Low Distortion Section
Figure 8. On Response vs. Frequency,
Low Distortion Section (SPDT)
Rev. 0 | Page 8 of 20
ADG790
0
–2
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
V
= 3.3V
= 25°C
DD
T
A
WIDE BANDWIDTH AND LOW
DISTORTION SECTIONS
V
= 3.3V
= 25°C
DD
–4
T
A
–6
–8
–10
–12
–14
–16
–18
–20
0.01
0.1
1
10
100
1000
0.0001
0.001
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Off Isolation vs. Frequency
Figure 9. On Response vs. Frequency,
Low Distortion Section (4:1 Multiplexers)
–20
–30
V
= 3.3V
= 25°C
DD
T
A
WIDE BANDWIDTH AND
LOW DISTORTION SECTIONS
INPUT SIGNAL = 0dBm
DC BIAS = 0.5V
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.0001
0.001
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
X = 20ns/DIV Y = 835mV/DIV
Figure 13. Crosstalk vs. Frequency
Figure 10. USB 1.1 Eye Diagram
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
WIDE BANDWIDTH SECTION
V
R
V
= 3.3V
= 32ꢀ
= 2V p-p
= 25°C
DD
L
S
A
T
DC BIAS = 1.65V
LOW DISTORTION SECTION
10
100
1000
10000
100000
FREQUENCY (Hz)
X = 250ps/DIV Y = 100mV/DIV
Figure 14. THD + N vs. Frequency
Figure 11. USB 2.0 Eye Diagram
Rev. 0 | Page 9 of 20
ADG790
500
450
400
350
300
250
200
150
100
50
0
–20
V
T
= 3.3V
= 25°C
V
T
= 3.3V
= 25°C
DD
DD
A
A
WIDE BANDWIDTH AND LOW
DISTORTION SECTIONS.
0dBm SIGNAL SUPERIMPOSED
ON SUPPLY VOLTAGE.
NO DECOUPLING CAPACITORS
USED.
–40
–60
–80
–100
–120
0
0
0.5
1.0
1.5
V
2.0
2.5
3.0
0.0001
0.001
0.01
0.1
1
10
100
1000
(V)
FREQUENCY (MHz)
IN
Figure 17. Power Supply Rejection Ratio vs. Frequency
Figure 15. Supply Current vs. Input Logic Level
8
7
6
5
4
LOW DISTORTION
SECTION
3
V
C
= 3.3V
= 1nF
= 25°C
DD
WIDE BANDWIDTH
SECTION
2
1
L
T
A
0
–1
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
S
Figure 16. Charge Injection vs. Source Voltage
Rev. 0 | Page 10 of 20
ADG790
TEST CIRCUITS
V
V
DD
I
0.1µF
DS
NETWORK
ANALYZER
V1
DD
SxA
V
OUT
S
D
R
L
50ꢀ
Dx
SxB
R
L
50ꢀ
V
R
= V1/I
DS
S
ON
50ꢀ
V
S
GND
Figure 18. On Resistance
V
OUT
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
I
(OFF)
A
I
(OFF)
A
S
D
Figure 22. Channel-to-Channel Crosstalk
S
D
V
DD
V
V
D
S
0.1µF
NETWORK
ANALYZER
V
DD
Figure 19. Off Leakage
50ꢀ
SxB
SxA
Dx
V
S
I
(ON)
A
V
D
OUT
R
L
S
D
NC
50ꢀ
GND
V
D
NC = NO CONNECT
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 20. On Leakage
Figure 23. –3 dB Bandwidth
V
V
DD
DD
0.1µF
NETWORK
ANALYZER
50ꢀ
SxB
SxA
50ꢀ
NC
V
S
Dx
V
OUT
R
L
50ꢀ
GND
V
OUT
OFF ISOLATION = 20 log
NC = NO CONNECT
V
S
Figure 21. Off Isolation
Rev. 0 | Page 11 of 20
ADG790
V
V
DD
DD
0.1µF
V
IN
50%
50%
SxA
SxB
V
OUT
Dx
V
S
90%
R
50ꢀ
C
L
L
10%
35pF
INx
V
OUT
tOFF
tON
GND
Figure 24. Switching Times (tON, tOFF
)
V
DD
0.1µF
V
DD
V
IN
50%
50%
SxA
SxB
V
L
OUT
Dx
0V
V
S
80%
80%
R
50ꢀ
C
L
V
V
S
35pF
OUT
INx
tBBM
tBBM
GND
Figure 25. Break-Before-Make Time Delay (tBBM
)
V
DD
0.1µF
V
DD
SxB TO Dx ON
SxA
SxB
V
IN
NC
Dx
SxB TO Dx OFF
V
OUT
C
V
L
S
V
ΔV
OUT
INx
OUT
1nF
Q
= C × ΔV
L OUT
INJ
GND
NC = NO CONNECT
Figure 26. Charge Injection
Rev. 0 | Page 12 of 20
ADG790
THEORY OF OPERATION
resistance and flatness while maintaining a wide bandwidth that
makes them suitable for a wide range of applications, including
low distortion audio and standard definition video signals. The
channels from the 4:1 multiplexers are matched to provide
optimal performance when used with differential signals such
as S-Video.
The ADG790 is a single-chip, CMOS switching solution that
comprises four SPDT switches and two 4:1 multiplexers. The
internal architecture used by the device groups the switches into
two sections, each optimized to provide the best performance in
terms of bandwidth and distortion. The on-chip parallel
interface controls the operation of all switches, allowing the
user to control switches from both sections simultaneously.
CONTROL INTERFACE
The operation of the ADG790 is controlled via a 4-wire parallel
interface. The logic levels applied to the IN1, IN2, and IN3 pins
control the operation of the switches from both the wide band-
width and low distortion sections, as shown in Table 4. The
shutdown pin (S/D) allows the user to disable all four SPDT
switches and force the 4:1 multiplexers into the S5B and S6B
positions, respectively. This function can be used to set up a low
speed communication protocol between the circuitry from both
sides of the device, which allows automatic configuration of the
switching function.
WIDE BANDWIDTH SECTION
The wide bandwidth section contains three SPDT switches
S1A/S1B-D1, S2A/S2B-D2, and S3A/S3B-D3. These switches
use a CMOS topology that ensures, besides low on resistance
and excellent flatness, the ability to switch signals up to the
supply rails. This, combined with the low switch capacitance,
provides the wide bandwidth required when switching high
frequency signals. The three SPDT switches are also optimized
to provide low propagation delay and excellent matching
between the channels, making the ADG790 ideal for applica-
tions that use multiple signals, such as universal USB switches
(full and high speed), or RGB video signals, such as VGA.
For example, in modern handset applications, where a single
connector is used as a multifunction communication port, the
S5B-D5 and S6B-D6 configuration obtained by setting the S/D
pin high can be used to detect the type of peripheral device
connected to the handset. The ADG790 then automatically routes
the required signals to the communication port connector.
LOW DISTORTION SECTION
The low distortion section contains a single SPDT switch
(S4A/S4B-D4) and two 4:1 multiplexers (S5A/S5B/S5C/S5D-D5
and S6A/S6B/S6C/S6D-D6, respectively). The switches from
this section also use a CMOS topology that exhibits very low on
Table 4. Truth Table
Logic Control Inputs
Switch Status
S1A-D1
S2A-D2
S3A-D3
S5D-D5
S6D-D6
S1B-D1
S2B-D2
S3B-D3
S5A-D5
S6A-D6
S5B-D5
S6B-D6
S5C-D5
S6C-D6
S/D
1
0
0
0
0
0
0
0
IN1
X1
0
0
0
0
1
1
1
IN2
X1
0
0
1
1
0
0
1
IN3
X1
0
1
0
1
0
1
0
S4A-D4
Off
Off
On
On
On
On
Off
Off
S4B-D4
Off
On
Off
Off
Off
Off
On
On
Off
Off
On
Off
Off
Off
On
Off
Off
Off
On
Off
On
On
On
Off
On
On
Off
Off
Off
Off
Off
On
Off
On
Off
On
Off
Off
On
Off
Off
Off
Off
On
Off
On
Off
Off
On
Off
Off
Off
Off
0
1
1
1
Off
On
1 X = logic state doesn’t matter.
Rev. 0 | Page 13 of 20
ADG790
EVALUATION BOARD
The ADG790 evaluation board allows designers to evaluate the
high performance of the device with a minimum of effort.
USING THE ADG790 EVALUATION BOARD
The ADG790 evaluation board is a test system designed to
simplify the evaluation of the device. Each input/output of the
part comes with a standardized socket to allow connection to
and from USB, CVBS, S-Video, and VGA signal sources. A data
sheet for the ADG790 evaluation board is also available with
full information on setup and operation.
The EVAL-ADG790 includes a printed circuit board populated
with the ADG790; it can be used to evaluate the performance of
the device. It interfaces to the USB port of a PC, allowing the user
to easily program the ADG790 through the USB port using the
software provided with the board. Schematics of the evaluation
board are shown in Figure 27 and Figure 28. The software runs
on any PC that has Microsoft® Windows® 2000 or Windows®
XP installed.
Rev. 0 | Page 14 of 20
ADG790
1 0 3 7 - 3 5 0 6
5 6
5 3
4 1
2 8
2 6
1 2
1 0
5 5
4 3
3 2
2 7
1 7
1 1
7
D
G N
C
V C
Figure 27. EVAL-ADG790 Schematic
USB Controller Section
Rev. 0 | Page 15 of 20
ADG790
4
0 1 7 - 3 5 0 6
D D
C 4
D 4
D 2
C 2
V
D
G N
D
D
G N
G N
Figure 28. EVAL-ADG790 Schematic
Switch Section
Rev. 0 | Page 16 of 20
ADG790
OUTLINE DIMENSIONS
0.65
0.59
0.53
2.56
2.50
2.44
SEATING
PLANE
5
4
3
2
1
A
B
C
D
E
F
BALL A1
CORNER
0.36
0.32
0.28
3.06
3.00
2.94
0.50
BALL PITCH
TOP VIEW
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
0.28
0.24
0.20
Figure 29. 30-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-30-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG790BCBZ-REEL1
EVAL-ADG790EBZ1
–40°C to +85°C
30-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
CB-30-1
1 Z = Pb-free part.
Rev. 0 | Page 17 of 20
ADG790
NOTES
Rev. 0 | Page 18 of 20
ADG790
NOTES
Rev. 0 | Page 19 of 20
ADG790
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06357-0-1/07(0)
Rev. 0 | Page 20 of 20
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