ADG798HFRZ [ADI]
High Temperature, Low Voltage 8-Channel Multiplexer;
| 型号： | ADG798HFRZ |
| 厂家： | 
ADI |
| 描述： | High Temperature, Low Voltage 8-Channel Multiplexer |
| 文件： | 总22页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Temperature, Low Voltage
8-Channel Multiplexer
ADG798
Data Sheet
FEATURES
Extreme high temperature operation
Specified temperature range
−55°C to +210°C (16-lead FLATPACK)
−55°C to +175°C (16-lead TSSOP)
3.0 V to 5.5 V single supply
2.5 V dual supply
FUNCTIONAL BLOCK DIAGRAM
ADG798
S1
D
10 Ω on resistance, maximum
2 Ω on-resistance flatness, maximum
12 ns switching times
S8
Single 8:1 multiplexer
Low power consumption
1 OF 8
DECODER
TTL-/CMOS-compatible inputs
APPLICATIONS
A0 A1
A2 EN
Downhole drilling and instrumentation
Avionics
Figure 1.
Heavy industrial
High temperature environments
GENERAL DESCRIPTION
packages have an operating temperature range of −55°C to +210°C.
A 16-lead TSSOP package is also available that has an operating
temperature range of −55°C to +175°C. All packages are designed
for robustness at extreme temperatures, and are qualified for
1000 hours of continuous operation at the maximum temperature
rating.
The ADG798 is a low voltage, CMOS, analog multiplexer
designed to operate at very high temperatures up to 210°C. The
ADG798 switches one of eight inputs (S1 to S8) to a common
output, D, as determined by the 3-bit binary address lines A0,
A1, and A2. An EN input on the device enables or disables the
device. When the device is disabled, all channels are switched off.
The ADG798 is a member of a growing series of high temperature
qualified products offered by Analog Devices, Inc. For a complete
selection table of available high temperature products, see the
high temperature product list and qualification data available at
http://www.analog.com/hightemp.
The ADG798 features low power consumption and a 3.3 V to
5.5 V operating supply range. All channels exhibit break-before-
make switching action, preventing momentary shorting when
switching channels. These switches are designed with an enhanced
submicron process that provides low power dissipation, high
switching speed, and very low on resistance.
PRODUCT HIGHLIGHTS
1. Single-Supply/Dual-Supply Operation.
The on resistance (RON) is a maximum of 10 Ω and is closely
matched between switches and very flat over the full signal range.
The ADG798 operates equally well as either a multiplexer or a
demultiplexer and has an input signal range that extends to
the supplies.
The ADG798 is fully specified and guaranteed with 3.3 V
and 5 V single-supply rails and 2.5 V dual-supply rails.
2. Low RON
.
The RON of the ADG798 is specified at 5 Ω, typical, at 210°C.
3. Low Power Consumption.
The power consumption of the ADG798 is specified at
<0.01 μW.
4. Guaranteed Break-Before-Make Switching Action.
This mux is available in a 16-lead ceramic flat package
(FLATPACK) and a 16-lead ceramic flat package with reverse
formed gullwing leads (FLATPACK_RF). Both of the flat
Rev. A
Document Feedback
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responsibility is assumed byAnalog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2016–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADG798
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions........................... 10
Truth Table .................................................................................. 10
Typical Performance Characteristics ........................................... 11
Test Circuits..................................................................................... 15
Terminology.................................................................................... 18
Theory of Operation ...................................................................... 19
Applications Information.............................................................. 20
Power Supply Sequencing ......................................................... 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply................................................................................... 7
Continuous Current per Channel, Sx or D............................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
REVISION HISTORY
6/2018—Rev. 0 to Rev. A
Added TSSOP Package ......................................................Universal
Changes to Features.......................................................................... 1
Changes to General Description .................................................... 1
Changes to Specifications, Table 1.................................................. 3
Changes to Specifications, Table 2.................................................. 5
Changes to Specifications, Table 3.................................................. 7
Changes to Specifications, Table 4.................................................. 8
Added TSSOP Operating Temperature Range and Junction
Temperature Range, Table 5............................................................ 9
Added RU-16 Thermal Characteristics, Table 6........................... 9
Changes to Figure 2 Caption......................................................... 10
9/2016—Revision 0: Initial Version
Rev. A | Page 2 of 22
Data Sheet
ADG798
SPECIFICATIONS
VDD = 5 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. TSSOP temperature range = −55°C ≤ TA ≤ +175°C and FLATPACK
temperature range = −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 1.
TSSOP
Typ 2
FLATPACK
Typ2
Parameter
Symbol Test Conditions/Comments1
Min
Max Min
Max
Unit
ANALOG SWITCH
Analog Signal Range
On Resistance
0
VDD
9
0
VDD
10
V
Ω
RON
VS = 0 V to VDD, IDS = 10 mA; see
Figure 24
VS = 0 V to VDD, IDS = 10 mA
4.5
0.6
5
Matching Between
Channels
Flatness
ΔRON
RFLAT (ON)
1.2
1.5
1.25
0.75
1.5
2
Ω
Ω
VS = 0 V to VDD, IDS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V; see
Figure 25
VD = 4.5 V/1 V, VS = 1 V/4.5 V; see
Figure 26
LEAKAGE CURRENTS
Source Off Leakage
IS (Off )
−50
0.01
0.01
0.01
+50
−180
0.01
0.01
0.01
+180
nA
Drain Off Leakage
ID (Off)
−650
+650 −2600
+650 −2600
+2600 nA
+2600 nA
Channel On Leakage
ID (On),
IS (On)
VD = VS = 1 V or 4.5 V; see Figure 27 −650
DIGITAL INPUTS
Input Voltage
High
VINH
VINL
2.4
2.4
0.8
V
V
Low
0.8
Input Current
IINL or
IINH
VIN = VINL or VINH
−800 +0.005 +800 −800
+0.005 +800
nA
Digital Input Capacitance
DYNAMIC CHARACTERISTICS3
Transition Time
CIN
2
2
pF
ns
tTRANSITION RL = 150 Ω, CL = 15 pF; see
Figure 28
12
8
21
12
8
23
VS1 = 3 V/0 V, VS8 = 0 V/3 V
RL = 150 Ω, CL = 15 pF, VS = 3 V;
see Figure 29
Break-Before-Make Time
Delay
tOPEN
1
1
ns
TA = maximum temperature
RL = 150 Ω, CL = 15 pF
VS = 3 V; see Figure 30
9
11
9
11
ns
ns
On Time
Off Time
tON (EN)
17
11
20
12
tOFF (EN) RL = 150 Ω, CL = 15 pF
VS = 3 V; see Figure 30
5.5
3
5.5
3
ns
Charge Injection
Off Isolation
QINJ
VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see
Figure 31
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 32
pC
−60
−80
−60
−80
dB
dB
Channel to Channel
Crosstalk
RL = 50 Ω, CL = 5 pF, f = 10 MHz
−60
−80
−60
−80
dB
dB
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 33
−3 dB Bandwidth
Source Capacitance, Off
RL = 50 Ω, CL = 5 pF; see Figure 34
f = 1 MHz
55
13
55
13
MHz
pF
CS (Off )
Rev. A | Page 3 of 22
ADG798
Data Sheet
TSSOP
Typ 2
85
FLATPACK
Parameter
Drain Capacitance, Off
Symbol Test Conditions/Comments1
CD (Off ) f = 1 MHz
Min
Max Min
Typ2
Max
Unit
pF
85
Source/Drain Capacitance,
On
CD (On), f = 1 MHz
CS (On)
96
96
pF
POWER REQUIREMENTS
Supply Current
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
IDD
5
35
40
70
μA
1 The ADG798 is qualified for a minimum of 1000 hours of continuous operation at the maximum temperature rating.
2 TA = 25°C, except for the analog switch and power requirements values where TA = 175°C (TSSOP only) or 210°C (FLATPACK only).
3 Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 22
Data Sheet
ADG798
VDD = 3.3 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. TSSOP temperature range = −55°C ≤ TA ≤ +175°C and FLATPACK
temperature range = −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 2.
TSSOP
Typ 2
FLATPACK
Typ2
Parameter
Symbol Test Conditions/Comments1
Min
Max Min
Max
Unit
ANALOG SWITCH
Analog Signal Range
On Resistance
0
VDD
15
0 V
VDD
20
V
Ω
RON
VS = 0 V to VDD, IDS = 10 mA; see
Figure 24
7
8
Matching Between
Channels
Flatness
ΔRON
RFLAT (ON)
VS = 0 V to VDD, IDS = 10 mA
0.4
2.5
1.2
3.5
0.5
3
1.5
4.5
Ω
Ω
VS = 0 V to VDD, IDS = 10 mA
VDD = 3.63 V
VD = 2.3 V/1 V, VS = 1 V/2.3 V; see
Figure 25
VD = 2.3 V/1 V, VS = 1 V/2.3 V; see
Figure 26
VD = VS = 1 V or 2.3 V; see
Figure 27
LEAKAGE CURRENTS
Source Off Leakage
IS (Off )
−50
0.01
0.01
0.01
+50
−180
0.01
0.01
0.01
+180
nA
Drain Off Leakage
ID (Off)
−650
−650
+650 −2600
+650 −2600
+2600 nA
+2600 nA
Channel On Leakage
ID (On),
IS (On)
DIGITAL INPUTS
Input Voltage
High
VINH
VINL
2.4
2.0
0.8
V
V
Low
0.8
Input Current
IINL or
IINH
VIN = VINL or VINH
−800 +0.005 +800 −800
+0.005 +800
nA
Digital Input Capacitance
DYNAMIC CHARACTERISTICS3
Transition Time
CIN
2
2
pF
ns
tTRANSITION RL = 150 Ω, CL = 15 pF; see
Figure 28
18
10
34
18
10
38
VS1 = 2 V/0 V, VS8 = 0 V/2 V
RL = 150 Ω, CL = 15 pF, VS = 2 V;
see Figure 29
Break-Before-Make Time
Delay
tOPEN
1
1
ns
TA = maximum temperature
RL = 150 Ω, CL = 15 pF
VS = 2 V; see Figure 30
15
14
15
14
ns
ns
On Time
Off Time
tON (EN)
26
16
28
17
tOFF (EN) RL = 150 Ω, CL = 15 pF
VS = 2 V; see Figure 30
8.5
3
8.5
3
ns
Charge Injection
Off Isolation
QINJ
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see
Figure 31
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
pC
−60
−80
−60
−80
dB
dB
Channel to Channel
Crosstalk
RL = 50 Ω, CL = 5 pF, f = 10 MHz
−60
−80
−60
−80
dB
dB
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 33
−3 dB Bandwidth
Source Capacitance, Off
Drain Capacitance, Off
Source/Drain Capacitance,
On
RL = 50 Ω, CL = 5 pF; see Figure 34
55
13
85
96
55
13
85
96
MHz
pF
pF
CS (Off )
CD (Off )
CD (On),
CS (On)
f = 1 MHz
f = 1 MHz
f = 1 MHz
pF
Rev. A | Page 5 of 22
ADG798
Data Sheet
TSSOP
Typ 2
FLATPACK
Typ2
Parameter
Symbol Test Conditions/Comments1
Min
Max Min
Max
Unit
POWER REQUIREMENTS
Supply Current
VDD = 3.63 V
Digital inputs = 0 V or 3.63 V
IDD
5
35
40
70
μA
1 The ADG798 is qualified for a minimum of 1000 hours of continuous operation at the maximum temperature rating.
2 TA = 25°C, except for the analog switch and power requirements values where TA = 175°C (TSSOP only) or 210°C (FLATPACK only).
3 Guaranteed by design, not subject to production test.
Rev. A | Page 6 of 22
Data Sheet
ADG798
DUAL SUPPLY
VDD = 2.5 V 10%, VSS = −2.5 V 10%, GND = 0 V, unless otherwise noted. TSSOP temperature range = −55°C ≤ TA ≤ +175°C and
FLATPACK temperature range = −55°C ≤ TA ≤ +210°C, unless otherwise noted.
Table 3.
TSSOP
Typ 2
FLATPACK
Typ2
Parameter
Symbol
Test Conditions/Comments1
Min
Max Min
Max
Unit
ANALOG SWITCH
Analog Signal Range
On Resistance
0
VDD
9
VSS
VDD
10
V
Ω
RON
VS = VSS to VDD, IDS = 10 mA;
see Figure 24
VS = VSS to VDD, IDS = 10 mA
4.5
0.6
5
Matching Between
Channels
Flatness
ΔRON
RFLAT (ON)
1.2
1.5
1.25
0.6
1.5
2
Ω
Ω
VS = VSS to VDD, IDS = 10 mA
VDD = +2.75 V, VS = −2.75 V
VS = +2.25 V/−1.25 V, VD =
−1.25 V/+2.25 V; see Figure 25
VS = +2.25 V/−1.25 V, VD =
−1.25 V/+2.25 V; see Figure 26
VD = VS = −1.25 V/+2.25 V; see
Figure 27
LEAKAGE CURRENTS
Source Off Leakage
IS (Off )
−50
0.01
0.01
0.01
+50
−180
0.01
0.01
0.01
+180
nA
Drain Off Leakage
ID (Off)
−650
−650
+650 −2600
+650 −2600
+2600 nA
+2600 nA
Channel On Leakage
ID (On),
IS (On)
DIGITAL INPUTS
Input Voltage
High
VINH
VINL
2.4
2.0
0.8
V
V
Low
0.8
Input Current
Digital Input Capacitance
DYNAMIC CHARACTERISTICS3
Transition Time
IINL or IINH
CIN
VIN = VINL or VINH
−800 +0.005 +800 −800
2
+0.005 +800
2
nA
pF
tTRANSITION
RL = 150 Ω, CL = 15 pF; see
Figure 28
VS1 = 1.5 V/0 V, VS8 = 0 V/1.5 V
RL = 150 Ω, CL = 15 pF, VS = 2 V;
see Figure 29
18
10
28
14
10
30
ns
ns
Break-Before-Make Time
Delay
tOPEN
1
1
TA = maximum temperature
RL = 150 Ω, CL = 15 pF
VS = 2 V; see Figure 30
RL = 150 Ω, CL = 15 pF
VS = 2 V; see Figure 30
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 10 MHz
13
19
13
19
ns
ns
On Time
Off Time
tON (EN)
tOFF (EN)
QINJ
28
19
30
20
11.5
3
11.5
3
ns
Charge Injection
Off Isolation
pC
−60
−80
−60
−80
dB
dB
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 32
Channel to Channel
Crosstalk
RL = 50 Ω, CL = 5 pF, f = 10 MHz
−60
−80
55
−60
−80
55
dB
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 33
RL = 50 Ω, CL = 5 pF; see
Figure 34
dB
−3 dB Bandwidth
MHz
pF
Source Capacitance, Off
CS (Off )
f = 1 MHz
13
13
Rev. A | Page 7 of 22
ADG798
Data Sheet
TSSOP
Typ 2
85
FLATPACK
Parameter
Drain Capacitance, Off
Symbol
CD (Off )
Test Conditions/Comments1
f = 1 MHz
Min
Max Min
Typ2
Max
Unit
pF
85
Source/Drain Capacitance, CD (On), CS f = 1 MHz
96
96
pF
On
(On)
POWER REQUIREMENTS
Supply Current
VDD = 2.75 V
Digital inputs = 0 V or 2.75 V
VSS = −2.75 V; digital inputs = 0 V
or 2.75 V
IDD
ISS
5
5
35
35
40
40
70
70
μA
μA
1 The ADG798 is qualified for a minimum of 1000 hours of continuous operation at the maximum temperature rating.
2 TA = 25°C, except for the analog switch and power requirements values where TA = 175°C (TSSOP) or 210°C (FLATPACK).
3 Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR D
Table 4.
Parameter
175°C
210°C
Unit
CONTINUOUS CURRENT, Sx OR D
FLATPACK θJA = 70°C/W
VDD = 5 V, VSS = 0 V
30
30
30
30
30
30
mA maximum
mA maximum
mA maximum
VDD = 3 V, VSS = 0 V
VDD = +2.5 V, VSS = −2.5 V
TSSOP θJA = 109.6°C/W
VDD = 5 V, VSS = 0 V
VDD = 3 V, VSS = 0 V
VDD = +2.5 V, VSS = −2.5 V
30
30
30
mA maximum
mA maximum
mA maximum
Rev. A | Page 8 of 22
Data Sheet
ADG798
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 5.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Rating
7 V
−0.3 V to +7 V
+0.3 V to −3.5 V
VSS − 0.3 V to VDD + 0.3 V
or 30 mA, whichever
occurs first
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Digital Inputs1
−0.3 V to VDD + 0.3 V or
30 mA, whichever
occurs first
Thermal performance is directly linked to PCB design and
operating environment. Close attention to PCB thermal design
is required.
Peak Current, Sx or D (Pulsed at 1 ms,
10% Duty Cycle Maximum)
94.9 mA
Continuous Current, Sx or D2
Operating Temperature Range
TSSOP
FLATPACK
Junction Temperature
TSSOP
Data + 5%
Table 6. Thermal Resistance
Package Type1
F-16-1
θJA
70
70
109.6
θJC
22
10
Unit
°C/W
°C/W
°C/W
−55°C to +175°C
−55°C to +210°C
FR-16-1
RU-16
36.5
180°C
211°C
1 Thermal impedance simulated values are based on a JEDEC 2s2p thermal
test board. See JEDEC JESD51.
FLATPACK
1 Overvoltages at Ax, EN, Sx, or D are clamped by internal codes. Limit the
current to the maximum ratings given.
2 See Table 4.
ESD CAUTION
Rev. A | Page 9 of 22
ADG798
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
A0
EN
V
A1
A2
1
2
3
4
5
6
7
8
16 A1
15 A2
14
A0
EN
GND
SS
ADG798
V
V
S1
S2
S3
S4
D
GND
SS
S1
S2
S3
S4
D
DD
TOP VIEW
S5
S6
S7
S8
ADG798
TOP VIEW
(Not to Scale)
V
13
12
11
10
9
(Not to Scale)
DD
S5
S6
S7
S8
Figure 2. TSSOP and FLATPACK Pin Configuration
Figure 3. Reversed Formed FLATPACK Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
A0
EN
VSS
S1
Digital Input. This pin controls the configuration of the switch, as shown in the truth table (see Table 8).
Digital Input. This pin controls the configuration of the switch, as shown in the truth table (see Table 8).
Most Negative Power Supply Pin in Dual-Supply Applications. For single-supply applications, tie this pin to GND.
Source Terminal. This pin can be an input or output.
5
S2
Source Terminal. This pin can be an input or output.
6
S3
Source Terminal. This pin can be an input or output.
7
S4
Source Terminal. This pin can be an input or output.
8
D
Drain Terminal. This pin can be an input or output.
9
S8
Source Terminal. This pin can be an input or output.
10
11
12
13
14
15
16
S7
S6
S5
VDD
GND
A2
A1
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Source Terminal. This pin can be an input or output.
Most Positive Power Supply Pin.
Ground (0 V) Reference.
Digital Input. This pin controls the configuration of the switch, as shown in the truth table (see Table 8).
Digital Input. This pin controls the configuration of the switch, as shown in the truth table (see Table 8).
TRUTH TABLE
Table 8. Truth Table
A2
X1
0
A1
X1
0
A0
X1
0
EN
0
1
Switch Condition
None
S1
0
0
1
1
S2
0
1
0
1
S3
0
1
1
1
S4
1
0
0
1
S5
1
0
1
1
S6
1
1
0
1
S7
1
1
1
1
S8
1 X means don’t care.
Rev. A | Page 10 of 22
Data Sheet
ADG798
TYPICAL PERFORMANCE CHARACTERISTICS
8
7
6
5
4
3
2
1
0
V
V
= 3.3V
= 0V
T
= 25°C
DD
SS
A
V
= 0V
SS
7
6
5
V
= 2.7V
DD
V
= 3.3V
DD
4
3
2
1
0
V
= 4.5V
DD
V
= 5.5V
DD
–55°C
–40°C
+25°C
+85°C
+125°C
+175°C
+210°C
0
1
2
3
0
1
2
3
4
5
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
V , V (V)
D
S
S
D
Figure 4. On Resistance as a Function of VD (VS) for Single Supply
Figure 7. On Resistance as a Function of VS (VD) for Different Temperatures,
3.3 V Single Supply
8
5.0
V
V
= +2.5V
= –2.5V
DD
SS
T
= 25°C
A
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
7
6
5
4
3
2
1
0
V
V
= +2.25V
= –2.25V
DD
SS
–55°C
–40°C
+25°C
+85°C
+125°C
+175°C
+210°C
V
V
= +2.75V
= –2.75V
DD
SS
–2.5
–1.5
–0.5
0.5
1.5
2.5
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
V
OR V – DRAIN OR SOURCE VOLTAGE (V)
V , V (V)
D
S
S
D
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VS (VD) for Different Temperatures,
2.5 V Dual Supply
5.0
0.12
V
V
= +5V
= 0V
DD
SS
V
V
= 5V
= 0V
= 25°C
DD
SS
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
A
0.08
I
(ON)
D
0.04
0
I
(OFF)
S
–0.04
–0.08
–0.12
–55°C
–40°C
+25°C
+85°C
+125°C
+175°C
+210°C
I
(OFF)
D
0
1
2
3
4
5
0
1
2
3
4
5
V , V (V)
S
D
V
, (V = V – V ) (V)
D DD S
S
Figure 6. On Resistance as a Function of VS, VD for Different Temperatures,
5 V Single Supply
Figure 9. Leakage Current as a Function of VD (VS)
Rev. A | Page 11 of 22
ADG798
Data Sheet
0.12
1600
1400
1200
1000
800
600
400
200
0
V
V
= +2.5V
= –2.5V
DD
SS
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
D
D
V
V
= 3V
= 0V
= 25°C
S
D
S
D
S
S
DD
SS
T
A
0.08
I , I (ON) + +
I , I (ON) – –
I
(ON)
D
0.04
0
–0.04
–0.08
I
(OFF)
S
I
(OFF)
D
–0.12
0
–200
0
50
100
150
200
0.5
1.0
1.5
2.0
2.5
3.0
V
, (V = V – V ) (V)
D
S
DD
D
TEMPERATURE (°C)
Figure 13. Leakage Current as a Function of Temperature, VDD = +2.5 V,
VSS = −2.5 V
Figure 10. Leakage Current as a Function of VD (VS)
0.12
0.08
2000
V
V
= 5V
= 0V
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
D
D
DD
SS
V
V
= +2.5V
S
D
S
D
DD
SS
= –2.5V
1800
1400
1400
1200
1000
800
T
= 25°C
A
I , I (ON) + +
S
I , I (ON) – –
S
I
(ON), V = V
S D
0.04
D
0
–0.04
–0.08
600
I
(OFF)
S
I
(OFF)
D
400
200
0
–0.12
–200
0
50
100
150
200
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0
V
, (V = V – V ) (V)
TEMPERATURE (°C)
S
D
DD
S
Figure 11. Leakage Current as a Function of VD (VS)
Figure 14. Leakage Current vs. Temperature, VDD = 5 V
1600
1400
1200
1000
800
600
400
200
0
10m
1m
V
V
= 3.3V
= 0V
T
= 25°C
I
I
I
I
(OFF) + –
(OFF) + –
(OFF) – +
(OFF) – +
D
D
DD
SS
A
S
D
S
D
I , I (ON) + +
S
I , I (ON) – –
S
V
V
= +2.5V
= –2.5V
DD
SS
100µ
10µ
1µ
V
= +5V
DD
V
= +3V
DD
100n
10n
1n
–200
0
50
100
150
200
10
100
1k
10k
100k
1M
10M
INPUT SWITCHING FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 15. Supply Current vs. Input Switching Frequency
Figure 12. Leakage Current as a Function of Temperature, VDD = 3.3 V, VSS = 0 V
Rev. A | Page 12 of 22
Data Sheet
ADG798
0
40
30
V
= 5V
= 25°C
DD
T
A
–20
20
–40
10
–60
0
–80
–10
–20
–30
–100
+25°C
+175°C
+210°C
–120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
30k
100k
1M
10M
100M
FREQUENCY (Hz)
V
(V ) (V)
S
D
Figure 16. Off Isolation vs. Frequency
Figure 19. Charge Injection as a Function of VS (VD) for Various Temperatures,
5 V Single Supply
0
35
V
= 5V
+25°C
DD
= 25°C
+175°C
T
A
30
+210°C
–20
25
20
15
10
5
–40
–60
–80
0
–5
–10
–15
–100
–120
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
30k
100k
1M
10M
100M
FREQUENCY (Hz)
V
S
Figure 17. Crosstalk vs. Frequency
Figure 20. Charge Injection as a Function of VS (VD) for Various Temperatures,
3.3 V Single Supply
0
–5
40
30
20
10
0
V
= 5V
= 25°C
DD
T
A
–10
–15
–20
–10
–20
+25°C
+175°C
+210°C
–30
100k
1M
10M
100M
30k
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (Hz)
V
(V ) (V)
S
D
Figure 18. On Response vs. Frequency
Figure 21. Charge Injection as a Function of VS (VD) for Various Temperatures,
2.5 V Dual Supply
Rev. A | Page 13 of 22
ADG798
Data Sheet
20
14
13
12
11
10
9
V
V
V
= 5V, V = 0V
SS
T
= 25°C
DD
DD
DD
A
= 3V, V = 0V
SS
= +2.5V, V = –2.5V
SS
10
V
V
= +5V
= 0V
DD
SS
0
V
V
= +3V
= 0V
DD
SS
–10
–20
–30
V
V
= +2.5V
= –2.5V
DD
SS
8
7
–40
–3
6
–55 –35 –15
5
25 45 65 85 105 125 145 165 185 205
TEMPERATURE (°C)
–2
–1
0
1
2
3
4
5
SOURCE VOLTAGE (V)
Figure 23. Break-Before-Make Time vs. Temperature
Figure 22. Charge Injection (QINJ) vs. Source Voltage
Rev. A | Page 14 of 22
Data Sheet
ADG798
TEST CIRCUITS
I
DS
V
V
V
V
DD
SS
V1
DD
SS
S1
S2
I
(OFF)
A
D
Sx
D
D
S8
V
V
S
D
0.8V
EN
V
GND
S
R
= V1/I
ON
DS
Figure 24. On Resistance
Figure 26. ID (Off)
V
V
V
V
DD
SS
DD
SS
V
V
V
V
SS
DD
SS
DD
I (OFF)
S
S1
S2
S8
I
(ON)
A
A
D
S1
D
D
V
S
S8
V
D
V
S
0.8V
2.4V
EN
EN
V
GND
GND
D
Figure 25. IS (Off)
Figure 27. ID (On)
V
V
DD
SS
3V
0V
V
V
DD
SS
ADDRESS
DRIVE (V
50%
50%
)
IN
V
S1
A2
A1
A0
S1
V
S2 TO S7
IN
50Ω
S8
V
R
S8
V
ADG798
S1
90%
V
D
OUT
V
+0.1V
EN
INH
V
C
35pF
OUT
L
L
GND
300Ω
10%
V
S8
tTRANSITION
tTRANSITION
Figure 28. Switching Time of Multiplexer, tTRANSITION
V
V
V
3V
DD
SS
ADDRESS
V
DRIVE (V
)
DD
SS
IN
V
S1
S
A2
A1
A0
0V
V
S2 TO S7
IN
50Ω
ADG798
S8
D
90%
90%
V
OUT
V
+0.1V
EN
INH
V
OUT
C
35pF
R
300Ω
L
L
GND
tOPEN
Figure 29. Break-Before-Make Delay, tOPEN
Rev. A | Page 15 of 22
ADG798
Data Sheet
V
V
V
SS
3V
DD
ENABLE
50%
50%
V
DRIVE (V
)
DD
SS
IN
A2
A1
A0
V
S1
S2 TO S8
S
0V
tOFF (EN)
0.9V
V
OUT
ADG798
0.9V
OUT
OUT
V
OUTPUT
0V
EN
D
OUT
C
35pF
R
300Ω
GND
L
V
IN
L
50Ω
tON (EN)
Figure 30. Enable Delay, tON (EN), tOFF (EN)
V
V
V
3V
DD
SS
LOGIC INPUT
(V
)
IN
V
DD
SS
A2
A1
A0
0V
ADG798
R
S
D
Sx
V
V
C
1nF
ΔV
OUT
OUT
OUT
V
L
S
EN
Q
= C × ΔV
L OUT
INJ
V
GND
IN
Figure 31. Charge Injection
V
V
SS
DD
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
SS
DD
A2
A1
A0
50Ω
Sx
50Ω
V
S
D
V
OUT
2.4V
EN
R
L
50Ω
GND
V
OUT
OFF ISOLATION = 20 log
V
S
Figure 32. Off Isolation
V
V
SS
DD
0.1µF
0.1µF
V
V
SS
DD
A2
A1
A0
S1
EN
2.4V
NETWORK
ANALYZER
ADG798
50Ω
D
NETWORK
V
OUT
ANALYZER
R
50Ω
L
50Ω
S2
S8
GND
V
S
V
OUT
CHANNEL TO CHANNEL CROSSTALK = 20 log
V
S
Figure 33. Channel to Channel Crosstalk
Rev. A | Page 16 of 22
Data Sheet
ADG798
V
V
SS
DD
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
SS
DD
A2
A1
A0
Sx
50Ω
V
S
D
V
OUT
2.4V
EN
R
L
50Ω
GND
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 34. −3 dB Bandwidth
Rev. A | Page 17 of 22
ADG798
Data Sheet
TERMINOLOGY
VDD
tTRANSITION
V
DD is the most positive power supply potential.
tTRANSITION is the delay time measured between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
VSS
V
SS is the most negative power supply in a dual-supply application.
In single-supply applications, tie VSS to ground at the device.
tON (EN)
tON (EN) is the delay time between the 50% and 90% points of
the EN digital input and the switch on condition.
GND
GND is the ground (0 V) reference.
t
OFF (EN)
Sx
tOFF (EN) is the delay time between the 50% and 90% points of
Sx are the source terminals and can be inputs or outputs.
the EN digital input and the switch off condition.
D
tOPEN
D is the drain terminal and can be an input or an output.
tOPEN is the off time measured between the 80% points of both
switches when switching from one address state to another.
Ax
Ax is the logic control input.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
EN
EN is the active high enable.
Channel to Channel Crosstalk
RON
Channel to channel crosstalk is a measure of unwanted signal
that is coupled through from one channel to another as a result
of parasitic capacitance.
R
ON is the ohmic resistance between D and Sx.
RFLAT (ON)
RFLAT (ON) flatness is the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from injection of the digital input to the analog output during
switching.
IS (Off)
IS (Off) is the source leakage current with the switch off.
−3 dB Bandwidth
−3 dB bandwidth is the frequency at which the output is
attenuated by 3 dB.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID, IS (On)
On Response
ID, IS (On) is the channel leakage current with the switch on.
On response is the frequency response of the on switch.
VD (VS)
On Loss
VD (VS) is the analog voltage on Terminal D and Terminal Sx.
On loss is the loss due to the on resistance of the switch.
CS (Off)
VINL
CS (Off) is the off switch source capacitance and is measured with
reference to ground.
V
INL is the maximum input voltage for Logic 0.
VINH
CD (Off)
V
INH is the minimum input voltage for Logic 1.
CD (Off) is the off switch drain capacitance and is measured with
reference to ground.
IINL (IINH
)
I
INL (IINH) is the input current of the digital input.
CD, CS (On)
IDD
CD, CS (On) is the on switch capacitance and is measured with
reference to ground.
I
DD is the positive supply current.
ISS
CIN
I
SS is the negative supply current.
C
IN is the digital input capacitance.
Rev. A | Page 18 of 22
Data Sheet
ADG798
THEORY OF OPERATION
makes this device ideal for applications where the error due to
on resistance is key. The ADG798 also exhibits extremely fast
switching times and extremely low power consumption, making
the device useful in applications where there is a tight power
budget. The ADG798 is compatible with single-supply systems
that have a VDD range from 5.5 V to 3.3 V and dual-supply
systems at 2.5 V.
The ADG798 is a bidirectional, 8:1 CMOS multiplexer designed
for very high temperature operation. The device is controlled by
four parallel digital inputs (EN, A0, A1, and A2). The EN input
allows the ADG798 to be enabled or disabled. When the
ADG798 is disabled, the source pins (S1 to S8) disconnect from
the drain pin (D). When the ADG798 is enabled, the address
lines (A0, A1, and A2) can determine which source pin (S1 to
S8) is connected to the drain pin (D).
The ADG798 operates in a wide ambient temperature range
from −55°C to +210°C (FLATPACK) or −55°C to +175°C
(TSSOP), making the ADG798 perfect for use in harsh
environments that subject the device to extreme temperature
ranges, such as downhole drilling and avionics.
The low on resistance and on-resistance flatness of this device
means that there is minimal signal distortion across the entire
signal range of the device. This minimal signal distortion,
combined with the close on-resistance match between channels,
Rev. A | Page 19 of 22
ADG798
Data Sheet
APPLICATIONS INFORMATION
Always apply digital and analog inputs after power supplies and
ground. For single-supply operation, tie VSS to GND as close to
the device as possible.
POWER SUPPLY SEQUENCING
When using CMOS devices, take care to ensure correct power
supply sequencing. Incorrect power supply sequencing may
subject the device to stresses beyond the absolute maximum
ratings listed in Table 5.
Rev. A | Page 20 of 22
Data Sheet
ADG798
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
25.65
25.40
25.15
7.01
6.86
6.71
8.89 MIN
5.23
5.08
4.93
1.34
1.27
1.20
1
16
10.36
10.16
9.96
7.40
7.24
7.09
1.02
MIN
8
9
0.48
0.43
0.38
0.89
BSC
TOP VIEW
END VIEW
BOTTOM VIEW
0.70 REF
R 0.32
BSC
2.32
2.11
1.90
0.152
0.127
0.102
0.20 MIN
SIDE VIEW
0.66 MIN
Figure 36. 16-Lead Ceramic Flat Package [FLATPACK]
(F-16-1)
Dimensions shown in millimeters
Rev. A | Page 21 of 22
ADG798
Data Sheet
10.36
10.16
9.96
7.40
7.24
7.09
8
1
5.23
5.08
4.93
7.01
6.86
6.71
12.446
REF
16
9
BOTTOM VIEW
4.978
4.826
4.673
2.32
2.11
1.90
0.66 MIN
1.524
1.397
1.270
SIDE VIEW
3.02
2.74
2.46
0.254
0.203
0.152
0.432
0.381
0.330
END VIEW
0.152
0.127
0.102
0.254
0.203
0.152
1.524
1.397
1.270
0.48
0.43
0.38
SEATING
PLANE
1.34
1.27
1.20
Figure 37. 16-Lead Ceramic Flat Package with Reverse Formed Gullwing Leads [FLATPACK_RF] Cavity Down
(FR-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG798HRUZ
ADG798HFZ
ADG798HFRZ
EVAL-ADG798EB1Z
Temperature Range
−55°C to +175°C
−55°C to +210°C
−55°C to +210°C
Package Description
Package Option
RU-16
F-16-1
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Ceramic Flat Package [FLATPACK]
16-Lead Ceramic Flat Package [FLATPACK_RF]
Evaluation Board
FR-16-1
1 Z = RoHS Compliant Part.
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14880-0-6/18(A)
Rev. A | Page 22 of 22
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