ADG802BRT-REEL [ADI]
1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO6, MO-178AB, SOT-23, 6 PIN;
| 型号： | ADG802BRT-REEL |
| 厂家： | 
ADI |
| 描述： | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO6, MO-178AB, SOT-23, 6 PIN 开关 |
| 文件： | 总9页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
<0.5 Ω
a
CMOS, Low Voltage, SPST Switches
ADG801/ADG802
FEATURES
FUNC TIO NAL BLO C K D IAGRAMS
Low On Resistance < 0.5 Ω m ax at 5 V supply
0.1 Ω On Resistance Flatness
+1.8 V to +5.5 V Single Supply
100pA Leakage Currents
ADG801
ADG802
14ns Sw itching Tim es
Extended Tem perature Range -40oC to +125oC
High Current Carrying Capability
Tiny 6 lead SOT23 and 8 Lead µSOIC Packages
Low Pow er Consum ption
S
S
D
D
TTL/ CMOS Com patible Inputs
Pin Com patible w ith ADG701/ ADG702
IN
IN
APPLICATIONS
Pow er Routing
SWITCHES SHOWN FOR A LOGIC "1" INPUT
Audio and Video Signal Routing
Cellular Phones
Modem s
PCMCIA Cards
Hard Drives
Data Acquisition System s
Com m unication System s
Relay replacem ent
Audio and Video Sw itching
Battery Pow ered System s
GE NE RAL D E SC RIP TIO N
P RO D UC T H IGH LIGH TS
T he ADG801/ADG802 are monolithic CMOS SPST (Single
Pole, Single T hrow) switches with On Resistance of less than
0.5Ω. T hese switches are designed on an advanced submicron
process that provides extremely low on resistance, high switch-
ing speed and low leakage currents.
1. Low On Resistance (0.25 Ω typical).
2. +1.8V to +5.5V Single Supply Operation.
3. T iny 6 Lead SOT 23 and 8 Lead µSOIC Packages.
4. Pin Compatible with ADG701 (ADG801)
Pin Compatible with ADG702 (ADG802).
T he low On Resistance of <0.5Ω means these parts are ideal
for applications where low on resistance switching is critical.
T he ADG801 is a normally open (NO) switch, while the
ADG802 is normally closed (NC). Each switch conducts
equally well in both directions when ON.
T he ADG801 and ADG802 are available in 6-lead SOT -23
and 8 Lead µSOIC packages.
REV. PrE J an ‘02
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
1
ADG801/ADG802–SPECIFICATIONS
(V = 5 V ±10%, V = GND = 0 V. All specifications –40°C to +125°C unless otherwise noted.)
DD
SS
–40oC to –40oC to
P ar am eter
+25oC
+85oC
+125oC
Units
Test Conditions/Com m ents
AN ALO G SWIT C H
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
0.25
0.4
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IS = –10 mA;
T est Circuit 1
VS = 0 V to VDD, IS = –10 mA
0.5
0.1
0.75
0.2
On-Resistance Flatness (RFLAT (ON )) 0.05
LEAKAG E C U RREN T S
VDD = +5.5 V
Source OFF Leakage IS (OFF)
D rain OFF Leakage ID (OFF)
± 0.01
nA typ
nA max T est Circuit 2
nA typ
nA max T est Circuit 2
nA typ
nA max T est Circuit 3
VS = 4.5 V/1 V, VD = 1 V/4.5 V;
± 0.5
± 0.01
± 0.5
± 1
± 1
± 1
tbd
tbd
tbd
VS = 4.5 V/1 V, VD = 1 V/4.5 V;
Channel ON Leakage ID, IS (ON) ± 0.01
± 0.5
VS = VD = 1 V, or 4.5 V;
D IG IT AL IN PU T S
Input H igh Voltage, VIN H
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IIN H
0.005
5
µA typ
µA max
pF typ
VIN = VINL or VINH
± 0.1
CIN , Digital Input Capacitance
D YN AM IC C H ARAC T ERIST IC S2
t O N
30
ns typ
RL = 50 Ω, CL = 35 pF
T BD
T BD
T BD
ns max VS = 3 V; T est Circuit 4
tO F F
20
T BD
± 20
ns typ RL = 50 Ω, CL = 35 pF
ns max VS = 3 V; T est Circuit 4
pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, T est
Circuit 5
C harge Injection
Off Isolation
–65
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
T est Circuit 6
Bandwidth –3 dB
C S (O F F )
C D (O F F )
30
55
55
110
MH z typ RL = 50 Ω, CL = 5 pF, T est Circuit 7
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
CD , CS (ON )
P O WER REQ U IREM EN T S
I D D
VDD = +5.5 V
Digital Inputs = 0 V or 5.5 V
0.001
µA typ
1.0
µA max
N O T E S
1T emperature ranges are as follows: Extended T emperature Range: – 40°C to + 125°C .
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. PrE
–2–
PRELIMINARY TECHNICAL DATA
ADG801/ADG802
1
(V = 2.7 V to 3.6 V, V = GND = 0 V. All specifications –40°C to +125°C unless otherwise noted.)
SPECIFICATIONS
DD
SS
–40oC to –40oC to
P ar am eter
+25oC
+85oC
+125oC
Units
Test Conditions/Com m ents
AN ALO G SWIT C H
Analog Signal Range
0 V to VDD
1
V
On Resistance (RON
)
0.3
0.7
Ω typ
Ω max
Ω typ
VS = 0 V to VDD , IS = –10 mA;
T est Circuit 1
VS = 0 V to VDD , IS = –10 mA
0.8
On-Resistance Flatness(RF LAT (ON )) 0.1
0.3
LEAKAG E C U RREN T S
VDD = +3.3 V
Source OFF Leakage IS (OFF)
D rain OFF Leakage ID (OFF)
± 0.01
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V;
T est Circuit 2
VS = 3 V/1 V, VD = 1 V/3 V;
T est Circuit 2
VS = VD = 1 V, or 3 V;
T est Circuit 3
± 0.5
± 0.01
± 0.5
± 0.1
± 0.1
± 0.1
tbd
tbd
tbd
Channel ON Leakage ID , IS (ON) ± 0.01
± 0.5
D IG IT AL IN PU T S
Input H igh Voltage, VIN H
Input Low Voltage, VINL
Input Current
2.0
0.4
V min
V max
IINL or IIN H
0.005
5
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
CIN , Digital Input Capacitance
D YN AM IC C H ARAC T ERIST IC S2
tO N
50
T BD
40
T BD
± 20
ns typ
ns max
ns typ
RL = 50 Ω, CL = 35 pF
VS = 1.5 V, T est Circuit 4
RL = 50 Ω, CL = 35 pF
T BD
T BD
tO F F
ns max
VS = 1.5 V, T est Circuit 4
C harge Injection
Off Isolation
pC typ
dB typ
VS = 0 V, RS = 0 Ω, CL = 1 nF, T est
Circuit 5
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
T est Circuit 6
–65
Bandwidth –3 dB
CS (O F F )
C D (O F F )
30
55
55
110
MH z typ RL = 50 Ω, CL = 5 pF, T est Circuit 7
pF typ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
f = 1 MHz
CD , CS (ON )
P O WER REQ U IREM EN T S
I D D
VDD = +3.3 V
Digital Inputs = 0 V or 3.3 V
0.001
µA typ
1.0
µA max
N O T E S
1T emperature ranges are as follows: Extended T emperature Range: –40°C to + 125°C .
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. PrE
–3–
PRELIMINARY TECHNICAL DATA
ADG801/ADG802
AB SO LU T E M AXIM U M RAT ING S1
(TA = +25°C unless otherwise noted)
N O T E S
1Stresses above those listed under Absolute M axim um Ratings m ay
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Inputs2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD +0.3 V
. . . . . . . . . . . . . . . . . . . . or 30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . 400 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . 800 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
cause permanent damage to the device. T his is
a stress rating only;
functional operation of the device at these or any other conditions above
those listed in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability. Only one absolute maximum rating may
be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
Operating T emperature Range
Extended . . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C
Storage T emperature Range . . . . . . . . . –65°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . + 150°C
µSOIC Package, Power D issipation . . . . . . . . . . . 315 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . . 206°C /W
θJC T hermal Impedance . . . . . . . . . . . . . . . . . . . 44°C /W
SOT -23 Package, Power D issipation . . . . . . . . . . 282 mW
θJA T hermal Impedance . . . . . . . . . . . . . . . . . 229.6°C /W
θJC T hermal Impedance . . . . . . . . . . . . . . . . . 91.99°C /W
Lead T emperature, Soldering (10seconds) . . . . . . . 300°C
IR Reflow, Peak T emperature . . . . . . . . . . . . . . . . . + 220°C
ESD .....................................................................2kV
Table I. Tr uth Table
AD G801 In
AD G802 In
Switch Condition
0
1
1
0
OFF
ON
P IN CO NFIGURATIO NS
6-Lead P lastic Sur face Mount (SO T-23)
(RT-6)
8-Lead Sm all O utline µSO IC
(RM-8)
1
2
3
6
5
4
D
S
V
DD
1
2
3
4
8
7
6
5
D
S
ADG801/
ADG802
TOP VIEW
NC
IN
ADG801/
ADG802
TOP VIEW
NC
GND
GND
NC
IN
(Not to Scale)
(Not to Scale)
V
NC
NC = NO CONNECT
DD
NC = NO CONNECT
O RD E RING GUID E
Tem perature Range Supply O ption1 Br an d1
Model
P ackage D escriptions
SOT -23 (Plastic Surface M ount) RT -6
µSOIC (Small Outline) RM -8
SOT -23 (Plastic Surface M ount) RT -6
P ackage O ptions
AD G 801BRT
AD G 801BRM
AD G 802BRT
AD G 802BRM
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
3 V, 5 V
3 V, 5 V
3 V, 5 V
3 V, 5 V
S L B
S L B
S M B
S M B
µSOIC (Small Outline)
RM -8
1Branding on SOT -23 and µSOIC packages is limited to 3 characters due to space constraints.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD G801/AD G802 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. PrE
–4–
PRELIMINARY TECHNICAL DATA
ADG801/ADG802
TE RMINO LO GY
VDD
IDD
Most positive power supply potential.
Positive supply current.
GND
S
Ground (0 V) reference.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
D
IN
VD (VS)
RON
Analog voltage on terminals D, S
Ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured
over the specified analog signal range.
IS (OFF)
ID (OFF)
ID, IS (ON)
VINL
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Maximum input voltage for logic “0”.
VINH
Minimum input voltage for logic “1”.
IINL(IINH
)
Input current of the digital input.
CS (OFF)
CD (OFF)
“OFF” switch source capacitance. Measured with reference to ground.
“OFF” switch drain capacitance. Measured with reference to ground.
CD,CS(ON) “ON” switch capacitance. Measured with reference to ground.
CIN
tON
tOFF
Digital input capacitance.
Delay between applying the digital control input and the output switching on. See T est Circuit 4.
Delay between applying the digital control input and the output switching off.
Charge
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
Injection
Off Isolation A measure of unwanted signal coupling through an “OFF” switch.
Crosstalk
A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic
capacitance.
Bandwidth
T he frequency at which the output is attenuated by 3dBs.
On Response T he Frequency response of the “ON” switch.
Insertion
Loss
T he loss due to the ON resistance of the switch.
REV. PrE
–5–
PRELIMINARY TECHNICAL DATA
ADG801/ADG802
TYPICAL PERFORMANCE CHARACTERISTICS
TBD
TBD
TBD
Figure 4. Leakage Currents as a func-
tion of VD(VS)
Figure 7. Leakage Currents as a
Function of Tem perature
Figure 1. On Resistance as a Function
of VD(VS)
TBD
TBD
TBD
Figure 5. Leakage Currents as a func-
tion of VD(VS)
Figure 8. Supply Currents vs. Input
Switching Frequency
Figure 2. On Resistance as a Function
of VD(VS) for Different Tem peratures
TBD
TBD
TBD
Figure 6. Leakage Currents as a func-
tion of Tem perature
Figure 9. Charge Injection vs. Source
Voltage
Figure 3. On Resistance as a Function
of VD(VS) for Different Tem peratures
REV. PrE
–6–
PRELIMINARY TECHNICAL DATA
ADG801/ADG802
TBD
TBD
Figure 13. On Response vs. Fre-
Figure 10. TON/TOFF Tim es vs. Tem -
perature
quency
TBD
Figure 11. Off Isolation vs. Frequency
TBD
Figure 12. Crosstalk vs. Frequency
REV. PrE
–7–
PRELIMINARY TECHNICAL DATA
ADG801/ADG802
Test Circuits
I
DS
V1
I
(OFF)
A
I
(OFF)
A
I
D (ON)
S
D
S
D
S
D
S
D
NC
A
V
R
= V1/I
V
S
V
D
V
S
ON
DS
D
NC=No Connect
Test Circuit 1. On Resistance
Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage
V
DD
0.1µF
ADG801
V
50%
50%
50%
IN
V
DD
V
OUT
S
D
V
50%
90%
IN
ADG802
R
C
L
35pF
L
V
S
300⍀
IN
90%
V
OUT
GND
tOFF
tON
Test Circuit 4. Switching Tim es
V
DD
V
DD
V
ADG801
ADG802
IN
ON
OFF
V
R
OUT
S
S
D
V
C
L
S
V
IN
1nF
IN
V
OUT
⌬V
OUT
GND
Q
= C
؋
⌬V L OUT
INJ
Test Circuit 5. Charge Injection
V
DD
V
DD
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
DD
V
DD
S
50
Ω
S
50
Ω
IN
50
Ω
V
S
IN
V
S
D
D
V
OUT
V
V
IN
R
OUT
L
V
IN
R
L
50
Ω
GND
50
Ω
GND
V
OUT
V
WITH SWITCH
OFF ISOLATION = 20 LOG
OUT
V
INSERTION LOSS = 20 LOG
S
V
WITHOUT SWITCH
OUT
Test Circuit 6. Off Isolation
Test Circuit 7. Bandwidth
REV. PrE
–8–
PRELIMINARY TECHNICAL DATA
ADG801/ADG802
O UTLINE D IME NSIO NS
D imensions shown in inches and (mm).
8-Lead µSO IC
(RM-8)
6-Lead SO T-23
(RT-6)
0.122 (3.10)
0.114 (2.90)
0.122 (3.10)
0.106 (2.70)
8
1
5
4
6
1
5
2
4
3
0.071 (1.80)
0.059 (1.50)
0.118 (3.00)
0.098 (2.50)
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
PIN 1
PIN 1
0.037 (0.95) BSC
0.0256 (0.65) BSC
0.120 (3.05)
0.075 (1.90)
BSC
0.120 (3.05)
0.112 (2.84)
0.112 (2.84)
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
0.043 (1.09)
0.037 (0.94)
0.006 (0.15)
0.002 (0.05)
33°
27°
10؇
0؇
0.018 (0.46)
0.020 (0.50)
0.010 (0.25)
0.022 (0.55)
0.014 (0.35)
0.006 (0.15)
0.000 (0.00)
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
0.003 (0.08)
SEATING
PLANE
SEATING
PLANE
0.009 (0.23)
0.003 (0.08)
0.008 (0.20)
REV. PrE
–9–
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