ADGM1004JCPZ-R2 [ADI]
0 Hz/DC to 13 GHz, 2.5 kV HBM ESD, SP4T, MEMS Switch with Integrated Driver;
| 型号： | ADGM1004JCPZ-R2 |
| 厂家： | 
ADI |
| 描述： | 0 Hz/DC to 13 GHz, 2.5 kV HBM ESD, SP4T, MEMS Switch with Integrated Driver |
| 文件： | 总32页 (文件大小：1379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0 Hz/DC to 13 GHz, 2.5 kV HBM ESD,
SP4T, MEMS Switch with Integrated Driver
ADGM1004
Data Sheet
FEATURES
APPLICATIONS
Fully operational down to 0 Hz/dc
On resistance: 2.9 Ω (maximum)
Off leakage: 0.5 nA (maximum)
−3 dB bandwidth
Relay replacements
Automatic test equipment (ATE): RF, digital, and mixed signals
Load and probe boards: RF, digital, and mixed signals
RF test instrumentation
10.8 GHz (typical) for RF1, RF4
13 GHz (typical) for RF2, RF3
RF performance characteristics
Insertion loss: 0.45 dB (typical) at 2.5 GHz
Isolation: 24 dB (typical) at 2.5 GHz
IP3: 67 dBm (typical)
RF input power: 32 dBm (maximum)
Actuation lifetime: 1 billion cycles (minimum)
Hermetically sealed switch contacts
On switching time: 75 μs (maximum)
ESD HBM rating
Reconfigurable filters and attenuators
High performance RF switching
GENERAL DESCRIPTION
The ADGM1004 is a wideband, single-pole, four-throw (SP4T)
switch fabricated using Analog Devices, Inc., microelectro-
mechanical system (MEMS) switch technology. This technology
enables a small form factor, wide RF bandwidth, highly linear, low
insertion loss switch that is operational from 0 Hz/dc to 13 GHz,
making it an ideal solution for a wide range of RF and precision
equipment switching needs.
5 kV for RF1 to RF4 and RFC pins
2.5 kV for all other pins
Integrated driver removes the need for an external driver
Supply voltage: 3.0 V to 3.6 V
An integrated driver chip generates a high voltage to
electrostatically actuate switch that can be controlled by a parallel
interface and a serial peripheral interface (SPI). All four switches
are independently controllable.
CMOS/LVTTL compatible
The device is packaged in a 24-lead, 5 mm × 4 mm × 1.45 mm,
lead frame chip-scale package (LFCSP).
Parallel and SPI Interface
Independently controllable switches
Switch is in an open state with no power supply present
Requirement to avoid floating nodes on all RFx pins (see the
Floating Node section)
5 mm × 4 mm × 1.45 mm, 24-lead LFCSP
Operating temperature range: 0°C to +85°C
To ensure optimum operation of the ADGM1004, follow the
Critical Operational Requirements section exactly.
The on resistance (RON) performance of the ADGM1004 is
affected by part to part variation, channel to channel variation,
cycle actuations, settling time post turn on, bias voltage, and
temperature changes.
Note that throughout this data sheet, multifunction pins, such
as IN1/SDI, are referred to either by the entire pin name or by a
single function of the pin, for example, SDI, when only that
function is relevant.
Rev. D
Document Feedback
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Tel: 781.329.4700 ©2017–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADGM1004
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Internal Oscillator Feedthrough............................................... 25
Internal Oscillator Feedthrough Mitigation ........................... 25
Low Power Mode........................................................................ 25
Typical Operating Circuit ......................................................... 26
Applications Information.............................................................. 27
Switchable RF Attenuator.......................................................... 27
Reconfigurable RF Filter ........................................................... 27
Critical Operational Requirements.............................................. 28
System Error Considerations Due to On-Resistance Drift... 28
Floating Node ............................................................................. 28
Cumulative On Switch Lifetime............................................... 29
Handling Precautions ................................................................ 29
Register Details ............................................................................... 31
Switch Data Register .................................................................. 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Test Circuits..................................................................................... 17
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 22
Parallel Digital Interface............................................................ 22
SPI Digital Interface................................................................... 23
REVISION HISTORY
11/2019—Rev. C to Rev. D
Change to Features Section and General
Added Critical Operational Requirements Section, System
Error Considerations Due to On-Resistance Drift Section,
Figure 52, Table 7, Floating Node Section, Figure 53, Figure 54,
Figure 55, Figure 56, and Figure 57.............................................. 28
Added Figure 58, Figure 59, Cumulative On Switch Lifetime
Section, Handling Precautions Section, and Figure 61 ............. 29
Moved Figure 60 and Electrical Overstress (EOS)
Applications Section......................................................................... 1
Moved Functional Block Diagram Section................................... 4
Changes to Figure 1.......................................................................... 4
Changes to Specifications Section and Table 1............................. 5
Added Timing Characteristics Section and Table 2;
Renumbered Sequentially................................................................ 7
Added Timing Diagrams Section, Figure 2, Figure 3, and
Figure 4; Renumbered Sequentially ............................................... 8
Changes to Absolute Maximum Rating Section
and Table 3......................................................................................... 9
Changes to Figure 5 and Table 5................................................... 10
Changes to Typical Performance Characteristics Section......... 12
Changes to Terminology Section.................................................. 20
Changes to Parallel Digital Interface Section and
Table 6 Title ..................................................................................... 22
Added SPI Digital Interface Section, Addressable Mode Section,
and Figure 45................................................................................... 23
Added Daisy-Chain Mode Section, Figure 46, Figure 47, and
Figure 48 .......................................................................................... 24
Added Hardware Reset Section and Internal Error Status
Section.............................................................................................. 25
Changes to Internal Oscillator Feedthrough Section and
Internal Oscillator Feedthrough Mitigation Section ................. 25
Changes to Typical Operating Circuit Section and
Precautions Section........................................................................ 29
Added Mechanical Shock Precautions Section and Table 8 ..... 30
Changes to Figure 62...................................................................... 30
Added Register Details Section, Switch Data Register Section,
and Table 9....................................................................................... 31
Change to Ordering Guide............................................................ 32
3/2019—Rev. B to Rev. C
Change to Features Section and Figure 1.......................................1
Changes to Specifications Section and Table 1..............................3
Deleted Endnote 1, Endnote 3, and Endnote 6 in Table 1;
Renumbered Sequentially ................................................................4
Changes to Table 2.............................................................................5
Changes to Table 4.............................................................................6
Updated Typical Performance Characteristics Section
Format.................................................................................................7
Changes to Figure 6 to Figure 8 Captions......................................7
Added Figure 9 to Figure 12; Renumbered Sequentially .............8
Deleted Figure 15...............................................................................9
Added Figure 19 and Figure 20 .......................................................9
Added Figure 24 to Figure 26 ....................................................... 10
Added Figure 27 to Figure 30 ....................................................... 11
Figure 49 .......................................................................................... 26
Deleted Handling Guidelines Section, DC Voltage Range
Section, and Voltage Standoff Limit Section............................... 27
Rev. D | Page 2 of 32
Data Sheet
ADGM1004
Changes to Figure 32 Caption .......................................................12
Added Figure 33 ..............................................................................12
Deleted Figure 27 to Figure 29 ......................................................12
Changes to Figure 35 ......................................................................13
Changes to Figure 37 Caption .......................................................13
Added Figure 39, Figure 40, and Figure 42..................................14
Changes to Terminology Section ..................................................15
Changes to Theory of Operation Section ....................................17
Changed Internal Oscillator/EXTD_EN Section to Internal
Oscillator Section ............................................................................18
Changes to Internal Oscillator Section, Typical Operating
Circuit Section.................................................................................18
Replaced Figure 44..........................................................................18
Added Oscillator Feedthrough Mitigation Section and Low
Power Mode Section .......................................................................18
Changes to Figure 50 and Figure 51 .............................................19
Added Voltage Standoff Limit Section .........................................22
3/2018—Rev. A to Rev. B
Changes to Features Section............................................................1
Changes to Table 1 ............................................................................3
Added Endnote 5 to Table 1; Renumbered Sequentially .............3
Changes to Table 2 ............................................................................5
Added Figure 27, Figure 28, and Figure 29; Renumbered
Sequentially......................................................................................12
Changes to Floating Node Avoidance Section and Figure 36.....17
Updated Outline Dimensions........................................................21
2/2017—Rev. 0 to Rev. A
Changes to Features Section............................................................1
Changes to On Resistance Parameter, Table 1 ..............................3
Change to Table 2..............................................................................5
Changes to Figure 13 and Figure 14 ...............................................8
Updated Outline Dimensions........................................................20
1/2017—Revision 0: Initial Version
Rev. D | Page 3 of 32
ADGM1004
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
RF1 IN RF2 IN
0.1µF
47pF
10MΩ*
10MΩ*
EXTD_EN
V
V
DD
RF1
RF2
CP
ADGM1004
CHARGE
PUMP
OSCILLATOR
PIN/SPI
V
CP
REFERENCE
AND BIAS
REGULATOR
LEVEL
LV
LV
LV
LV
HV
IN1/SDI
IN2/CS
SHIFTER
RFC
LEVEL
SHIFTER
RFC IN
HV
HV
HV
10MΩ*
LEVEL
SHIFTER
IN3/SCLK
IN4/SDO
LEVEL
SHIFTER
RF4
RF3
GND
10MΩ*
10MΩ*
RF4 IN RF3 IN
*10MΩ RESISTORS ARE REQUIRED TO AVOID ANY FLOATING NODES.
FOR MORE INFORMATION, REFER TO THE CRITICAL OPERATIONAL REQUIREMENTS SECTION
NOTES
1. LV = LOW VOLTAGE.
HV = HIGH VOLTAGE.
Figure 1.
Rev. D | Page 4 of 32
Data Sheet
ADGM1004
SPECIFICATIONS
Supply voltage (VDD) = 3.0 V to 3.6 V, GND = 0 V, and all specifications at TA = 25°C, unless otherwise noted. Typical specifications tested
at TA = 25°C with VDD = 3.3 V.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments1
ON-RESISTANCE PROPERTIES
See Figure 6 to Figure 13 for more details
Initial On-Resistance
Properties
On Resistance
RON
2.9
1
Ω
Ω
Drain source current (IDS) = 50 mA, 0 V input bias,
at 1 ms after first actuation, maximum
specification from 0°C to 85°C
Maximum value tested from 0°C to 85°C
On-Resistance Match
Between Channels
ΔRON CH_CH
On-Resistance Drift
Over Time2
ΔRON TIME
ΔRON
−0.25
5
Ω
Ω
Ω
RON changed from 1 ms to 100 ms after first
actuation, maximum value tested from 0°C to 85°C
Over Actuations3
0.5
7.2
109 actuations, switch is actuated at 25°C and
RON is measured at 25°C
109 actuations, switch is actuated at 85°C and RON is
measured at 25°C, 1 kHz actuating frequency,
220 mA load applied between toggles4
RELIABILITY PROPERTIES
Continuously On Lifetime
Years
Median time before failure at 50°C5, see Figure 60
for more details
Actuation Lifetime
Cold Switched
Hot Switched
109
Actuations Load between toggling is 220 mA, tested at 85°C
RF power = continuous wave (CW), terminated
into 50 Ω, see Figure 14 for details
10 dBm
15 dBm
20 dBm
5.16 ×
109
3.21 ×
106
390 ×
103
Actuations 50% of test population failure point (T50)
Actuations 50% of test population failure point (T50)
Actuations 50% of test population failure point (T50)
DYNAMIC CHARACTERISTICS
Operating Frequency
−3 dB Bandwidth
RF1, RF4
RF2, RF3
Insertion Loss
0/dc
13
GHz
BW
IL
9.5
11.5
10.8
13
0.45
0.63
GHz
GHz
dB
RF1 to RFC and RF4 to RFC channels
RF2 to RFC and RF3 to RFC channels
At 2.5 GHz, RFC to RFx
0.6
0.95
dB
At 6.0 GHz, RFC to RFx
Isolation
RFx to RFC
22
16
24
19
27
26
30
24
17
67
dB
dB
At 2.5 GHz, RFx to RFC (all channels off)
At 6.0 GHz, RFx to RFC (all channels off)
At 6 GHz, RF2 to RFC is on, RF1 to RFC is off
At 6 GHz, RF1 to RFC is on, RF2 to RFC is off
At 2.5 GHz, RFx to RFx
At 6.0 GHz, RFx to RFx
DC to 6.0 GHz
Input: 900 MHz and 901 MHz, input power =
27 dBm
RF1 to RFC
RF2 to RFC
Crosstalk
27
22
14
dB
dB
dB
dBm
Return Loss
Third-Order Intermodulation
Intercept
RL
IP3
Second-Order Intermodulation
Intercept
IP2
95
dBm
Input: 900 MHz and 901 MHz, input power =
27 dBm
Second Harmonic Distortion
HD2
−90
−74
dBc
dBc
Input: 5.4 MHz, input power = 0 dBm
Input: 150 MHz and 800 MHz, input power =
27 dBm
Rev. D | Page 5 of 32
ADGM1004
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments1
Third Harmonic Distortion
HD3
−80
dBc
Input: 150 MHz and 800 MHz, input power =
27 dBm
Total Harmonic Distortion plus THD + N
Noise
RF Input Power
−102
dBc
dBm
V
Load resistance (RL) = 300 Ω, f = 1 kHz, RFx =
2.5 V p-p
Switch in the on state and terminated into 50 Ω,
maximum specification tested at 25℃
On switch dc voltage operation range, 0°C to
85°C
50% INx to 90% (0.05 dB of final IL value) RFx,
50 Ω termination, 0°C to 85°C
50% INx to 10% (0.05 dB of final IL value) RFx,
50 Ω termination, 0°C to 85°C
All switches toggled simultaneously, 0°C to 85°C
CCP = 47 pF, 95% VDD to 90% RFx, 0°C to 85°C
1 MΩ termination at RFx pin
32
+6
75
75
5
DC Voltage Range
−6
0
On Switching Time6
Off Switching Time6
tON
μs
tOFF
0
μs
Actuation Frequency
Power-Up Time
Video Feedthrough
Internal Oscillator Frequency
Internal Oscillator
Feedthrough7
kHz
ms
mV peak
MHz
dBm
0.75
16
10
8
12
0°C to 85°C
−123
Spectrum analyzer resolution bandwidth (RBW) =
200 Hz, one switch in on state, all other switches
off with 50 Ω terminations8
−146
dBm/Hz
CAPACITANCE PROPERTIES
At 1 MHz, includes LFCSP package capacitance
On Switch Channel
Capacitance
Off Switch Channel
Capacitance
CRF ON
CRF OFF
3
pF
pF
1.5
LEAKAGE PROPERTIES
On Leakage
Maximum specification from 0°C to 85°C
RFx (off channels) = −6 V, RFC to RFx (on
channel) = −6 V
5
nA
nA
Off Leakage
0.5
RFx = 6 V, RFC = −6 V
DIGITAL INPUTS
Minimum and maximum over 0°C to 85°C
Input High Voltage
Input Low Voltage
Input Current
VINH
VINL
IINL, IINH
2
V
V
μA
0.8
1
0.025
Input voltage (VIN) = VINL or VINH
Minimum and maximum over 0°C to 85°C
Sink current (ISINK) = 1 mA
DIGITAL OUTPUTS
Output Low Voltage
Output High Voltage
VOL
VOH
0.4
VMAX
VMIN
VDD
0.4
−
Source current (ISOURCE) = 1 mA
POWER REQUIREMENTS
Supply Voltage
Supply Current
Minimum and maximum over 0°C to 85°C
VDD
IDD
3.0
3.6
2.5
V
mA
Digital inputs = 0 V or VDD, SDO is floating in
SPI mode
Low Power Mode Current9
External Drive Voltage10
External Drive Current
IDD EXT VCP
VCPEXT
ICP EXT VCP
50
80.8
20
μA
V
μA
This value is IDD in low power mode
79.2
80
1 RFx is RF1, RF2, RF3, and RF4. INx is IN1, IN2, IN3, and IN4.
2 Maximum RON over time is RON (max) + ∆RON TIME (max) = 2.65 Ω.
3 Maximum RON after 1 billion actuations is RON (max) + ΔRON (max) = 7.9 Ω.
4 Actuating the switch at 85°C and measuring RON at 25°C is the most severe condition for ADGM1004 RON drift over actuations.
5 Failure occurs when 50% of a sample lot fails. For more details, see the Cumulative On Switch Lifetime section.
6 Switch is settled after 75 μs. Do not apply RF power between 0 μs and 75 μs.
7 Disable the internal oscillator to eliminate feedthrough. When the internal oscillator and charge pump circuitry is disabled, the VCP pin (Pin 24) must be driven with
80 V dc (VCPEXT) from an external voltage supply required for MEMS switch actuation, as outlined in Table 3.
8 The spectrum analyzer setup is as follows: RBW = 200 Hz, video bandwidth (VBW) = 2 Hz, span = 100 kHz, input attenuator = 0 dB, the detector type is peak, and the
maximum hold is off. The fundamental feedthrough noise or harmonic (whichever is higher) is tested.
9 For more details, see the Low Power Mode section.
10 For more details, see the Internal Oscillator Feedthrough Mitigation section.
Rev. D | Page 6 of 32
Data Sheet
ADGM1004
TIMING CHARACTERISTICS
VDD = 3.0 V to 3.6 V, GND = 0 V, and all specifications TMIN to TMAX = 0°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Description
Limit at TMIN
Limit at TMAX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
t8
SCLK period
SCLK high pulse width
SCLK low pulse width
CS falling edge to SCLK active edge
Data setup time
100
45
45
25
20
20
25
Data hold time
SCLK active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high impedance
CS high time between SPI commands
SCLK edge rejection to CS falling edge
CS rising edge to SCLK edge rejection
20
40
25
1
t9
t10
t11
t12
t13
100
25
25
1 Measured with a 20 pF load, t9 determines the maximum SCLK frequency when the SDO pin is used.
Rev. D | Page 7 of 32
ADGM1004
Data Sheet
Timing Diagrams
t1
SCLK
CS
t2
t3
t7
t4
t6
t5
SDI
R/W
A6
A5
1
D2
D2
D1
D1
D0
D0
t10
t9
SDO
0
0
t8
Figure 2. Addressable Mode Timing Diagram
t1
SCLK
CS
t2
t3
t7
t4
t6
t5
SDI
D7
D6
D0
D7
D6
D1
D0
INPUT BYTE FOR DEVICE N
t9
INPUT BYTE FOR DEVICE N + 1
t10
SDO
0
0
0
D7
D6
D1
D0
ZERO BYTE
INPUT BYTE FOR DEVICE N
t8
Figure 3. Daisy-Chain Timing Diagram
t11
CS
SCLK
t13
t12
CS
Figure 4. SCLK/ Timing Relationship
Rev. D | Page 8 of 32
Data Sheet
ADGM1004
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
VDD to GND
Digital Inputs1
Rating
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V or
+30 mA (whichever occurs
first)
7 V
20 V
DC Voltage Rating2
Standoff Voltage3
RFx to AGND
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
10 V
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
RFC to AGND
RFx to RFC
10 V
20 V
250 mA
33 dBm
Current Rating2
RF Power Rating4
Temperature
Operating Range
Storage Range
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
0°C to +85°C
−65°C to +150°C
Table 4. Thermal Resistance
Package Type
CP-24-41
Reflow Soldering (Pb-Free)
Peak
Time at Peak
θJA
θJC
Unit
260 (+0/−5)°C
10 sec to 30 sec
60
75
°C/W
Electrostatic Discharge (ESD)
Human Body Model (HBM)
RF1 to RF4 and RFC
All Other Pins
Field Induced Charged Device
Model5
1 A simulated θJA number is evaluated using the maximum junction
temperature in the package and the total power being dissipated in the
package under operating conditions. For thermal performance calculation
purposes at 25°C, a power dissipation of 113 mW per switch can be used.
This value is calculated from a typical RON of 1.8 Ω and an absolute maximum
current rating of 250 mA.
5 kV
2.5 kV
All Pins
Group D
1.25 kV
ESD CAUTION
Mechanical Shock (with 0.5 ms 1500 g
Pulse) 6
Vibration (Acceleration at 50 g) 20 Hz to 2000 Hz
Constant Acceleration
30,000 g
1 Clamp overvoltages at INx by internal diodes. Limit the current to the
maximum ratings given.
2 This rating is with respect to the switch in the on position with no radio
frequency signal applied.
3 This rating is with respect to the switch in the off position.
4 This rating is with respect to the switch in the on position and terminated
into 50 Ω. The rating is 27 dBm when the switch is unterminated.
5 A safe automated handling and assembly process is achieved at this rating
level by implementing industry standard ESD controls.
6 If the device is dropped during handling, do not use the device.
Rev. D | Page 9 of 32
ADGM1004
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN1/SDI 1
17 GND
IN2/CS
2
3
16 GND
15 RFC
14 GND
13 GND
ADGM1004
TOP VIEW
(Not to Scale)
IN3/SCLK
IN4/SDO 4
GND
EP1
EP2
5
NOTES
1. EXPOSED PAD 1. EP1 IS INTERNALLY CONNECTED TO EP2
AND MUST BE CONNECTED TO GND.
2. EXPOSED PAD 2. EP2 IS INTERNALLY CONNECTED TO EP1
AND MUST BE CONNECTED TO GND.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic Description
1
IN1/SDI
Parallel Logic Digital Control Input 1. The voltage applied to this pin controls the gate of the RF1 to RFC
MEMS switch. In SPI mode, this pin is the serial data input pin. In parallel mode, if the IN1 pin is low, the
RF1 to RFC switch is open (off). If the IN1 pin is high, the RF1 to RFC switch is closed (on). In SPI mode, this
pin functions as the serial data input (SDI) pin.
2
IN2/CS
Parallel Logic Digital Control Input 2. The voltage applied to this pin controls the gate of the RF2 to RFC
MEMS switch. In parallel mode, if IN2 is low, the RF2 to RFC switch is open (off). If IN2 is high, the RF2 to
RFC switch is closed (on). In SPI mode, this pin is the chip select (CS) pin. CS is an active low signal that
selects the slave device with which the master device intends to communicate. Typically, there is a
dedicated CS signal between the master device and each slave device. The CS pin also functions to
synchronize and frame the communications to and from the slave device.
3
4
IN3/SCLK
IN4/SDO
GND
Parallel Logic Digital Control Input 3. The voltage applied to this pin controls the gate of the RF3 to RFC
MEMS switch. In parallel mode, if IN3 is low, the RF3 to RFC switch is open (off). If IN3 is high, the RF3 to
RFC switch is closed (on). In SPI mode, this pin functions as the serial clock (SCLK) pin that synchronizes the
slave device(s) to the master device. Typically, the SCLK signal is shared for all slave devices on the serial
bus. The SCLK signal is always driven by the master device.
Parallel Logic Digital Control Input 4. The voltage applied to this pin controls the gate of the RF4 to RFC
MEMS switch. In parallel mode, if IN4 is low, the RF4 to RFC switch is open (off). If IN4 is high, the RF4 to
RFC switch is closed (on). In SPI mode, this pin functions as the serial data output (SDO) pin. Typically, the
SDO pin is shared for all slave devices on the serial bus. The SDO pin is driven by only one slave device at a time,
otherwise it is high impedance. The SDO pin is always high impedance when the CS pin is deasserted high.
5, 8, 9, 11, 13,
14, 16, 17,
19, 21, 22
Ground Connection.
6
PIN/SPI
Parallel or Serial Logic Control Enable Pin. The SPI interface is enabled when this pin is high. When this pin
is low the parallel digital interface is enabled.
7
EXTD_EN
External Voltage Drive Enable. In normal operation, set EXTD_EN low to enable the built in 10 MHz oscillator,
which enables the internal driver IC voltage boost circuitry. Setting EXTD_EN high disables the internal 10 MHz
oscillator and driver boost circuitry. With the oscillator disabled, the switch can still be controlled via the
logic interface pins (IN1 to IN4) or via SPI interface, but the VCP pin must be driven with 80 V dc from an
external voltage supply. In this mode, the ADGM1004 only consumes 50 μA maximum supply current.
Disabling the internal oscillator eliminates the associated 10 MHz noise feedthrough from the switch.
10
12
RF4
RF3
RF4 Port. This pin can be an input or an output. If unused, connect the pin to GND or terminate the pin
with a 50 Ω resistor to GND.
RF3 Port. This pin can be an input or an output. If unused, connect the pin to GND or terminate the pin
with a 50 Ω resistor to GND.
15
18
RFC
RF2
Common RF Port. This pin can be an input or an output.
RF2 Port. This pin can be an input or an output. If unused, connect the pin to GND or terminate the pin
with a 50 Ω resistor to GND.
20
RF1
RF1 Port. This pin can be an input or an output. If unused, connect the pin to GND or terminate the pin
with a 50 Ω resistor to GND.
Rev. D | Page 10 of 32
Data Sheet
ADGM1004
Pin No.
Mnemonic Description
23
VDD
Positive Power Supply Input. The recommended decoupling capacitor to ground value is 0.1 μF. For the
recommended input voltage for this chip, see the Specifications section.
24
VCP
Charge Pump Capacitor Terminal. The recommended shunt capacitor to ground value is 47 pF (100 V
rated). If the EXTD_EN pin is high, input an 80 V dc drive voltage into VCP to drive the switches.
EP1
EP2
Exposed Pad 1. EP1 is internally connected to EP2 and must be connected to GND.
Exposed Pad 2. EP2 is internally connected to EP1 and must be connected to GND.
Rev. D | Page 11 of 32
ADGM1004
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
In Figure 14, T50 refers to the number of cycles required for 50% of the population to fail.
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
100
90
80
70
60
50
40
30
20
10
0
V
A
= 3.3V
RF1 TO RFC
RF2 TO RFC
RF3 TO RFC
RF4 TO RFC
DD
T
= 25°C
1 ACTUATION
167 MILLION ACTUATIONS
500 MILLION ACTUATIONS
1 BILLION ACTUATIONS
SWITCH ACTUATED AT 85°C
R
MEASURED AT 25°C
= 3.3V
ON
DD
V
0
1
2
3
4
5
6
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
ASOLUTE R
(ꢀ)
TIME (Seconds)
ON
Figure 9. Absolute RON vs. Time (1 ms to 5 sec) on Linear Scale
Figure 6. Population Percentage vs. Absolute RON, Switch Actuated at 85°C
and RON measured at 25°C
0
3.0
SWITCH ACTUATED AT 25°C
MEASURED AT 25°C
V
= 3.3V
DD
R
V
A
= 3.3V
ON
DD
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
T
= 25°C
2.5
2.0
1.5
1.0
0.5
0
RF1 TO RFC
RF2 TO RFC
RF3 TO RFC
RF4 TO RFC
RF1 TO RFC
RF2 TO RFC
RF3 TO RFC
RF4 TO RFC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
10
100
1k
10k
100k
1M
10M
100M
TIME (Seconds)
SWITCH ACTUATION NUMBER
Figure 10. RON Drift vs. Time (1 ms to 5 sec) on Linear Scale, Normalized at Zero
Figure 7. Absolute RON vs. Switch Actuation Number, Switch Actuated at 25°C
and RON Measured at 25°C
0
1.0
SWITCH ACTUATED AT 25°C
V
= 3.3V
DD
R
MEASURED AT 25°C
= 3.3V
T = 25°C
A
ON
DD
0.8
0.6
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
V
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
RF1 TO RFC
RF2 TO RFC
RF3 TO RFC
RF4 TO RFC
RF1 TO RFC
RF2 TO RFC
RF3 TO RFC
RF4 TO RFC
1
10
100
1k
10k
100k
1M
10M
100M
0.001
0.01
0.1
1
10
TIME (Seconds)
SWITCH ACTUATION NUMBER
Figure 11. RON Drift vs. Time (1 ms to 5 sec) on Log Scale, Normalized at Zero
Figure 8. RON Drift vs. Switch Actuation Number, Normalized at Zero, Switch
Actuated at 25°C and RON Measured at 25°C
Rev. D | Page 12 of 32
Data Sheet
ADGM1004
2.0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
V
V
V
= 3.0V
T
= 25°C
DD
DD
DD
RF2 TO RFC
RF1 TO RFC
A
= 3.3V
= 3.6V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= 25°C
A
V
= 3.3V
DD
–6
–4
–2
0
2
4
6
0
2
4
6
8
10
12
14
16
SIGNAL BIAS VOLTAGE (V)
FREQUENCY (GHz)
Figure 12. RON vs. Signal Bias Voltage over Supply Voltages (Measured 5 sec
Post Switch Turn On Time, RF1 to RFC on)
Figure 15. Insertion Loss vs. Frequency, Linear Scale (VDD = 3.3 V)
2.0
0
T
T
T
= 0°C
A
A
A
V
= 3.3V
85°C
25°C
0°C
DD
= 25°C
= 85°C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.5
–1.0
–1.5
–2.0
–2.5
V
= 3.3V
DD
–3.0
100M
–6
–4
–2
0
2
4
6
1G
10G
FREQUENCY (Hz)
100G
SIGNAL BIAS VOLTAGE (V)
Figure 13. RON vs. Signal Bias Voltage over Temperature (Measured 5 sec Post
Switch Turn On Time, RF1 to RFC on)
Figure 16. Insertion Loss vs. Frequency over Temperature (VDD = 3.3 V, RF1 to RFC)
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
0
T
V
= 25°C
A
98
= 3.3V
DD
10dBm
15dBm
20dBm
–10
–20
–30
–40
–50
–60
–70
–80
94
90
82
65
T50
45
25
14
8
4
INSERTION LOSS
OFF ISOLATION
RETURN LOSS
1
10k
100k
1M
10M
100M
1B
10B
100B
0
50
100
150
200
SWITCH ACTUATIONS (Cycles)
FREQUENCY (MHz)
Figure 14. Hot Switching Probability Distribution on Log Normal with 95%
Confidence Interval (CI) (RF Power = CW, Terminated into 50 Ω, TA = 25°C,
VDD = 3.3 V)
Figure 17. Insertion Loss and Off Isolation/Return Loss vs. Frequency
(VDD = 3.3 V, RF1 to RFC)
Rev. D | Page 13 of 32
ADGM1004
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
T
V
= 25°C
RF1 TO RFC
RF2 TO RFC
A
RF1
RF2
RFC (RF1 ON)
T
V
= 25°C
= 3.3V
A
= 3.3V
DD
DD
–10
–20
–30
–40
–50
–60
–70
–80
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 18. Off Isolation vs. Frequency, All Channels Off (VDD = 3.3 V)
Figure 21. Return Loss vs. Frequency (VDD = 3.3 V)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
T
T
T
= 85°C
= 25°C
= 0°C
T
V
= 25°C
A
A
A
V
= 3.3V
RF1 TO RF2
RF2 TO RF1
A
DD
= 3.3V
DD
–10
–20
–30
–40
–50
–60
–70
–80
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 19. Off Isolation vs. Frequency over Temperature, All Channels Off
(VDD = 3.3 V, RF1 to RFC)
Figure 22. Crosstalk vs. Frequency (VDD = 3.3 V)
0
0
–10
–20
–30
–40
–50
–60
–70
–80
T
T
T
= 85°C
= 25°C
= 0°C
V
= 3.3V
A
A
A
DD
T
V
= 25°C
= 3.3V
A
DD
–10
–20
–30
–40
–50
–60
RF2 TO RFC
RF3 TO RFC
RF4 TO RFC
–70
–80
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 20. Off Isolation vs. Frequency, RF1 to RFC On (VDD = 3.3 V)
Figure 23. Crosstalk vs. Frequency over Temperature (VDD = 3.3 V, RF2 to RF1)
Rev. D | Page 14 of 32
Data Sheet
ADGM1004
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
OFF SWITCH CAPACITANCE
ON SWITCH CAPACITANCE
V
= 3.3V
DD
100Hz
1kHz
5kHz
10kHz
15kHz
20kHz
–20
–40
–60
–80
–100
–120
–6
–4
–2
0
2
4
6
0
2
4
6
8
10
12
SIGNAL BIAS VOLTAGE (V)
SIGNAL AMPLITUDE (V p-p)
Figure 24. THD + N vs. Signal Amplitude (VDD = 3.3 V, RLOAD = 300 Ω, TA = 25°C,
Signal Source Impedance = 20 Ω)
Figure 27. Switch Capacitance vs. Signal Bias Voltage
0
32
28
24
20
16
12
8
V
= 3.3V
DD
T
V
= 25°C
= 3.3V
–10
–20
A
DD
–30
–40
0dBm
5dBm
10dBm
14.5dBm
–50
–60
–70
–80
–90
–100
–110
–120
4
0
0
2
4
6
8
10
12
14
16
18
20
0
4
8
12
16
20
24
28
32
FREQUENCY (kHz)
P
(dBm)
IN
Figure 25. THD + N vs. Frequency (VDD = 3.3 V, RLOAD = 300 Ω, TA = 25°C, Signal
Source Impedance = 20 Ω
Figure 28. Output Power (POUT) vs. Input Power (PIN) (VDD = 3.3 V, Signal
Frequency = 4 GHz)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
0.8
T
V
= 25°C
A
0.6
= 3.3V
DD
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DIGITAL CONTROL
tON tOFF TEST SIGNAL
/
V
A
= 3.3V
DD
–4.5
–5.0
T
= 25°C
–0.5
FREQUENCY = 4GHz
12
INPUT POWER (dBm)
0
10
20
TIME (µs)
30
40
0
4
8
16
20
24
28
32
Figure 26. Digital Control Signal and Test Signal vs. Time (VDD = 3.3 V)
Figure 29. Insertion Loss vs. Input Power
Rev. D | Page 15 of 32
ADGM1004
Data Sheet
–120
–122
–124
–126
–128
–130
–132
–134
–136
–120
NORMAL OPERATING MODE
INTERNAL OSCILLATOR DISABLED
T
V
= 25°C
= 3.3V
T
V
= 25°C
= 3.3V
A
A
DD
–122
–124
–126
–128
–130
–132
–134
DD
–136
10.17
10.19
10.21
10.23
10.25
10.27
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 31. Oscillator Feedthrough vs. Frequency, Wide Bandwidth
(VDD = 3.3 V)
Figure 30. Oscillator Feedthrough vs. Frequency, Zoomed in at 10.2 MHz
(VDD = 3.3 V)
Rev. D | Page 16 of 32
Data Sheet
ADGM1004
TEST CIRCUITS
The test circuits shown in Figure 32 to Figure 43 are applicable to all channels. Additional pins are omitted for clarity and VS is the source voltage.
V
V
DD
DD
0.1µF
0.1µF
V
OUT
50ꢀ
R
50ꢀ
L
V
S
V
V
DD
DD
RF1
RF2
RF1
RF2
V
OUT
R
50ꢀ
L
50ꢀ
NETWORK
ANALYZER
RFC
RFC
IN2
IN1
50ꢀ
50ꢀ
IN2
IN1
NETWORK
ANALYZER
V
S
V
IN2
V
IN2
RF3
RF4
RF3
RF4
V
IN1
V
IN1
50ꢀ
50ꢀ
50ꢀ
50ꢀ
IN4
IN3
IN4
IN3
V
IN4
V
IN4
GND
GND
GND
GND
V
IN3
V
IN3
Figure 32. Insertion Loss and Return Loss
Figure 34. Isolation (RF2 to RFC On, RF1 to RFC Off)
V
V
DD
DD
0.1µF
0.1µF
50ꢀ
NETWORK
ANALYZER
V
S
V
DD
V
DD
RF1
RF2
RF1
RF2
V
OUT
50ꢀ
R
50ꢀ
V
L
S
RFC
RFC
50ꢀ
V
OUT
R
50ꢀ
IN2
IN1
L
IN2
IN1
50ꢀ
NETWORK
ANALYZER
V
IN2
V
IN2
RF3
RF4
RF3
RF4
V
IN1
V
50ꢀ
50ꢀ
IN1
50ꢀ
50ꢀ
IN4
IN3
IN4
IN3
V
IN4
V
GND
GND
IN4
GND
GND
V
IN3
V
IN3
Figure 35. Crosstalk
Figure 33. Isolation (All Switches Off)
Rev. D | Page 17 of 32
ADGM1004
Data Sheet
V
DD
0.1µF
V
DD
RF1
RF2
NC
INTERNAL 50ꢀ
TERMINATION
RFC
OSCILLOSCOPE
IN2
IN1
1Mꢀ
V
V
DD
IN2
0.1µF
RFC
RF3
RF4
V
IN1
NC
NC
V
DD
V
OUT
RFx
50%
50%
V
IN4
IN3
R
L
INx
V
S
INx
50ꢀ
V
10%
90%
IN4
V
OUT
GND
GND
GND
GND
V
IN3
tON
tOFF
Figure 38. Switch Timing, tON and tOFF (All RFx Terminals Connected to
50 Ω Termination)
Figure 36. Video Feedthrough
V
V
DD
DD
0.1µF
0.1µF
V
V
DD
DD
RF1
RF2
RF1
50ꢀ
50ꢀ
RFC
50ꢀ
RFC
RF
AMPLIFIER
SPECTRUM
RF
ANALYZER
SOURCE
RF
SOURCE
INPUT
RF2
COMBINER
NETWORK
IN2
IN2
IN1
RF
SOURCE
V
IN2
IN1
V
IN2
RF3
RF4
RF3
RF4
V
V
IN1
IN1
50ꢀ
50ꢀ
50ꢀ
IN4
IN3
IN4
IN3
50ꢀ
V
V
IN4
IN4
GND GND
GND
GND
V
V
IN3
IN3
Figure 39. Hot Switching Evaluation Setup, 2 GHz RF Source, 50% Duty Cycle,
5 kHz Switching Actuation Speed
Figure 37. IP2 and IP3
Rev. D | Page 18 of 32
Data Sheet
ADGM1004
V
V
DD
DD
0.1µF
RF1
RF2
50ꢀ
RFC
SPECTRUM
ANALYZER
RF
SOURCE
IN2
IN1
V
V
DD
V
0.1µF
RFC
IN2
RF3
RF4
V
IN1
50ꢀ
50ꢀ
V
DD
RFx
IN4
IN3
INx
V
IN4
GND
GND
GND
GND
V
IN3
V
INx
Figure 40. On Resistance
Figure 42. Second and Third Harmonics, RF Power
V
V
DD
DD
0.1µF
0.1µF
V
V
DD
DD
RF1
RF1
A
A
6V
6V
–6V
RFC
RFC
A
RF2
–6V
V
–6V
RF2
A
NC
IN2
IN1
IN2
IN1
V
IN2
IN2
RF3
RF4
RF3
–6V
V
V
IN1
IN1
A
A
6V
6V
RF4
–6V
IN4
IN3
IN4
IN3
V
V
IN4
IN4
GND
GND
GND
GND
V
V
IN3
IN3
NC = NO CONNECT
NC = NO CONNECT
Figure 41. Off Leakage
Figure 43. On Leakage
Rev. D | Page 19 of 32
ADGM1004
Data Sheet
TERMINOLOGY
Insertion Loss
Second-Order Intermodulation Intercept (IP2)
Insertion loss is the amount of signal attenuation between the
input and output ports of the switch when the switch is in the
on state. Expressed in decibels, ensure that insertion loss is as
small as possible for maximum power transfer.
IP2 is the intersection point of the fundamental POUT vs. PIN
extrapolated line and the second-order intermodulation products
extrapolated line of a two-tone test. IP2 is a figure of merit that
characterizes the switch linearity.
An example calculation of insertion loss based on the setup in
Figure 32 is as follows:
Second Distortion Harmonic (HD2)
HD2 is the amplitude of the second distortion harmonic, where, for
a signal whose fundamental frequency is f, the second distortion
harmonic has a frequency of 2 f. This measurement is a single-
tone test expressed with reference to the carrier signal (dBc).
Insertion Loss (dB) = −20log10|SRF2RFC
|
where SRF2RFC is the transmission coefficient measured from RF2
to RFC with RF2 in the on position. All unused switches are in
the off position and terminated in a purely resistive load of 50 Ω.
Third Distortion Harmonic (HD3)
HD3 is the amplitude of the third distortion harmonic, where, for a
signal whose fundamental frequency is f, the third distortion
harmonic has a frequency of 3 f. This measurement is a single
tone test expressed with reference to the carrier signal (dBc).
Isolation
Isolation is the amount of signal attenuation between the input
and output ports of the switch when the switch is in the off
state. Expressed in decibels, ensure that isolation is as large as
possible.
On Switching Time (tON
)
tON is the time it takes for the switch to turn on. tON is measured
An example calculation of isolation based on the setup in Figure 33
is as follows:
from 50% of the control signal (INx) to 90% of the on level. No
power was applied through the switch during this test (cold
switched). The switch was terminated into a 50 Ω load.
Isolation (dB) = −20log10|SRFCRF1
|
where SRFCRF1 is the transmission coefficient measured from RFC
to RF1 with RF1 in the off position. All unused switches are in
the off position and terminated in a purely resistive load of 50 Ω.
Off Switching Time (tOFF
)
tOFF is the time it takes for the switch to turn off. tOFF is measured
from 50% of the control signal (INx) to 10% of the on level. No
power was applied through the switch during this test (cold
switched). The switch was terminated into a 50 Ω load.
Crosstalk
Crosstalk is a measure of unwanted signals coupled through
from one channel to another because of parasitic capacitance.
Actuation Frequency
The actuation frequency refers to the speed at which the
ADGM1004 can be switched on and off. The actuation
frequency is dependent on both the settling times and the on
and off switching times.
An example calculation of crosstalk based on the setup in
Figure 35 is as follows:
Crosstalk (dB) = −20log10|SRF1RF2
|
where SRF1RF2 is the transmission coefficient measured from RF1
to RF2 with RF1 in the off position and RF2 in the on position.
All unused switches are in the off position and terminated in a
purely resistive load of 50 Ω.
Power-Up Time
The power-up time is a measure of the time required for the
device to power up and start to pass 90% of an RF input signal
after the VDD pin reaches 95%.
Return Loss
Video Feedthrough
Return Loss is the magnitude of the reflection coefficient
expressed in decibels, and the amount of reflected signal relative
to the incident signal.
Video feedthrough is a measure of the spurious signals present
at the RFx ports of the switch when the control voltage is switched
from high to low or from low to high without an RF signal present.
An example calculation of return loss based on the setup in
Figure 32 is as follows:
Internal Oscillator Frequency
The internal oscillator frequency is the value of the on-board
oscillator that drives the gate control chip of the ADGM1004.
Return Loss (dB) = −20log10|S11|
where S11 is the reflection coefficient of the port under test.
Internal Oscillator Feedthrough
The internal oscillator feedthrough is the amount of internal
oscillator signal that feeds through to the RFx and RFC pins of
the switch. This signal appears as a noise spur on the RFx and
RFC pins of the switch at the frequency the oscillator is
operating at and the harmonics thereof.
Third-Order Intermodulation Intercept (IP3)
IP3 is the intersection point of the fundamental POUT vs. PIN
extrapolated line and the third-order intermodulation products
extrapolated line of a two-tone test. IP3 is a figure of merit that
characterizes the switch linearity.
Rev. D | Page 20 of 32
Data Sheet
ADGM1004
On Resistance (RON
)
Hot Switching
RON is the resistance of a switch in the closed/on state measured
Hot switching is operating the switch in a mode where a voltage
differential exists between the source and the drain when the
switch is closed and/or current is flowing from RFx to RFC
when the switch opens. Hot switching results in a reduced switch
life, depending on the magnitude of the open circuit voltage
between the source and the drain.
between the RFx and RFC package pins. Measure resistance in
4-wire mode to null out any cabling or PCB series resistances.
On Resistance Drift
On resistance drift is the change in the RON of the switch over
the specified criteria in Table 1.
Input High Voltage (VINH
INH is the minimum input voltage for Logic 1.
Input Low Voltage (VINL
INL is the maximum input voltage for Logic 0.
Input Current (IINL, IINH
INL and IINH are the low and high input currents of the digital
inputs.
Low Power Mode Current (IDD EXT VCP
DD EXT VCP is the amount of supply current used by the gate driver
)
Continuously On Lifetime
V
The continuously on lifetime parameter measures how long the
switch is left in a continuously on state. If the switch is left in
the on position for an extended period, this parameter affects
the turn off mechanism of the device.
)
V
)
Actuation Lifetime
I
Actuation lifetime is the number of consecutive open, close, and
open cycles that the device can complete without the RON
exceeding a specified limit and no occurrence of failures to
open (FTO) or failures to close (FTC).
)
I
circuity when the internal oscillator and the charge pump
circuitry are disabled by setting the EXTD_EN pin high.
Cold Switching
Cold switching operates the switch in a mode so that no voltage
differential exists between the source and the drain when the
switch is closed and/or no current is flowing from the source to
the drain when the switch opens. All switches have longer lives
when cold switched.
External Drive Current (ICP EXT VCP
)
I
CP EXT VCP is the amount of current used by the ADGM1004
from the external 80 V power supply when the internal
oscillator and the charge pump circuitry are turned off by
setting EXTD_EN pin high.
Rev. D | Page 21 of 32
ADGM1004
Data Sheet
THEORY OF OPERATION
The ADGM1004 is a wideband SP4T switch fabricated using
Analog Devices MEMS switch technology. This technology
enables high power, low loss, low distortion GHz switches for
use in demanding RF applications.
When the bias voltage between the gate and the source exceeds
the threshold voltage of the switch (VTH) the contacts on the
beam touch the drain, which completes the circuit between the
source and the drain and turns the switch on. When the bias
voltage is removed, that is, the 0 V on the gate electrode, the
beam acts as a spring generating a sufficient restoring force to
open the connection between the source and the drain, thus
breaking the circuit and turning the switch off.
The MEMS switch simultaneously brings together high
frequency RF performance and 0 Hz/dc precision performance.
This combination, coupled with superior reliability and a tiny
surface-mountable form factor, makes the MEMS switch an
ideal switching solution for all RF and precision signal
instrumentation needs.
The silicon cap covering the switch die is shown in Figure 44. This
cap hermetically seals the switch, which improves reliability.
The switch contacts do not suffer from dry switching or low power
switching lifetime degradation.
Figure 44 shows a cross section of the switch with dimensions.
The switch is an electrostatically actuated cantilever beam
connected in a 3-terminal configuration. Functionally, the switch is
analogous to a field effect transistor (FET). The terminals can
be used as a source, gate, or drain.
PARALLEL DIGITAL INTERFACE
The ADGM1004 is controlled via a parallel digital interface.
Standard complimentary metal-oxide semiconductor (CMOS)/
low voltage transistor to transistor logic (LVTTL) signals
applied through this interface control the actuation or release of
all ADGM1004 switch channels. Gate signals applied are
boosted to provide the required voltages required to actuate the
MEMS switch.
SILICON CAP
CANTILEVER BEAM
SOURCE
DRAIN
METAL
GATE
CONTACT GAP
Setting the
/SPI pin low enables the parallel digital interface
PIN
in 4-wire SP4T mode. In parallel mode, Pin 1 to Pin 4 (IN1 to
IN4) control the switching functions of the ADGM1004. When
a Logic 1 is applied to one of these pins, the gate of the
corresponding switch is activated and the switch turns on.
Conversely, when a Logic 0 is applied to one of these pins, the
switch turns off. Note that it is possible to connect more than
one RFx input to RFC at a time. See Table 6 for the ADGM1004
truth table.
SILICON
Figure 44. Cross Section of the MEMS Switch Design Showing the Cantilever
Switch Beam (Not to Scale)
When a dc actuation voltage is applied between the gate
electrode and the source (the switch beam), an electrostatic
force is generated, resulting in attracting the beam toward the
substrate. A separate on-board driver IC generates the 80 V bias
voltage used for actuation.
Table 6. Truth Table When in Parallel Digital Interface Mode
IN1
IN2
IN3
IN4
RF1 to RFC
RF2 to RFC
Off
RF3 to RFC
Off
RF4 to RFC
Off
0
0
0
0
Off
0
0
0
1
Off
Off
Off
On
0
0
1
0
Off
Off
On
Off
0
0
1
1
Off
Off
On
On
0
1
0
0
Off
On
Off
Off
0
1
0
1
Off
On
Off
On
0
1
1
0
Off
On
On
Off
0
1
1
1
Off
On
On
On
1
0
0
0
On
Off
Off
Off
1
0
0
1
On
Off
Off
On
1
0
1
0
On
Off
On
Off
1
0
1
1
On
Off
On
On
1
1
0
0
On
On
Off
Off
1
1
0
1
On
On
Off
On
1
1
1
0
On
On
On
Off
1
1
1
1
On
On
On
On
Rev. D | Page 22 of 32
Data Sheet
ADGM1004
Addressable Mode
SPI DIGITAL INTERFACE
Addressable mode is the default mode for the ADGM1004
upon power-up. A single SPI frame in addressable mode is bound
The ADGM1004 can be controlled via a digital SPI when the
/SPI pin is high. The SPI is compatible with SPI Mode 0
PIN
by a
falling edge and the succeeding
rising edge. The
CS
CS
(clock polarity (CPOL) = 0, clock phase (CPHA) = 0) and Mode 3
(CPOL = 1, CPHA = 1) and it operates with SCLK frequencies up
to 10 MHz. When the SPI is active, the default mode is
frame is comprised of 16 SCLK cycles. The timing diagram for
addressable mode is shown in Figure 45. The first SDI signal bit
indicates if the SPI command is a read or write command. The
next seven bits determine the target register address. The
remaining eight bits provide the data to the addressed register.
The first eight bits are ignored during a read command because
the SDO pin propagates out the data contained in the addressed
register during these clock cycles.
addressable, in which, the device registers are accessed by a 16-bit
SPI command that is bound by the state of the
pin. The
CS
ADGM1004 can also operate in daisy-chain mode.
The SPI interface pins of the ADGM1004 are , SCLK, SDI,
CS
pin low when using the SPI. The data on
and SDO. Hold the
CS
the SDI pin is captured on the rising edge of SCLK, and data is
propagated out on the SDO pin on the falling edge of SCLK. The
SDO pin has a push pull output driver architecture. Therefore,
the ADGM1004 does not require pull-up resistors. The two
modes of SPI operation are: addressable and daisy-chain.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates
out on the SDO pin from the 9th to the 16th SCLK falling edge
during SPI reads. A register write occurs on the 16th SCLK rising
edge during SPI writes. During any SPI command, the SDO pin
sends out eight alignment bits on the first eight SCLK falling
edges. The alignment bits observed at the SDO pin are 0x25.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
SDI
R/W A6
0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Figure 45. Addressable Mode Timing Diagram
Rev. D | Page 23 of 32
ADGM1004
Data Sheet
For the timing diagram of a typical daisy-chain SPI frame,
see Figure 48. When the
pin goes high, Device 1 writes
Daisy-Chain Mode
CS
The connection of several ADGM1004 devices in a daisy-chain
Command 0, Bits[7:0], to the SWITCH_DATA register, Device 2
writes Command 1, Bits[7:0], to the switches, and so on. The
SPI block uses the last eight bits received through the SDI pin to
update the switches. After entering daisy-chain mode, the first
configuration is possible. All devices share the same
and
CS
SCLK lines while the SDO pin of one device forms a connection
to the SDI pin of the next device, creating a shift register. In
daisy-chain mode, the SDO signal is an 8-cycle delayed version
of the SDI signal (see Figure 47).
eight bits sent out by the SDO pin are 0x00. When
goes
CS
high, the internal shift register value does not reset back to 0.
The ADGM1004 can only enter daisy-chain mode from
addressable mode by sending the 16-bit SPI command, 0x2500.
See Figure 47 for an example of this command. When the
ADGM1004 receives this command, the SDO pin of the devices
sends out the same command because the alignment bits at the
SDO pin are 0x25. This command allows multiple daisy-
chained devices to enter daisy-chain mode in a single SPI frame.
A hardware reset is required to exit daisy-chain mode.
An SCLK rising edge reads in data on the SDI pin while data is
propagated out of the SDO pin on an SCLK falling edge. The
expected number of SCLK cycles are a multiple of eight before
the
pin goes high. When this is not the case, the SPI
CS
interface sends the last eight bits received to the
SWITCH_DATA register.
DEVICE 1
DEVICE 2
ADGM1004
ADGM1004
RF2
RF3
RF4
RF2
RFC
RFC
RF3
RF4
SDO
SDO
SPI
INTERFACE
SPI
INTERFACE
SDI
CS
SCLK
Figure 46. Two SPI Controlled ADGM1004 Switches Connected in Daisy-Chain Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
SDI
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Figure 47. SPI Command to Enter Daisy-Chain Mode
CS
SDI
COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0]
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
SDO
8’h00
8’h00
8’h00
COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0]
SDO2
SDO3
8’h00
8’h00
COMMAND3[7:0] COMMAND2[7:0]
8’h00 COMMAND3[7:0]
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 48. Example of SPI Frame with Three ADGM1004 Switches Connected in Daisy-Chain Mode
Rev. D | Page 24 of 32
Data Sheet
ADGM1004
Hardware Reset
INTERNAL OSCILLATOR FEEDTHROUGH
MITIGATION
The digital section of the ADGM1004 goes through an
initialization phase during VDD power-up. To hardware reset the
device, power cycle the VDD input. After power-up or a hardware
reset, ensure that there is a minimum of 10 μs from the time of
power-up or reset before any SPI command is issued. Ensure that
In normal operation, the 80 V actuation voltage is supplied by
the driver IC. Setting the EXTD_EN pin low enables the built in
10 MHz oscillator. This setting enables the charge pump circuitry
to generate the 80 V required for MEMS switch actuation. The
internal oscillator is a source of noise that couples through to
the RF ports. The magnitude of this feedthrough noise spur is
specified in Table 1 and is typically −123 dBm or −146 dBm/Hz
when one switch is on. To eliminate the internal oscillator
feedthrough, set the EXTD_EN pin high to disable the internal
oscillator and charge pump circuitry. When the internal oscillator
and charge pump circuitry is disabled, the VCP pin must be
driven with 80 V dc (VCPEXT) from an external voltage supply
required for MEMS switch actuation, as shown in Table 5. The
switch can still be controlled via the digital logic interface pins.
V
V
DD does not drop out during the 10 μs initialization phase because
DD dropout can result in incorrect operation of the ADGM1004.
Internal Error Status
When an internal error is detected in the device, the internal
error is flagged by the INTERNAL_ERROR bits (Bits[7:6]) of
the SWITCH_DATA register (Register 0x20), as shown in Table 9.
An internal error results from an error in the configuration of
the device at power up.
INTERNAL OSCILLATOR FEEDTHROUGH
The ADGM1004 has an internal oscillator running at a nominal
10 MHz. This oscillator drives the charge pump circuitry that
provides the actuation voltage for each switch gate electrode.
Although this oscillator is low power, the 10 MHz signal is
coupled to the switch and is considered a noise spur on the
switch channels. The magnitude of this feedthrough noise spur is
specified in Table 1 and is typically −123 dBm or −146 dBm/Hz
when one switch is on. When all four switches are simultaneously
on, the feedthrough goes up to −120 dBm. VDD level and
temperature changes affect the frequency of the noise spur. For
the maximum and minimum frequency range over temperature
and voltage supply range, see Table 1.
LOW POWER MODE
Setting the EXTD_EN pin high shuts down the internal
oscillator. The ADGM1004 enters a low power quiescent state,
drawing only 50 μA maximum supply current.
Rev. D | Page 25 of 32
ADGM1004
Data Sheet
reference clock to the driver IC control circuit. Alternatively, set
the EXTD_EN pin high and apply 80 V dc directly to the VCP pin
to disable the internal oscillator and eliminate all oscillator
feedthrough. The switches can then be controlled normally via
the logic control interface, IN1 to IN4.
TYPICAL OPERATING CIRCUIT
Figure 49 shows the typical operating circuit for the ADGM1004
as used in the EVAL-ADGM1004SDZ evaluation board. A 47 pF
(100 V rated) external capacitor (CCP) is required on the VCP pin.
This capacitor is a holding capacitor for the 80 V dc gate drive
voltage.
To avoid any floating nodes, connect a 10 MΩ shunt resistor to
GND on all RFx pins (RF1 to RF4, and RFC), as shown in
Figure 49. See the Floating Node section for more information.
In the circuit shown in Figure 49, VDD is connected to 3.3 V. EP1
connects to EP2 internally. Typically, one large GND pad on the
PCB is used to short together EP1 and EP2. Figure 49 shows the
ADGM1004 configured to use the internal oscillator as the
3.3V
0.1µF
RF2 IN
RF1 IN
10Mꢀ*
10Mꢀ*
47pF
24
23
22
21
20
19
18
GND
GND
RFC
17
16
IN1
IN2
IN3
1
2
3
4
5
IN1
IN2
ADGM1004
RFOUT
15
14
13
IN3
IN4
TOP VIEW
10Mꢀ*
GND
GND
IN4
GND
6
7
10
10Mꢀ*
11
12
8
9
10Mꢀ*
RF4 IN
RF3 IN
*10Mꢀ RESISTORS ARE REQUIRED TO AVOID ANY FLOATING NODES. FOR MORE INFORMATION,
REFER TO THE FLOATING NODES SECTION.
Figure 49. Typical Operating Circuit
Rev. D | Page 26 of 32
Data Sheet
ADGM1004
APPLICATIONS INFORMATION
SWITCHABLE RF ATTENUATOR
RECONFIGURABLE RF FILTER
RF attenuator networks are commonly used in RF instrumentation
equipment, such as vector network analyzers, spectrum analyzers,
and signal generators. Routing RF signals through an attenuator
can enable the equipment to accept higher power signals and,
therefore, increase the dynamic range of the instrument. In
RF attenuation applications like the vector network analyzers,
spectrum analyzers, and signal generators, maintaining the
bandwidth of the signal after the signal passes through the
network is critical. Any degradation of the signal reduces the
performance of the equipment. Therefore, the RF characteristics
of the switches used for routing are an integral part of the quality
of an attenuator network.
A reconfigurable RF filter is advantageous in many RF front-
end applications. A reconfigurable RF filter provides more saved
space. As space becomes more constrained in applications, the
option to have an economical reconfigurable RF filter instead of
individual frequency dependent filters is preferred.
The ADGM1004 low flat insertion loss, wide RF bandwidth,
low parasitic, low capacitance, and high linearity are required to
turn on the lump components (capacitor and inductor), which
make the MEMS switch suited for reconfigurable filter application.
In applications such as wireless communications or mobile radios,
the number of bands and/or modes constantly increases. A
reconfigurable RF filter allows more bands and/or modes to be
covered using the same components.
The ADGM1004 MEMS switch with low flat insertion loss, wide
RF bandwidth, and high reliability is suited for use as a switchable
RF attenuator. The ADGM1004, as an SP4T switch, also brings
added flexibility. Figure 50 shows an example attenuation
network configuration using two ADGM1004 switches and
three different attenuators. The fourth channel of the switches is
used as a nonattenuated route in Figure 50.
Figure 51 shows an example of a reconfigurable band-pass filter.
The topology shown is of a generalized, two section, inductively
coupled, single-ended band-pass filter, nominally centered on a
400 MHz ultrahigh frequency (UHF) band. The MEMS switches
are positioned in series with each shunt inductor.
The function of the switches includes or omits a shunt inductor
from the circuit. Changing the shunt inductor value affects the
bandwidth and center frequency of the filter. Using inductance
values from 15 nH to 30 nH significantly alters the bandwidth
and center frequency, allowing the filter to dynamically configure
to operate in the UHF bands or very high frequency (VHF)
bands while preserving the 50 Ω match on the input and output
ports. The low RON value and wide bandwidth of the MEMS
switch makes the switch an ideal choice for this application. The
low RON reduces the negative effect a series resistance has on the
quality factor of the shunt inductor. The large bandwidth enables
higher frequency band-pass filters.
15dB
10dB
I/O
I/O
ADGM1004
ADGM1004
5dB
Figure 50. Switching RF Attenuators Using Two ADGM1004 MEMS Switches
22nH
INPUT
OUTPUT
50ꢀ
50ꢀ
13pF
13pF
24nH
30nH
18nH
15nH
15nH
18nH
30nH
24nH
GND
Figure 51. Reconfigurable Band-Pass Filter Achieved Using Two ADGM1004 MEMS Switches
Rev. D | Page 27 of 32
ADGM1004
Data Sheet
CRITICAL OPERATIONAL REQUIREMENTS
SYSTEM ERROR CONSIDERATIONS DUE TO
ON-RESISTANCE DRIFT
FLOATING NODE
The ADGM1004 has no internal impedance to ground, and
charges can develop on the switch terminals leading to unreliable
switch behavior To mitigate this behavior, provide a discharge
path to all switch nodes. Figure 53 to Figure 56 show examples
of cases to avoid where floating nodes can occur when using the
switch. Conditions to avoid include the following:
The RON performance of the ADGM1004 is affected by part to
part variation, channel to channel variation, cycle actuations,
settling time post turn on, bias voltage, and temperature changes
(see Figure 6 to Figure 13).
In a 50 Ω system, the on-resistance drift over switch actuations
(ΔRON) can introduce system inaccuracy. Figure 52 shows the
ADGM1004 connected with the load in a 50 Ω system, where
RS is the source impedance. TO calculate the system error
caused by the ADGM1004 on-resistance drift, use the following
equation:
Leaving the RFx pins open circuit (see Figure 53).
Connecting a series capacitor directly to the switch (see
Figure 54).
Connecting the RFx pin of two switches together directly
or connecting the RFC pin to the RFx pin (see Figure 55
and Figure 56).
System Error (%) = ΔR/RLOAD
where:
RFx
RFC
OPEN CIRCUIT
ΔR is the ADGM1004 on-resistance drift.
FLOATING
R
LOAD is the load impedance.
The ADGM1004 on-resistance drift also affects insertion loss,
which must be considered when using the device. To calculate
the on-resistance impact on insertion loss, use the following
equation:
Figure 53. RFx Pins Left Open Circuit
RFx
RFC
FLOATING
Insertion Loss = 10log(1 + (ΔR/RLOAD))
RS
50ꢀ
∆R
Figure 54. Series Capacitor Directly Connected to MEMS Switch
RFC
RFx
RFx
RFC
R
50ꢀ
LOAD
VS
FLOATING
Figure 52. 50 Ω System Representation Where the ADGM1004 is Connected
with the Load
Figure 55. RFx Pins of Two MEMS Switches Directly Connected
RFx
RFC
RFC
RFx
Table 7. System Error and Insertion Loss Error Due to
ADGM1004 RON Drift
FLOATING
System
Error (%)
On-Resistance Drift
Insertion Loss Error (dB)
Figure 56. RFC Connected to RFx
4.75
5
9.5
10
0.39
0.41
Provide a discharge path to the switch nodes to avoid floating
nodes. In a typical application, a 50 Ω termination connected to
the switch provides this path. Driving switch nodes with a
device of adequate impedance (<10 MΩ) provides a discharge
path. If there is no discharge path in the application circuit, add
a 10 MΩ shunt resistor or inductor on the source RFx pin of the
MEMS switch to provide the discharge path. Note that the
shunt resistors introduce leakage. Figure 57 shows an example
of a configuration providing a discharge path.
RFx
RFC
OR
OR
Figure 57. Switch Configuration Providing a Discharge Path
Rev. D | Page 28 of 32
Data Sheet
ADGM1004
HANDLING PRECAUTIONS
Electrical Overstress (EOS) Precautions
Figure 58 and Figure 59 illustrate typical cascaded switch use cases
and the corresponding schemes to mitigate floating node risks.
The ADGM1004 is susceptible to EOS. Therefore, take the
following precautions:
RF1
RF1
RF2
RF3
RF4
RF2
ADGM1004 RF3
RF4
RFC
RFC
ADGM1004
The ADGM1004 is an ESD sensitive device. Ensure to take
all of the normal handling precautions, including working
only on static dissipative surfaces, wearing wrist straps or
other ESD control devices, and storing unused devices in
conductive foam.
Avoid running measurement instruments, such as digital
multimeters (DMMs), in autorange modes. Some
instruments generate large transient compliance voltages
when switching between ranges.
Figure 58. Two ADGM1004 Devices Connected in Path Selection
Configuration with 10 MΩ Shunt Resistors to Mitigate Floating Nodes
RF1
RF2
RFC
ADGM1004
RF3
RF1
RF2
RF4
RFC
Use the highest practical DMM range setting (the lowest
resolution) for resistance measurements to minimize
compliance voltages, particularly during switching.
Discharge coaxial cables before connecting directly to the
switch. Note that coaxial cables can store charge and lead
to EOS when directly connected to the switch.
Avoid connecting large capacitive terminations directly to
the switch, as shown in Figure 61. A shunt capacitor can
store a charge that potentially leads to hot switching events
when the switch opens or closes, affecting the lifetime of
the switch.
ADGM1004
RF3
RF4
RF1
RF2
RFC
ADGM1004
RF3
RF4
Figure 59. Three ADGM1004 Devices Connected in Fanout Configuration
with 10 MΩ Shunt Resistors to Mitigate Floating Nodes
Avoid connecting shunt capacitors directly to the switch. A
capacitor can store a charge and potentially lead to hot switching
events when the switch opens or closes if there are no alternative
discharge paths. These events affect the cycle lifetime of the switch.
RFx
RFC
CUMULATIVE ON SWITCH LIFETIME
Leaving the switch in an on state for a long period affects the
lifetime of the switch because of mechanical degradation effects.
These effects can result in the switch failing to turn off. Figure 60
shows a failure rate at 50°C where the mean time to failure is
7.2 years (2628 days), resulting in 50% of the sample lot failing
at this point.
Figure 61. Avoid Having a Large Capacitor Directly Connected to the
MEMS Switch
Temperatures above 50°C further reduce the switch lifetime.
The cumulative on switch lifetime specification is also duty cycle
dependent. If the user operates the MEMS switch with a duty
cycle of less than 50% the lifetime of the MEMS switch improves.
99
V
= 3.3V
DD
90
70
30
10
1
10
100
1,000
10,000
100,000
CONTINUOUSLY ON TIME (DAYS)
Figure 60. Cumulative On Switch Lifetime at 50°C, VDD = 3.3 V,
Sample Size 31 Parts
Rev. D | Page 29 of 32
ADGM1004
Data Sheet
Mechanical Shock Precautions
Figure 62 shows examples of loose device handling situations to
avoid for risk of mechanical shock and ESD events.
The ADGM1004 passes extensive mechanical shock
qualification tests, as described in Table 8. These tests validate
the robustness of the device when exposed to normal
mechanical shocks.
NOT RECOMMENDED
Table 8. Mechanical Qualification Summary
Parameter
Qualification
Mechanical Shock
Random Drop
Powered (PMS) IEC 60068-2-27
AEC-Q100 Test G5, five drops from
0.6 m
DEVICES STORED BULK
IN BINS
DEVICES DUMPED OUT
ON BENCHTOP
Vibration Testing
MIL-STD-883, M2007.3, Condition B,
20 Hz to 2000 Hz at 50 g
Group D, Sub 4, MIL-
STD-883, M5005
Mechanical shock, 1500 g, 0.5 ms;
vibration 50 g sine sweep, 20 Hz to
2000 Hz; acceleration 30,000 g
DEVICE DROPPED
Do not use the ADGM1004 if dropped. Ensure minimal
mechanical shocks during the handling and manufacturing of
the device.
Figure 62. Situations to Avoid During Handling
Rev. D | Page 30 of 32
Data Sheet
ADGM1004
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x20, Reset: 0x00, Name: SWITCH_DATA
The switch data register controls the status of the four ADGM1004 switches.
Table 9. Bit Descriptions for SWITCH_DATA
Bits
Bit Name
Description
Reset
Access
[7:6]
INTERNAL_ERROR
Internal Error Detection. These bits determine if an internal error has occurred.
00: no error detected.
01: error detected.
0x0
R
10: error detected.
11: error detected.
[5:4]
3
RESERVED
SW4_EN
Reserved. These bits are reserved. Set these bits to 0.
Enable for Switch 4.
0x0
0x0
R
R/W
0: Switch 4 open.
1: Switch 4 closed.
2
1
0
SW3_EN
SW2_EN
SW1_EN
Enable for Switch 3.
0: Switch 3 open.
1: Switch 3 closed.
0x0
0x0
0x0
R/W
R/W
R/W
Enable for Switch 2.
0: 00: Switch 2 open.
1: Switch 2 closed.
Enable for Switch 1.
0: Switch 1 open.
1: Switch 1 closed.
Rev. D | Page 31 of 32
ADGM1004
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.33 NOM
1.30 NOM
5.10
5.00
4.90
0.16 NOM
1.47 NOM
PIN 1
INDICATOR
PIN 1
IONS
INDIC ATOR AREA OPT
(SEE DETAIL A)
0.50
BSC
18
24
17
1
4.10
4.00
3.90
*
*
EXPOSED
PA D
EXPOSED
PA D
2.15 NOM
5
13
12
6
0.65
0.55
0.45
BOTTOM VIEW
TOP VIEW
SIDE VIEW
1.50
1.45
1.40
*
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
0.08
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.15 REF
0.30
0.25
0.18
Figure 63. 24-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 4 mm Body, and 1.45 mm Package Height
(CP-24-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
0°C to 85°C
0°C to 85°C
Package Description
Package Option
CP-24-4
CP-24-4
ADGM1004JCPZ-R2
ADGM1004JCPZ-RL7
EVAL-ADGM1004SDZ
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2017–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15173-0-11/19(D)
Rev. D | Page 32 of 32
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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