ADGM1304 [ADI]
Fully operational down to 0 Hz/dc;型号: | ADGM1304 |
厂家: | ADI |
描述: | Fully operational down to 0 Hz/dc |
文件: | 总21页 (文件大小:595K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
0 Hz/DC to 14 GHz, Single-Pole, Four-Throw
MEMS Switch with Integrated Driver
ADGM1304
Data Sheet
FEATURES
GENERAL DESCRIPTION
Fully operational down to 0 Hz/dc
Actuation lifetime: 1 billion cycles (minimum)
−3 dB bandwidth
11 GHz (typical) for RF1, RF4
14 GHz (typical) for RF2, RF3
Insertion loss: 0.26 dB (typical) at 2.5 GHz
Isolation: 24 dB (typical) at 2.5 GHz
High linearity IIP3: 69 dBm (typical)
On switching time: 30 μs (typical)
Radio frequency (RF) power rating: 36 dBm (maximum)
On resistance 1.6 Ω (typical)
Supply voltage: 3.1 V to 3.3 V nominal
Hermetically sealed switch contacts
Integrated driver removes the need for an external driver
CMOS-/LVTTL-compatible
The ADGM1304 is a wideband, single-pole, four-throw (SP4T)
switch, fabricated using Analog Devices, Inc., microelectro-
mechanical system (MEMS) switch technology. This technology
enables a small, wide bandwidth, highly linear, low insertion
loss switch that is operational down to 0 Hz/dc, making it an
ideal switching solution for a wide range of RF applications.
An integrated control chip generates the high voltage necessary
to electrostatically actuate the switch via a complementary metal-
oxide semiconductor (CMOS)-/low voltage transistor-transistor
logic (LVTTL)-compatible parallel interface. All four switches are
independently controllable.
The ADGM1304 is packaged in a 24-lead, 5 mm × 4 mm ×
0.95 mm, lead frame chip-scale package (LFCSP).
Parallel interface
I
DD sleep mode current: 1 μA typical power consumption
24-lead, 5 mm × 4 mm × 0.95 mm, LFCSP
APPLICATIONS
Relay replacements
Automatic test equipment (ATE): RF/digital/mixed signals
Load/probe boards: RF/digital/mixed signals
RF test instrumentation
Reconfigurable filters/attenuators
High performance RF switching
FUNCTIONAL BLOCK DIAGRAM
C
CP
V
V
EXTCLK
CLKSEL
MUX
DD
CP
RF1
RF2
ADGM1304
CHARGE
PUMP
÷2
V
CP
OSCILLATOR
REGULATOR
REFERENCE
AND BIAS
SLEEP
LEVEL
LV
LV
LV
LV
HV
IN1
IN2
SHIFTER
LEVEL
SHIFTER
RFC
HV
HV
HV
LEVEL
SHIFTER
IN3
IN4
LEVEL
SHIFTER
AGND
RFGND
RF4
RF3
NOTES
1. LV = LOW VOLTAGE.
HV = HIGH VOLTAGE.
Figure 1.
Rev. C
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
ADGM1304
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver IC Oscillator ................................................................... 15
External Clock (EXTCLK)........................................................ 15
Typical Operating Circuit ......................................................... 16
Applications Information .............................................................. 17
Floating Node Avoidance.......................................................... 17
Continuously on Lifetime ......................................................... 18
Suggested Application Circuits..................................................... 19
Switchable RF Attenuator.......................................................... 19
Reconfigurable RF Filter ........................................................... 19
Handling Precautions .................................................................... 20
ESD Precautions ......................................................................... 20
Electrical Overstress (EOS) Precautions................................. 20
Mechanical Shock Precautions ................................................. 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 21
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 10
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 14
Digital Interface .......................................................................... 14
Sleep Mode (SLEEP) .................................................................. 14
REVISION HISTORY
10/2016—Revision C: Initial Version
Rev. C | Page 2 of 21
Data Sheet
ADGM1304
SPECIFICATIONS
VDD = 3.3 V, AGND = 0 V, RFGND = 0 V, all specifications TMIN to TMAX = 0°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Min Typ 1
Max Unit
Test Conditions/Comments2
DYNAMIC CHARACTERISTICS
−3 dB Bandwidth3
RF1, RF4
RF2, RF3
Insertion Loss3
BW
9.3
12
11
14
0.26
0.4
24
19
30
24
18
69
GHz
GHz
0.55 dB
RF1 to RFC and RF4 to RFC channels
RF2 to RFC and RF3 to RFC channels
At 2.5 GHz; RFC to RFx channel; 25°C
At 6.0 GHz; RFC to RFx channel; 25°C
At 2.5 GHz; RFC to RFx channel
At 6.0 GHz; RFC to RFx channel
At 2.5 GHz; RFx to RFx channel
At 6.0 GHz; RFx to RFx channel
Up to 6.0 GHz
IL
0.9
dB
dB
dB
dB
dB
dB
dBm
Isolation3
ISO
CTK
23
17
27
22
13
Crosstalk3
Return Loss3
Input Third-Order Intermodulation
Intercept
RL
IIP3
Input: 900 MHz and 901 MHz;
input power = 27 dBm
Input Second-Order Intermodulation
Intercept
IIP2
119
dBm
Input: 900 MHz and 901 MHz;
input power = 27 dBm
Second Harmonic
HD2
HD2
−90
−85
dBc
dBc
Input: 5.4 MHz; input power = 0 dBm
Input: 150 MHz and 800 MHz;
input power = 36 dBm
Third Harmonic
HD3
−85
dBc
Input: 150 MHz and 800 MHz;
input power = 36 dBm
Total Harmonic Distortion and Noise
RF Power Rating3, 4
DC Voltage Range
Time
THD + N
−110
dBc
dBm
V
RL = 300 Ω, f = 1 kHz, RFx pin = 2.5 V p-p
50 Ω termination
On switch dc voltage operation range
36
+6
−6
On Switching
Off Switching
tON
tOFF
30
5
75
30
µs
µs
50% INx pin to 90% RFx pin, 50 Ω termination
50% INx pin to 10% RFx pin, 50 Ω termination
Settling
Rising Edge3
40
8
µs
µs
50% INx pin to 0.05 dB final IL value,
50 Ω termination
50% INx pin to 0.05 dB final IL value,
50 Ω termination
Falling Edge3
Wake-Up
Actuation Frequency3
Video Feedthrough3
Internal Oscillator Frequency
Internal Oscillator Feedthrough3, 5
0.55
1.2
5
ms
kHz
CCP = 47 pF; 50% INx pin to 90% RFx pin
All switches toggled simultaneously
16
mV peak 1 MΩ termination
MHz
dBm
7.9
15
−115
Spectrum analyzer resolution bandwidth
(RBW) = 200 Hz; one switch in on state, all
others off with 50 Ω terminations
SWITCH PROPERTIES
On Resistance
On Resistance Stability3
RON
ΔRON
1.6
1.4
3.6
Ω
Ω
IDS = 50 mA, 0 V to 6 V
109 actuations; full temperature range;
1 kHz cycling frequency;
220 mA load between toggles
RF Port
On Capacitance3
Off Capacitance3
On Leakage
CRF On
CRF Off
3.3
1.6
pF
pF
nA
At 1 MHz
At 1 MHz
RFx (off channels) = 6 V;
5
RFC/RFx (on channel) = −6 V
Off Leakage
Continuously On Lifetime3
Actuation Lifetime3
0.5
nA
Years
Cycles
RFx pin = 6 V; RFC = −6 V
7.2
Median time before failure6 at 50°C
109
Cold switched; load between toggling is
220 mA; tested at 85°C
Rev. C | Page 3 of 21
ADGM1304
Data Sheet
Parameter
Symbol
Min Typ 1
Max Unit
Test Conditions/Comments2
EXTCLK PROPERTIES
EXTCLK Input Range
EXTCLK Input High Voltage
EXTCLK Input Low Voltage
EXTCLK Input Current
DIGITAL INPUTS
20
1.5
23
MHz
V
V
EVINH
EVINL
EIINL/EIINH
0.5
10
µA
EVIN = EVINL or EVINH
Input High Voltage
Input Low Voltage
Input Current
VINH
VINL
IINL/IINH
2
V
V
µA
0.8
1
0.025
VIN = VINL or VINH
POWER REQUIREMENTS
Supply Voltage
Supply Current
VDD
IDD
3.1
2.9
1
3.3
3.2
V
mA
µA
VDD = 3.3 V; digital inputs = 0 V or 3.3 V
IDD Sleep Mode Current
1 Typical specifications tested at 25°C with VDD = 3.3 V.
2 RFx is the RF1, RF2, RF3, and RF4 pins, and INx is the IN1, IN2, IN3, and IN4 pins.
3 Guaranteed by design, not subject to production test.
4 The 1 dB compression point (P1dB) is not reached up to the maximum power rating of the switch.
5 Disable the internal oscillator to eliminate feedthrough. See the Driver IC Oscillator section and the External Clock (EXTCLK) section.
6 This value shows the median time it takes for 50% of a sample lot to fail.
Rev. C | Page 4 of 21
Data Sheet
ADGM1304
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 2.
Parameter
Rating
VDD to AGND
Digital Inputs1
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V or 30 mA
(whichever occurs first)
10 V
250 mA
DC Voltage Rating2
Current Rating2
RF Power Rating
Stand Off Voltage3
Only one absolute maximum rating can be applied at any
one time.
37 dBm
100 V (RFC pin)
20 V (RFx pins)
0 V
−0.3 V to VDD + 0.3 V or 30 mA
(whichever occurs first)
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Hot Switching4
EXTCLK Input Voltage
Operating Temperature Range
Storage Temperature Range
Reflow Soldering (Pb-Free)
Peak Temperature
0°C to +85°C
−65°C to +150°C
Table 3. Thermal Resistance
Package Type
CP-24-91
θJA
θJC
Unit
49.1
11.5
°C/W
260(+0/−5)°C
10 sec to 30 sec
1 See JEDEC standard JESD51-2 for additional information on optimizing the
thermal impedance (PCB with 3 × 3 vias).
Time at Peak Temperature
ESD
Human Body Model (HBM)5
RF1 to RF4 Pins and RFC Pin 100 V
ESD CAUTION
All Other Pins
2.5 kV
Field-Induced Charged-
Device Model (FICDM)6
All Pins
500 V
Group D
Mechanical Shock7
1500 g with 0.5 ms pulse
Vibration
20 Hz to 2000 Hz acceleration at
50 g
Constant Acceleration
30,000 g
1 Clamp overvoltages at INx pin by internal diodes. Limit the current to the
maximum ratings given.
2 This rating is with respect to the switch in the on position with no RF signal
applied.
3 This rating is with respect to the switch in the off position.
4 Hot switching is not recommended.
5 Take proper precautions during handling as outlined in the Handling
Precautions section.
6 A safe automated handling and assembly process is achieved at this rating
level by implementing industry-standard ESD controls.
7 If the device is dropped during handling, do not use the device.
Rev. C | Page 5 of 21
ADGM1304
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN1 1
IN2 2
IN3 3
17 RFGND
16 RFGND
15 RFC
14 RFGND
13 RFGND
ADGM1304
TOP VIEW
IN4 4
EP1
EP2
EXTCLK 5
NOTES
1. EXPOSED PAD 1. EP1 IS INTERNALLY CONNECTED TO AGND.
IT IS RECOMMENDED TO CONNECT TO BOTH AGND AND REFGND.
2. EXPOSED PAD 2. EP2 IS INTERNALLY CONNECTED TO RFGND.
IT IS RECOMMENDED TO CONNECT TO BOTH REFGND AND AGND.
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
IN1
Digital Control Input 1. The voltage applied to this pin controls the gate of the MEMS switch RF1 to RFC.
If IN1 is low, RF1 to RFC is open (off). If IN1 is high, connect RF1 to RFC (on).
2
3
4
5
IN2
Digital Control Input 2. The voltage applied to this pin controls the gate of the MEMS switch RF2 to RFC.
If IN2 is low, RF2 to RFC is open (off). If IN2 is high, connect RF2 to RFC (on).
Digital Control Input 3. The voltage applied to this pin controls the gate of the MEMS switch RF3 to RFC.
If IN3 is low, RF3 to RFC is open (off). If IN3 is high, connect RF3 to RFC (on).
Digital Control Input 4. The voltage applied to this pin controls the gate of the MEMS switch RF4 to RFC.
If IN4 is low, RF4 to RFC is open (off). If IN4 is high, connect RF4 to RFC (on).
External Clock Input. The ADGM1304 has a built-in oscillator that drives the internal driver boost circuitry. An
external clock source provided by the EXTCLK pin can disable and replace this internal oscillator. To enable
the EXTCLK pin, set the CLKSEL pin to high. See the Specifications section for the allowable input range for
the EXTCLK pin. In normal operation, when not using an external clock source, EXTCLK must be connected
to ground.
IN3
IN4
EXTCLK
6
7
SLEEP
Digital Input Pin. This feature shuts down internal circuitry, thereby reducing current consumption to
minimum levels. If SLEEP is low, the ADGM1304 is in normal operating mode. If SLEEP is high, the
ADGM1304 is in power-down mode, and the RFx pins are in a high impedance state.
Internal Oscillator Control. In normal operation, set CLKSEL low and use the built-in oscillator to clock the
driver boost circuitry. When CLKSEL is high, an external clock source on the EXTCLK pin can drive the boost
circuitry. Note that setting CLKSEL high and EXTCLK low disables the internal oscillator and driver boost
circuitry. Disabling the internal oscillator eliminates associated noise feedthrough into the switch. In this
configuration, supply 80 V to the VCP pin to drive the switches via the IN1 to IN4 pins
CLKSEL
8, 22
9, 11, 13, 14,
16, 17, 19, 21
AGND
RFGND
Analog Ground Connection.
RF Ground Connection
10
12
15
18
20
23
RF4
RF3
RFC
RF2
RF1
VDD
RF4 Port. This pin can be an input or an output. If unused, connect this pin to RFGND.
RF3 Port. This pin can be an input or an output. If unused, connect this pin to RFGND.
Common RF Port. This pin can be an input or an output.
RF2 Port. This pin can be an input or an output. If unused, connect this pin to RFGND.
RF1 Port. This pin can be an input or an output. If unused, connect this pin to RFGND.
Positive Power Supply Input. For the recommend input voltage for this chip, see the Specifications section.
Boost up the input voltage internally to generate the voltage required to turn on the MEMS switch.
24
VCP
Charge Pump Capacitor Terminal. The recommended capacitor value is 47 pF. To disable the internal
oscillator, set the CLKSEL pin high and the EXTCLK pin low. Disabling the internal oscillator eliminates
associated noise feedthrough into the switch. Applying 80 V to the VCP pin to drive the switches via the IN1
to IN4 pins.
EP1
EP2
Exposed Pad 1. EP1 is internally connected to AGND. It is recommended to connect to both AGND and RFGND.
Exposed Pad 2. EP2 is internally connected to RFGND. It is recommended to connect to both RFGND and AGND.
Rev. C | Page 6 of 21
Data Sheet
ADGM1304
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
25°C RF1
25°C RF2
+85°C RF1
+25°C RF1
0°C RF1
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
10M
100M
1G
10G
100G
0
2
4
6
8
10
12
14
16
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 3. Insertion Loss vs. Frequency on Linear Scale (VDD = 3.3 V)
Figure 6. Insertion Loss vs. Frequency over Temperature on Log Scale
(VDD = 3.3 V, RF1 to RFC)
0
25°C RF1
25°C RF2
+85°C RF1
+25°C RF1
0°C RF1
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
10M
100M
1G
10G
100G
0
2
4
6
8
10
12
14
16
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 4. Insertion Loss vs. Frequency on Log Scale (VDD = 3.3 V)
Figure 7. Insertion Loss vs. Frequency over Temperature on Linear Scale
(VDD = 3.3 V, RF1 to RFC)
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
0
0
T
V
= 25°C
= 3.3V
T
= 25°C
V = 3.3V
DD
A
A
DD
–10
–20
–30
–40
–50
–60
–70
–80
–10
–20
–30
–40
–50
–60
–70
–80
RF1 TO RFC
RF2 TO RFC
INSERTION LOSS
OFF ISOLATION
RETURN LOSS
0
50M
100M
150M
200M
0
2
4
6
8
10
FREQUENCY (Hz)
FREQUENCY (GHz)
Figure 5. Insertion Loss and Off Isolation/Return Loss vs.
Frequency (VDD = 3.3 V, RF1 to RFC)
Figure 8. Off Isolation vs. Frequency (VDD = 3.3 V)
Rev. C | Page 7 of 21
ADGM1304
Data Sheet
0
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
–0.50
T
V
= 25°C
= 3.3V
A
T
V
= 25°C
= 3.3V
A
DD
–10
DD
RF1 TO RF2
RF2 TO RF1
–20
–30
–40
–50
–60
–70
–80
2.5GHz RF1 TO RFC
6.0GHz RF1 TO RFC
1
10
100
1k
10k
100k
1M
10M
100M
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
SWITCH TOGGLES
Figure 9. Crosstalk vs. Frequency (VDD = 3.3 V)
Figure 12. Insertion Loss vs. Switching Toggles (VDD = 3.3 V)
0
–10
–20
–30
–40
–50
–60
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
T
V
= 25°C
= 3.3V
A
0.8
DD
T
V
= 25°C
A
0.6
= 3.3V
DD
RF1
RF2
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
DIGITAL CONTROL
tOFF TEST SIGNAL
tON
/
–0.5
0
1
2
3
4
5
6
7
8
9
10
0
10
20
TIME (µs)
30
40
FREQUENCY (GHz)
Figure 13. Digital Control Signal and Test Signal vs. Time (VDD = 3.3 V)
Figure 10. Return Loss vs. Frequency (VDD = 3.3 V)
0
2.0
1.5
V
T
= 3.3V
DD
1kHz SIGNAL
R
= 300Ω
LOAD
–20
–40
T
= 25°C
A
V
= 3.3V
= 85°C
= 25°C
DD
A
1.0
T
A
0.5
–60
0
–0.5
–1.0
–1.5
–2.0
–80
–100
–120
0
2
4
6
8
10
12
0
20M
40M
60M
80M
100M
SIGNAL AMPLITUDE (V p-p)
SWITCH ACTUATION NUMBER
Figure 14. Total Harmonic Distortion Plus Noise (THD + N) vs.
Signal Amplitude (VDD = 3.3 V)
Figure 11. RON Variation vs. Switch Actuation Number (VDD = 3.3 V, RF1 to RFC)
Rev. C | Page 8 of 21
Data Sheet
ADGM1304
120
HISTOGRAM DATA IS
HISTOGRAM DATA IS
2.5GHz AT 0°C
2.5GHz AT 25°C
2.5GHz AT 85°C
6.0GHz AT 0°C
6.0GHz AT 25°C
6.0GHz AT 85°C
COLLECTED USING A SOCKETED
TEST BOARD AND INCLUDES
ASSOCIATED LOSSES
COLLECTED USING A SOCKETED
TEST BOARD AND INCLUDES
ASSOCIATED LOSSES
100
80
60
40
20
0
V
= 3.3V
DD
V
= 3.3V
DD
INSERTION LOSS (dB)
INSERTION LOSS (dB)
Figure 15. 2.5 GHz Insertion Loss Histogram vs. Temperature (VDD = 3.3 V)
Figure 16. 6.0 GHz Insertion Loss Histogram vs. Temperature (VDD = 3.3 V)
Rev. C | Page 9 of 21
ADGM1304
Data Sheet
TEST CIRCUITS
Test circuits applicable to all channels; additional pins omitted for clarity.
V
V
DD
DD
0.1µF
0.1µF
V
OUT
R
50Ω
L
NETWORK
ANALYZER
V
DD
V
DD
RF1
RF2
RF1
RF2
50Ω
V
S
50Ω
NETWORK
ANALYZER
RFC
RFC
50Ω
V
OUT
R
50Ω
IN2
IN1
L
50Ω
IN2
IN1
V
S
V
IN2
V
IN2
RF3
RF4
RF3
RF4
V
IN1
V
50Ω
50Ω
IN1
50Ω
50Ω
IN4
IN3
IN4
IN3
V
IN4
V
RFGND AGND
IN4
RFGND AGND
V
IN3
V
IN3
Figure 19. Crosstalk
Figure 17. Insertion Loss/Return Loss
V
DD
V
DD
0.1µF
0.1µF
50Ω
V
V
DD
S
RF1
V
DD
NC
NC
RF1
RF2
V
OUT
RFC
R
50Ω
L
OSCILLOSCOPE
RFC
RF2
IN2
IN1
IN2
IN1
50Ω
NETWORK
ANALYZER
V
IN2
V
IN2
RF3
RF4
V
IN1
NC
NC
RF3
RF4
V
IN1
50Ω
50Ω
IN4
IN3
IN4
IN3
V
IN4
RFGND AGND
V
IN4
V
IN3
RFGND AGND
V
IN3
Figure 20. Video Feedthrough
Figure 18. Isolation
Rev. C | Page 10 of 21
Data Sheet
ADGM1304
V
V
V
V
DD
DD
DD
0.1µF
0.1µF
DD
RF1
RF2
RF1
RF2
50Ω
50Ω
RFC
RFC
SPECTRUM
ANALYZER
SPECTRUM
ANALYZER
RF
SOURCE
RF
SOURCE
INPUT
COMBINER
NETWORK
IN2
IN1
IN2
IN1
RF
SOURCE
RF
AMPLIFIER
V
V
IN2
IN2
RF3
RF3
RF4
V
V
IN1
IN1
50Ω
50Ω
50Ω
RF4
IN4
IN3
50Ω
IN4
IN3
V
IN4
V
IN4
RFGND AGND
RFGND AGND
V
IN3
V
IN3
Figure 21. Input Second-Order Intermodulation Intercept (IP2) and Input
Third-Order Intermodulation Intercept (IIP3)
Figure 23. Second and Third Harmonics, RF Power
V
DD
0.1µF
V
DD
V
OUT
RFx
RFC
50%
50%
V
R
INx
L
V
S
INx
50Ω
10%
90%
V
OUT
RFGND AGND
tON
tOFF
V
INx
Figure 22. Switch Timings, tON and tOFF
Rev. C | Page 11 of 21
ADGM1304
Data Sheet
TERMINOLOGY
Insertion Loss (IL)
Input Second-Order Intermodulation Intercept (IIP2)
IL is the amount of signal attenuation between the input and
output ports of the switch when the switch is in the on state.
Expressed in decibels, ensure that insertion loss is as small as
possible for maximum power transfer.
IIP2 is the intersection point of the fundamental POUT vs. PIN
extrapolated line and the second-order intermodulation products
extrapolated line of a two tone test. IIP2 is a figure of merit that
characterizes the switch linearity.
An example calculation of insertion loss based on the setup in
Figure 17 is as follows:
Second Harmonic (HD2)
HD2 is the amplitude of the second harmonic, where, for a signal
whose fundamental frequency is f, the second harmonic has a
frequency 2 f. This measurement is a single tone test, expressed
with reference to the carrier signal (dBc).
IL = −20log10|SRF2RFC| [dB]
where SRF2RFC is the transmission coefficient measured from RF2
to RFC with RF2 in the on position. All unused switches are in
the off position and terminated in a purely resistive load of 50 Ω.
Third Harmonic (HD3)
HD3 is the amplitude of the third harmonic, where, for a signal
whose fundamental frequency is f, the third harmonic has a
frequency 3 f. This measurement is a single tone test, expressed
with reference to the carrier signal (dBc).
Isolation (ISO
)
I
SO is the amount of signal attenuation between the input and
output ports of the switch when the switch is in the off state.
Expressed in decibels, ensure that isolation is as large as possible.
RF Power Rating
An example calculation of isolation based on the setup in Figure 18
is as follows:
The RF power rating is the maximum level of RF power that
passes through the switch without degradation to the switch
lifetime when it is in the on state.
ISO = −20log10|SRFCRF1| [dB]
where SRFCRF1 is the transmission coefficient measured from RFC
to RF1 with RF1 in the off position. All unused switches are in
the off position and terminated in a purely resistive load of 50 Ω.
On Switching Time (tON
)
tON is the time it takes for the switch to turn on. It is measured
from 50% of the control signal (INx) to 90% of the on level. No
power is applied through the switch during this test (cold
switched). The switch is terminated into a 50 Ω load.
Crosstalk (CTK
)
C
TK is a measure of unwanted signals coupled through from one
channel to another because of parasitic capacitance.
Off Switching Time (tOFF
)
t
OFF is the time it takes for the switch to turn off. It is measured
An example calculation of crosstalk based on the setup in
Figure 19 is as follows:
from 50% of the control signal (INx) to 10% of the on level. No
power is applied through the switch during this test (cold
switched). The switch is terminated into a 50 Ω load.
CTK = −20log10|SRF1RF2| [dB]
where SRF1RF2 is the transmission coefficient measured from RF1
to RF2 with RF1 in the off position and RF2 in the on position.
All unused switches are in the off position and terminated in a
purely resistive load of 50 Ω.
Settling Time Rising Edge
The settling time rising edge is the time it takes for the power of
an RF signal to settle within 0.05 dB of the final steady state
value. The switch is terminated into a 50 Ω load.
Return Loss (RL)
Settling Time Falling Edge
RL is the magnitude of the reflection coefficient expressed in
decibels, and the amount of reflected signal relative to the
incident signal. A large return loss value indicates good matching.
The settling time falling edge is the time it takes for the power
of an RF signal to settle within 0.05 dB of the final steady state
value. The switch is terminated into a 50 Ω load.
An example calculation of return loss based on the setup in
Figure 17 is as follows:
Actuation Frequency
The actuation frequency refers to the speed at which the
ADGM1304 can be switched on and off. It is dependent on both
settling times and on to off switching times.
RL = −20log10|S11| [dB]
where S11 is the reflection coefficient of the port under test.
Wake-Up Time
Input Third-Order Intermodulation Intercept (IIP3)
IIP3 is the intersection point of the fundamental POUT vs. PIN
extrapolated line and the third-order intermodulation products
extrapolated line of a two tone test. IIP3 is a figure of merit that
characterizes the switch linearity.
The wake-up time is a measure of the time required for the
voltage on VCP to reach the typical voltage of 80 V after the device
exits sleep mode.
Video Feedthrough
Video feedthrough is a measure of the spurious signals present
at the RF ports of the switch when the control voltage is switched
from high to low or from low to high without an RF signal present.
Rev. C | Page 12 of 21
Data Sheet
ADGM1304
Internal Oscillator Frequency
Cold Switching
The internal oscillator frequency is the value of the on-board
oscillator that drives the gate control chip of the ADGM1304.
The oscillator frequency can be overdriven through the
EXTCLK pin.
Cold switching operates the switch in a mode so that no voltage
differential exists between source and drain when the switch is
closed and/or no current is flowing source to drain when the
switch opens. All switches have longer lives when cold switched.
Internal Oscillator Feedthrough
Hot Switching
The internal oscillator feedthrough is the amount of internal
oscillator signal that feeds through to the RF pins of the switch.
This signal appears as a noise spur on the RFx and RFC pins of
the switch at the frequency the oscillator is operating at and
harmonics thereof.
Hot switching is operating the switch in a mode where a voltage
differential exists between source and drain when the switch is
closed and/or current is flowing RFx channel to RFC channel
when the switch is opened. Hot switching results in a reduced
switch life, depending on the magnitude of the open circuit
voltage between the source and the drain.
On Resistance (RON
)
RON is the resistance of a switch in the closed/on state measured
EXTCLK Input Range
between the package pins. Measure resistance in 4-wire mode
to null out any cabling or printed circuit board (PCB) series
resistances.
The EXTCLK input range is the allowable input frequency
range when using an external oscillator to drive the gate control
chip of the ADGM1304.
On Resistance Stability (ΔRON
)
EXTCLK Input High Voltage (EVINH
)
ΔRON is the variation in the on resistance of the switch over the
lifetime of the switch.
EVINH is the minimum input voltage for a recognized high when
using an external clock.
Continuously on Lifetime
EXTCLK Input Low Voltage (EVINL)
The continuously on lifetime measures how long the switch is
left in a continuously on state. If the switch is left in the on
position for an extended period, it affects the turn off
mechanism of the device.
EVINL is the maximum input voltage for a recognized low when
using an external clock.
I
DD Sleep Mode Current
DD sleep mode current is the measurement of the quiescent
current of the chip after the device enters sleep mode.
Input High Voltage (VINH
INH is the minimum input voltage for Logic 1.
Input Low Voltage (VINL
INL is the maximum input voltage for Logic 0.
I
Actuation Lifetime
Actuation lifetime is the number of consecutive open-close-
open cycles that can complete without the on resistance
exceeding a specified limit and no occurrence of failures to
open (FTO) or failures to close (FTC).
)
V
)
V
Rev. C | Page 13 of 21
ADGM1304
Data Sheet
THEORY OF OPERATION
The ADGM1304 is a wideband single-pole, four-throw (SP4T)
switch fabricated using Analog Devices, Inc., MEMS switch
technology. This technology enables high power, low loss, low
distortion gigahertz switches to be realized for demanding RF
applications.
Figure 24 shows a stylized cross section graphic of the switch
with dimensions. The switch is an electrostatically actuated
cantilever beam connected in a three terminal configuration.
Functionally, it is analogous to a field effect transistor (FET); the
terminals can be used as a source, gate, and drain.
SILICON
CANTILEVER BEAM
SOURCE
DRAIN
METAL
Figure 25. ADGM1304 LFCSP Package with Molding Compound Partially
Removed to Show MEMS Switch Die (Right), Controller Die (Left), and
Associated Wire Bonds
GATE
CONTACT GAP
DIGITAL INTERFACE
SILICON
The ADGM1304 is controlled via a parallel interface. Standard
CMOS/LVTTL signals applied through this interface controls the
actuation/release of all of the switch channels of the ADGM1304.
Applied gate signals are boosted to give the required voltages
needed to actuate the MEMS switches.
Figure 24. Cross Section of the MEMS Switch Design Showing the Cantilever
Switch Beam (Not to Scale)
When a dc actuation voltage is applied between the gate
electrode and the source (the switch beam), an electrostatic
force generates, resulting in attracting the beam toward the
substrate. A separate on-board charge pump IC generates the
bias voltage; 80 V is used for actuation.
Pin IN1 to Pin IN4 control the switching functions of the
ADGM1304. When Logic 1 is applied to one of the INx pins,
the gate of the corresponding switch is activated, and the switch
turns on. Conversely, when Logic 0 is applied to any of these
pins, the switch turns off. Note that, it is possible to connect
more than one RFx input to the RFC pin at a time. The truth
table for the ADGM1304 is given in Table 5.
When the bias voltage between the gate and the source exceeds
the threshold voltage of the switch, VTH, the contacts on the
beam touch the drain, which completes the circuit between the
source and the drain and turns the switch on. When the bias
voltage is removed, that is, 0 V on the gate electrode, the beam
acts as a spring generating a sufficient restoring force to open
the connection between the source and the drain, thus breaking
the circuit and turning the switch off.
SLEEP MODE (SLEEP)
Use the SLEEP pin to shut down the ADGM1304. Tying the pin
high places the device into a low power quiescent state, drawing
only 1 μA supply current.
Figure 25 shows the SP4T MEMS switch and controller die
within the LFCSP package. Some of the LFCSP plastic molding
material is removed to allow the MEMS switch die (right) and
controller die (left) with associated wire bonds to be visible. The
silicon hermetically sealed cap covering the switch die can be
seen on the right as a black rectangle. Hermetically sealing the
switches improves the reliability and lifetime of the switches by
keeping them in a controlled atmosphere. The switch contacts do
not suffer from dry switching or low power switching lifetime
degradation.
The low power state is especially useful for portable electronic
applications and other applications that rely on low power states
to deliver the desired field life.
Rev. C | Page 14 of 21
Data Sheet
ADGM1304
Table 5. Truth Table (X Means Any Logic State)
IN1
IN2
IN3
IN4
SLEEP
RF1 to RFC
Off
RF2 to RFC
Off
RF3 to RFC
Off
RF4 to RFC
Off
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
On
On
On
On
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
Off
On
On
On
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
DRIVER IC OSCILLATOR
EXTERNAL CLOCK (EXTCLK)
A companion driver IC drives the MEMS switch. This driver IC
converts the supply voltage to 80 V, which electrostatically actuates
the switch, turning it on. The driver IC contains a control logic
interface, a charge pump to generate 80 V, and a ramping drive
circuit to shape the 80 V output voltage.
In some applications, using a known external clock source instead
of the on-board oscillator is more convenient. The ADGM1304
offers an EXTCLK pin that allows a user to provide a clock
source to drive the boost circuitry of the device. Setting the
CLKSEL pin high activates the EXTCLK pin. The allowable
frequency range of an external clock source is 20 MHz to 23 MHz.
A nominal 11.5 MHz oscillator is part of the charge pump
architecture. Although this oscillator is very low power, the
11.5 MHz signal is coupled to the switch and can be seen as a
noise spur on the switch channels. The magnitude of this
feedthrough noise spur is specified in Table 1 and is typically
−115 dBm when one switch is on. When all four switches are
simultaneously on, the feedthrough goes up to −94 dBm.
In applications where the system noise floor level is important,
set the CLKSEL pin high and the EXTCLK pin low to disable the
charge pump and oscillator. In addition, there is zero oscillator
feedthrough. To drive the switch with the charge pump disabled,
apply an external 80 V drive voltage to the VCP pin, and the
digital interface can control the switch (see Table 5).
Note that the VDD level and temperature changes affect the
frequency of the noise spur. The maximum and minimum
frequency range over temperature and voltage supply range is as
detailed in Table 1.
Rev. C | Page 15 of 21
ADGM1304
Data Sheet
oscillator as the reference to the control circuit of the device.
The SLEEP pin is tied to ground, thereby operating the device in
normal operating mode.
TYPICAL OPERATING CIRCUIT
Figure 26 shows the typical operating circuit for the ADGM1304.
A 47 pF external capacitor is required on the VCP pin; this is a
holding capacitor for the 80 V gate drive voltage. VDD is connected
to 3.3 V. However, it can operate from 3.1 V to 3.3 V. RFGND is
separated from AGND internally in the device.
To disable the internal oscillator and eliminate all oscillator
feedthrough, set the CLKSEL pin to high and apply an 80 V dc
directly to the VCP pin. Then control the switches as normal via
the logic control interface IN1 to IN4 pins.
It is recommended to connect RFGND to AGND using one
large pad on the PCB to short together EP1 and EP2. Figure 26
displays the ADGM1304 configured to use the internal
+3.3V
0.1µF
47pF
24
23
22
21
20
19
18
RFGND
RFGND
RFC
17
16
IN1
IN2
IN3
1
2
3
4
5
IN1
IN2
TOP VIEW
RFOUT
15
14
13
IN3
IN4
EP1
EP2
RFGND
RFGND
IN4
EXTCLK
6
7
10
11
12
8
9
Figure 26. Typical Operating Circuit
Rev. C | Page 16 of 21
Data Sheet
ADGM1304
APPLICATIONS INFORMATION
Figure 32 and Figure 33 illustrate typical cascaded switch use cases
and the corresponding schemes to mitigate floating node risks.
FLOATING NODE AVOIDANCE
As outlined in the Theory of Operation section, applying 80 V
on the gate electrode under the beam of the switch creates an
electrostatic attraction force that pulls the beam down to actuate
the switch. To ensure correct switch actuation, do not float
the switch beam to an unknown voltage level. Four cases where
floating nodes can happen when using the switch including the
following (see Figure 27 to Figure 30):
RF1
RF2
RF3
RF4
RF1
RF2
RF3
RF4
RFC
RFC
Figure 32. Two ADGM1304 Devices Connected Together with Shunt Resistors
to Mitigate Floating Nodes
RFx pins left open circuit
Connecting a series capacitor directly to the switch
Connecting the RFx pin of two switches directly together
or connecting RFC to RFx
RF1
RFC
RF2
RF3
RF4
RF1
RF2
RF3
RF4
RFx
RFC
RFC
FLOATING
RF1
RF2
RF3
RF4
RFC
Figure 27. RFx Pins Left Open Circuit
RFx
RFC
FLOATING
Figure 33. Three ADGM1304 Devices Connected Together with Shunt
Resistors to Mitigate Floating Nodes
The path between the two switches needs a voltage reference to
ground; otherwise, the path can float to an unknown voltage
and subsequently cause unreliable actuations, possibly leading
to hot switching events or switches remaining in the on state.
Figure 28. Connecting a Series Capacitor Directly to the Switch
RFC
RFx
RFx
RFC
FLOATING
To avoid hot switching events or switches remaining in the on state,
add high value resistors to ground to the channel of the MEMS
switch, which is cascaded to another MEMS switch, as shown in
Figure 32 and Figure 33. These shunt resistors create a dc
voltage reference. A value of 10 MΩ or less is recommended.
The addition of the shunt resistors increases the leakage more
than what is specified in Table 1.
Figure 29. Connecting the RFx Pin of Two Switches Directly Together
RFx
RFC
RFC
RFx
FLOATING
Figure 30. Connecting RFC to RFx
Providing a dc voltage reference to the switch ensures correct
gate to beam voltage differential to drive the switch and prevents
floating nodes and unreliable actuation. In a typical application, a
50 Ω termination connected to the switch provides a constant dc
voltage reference. Most amplifiers and other active devices have
an internal dc voltage reference. Therefore, directly connecting
these devices to the switch provides a dc voltage reference and
avoids any floating node issues. If there is no inherent dc
voltage reference in the application circuit, a large shunt resistor
or inductor on the source (RFx) pin of the MEMS switch must be
added to provide one. Figure 31 shows this type of configuration.
RFx
RFC
OR
Figure 31. Switch Configuration Providing a Voltage Reference
Rev. C | Page 17 of 21
ADGM1304
Data Sheet
99
CONTINUOUSLY ON LIFETIME
V
= 3.3V
DD
Turning the switch on for a long period affects the lifetime of
the switch. The ADGM1304 has a continuous on lifetime
specification of 7.2 years typical (see Table 1). The continuously
on lifetime time of the switch must not exceed this specification
when the switch is in the on state to preserve good turn off
reliability.
90
70
30
10
Figure 34 shows the continuously on lifetime reliability data taken
at 50°C for 31 parts. In the case of 50% of the population, expect
a failure time of approximately 7.2 years. As the temperature
increases above 50°C, the continuously on lifetime degrades
significantly. When using the switch in duty cycle, less than 50%
of the lifetime is significantly better.
1
10
100
1,000
10,000
100,000
CONTINUOUSLY ON TIME (DAYS)
Figure 34. Continuously on Lifetime, VDD = 3.3 V, 50°C,
Sample Size 31 Parts
Rev. C | Page 18 of 21
Data Sheet
ADGM1304
SUGGESTED APPLICATION CIRCUITS
SWITCHABLE RF ATTENUATOR
RECONFIGURABLE RF FILTER
A reconfigurable RF filter is advantageous in many RF front-
end applications. A reconfigurable RF filter provides more
saved space. As space becomes more constrained in applications,
the option to have an economical reconfigurable RF filter
instead of individual frequency dependent filters is attractive.
It is common to see RF attenuator networks used in RF
instrumentation equipment such as vector network analyzers,
spectrum analyzers, and signal generators. Routing RF signals
through an attenuator can enable the equipment to accept higher
power signals and, therefore, increase the dynamic range of the
instrument. In RF attenuation applications like the vector network
analyzers, spectrum analyzers, and signal generators, maintaining
the bandwidth of the signal after it passes through the network
is critical. Any degradation of the signal reduces the performance of
the equipment. Therefore, the RF characteristics of the switches
used for routing is an integral part of the quality of an attenuator
network.
The ADGM1304 with low flat insertion loss, very wide RF
bandwidth, low parasitic, low capacitance, and high linearity is
needed to turn on the lump components (capacitor, inductor),
which make the MEMS switch suited for reconfigurable filter
application.
In applications such as wireless communications or mobile
radios, the number of bands and/or modes constantly increases.
A reconfigurable RF filter allows more bands/modes to be
covered using the same components.
The ADGM1304 MEMS switch with low flat insertion loss, very
wide RF bandwidth, and high reliability is suited for using it as a
switchable RF attenuator. The ADGM1304, as an SP4T switch, also
brings added flexibility. Figure 35 shows an example attenuation
network configuration using two ADGM1304 switches and three
different attenuators. The fourth channel of the switches is used
as a nonattenuated route in Figure 35.
Figure 36 shows an example of a reconfigurable band-pass filter.
The topology shown is of a generalized two section, inductively
coupled, single-ended band-pass filter, nominally centered on
400 MHz (UHF band). Note the MEMS switches are positioned
in series with each of the shunt inductors.
15dB
The function of the switches includes or omits a shunt inductor
from the circuit. Changing the shunt inductor value affects the
bandwidth and center frequency of the filter. Using inductance
values from 15 nH to 30 nH significantly alters the bandwidth
and center frequency, allowing the filter to dynamically configure
to operate in the ultrahigh frequency (UHF) or very high
frequency (VHF) bands while preserving the 50 Ω match on the
input and output ports. The low RON value and large bandwidth
of the MEMS switch makes it an ideal choice for this application.
The low RON reduces the negative effect a series resistance has
on the quality factor of the shunt inductor. The large bandwidth
enables higher frequency band-pass filters.
10dB
I/O
I/O
ADGM1304
ADGM1304
5dB
Figure 35. Switching RF Attenuators Using ADGM1304 MEMS Switches
INPUT
OUTPUT
22nH
50Ω
50Ω
13pF
13pF
24nH 30nH
18nH 15nH
15nH
18nH
30nH
24nH
GND
Figure 36. Reconfigurable Band-Pass Filter Realized Using Two ADGM1304 MEMS Switches
Rev. C | Page 19 of 21
ADGM1304
Data Sheet
HANDLING PRECAUTIONS
ESD PRECAUTIONS
All RFx pins of the ADGM1304 pass the following ESD limits:
DC Voltage Range
The dc voltage range of the switch is ±± V (see Table 1), which
is the dc signal range the switch is specified to carry.
100 V, Class 0 human body model (HBM),
ANSI/ESDA/JEDEC JS-001-2010
Voltage Standoff Limit
The standoff voltage is the highest voltage that can be applied to
the RFC drain electrode of the switch without adversely
affecting the performance or reliability of the switch.
500 V, Class C2 field-induced charged-device model
(FICDM), JEDEC JESD22_C101E
All the RFx pins are rated to 500 V FICDM, making the device
safe for automated handling and assembly process, according to
the Industry Council on ESD Target Levels, White Paper 2, “A
Case for Lowering Component Level CDM ESD Specifications
and Requirements.” Refer to the Absolute Maximum Ratings
section for more information.
The standoff voltage limit of the switch is 100 V on the RFC pin
(see Table 2).
MECHANICAL SHOCK PRECAUTIONS
The device passes an extensive mechanical shock qualification
process. Table ± shows a summary of the mechanical shock
qualification tests used on the ADGM1304. These tests validate
the robustness of the device to mechanical shocks.
ELECTRICAL OVERSTRESS (EOS) PRECAUTIONS
A stored charge inadvertently conducted through the switches
can result in immediate permanent damage to the ADGM1304.
Therefore, observe the following precautions:
Table 6. Mechanical Qualification Summary
Parameter
Qualification
Mechanical Shock
Random Drop
Vibration Testing
Powered (PMS) IEC 60068-2-27
AEC-Q100 Test G5, five drops from 0.6 m
MIL-STD-883, M2007.3, Condition B,
Treat the ADGM1304 as a static sensitive device and
observe all normal handling precautions, including
working only on static dissipative surfaces, wearing wrist
straps or other ESD control devices, and storing unused
devices in conductive foam.
Avoid running measurement instruments (for example,
digital multimeters (DMMs) in autorange modes). Some
instruments can generate large transient compliance
voltages when switching between ranges.
Use the highest practical DMM range setting (that is, the
lowest resolution) for resistance measurements minimizing
compliance voltages.
Coaxial cables can store charge and lead to EOS when directly
connected to the switch. Discharge cables before connecting
directly to the switch.
20 Hz to 2000 Hz at 50 g
Group D Sub 4 MIL-
STD-883, M5005
Mechanical shock, 1500 g, 0.5 ms;
vibration 50 g sine sweep, 20 Hz to
2000 Hz; acceleration 30,000 g
The device must be handled with care and, as is the case with
electromechanical relays, do not use the device if dropped and
ensure there are minimal mechanical shocks during the
handling and manufacturing of the device.
Figure 38 shows examples of loose device handling situations to
avoid due to mechanical shock and ESD event risk.
NOT RECOMMENDED
Avoid connecting large capacitive terminations directly to
the switch. A shunt capacitor can store a charge that can
potentially give rise to hot switching events when the switch
opens or closes, affecting the lifetime of the switch. Figure 37
shows where to avoid large capacitive terminations.
DEVICES DUMPED OUT
DEVICES STORED BULK
RFx
RFC
ON BENCHTOP
IN BINS
Figure 37. Avoid Large Capacitive Terminations Directly Connected to
the Switch
DEVICE DROPPED
Figure 38. Device Handling Precautions
Rev. C | Page 20 of 21
Data Sheet
ADGM1304
OUTLINE DIMENSIONS
0.33 NOM
1.30 NOM
0.16 NOM
1.47 NOM
5.00 BSC
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
18
24
17
1
5
*
*
EXPOSED
PA D
EXPOSED
PA D
4.00 BSC
2.15 NOM
13
12
6
0.60
0.55
0.50
BOTTOM VIEW
TOP VIEW
1.00
0.95
0.85
*
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.18
0.15 REF
Figure 39. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 4 mm Body, Very Thin Quad
(CP-24-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADGM1304JCPZ-RL7
EVAL-ADGM1304EBZ
0°C to +85°C
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-24-9
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12874-0-10/16(C)
Rev. C | Page 21 of 21
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ADI
ADGS1212BCPZ-RL7
SPI Interface, Quad SPST Switch, Low QINJ, Low CON, ±15 V/12 V, Mux Configurable
ADI
ADGS1408BCPZ
SPI Interface, 4 Ω RON, ±15 V/12 V/±5 V, 1.8 V Logic Control, 8:1/Dual 4:1 Muxes
ADI
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