ADGS1208BCPZ-RL7 [ADI]
SPI Interface, Low CON and QINJ, ±15 V/12 V, 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches;
| 型号： | ADGS1208BCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | SPI Interface, Low CON and QINJ, ±15 V/12 V, 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches |
| 文件： | 总33页 (文件大小：666K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPI Interface, Low CON and QINJ, ± ±1 ꢀV/±ꢁ ꢀ,
±.8 ꢀ Logic Control, 8:±VDual 4:± Mux Switches
Data Sheet
ADGS±ꢁ08VADGS±ꢁ09
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
SPI interface with error detection
ADGS1208
Includes CRC, invalid read/write address, and SCLK count
error detection
S1
Supports burst mode and daisy-chain mode
Industry standard SPI Mode 0 and SPI Mode 3 interface
compatible
D
Round robin mode allows switching times that are
comparable with a parallel interface
Four general-purpose digital outputs that can be used to
control other devices
<1 pC charge injection over full signal range
1 pF off capacitance
S8
GPO1
GPO2
GPO3
GPO4
CNV
SDO
SPI
INTERFACE
SCLK SDI CS RESET/V
VSS to VDD analog signal range
L
Fully specified at 1ꢀ V and +12 V
Figure 1. ADGS1208 Functional Block Diagram
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
24-lead LFCSP package
ADGS1209
S1A
APPLICATIONS
DA
S4A
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
S1B
DB
S4B
GPO1
CNV
SDO
GPO2
GPO3
GPO4
SPI
INTERFACE
GENERAL DESCRIPTION
The ADGS1208/ADGS1209 are analog multiplexers comprising
eight single channels and four differential channels, respectively. A
serial peripheral interface (SPI) controls the switches. The SPI
interface has robust error detection features, such as cyclic
redundancy check (CRC) error detection, invalid read/write
address detection, and SCLK count error detection.
SCLK SDI CS RESET/V
L
Figure 2. ADGS1209 Functional Block Diagram
The ultralow on capacitance (CON) and exceptionally low charge
injection (QINJ) of these multiplexers make them ideal solutions
for data acquisition and sample-and-hold applications, where
low glitch and fast settling are required.
It is possible to daisy-chain multiple ADGS1208/ADGS1209
devices together. Daisy-chain mode enables the configuration of
multiple devices with a minimal amount of digital lines. The
ADGS1208/ADGS1209 can also operate in burst mode to
decrease the time between SPI commands.
PRODUCT HIGHLIGHTS
1. SPI interface removes the need for parallel conversion,
logic traces, and reduces GPIO channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
3. CRC error detection, invalid read/write address detection,
and SCLK count error detection ensure a robust digital
interface.
iCMOS® construction ensures ultralow power dissipation,
making the devices ideally suited for portable and battery-
powered instruments.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies. In the off condition, signal levels up to the supplies
are blocked.
4. CRC and error detection capabilities allow the use of the
ADGS1208/ADGS1209 in safety critical systems.
Rev. 0
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ADGS1208/ADGS1209
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Software Reset............................................................................. 23
Daisy-Chain Mode..................................................................... 23
Power-On Reset.......................................................................... 24
Round Robin Mode.................................................................... 25
General-Purpose Outputs......................................................... 26
Applications Information .............................................................. 27
Digital Input Buffers .................................................................. 27
Settling Time............................................................................... 27
Power Supply Rails..................................................................... 27
Power Supply Recommendations............................................. 27
Register Summaries........................................................................ 28
Register Details ............................................................................... 29
Switch Data Register .................................................................. 29
Error Configuration Register.................................................... 30
Error Flags Register.................................................................... 30
Burst Enable Register................................................................. 31
Round Robin Enable Register................................................... 31
Round Robin Channel Configuration Register...................... 31
CNV Edge Select Register......................................................... 32
Software Reset Register ............................................................. 32
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 33
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
12 V Single Supply........................................................................ 5
Continuous Current per Channel, Sx or Dx............................. 8
Timing Characteristics ................................................................ 9
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 14
Test Circuits..................................................................................... 18
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 22
Address Mode ............................................................................. 22
Error Detection Features........................................................... 22
Clearing the Error Flags Register ............................................. 23
Burst Mode .................................................................................. 23
REVISION HISTORY
4/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 33
Data Sheet
ADGS1208/ADGS1209
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 1.
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
270
V
150
Ω typ
VS = 10 V, IS = −1 mA,
see Figure 39
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
200
3.5
240
Ω max
Ω typ
On Resistance Match Between
Channels, ∆RON
6
35
64
10
76
12
83
Ω max
Ω typ
Ω max
On Resistance Flatness, RFLAT (ON)
VS = 10 V, IS = −1 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.003
nA typ
VS = 10 V, VD =
see Figure 36
10 V,
0.1
0.003
0.6
1.0
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 10 V, VD =
see Figure 36
10 V,
0.1
0.02
0.3
0.6
0.6
1.0
1.0
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 10 V, see Figure 32
DIGITAL OUTPUTS
SDO
Output Voltage
Low, VOL
0.4
0.2
V max
V max
µA typ
µA max
pF typ
Sink current (ISINK) = 5 mA
ISINK = 1 mA
Output voltage (VOUT) = VGND or VL
High Impedance Leakage Current
0.001
0.1
High Impedance Output
Capacitance
4
GPOx
Output Voltage
High, VOH
Low, VOL
Timing
VL − 0.2 V
0.2
V min
V max
ISOURCE = 100 µA
ISINK = 100 µA
tON
95
115
15
20
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
CL = 15 pF, see Figure 44
CL = 15 pF, see Figure 44
CL = 15 pF, see Figure 45
115
25
115
25
tOFF
Break-Before-Make Time Delay, tD
35
Rev. 0 | Page 3 of 33
ADGS1208/ADGS1209
Data Sheet
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
DIGITAL INPUTS/OUTPUTS
Input Voltage
High, VINH
2
V min
3.3 V < VL ≤ 5.5 V
1.35
0.8
0.8
V min
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
Input voltage (VIN) = VGND or VL
Low, VINL
V max
V max
µA typ
µA max
pF typ
Input Current, IINL or IINH
0.001
4
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
90
145
92
110
120
135
32
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 41
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 42
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 42
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V, see Figure 40
VS = 0 V, RS = 0 Ω, CL = 1 nF,
see Figure 43
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 34
170
140
170
195
155
190
7
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
0.4
−85
−85
0.15
dB typ
dB typ
% typ
Channel to Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 33
RL = 110 Ω, 15 V p-p, f = 20 Hz to
20 kHz, see Figure 38
Total Harmonic Distortion Plus
Noise
−3 dB Bandwidth
ADGS1208
ADGS1209
RL = 50 Ω, CL = 5 pF, see Figure 37
550
630
−6
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 37
CS (Off)
1
1.6
pF typ
pF max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
CD (Off)
ADGS1208
5
5.5
2
pF typ
pF max
pF typ
pF max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
ADGS1209
3.5
CD (On), CS (On)
ADGS1208
5
6.5
3
pF typ
pF max
pF typ
pF max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
ADGS1209
4.5
Rev. 0 | Page 4 of 33
Data Sheet
ADGS1208/ADGS1209
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
All switches open
POWER REQUIREMENTS
IDD
0.002
220
μA typ
1.0
μA max
μA typ
μA max
μA typ
μA max
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
380
440
270
IL
Inactive
6.3
14
μA typ
μA max
μA typ
Digital inputs = 0 V or VL
8.0
Inactive, SCLK = 1 MHz
CS = VL and SDI = 0 V or VL,
VL = 5 V
7
μA typ
μA typ
μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
SCLK = 50 MHz
390
210
Inactive, SDI = 1 MHz
SDI = 25 MHz
15
μA typ
μA typ
μA typ
μA typ
mA typ
CS and SCLK = 0 V or VL, VL = 5 V
7.5
230
120
1.8
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz
Digital inputs toggle between
0 V and VL, VL = 5.5 V
2.1
1.0
mA max
mA typ
0.7
Digital inputs toggle between
0 V and VL, VL = 2.7 V
mA max
μA typ
μA max
V min
ISS
0.002
Digital inputs = 0 V or VL
1.0
4.5
16.5
VDD/VSS
GND = 0 V
GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
625
V
380
Ω typ
VS = 0 V to 10 V, IS = −1 mA,
see Figure 39
VDD = 10.8 V, VSS = 0 V
475
5
570
26
Ω max
Ω typ
On Resistance Match Between
Channels, ∆RON
VS = 0 V to 10 V, IS = −1 mA
16
200
27
Ω max
Ω typ
On Resistance Flatness, RFLAT (ON)
VS = 0 V to 10 V, IS = −1 mA
Rev. 0 | Page 5 of 33
ADGS1208/ADGS1209
Data Sheet
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 36
0.003
nA typ
0.1
0.003
0.6
0.6
0.6
1.0
1.0
1.0
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 36
0.1
0.02
nA max
nA typ
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/10 V,
see Figure 32
0.3
nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL
0.4
0.2
V max
V max
µA typ
µA max
pF typ
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
High Impedance Leakage Current
0.001
0.1
High Impedance Output Capacitance
4
GPOx
Output Voltage
High, VOH
Low, VOL
Timing
VL − 0.2 V
0.2
V min
V max
ISOURCE = 100 µA
ISINK = 100 µA
tON
95
115
15
20
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
CL = 15 pF, see Figure 44
CL = 15 pF, see Figure 44
CL = 15 pF, see Figure 45
115
25
115
25
tOFF
Break-Before-Make Time Delay, tD
35
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.35
0.8
0.8
Low, VINL
V max
V max
µA typ
µA max
pF typ
Input Current, IINL or IINH
0.001
4
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTIC1
Transition Time, tTRANSITION
110
185
120
140
130
145
35
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 41
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 42
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 42
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 40
VS = 6 V, RS = 0 Ω, CL = 1 nF,
see Figure 43
RL = 50 Ω, CL = 5 pF,
f = 1 MHz, see Figure 34
RL = 50 Ω, CL = 5 pF,
220
190
195
245
210
215
15
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
−0.2
−85
−85
dB typ
dB typ
Channel to Channel Crosstalk
f = 1 MHz, see Figure 33
Rev. 0 | Page 6 of 33
Data Sheet
ADGS1208/ADGS1209
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
−3 dB Bandwidth
RL = 50 Ω, CL = 5 pF,
see Figure 37
ADGS1208
ADGS1209
Insertion Loss
450
550
−12
MHz typ
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF,
f = 1 MHz, see Figure 37
CS (Off)
1.2
1.8
pF typ
pF max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
CD (Off)
ADGS1208
6
pF typ
pF max
pF typ
pF max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
6.5
3.2
4
ADGS1209
CD (On), CS (On)
ADGS1208
6
7
4
4.5
pF typ
pF max
pF typ
pF max
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = 13.2 V
ADGS1209
POWER REQUIREMENTS
IDD
0.002
220
µA typ
µA max
µA typ
µA max
µA typ
µA max
All switches open
1.0
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
380
440
270
IL
Inactive
6.3
14
µA typ
µA max
µA typ
Digital inputs = 0 V or VL
8.0
Inactive, SCLK = 1 MHz
CS = VL and SDI = 0 V or VL,
VL = 5 V
7
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
mA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS and SCLK = 0 V or VL,
VL = 5 V
CS and SCLK = 0 V or VL,
VL = 3 V
CS and SCLK = 0 V or VL,
VL = 5 V
CS and SCLK = 0 V or VL,
VL = 3 V
Digital inputs toggle between
0 V and VL, VL = 5.5 V
SCLK = 50 MHz
390
210
15
Inactive, SDI = 1 MHz
SDI = 25 MHz
7.5
230
120
1.8
Active at 50 MHz
2.1
mA max
mA typ
0.7
Digital inputs toggle between
0 V and VL, VL = 2.7 V
1.0
5
16.5
mA max
V min
V max
VDD
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
Rev. 0 | Page 7 of 33
ADGS1208/ADGS1209
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 3. ADGS1208, One Channel On
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR D1
VDD = +15 V, VSS = −15 V (θJA = 63.1°C/W)
VDD = 12 V, VSS = 0 V (θJA = 63.1°C/W)
29.3
37.7
21.9
27.3
14.1
19
mA max
mA max
1 Sx refers to the S1 to S8 pins.
Table 4. ADGS1209, Two Channels On
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx1
VDD = +15 V, VSS = −15 V (θJA = 63.1°C/W)
VDD = 12 V, VSS = 0 V (θJA = 63.1°C/W)
21.8
28.2
16.1
21.2
9.9
13.4
mA max
mA max
1 Sx refers to the S1A to S4A and S1B to S4B pins, and Dx refers to the DA and DB pins.
Rev. 0 | Page 8 of 33
Data Sheet
ADGS1208/ADGS1209
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization,
not production tested.
Table 5.
Parameter
Limit
Unit
Test Conditions/Comments
TIMING CHARACTERISTICS
t1
t2
t3
t4
t5
t6
t7
t8
20
8
8
10
6
8
10
20
20
20
20
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
SCLK or CNV period
SCLK or CNV high pulse width
SCLK or CNV low pulse width
CS falling edge to SCLK or CNV active edge
Data setup time
Data hold time
SCLK or CNV active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high impedance
CS high time between SPI commands
CS falling edge to SCLK or CNV edge rejection
CS rising edge to SCLK or CNV edge rejection
1
t9
t10
t11
t12
t13
8
1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams
t1
SCLK
t2
t7
t4
t3
CS
t6
t5
SDI
R/W
A6
A5
1
D2
D2
D1
D1
D0
D0
t10
t9
SDO
0
0
t8
Figure 3. Address Mode Timing Diagram
Rev. 0 | Page 9 of 33
ADGS1208/ADGS1209
Data Sheet
t1
SCLK
CS
t2
t3
t7
t4
t6
t5
SDI
D7
D6
D0
D7
D6
D1
D0
INPUT BYTE FOR DEVICE N
t9
INPUT BYTE FOR DEVICE N + 1
t10
SDO
0
0
0
D7
D6
D1
D0
ZERO BYTE
INPUT BYTE FOR DEVICE N
t8
Figure 4. Daisy Chain Timing Diagram
t11
CS
SCLK OR CNV
t13
t12
CS
Figure 5. SCLK or CNV and Timing Diagram
t4
CS
t2
t3
t7
CNV
t9
t1
t10
RESYNC
SDO
MUX
CHANNEL
S1
S2
S(LAST)
Figure 6. Round Robin Timing Diagram
Rev. 0 | Page 10 of 33
Data Sheet
ADGS1208/ADGS1209
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Table 6.
Parameter
Rating
VDD to VSS
35 V
VDD to GND
VSS to GND
VL to GND
−0.3 V to +25 V
+0.3 V to −25 V
−0.3 V to +6 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Table 7. Thermal Resistance
1
Package Type
CP-24-152
θJA
θJCB
Unit
63.1
27.3
°C/W
Analog Inputs1
1 θJCB is the junction to the bottom of the case value.
2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD51.
Digital Inputs1
Peak Current, Sx or Dx Pins2
−0.3 V to +6 V
59 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
−40°C to +125°C
−65°C to +150°C
150°C
Continuous Current, Sx or Dx2, 3
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD CAUTION
Reflow Soldering Peak
Temperature, Pb-Free
260(+0/−5)°C
1 Overvoltages at the digital Sx and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
3 See Table 4 and Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
Rev. 0 | Page 11 of 33
ADGS1208/ADGS1209
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
18
17
16
GPO1
GPO3
CNV
GPO2 2
3
4
GND
V
ADGS1208
TOP VIEW
(Not to Scale)
SS
15 V
S1
DD
S2 5
S3 6
14
S5
13 S6
NOTES
AD IS CONNECTED INTERNALLY.
1. THE EXPOSED P
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, V
2. NIC = NOT INTERNALLY CONNECTED.
.
SS
Figure 7. ADGS1208 Pin Configuration
Table 8. ADGS1208 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
GPO1
GPO2
VSS
General-Purpose Output 1. This pin is a digital output.
General-Purpose Output 2. This pin is a digital output.
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
Source Terminal 1. This pin can be an input or output.
Source Terminal 2. This pin can be an input or output.
Source Terminal 3. This pin can be an input or output.
Source Terminal 4. This pin can be an input or output.
Not Internally Connected. These pins are not connected internally.
Drain Terminal. This pin can be an input or output.
Source Terminal 8. This pin can be an input or output.
Source Terminal 7. This pin can be an input or output.
Source Terminal 6. This pin can be an input or output.
Source Terminal 5. This pin can be an input or output.
Most Positive Power Supply Potential.
4
5
6
7
8, 10
9
11
12
13
14
15
16
17
18
19
S1
S2
S3
S4
NIC
D
S8
S7
S6
S5
VDD
GND
CNV
GPO3
SDO
Ground (0 V) Reference.
Channel Cycle Input. When in round robin mode, the CNV pin is used to cycle through the selected channels.
General-Purpose Output 3. This pin is a digital output.
Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
20
RESET/VL
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate
registers are set to their default values.
21
22
23
24
CS
Active Low Control Input. CS is the frame synchronization signal for the input data.
SCLK
SDI
GPO4
EPAD
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
Serial Data Input. Data is captured on the positive edge of the serial clock input.
General-Purpose Output 4. This pin is a digital output.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
Rev. 0 | Page 12 of 33
Data Sheet
ADGS1208/ADGS1209
1
18
17
16
GPO1
GPO3
CNV
GPO2 2
3
4
GND
V
ADGS1209
TOP VIEW
(Not to Scale)
SS
15 V
S1A
DD
S2A 5
S3A 6
14
S1B
13 S2B
NOTES
AD IS CONNECTED INTERNALLY.
1. THE EXPOSED P
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, V
2. NIC = NOT INTERNALLY CONNECTED.
.
SS
Figure 8. ADGS1209 Pin Configuration
Table 9. ADGS1209 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
GPO1
GPO2
VSS
S1A
S2A
S3A
S4A
NIC
General-Purpose Output 1. This pin is a digital output.
General-Purpose Output 2. This pin is a digital output.
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
Source Terminal 1A. This pin can be an input or output.
Source Terminal 2A. This pin can be an input or output.
Source Terminal 3A. This pin can be an input or output.
Source Terminal 4A. This pin can be an input or output.
Not Internally Connected. This pin is not internally connected.
Drain Terminal A. This pin can be an input or output.
9
DA
10
11
12
13
14
15
16
17
18
19
DB
Drain Terminal B. This pin can be an input or output.
S4B
S3B
S2B
S1B
VDD
GND
CNV
GPO3
SDO
Source Terminal 4B. This pin can be an input or output.
Source Terminal 3B. This pin can be an input or output.
Source Terminal 2B. This pin can be an input or output.
Source Terminal 1B. This pin can be an input or output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Channel Cycle Input. When in round robin mode, the CNV pin is used to cycle through the selected channels.
General-Purpose Output 3. This pin is a digital output.
Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
20
RESET/VL
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate
registers are set to their default values.
21
22
23
24
CS
Active Low Control Input. CS is the frame synchronization signal for the input data.
SCLK
SDI
GPO4
EPAD
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
Serial Data Input. Data is captured on the positive edge of the serial clock input.
General-Purpose Output 4. This pin is a digital output.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
Rev. 0 | Page 13 of 33
ADGS1208/ADGS1209
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
180
500
450
400
350
300
250
200
150
100
50
V
V
= 12V
= 0V
DD
SS
T
= 25°C
A
160
140
120
100
80
T
= +125°C
A
V
V
= +13.5V
= –13.5V
DD
SS
T
= +85°C
A
T
= +25°C
A
V
V
= +15V
= –15V
DD
SS
V
V
= +16.5V
= –16.5V
DD
SS
T
= –40°C
A
60
40
20
0
0
–15
–10
–5
0
5
10
15
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 9. On Resistance vs. Source or Drain Voltage for Various Dual
Supplies
Figure 12. On Resistance vs. Source or Drain Voltage for Various
Temperatures, 12 V Single Supply
450
400
V
V
V
= +15V
= –15V
T
= 25°C
V
V
= 10.8V
= 0V
DD
SS
A
DD
SS
400
350
300
250
200
150
100
300
200
= +10V/–10V
BIAS
I
, I (ON) + +
S
D
V
V
= 12V
= 0V
DD
SS
I
(OFF) + –
I
D
100
(OFF) + –
S
0
V
V
= 13.2V
= 0V
DD
SS
I
, I (ON) – –
S
D
–100
–200
–300
–400
I
(OFF) – +
D
I
(OFF) – +
S
50
0
0
10 20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (°C)
0
2
4
6
8
10
12
14
SOURCE OR DRAIN VOLTAGE (V)
Figure 10. On Resistance vs. Source or Drain Voltage for Various Single
Supplies
Figure 13. Leakage Current vs. Temperature, 15 V Dual Supply
250
150
V
V
= +15V
= –15V
DD
SS
V
V
V
= 12V
= 0V
DD
SS
= 1V/10V
BIAS
100
50
200
150
I
(OFF) + –
S
I
I
, I (ON) + +
S
D
T
T
= +125°C
= +85°C
A
A
(OFF) + –
D
0
T
T
= +25°C
= –40°C
A
A
I
(OFF) – +
S
100
I
, I (ON) – –
S
D
–50
–100
–150
I
(OFF) – +
D
50
0
–15 –12
–9
–6
–3
0
3
6
9
12
15
0
10 20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (°C)
SOURCE OR DRAIN VOLTAGE (V)
Figure 11. On Resistance vs. Source or Drain Voltage for Various
Temperatures, 15 V Dual Supply
Figure 14. Leakage Current vs. Temperature, 12 V Single Supply
Rev. 0 | Page 14 of 33
Data Sheet
ADGS1208/ADGS1209
1.0
0
MUX (SOURCE TO DRAIN)
= 25°C
V
V
= +15V
= –15V
= 25°C
DD
T
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
SS
T
A
V
V
= +15V
= –15V
DD
SS
V
V
= +12V
= 0V
DD
SS
0.1
0
V
V
= +5V
= –5V
DD
SS
–100
–110
–15
–10
–5
0
5
10
15
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
V
(V)
S
Figure 15. Source to Drain Charge Injection vs. Source Voltage (VS)
Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply
6
20
0
DEMUX (DRAIN TO SOURCE)
V
V
T
= +15V
= –15V
= 25°C
DD
SS
T
= 25°C
A
A
4
2
V
V
= +5V
= –5V
DD
SS
–20
–40
–60
–80
V
V
= +12V
= 0V
DD
SS
0
ADJACENT CHANNELS
V
V
= +15V
= –15V
DD
SS
–2
NONADJACENT
CHANNELS
–4
–6
–100
–120
–15
–10
–5
0
5
10
15
10k
100k
1M
10M
100M
1G
V
(V)
FREQUENCY (Hz)
S
Figure 16. Drain to Source Charge Injection vs. Source Voltage (VS)
Figure 19. ADGS1208 Crosstalk vs. Frequency, 15 V Dual Supply
0
200
V
V
= +15V
= –15V
DD
180
SS
T
= 25°C
A
12V SS
15V DS
–20
–40
160
140
120
100
80
ADJACENT CHANNELS
–60
–80
60
40
–100
–120
NONADJACENT
CHANNELS
20
0
10k
100k
1M
10M
100M
1G
–40
–20
0
20
40
60
80
100
120
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 17. Transition Time (tTRANSITION) vs. Temperature for Single Supply
(SS) and Dual Supply (DS)
Figure 20. ADGS1209 Crosstalk vs. Frequency, 15 V Dual Supply
Rev. 0 | Page 15 of 33
ADGS1208/ADGS1209
Data Sheet
10
T
= 25°C
A
–6
–8
100nF DECOUPLING CAPACITOR
10µF + 100nF DECOUPLING CAPACITOR
NO DECOUPLING
V
V
= +15V
= –15V
DD
SS
–10
–30
T
= 25°C
A
–10
–12
–14
–16
–18
–20
V
V
= +15V
= –15V
DD
SS
–50
–70
–90
–110
–130
100
1k
10k
100k
1M
10M
100M
1G
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. ADGS1209 Insertion Loss vs. Frequency, 15 V Dual Supply
Figure 21. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency,
15 V Dual Supply
8
10
LOAD = 10kΩ
V
V
= +15V
= –15V
DD
T
= 25°C
7
6
5
4
3
2
1
0
A
SS
T
= 25°C
A
1
SOURCE/DRAIN ON
DRAIN OFF
V
= +5V, V = –5V, V = +3.5V rms
SS S
DD
V
= +15V, V = –15V, V = +5V rms
SS S
DD
0.1
SOURCE OFF
0.01
–15
–10
–5
0
5
10
15
10
100
1k
FREQUENCY (Hz)
10k
100k
SOURCE VOLTAGE (V)
Figure 25. ADG1208 Capacitance vs. Source Voltage, 15 V Dual Supply
Figure 22. THD + N vs. Frequency
8
–6
V
V
= +12V
= 0V
DD
SS
7
6
5
4
3
2
1
0
T
= 25°C
A
–8
–10
–12
–14
–16
–18
–20
T
V
V
= 25°C
SOURCE/DRAIN ON
DRAIN OFF
A
= +15V
= –15V
DD
SS
SOURCE OFF
100
1k
10k
100k
1M
10M
100M
1G
0
1
2
3
4
5
6
7
8
9
10 11 12
FREQUENCY (Hz)
SOURCE VOLTAGE (V)
Figure 26. ADG1208 Capacitance vs. Source Voltage,
12 V Single Supply
Figure 23. ADGS1208 Insertion Loss vs. Frequency, 15 V Dual Supply
Rev. 0 | Page 16 of 33
Data Sheet
ADGS1208/ADGS1209
300
250
200
150
100
50
5
4
3
2
1
0
T
= 25°C
A
V
V
= +12V
= 0V
= 25°C
DD
SS
ADGS1208 WITH S8 SLECTED
T
A
15V
SOURCE/DRAIN ON
DRAIN OFF
12V
SOURCE OFF
0
0
1
2
3
4
5
6
7
8
9
10 11 12
2.7
3.0
3.5
4.0
(V)
4.5
5.0
5.5
SOURCE VOLTAGE (V)
V
L
Figure 27. ADG1209 Capacitance vs. Source Voltage, 12 V Single Supply
Figure 30. IDD vs. VL
5
450
T
= 25°C
A
400
350
300
250
200
150
100
50
V
V
= +15V
= –15V
= 25°C
DD
SS
4
3
2
1
0
T
A
SOURCE/DRAIN ON
DRAIN OFF
V
= 5V
L
V
= 3V
L
SOURCE OFF
0
1
10
20
30
40
50
–15 –12
–9
–6
–3
0
3
6
9
12
15
SOURCE VOLTAGE (V)
SCLK FREQUENCY (MHz)
Figure 28. ADG1209 Capacitance vs. Source Voltage, 15 V Dual Supply
Figure 31. IL vs. SCLK Frequency when CS is High
0.20
SCLK = 2.5MHz
SCLK IDLE
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
0
2
4
6
8
TIME (µs)
Figure 29. Digital Feedthrough
Rev. 0 | Page 17 of 33
ADGS1208/ADGS1209
TEST CIRCUITS
Data Sheet
I
(OFF)
A
I
(OFF)
A
S
D
(ON)
D
Sx
Dx
Sx
Dx
V
S
V
D
V
V
D
S
Figure 32. On Leakage
Figure 36. Off Leakage
V
V
DD
SS
V
V
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
V
DD
SS
V
OUT
S1
R
L
50Ω
Sx
50Ω
D
R
L
50Ω
V
S
S2
Dx
V
V
OUT
S
R
50Ω
L
GND
GND
V
WITH SWITCH
V
OUT
OUT
INSERTION LOSS = 20 log
CHANNEL TO CHANNEL CROSSTALK = 20 log
V
WITHOUT SWITCH
V
S
S
Figure 33. Channel to Channel Crosstalk
Figure 37. Insertion Loss/−3 dB Bandwidth
V
V
DD
SS
0.1µF
0.1µF
V
V
DD
SS
0.1µF
0.1µF
NETWORK
V
V
ANALYZER
DD
SS
AUDIO PRECISION
V
V
DD
SS
Sx
50Ω
R
S
Sx
V
S
Dx
V
S
V p-p
V
OUT
R
50Ω
L
Dx
GND
V
OUT
R
110Ω
L
GND
V
OUT
OFF ISOLATION = 20 log
V
S
Figure 34. Off Isolation
Figure 38. THD + N
V
V
SS
NETWORK
ANALYZER
INTERNAL
BIAS
V
DD
SS
R
L
50Ω
V
S
I
V
NC
DS
OUT
R
50Ω
S1
D1
L
GND
V1
V
OUT
ACPSRR = 20 log
V
S
Sx
Dx
NOTES
S
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
R
= V /I
1 DS
FROM THE ACPSRR MEASUREMENT.
ON
Figure 35. ACPSRR
Figure 39. On Resistance
Rev. 0 | Page 18 of 33
Data Sheet
ADGS1208/ADGS1209
V
V
V
V
DD
SS
DD
SS
SCLK
0V
S1
V
S
S2 TO S7
S8
V
= V
S8
S1
80%
80%
ADGS12081
OUTPUT
OUTPUT
D
300Ω
GND
35pF
tD
1
SIMILAR CONNECTION FOR THE ADGS1209.
Figure 40. Break-Before-Make Time Delay, tD
V
V
V
V
DD
SS
DD
SS
SCLK
50%
50%
ADGS12081
S1
V
S1
S2 TO S7
S8
V
R
S8
90%
V
D
OUT
C
L
35pF
GND
L
300Ω
10%
tTRANSITION
tTRANSITION
1
SIMILAR CONNECTION FOR THE THE ADGS1209.
Figure 41. Transition Time, tTRANSITION
V
V
V
V
DD
SS
DD
SS
SCLK
50%
50%
ADGS12081
S1
V
S1
S2 TO S8
90%
V
D
OUT
R
300Ω
C
L
35pF
GND
L
10%
tOFF (EN)
tON (ENO)
1
SIMILAR CONNECTION FOR THE ADGS1209.
Figure 42. Switching Times, tON (EN) and tOFF (EN)
V
V
V
V
DD
SS
3V
DD
SS
SCLK
R
V
S
Sx
Dx
V
OUT
C
1nF
L
S
Q
= C × ΔV
L OUT
INJ
INPUT LOGIC
GND
V
OUT
ΔV
OUT
SWITCH OFF
SWITCH ON
Figure 43. Charge Injection, QINJ
Rev. 0 | Page 19 of 33
ADGS1208/ADGS1209
Data Sheet
V
V
DD
SS
SS
V
V
DD
SCLK
50%
50%
ADGS12081
S1
V
GPO
C
L
15pF
90%
GND
10%
tOFF (GPO)
tON (GPO)
1
SIMILAR CONNECTION FOR THE ADGS1209.
Figure 44. GPOx Timing, tON and tOFF
V
V
V
V
DD
DD
SS
SS
GPO1
V
V
GPO1
GPO2
C
15pF
L
GPO2
V
V
GPO2
GPO1
80%
80%
C
15pF
L
ADGS12081
GND
tD (GPO)
TIME DELAY BETWEEN
GPO1 TURNING OFF
AND GPO2 TURNING ON
1
SIMILAR CONNECTION FOR THE ADGS1209.
Figure 45. GPOx Break-Before-Make Time Delay, tD
Rev. 0 | Page 20 of 33
Data Sheet
ADGS1208/ADGS1209
TERMINOLOGY
IDD
CS (On), CD (On)
I
DD is the positive supply current.
CS (On) and CD (On) are the on switch capacitances, which are
measured with reference the ground.
ISS
ISS is the negative supply current.
CIN
CIN is the digital input capacitance.
VD, VS
VD and VS are the analog voltage on Terminal Dx and Terminal
Sx, respectively.
tON
tON is the delay between applying the digital control input and
the output switching on.
RON
RON is the ohmic resistance between Terminal Dx and Terminal
tOFF
Sx.
tOFF is the delay between applying the digital control input and
the output switching off.
∆RON
∆RON is the difference between the RON of any two channels.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
RFLAT (ON)
RFLAT (ON) is flatness that is the difference between maximum and
minimum on resistance values measured over the specified
analog signal range.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
IS (Off)
IS (Off) is the source leakage current with the switch off.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
IS (On), ID (On)
IS (On) and ID (On) are the channel leakage currents with the
switch on.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINL
On Response
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
INL and IINH are the low and high input currents of the digital
On response is the frequency response of the on switch.
Insertion Loss
V
Insertion loss is the loss due to the on resistance of the switch.
I
I
Total Harmonic Distortion + Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
inputs, respectively.
CS (Off)
AC Power Supply Rejection Ratio (ACPSRR)
CS (Off) is the off switch source capacitance, which is measured
with reference to ground.
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. ACPSRR is a measure of the ability of
the devices to avoid coupling noise and spurious signals that
appear on the supply voltage pin to the output of the switch. The dc
voltage on the device is modulated by a sine wave of 0.62 V p-p.
CD (Off)
CD (Off) is the off switch drain capacitance, which is measured
with reference to ground.
Rev. 0 | Page 21 of 33
ADGS1208/ADGS1209
THEORY OF OPERATION
Data Sheet
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the ninth to the 16th SCLK falling edge during SPI
reads. A register write occurs on the 16th SCLK rising edge
during SPI writes.
The ADGS1208/ADGS1209 are a set of serially controlled
analog multiplexers comprising eight single channels and four
differential channels, respectively, with error detection features.
SPI Mode 0 and SPI Mode 3 can be used with the devices, and
they operate with SCLK frequencies up to 50 MHz. The default
mode for the ADGS1208/ADGS1209 is address mode, in which
the registers of the device are accessed by a 16-bit SPI command
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25.
CS
bounded by . The SPI command becomes 24-bit if the user
enables CRC error detection. Other error detection features include
SCLK count error and invalid read/write error. If any of these
SPI interface errors occur, they are detectable by reading the
error flags register. The ADGS1208/ADGS1209 can also operate
in two other modes, namely burst mode and daisy-chain mode.
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI interface are
detectable. The three detectable errors are incorrect SCLK error
detection, invalid read and write address error detection, and
CRC error detection. Each error has a corresponding enable bit
in the error configuration register. In addition, there is an error
flag bit for each error in the error flags register.
CS
The interface pins of the ADGS1208/ADGS1209 are , SCLK,
CS
SDI, and SDO. Hold
low when using the SPI interface. Data
is captured on SDI on the rising edge of SCLK, and data is
propagated out on SDO on the falling edge of SCLK. SDO has an
open-drain output; thus, connect a pull-up to this output. When
not pulled low by the ADGS1208/ADGS1209, SDO is in a high
impedance state.
Cyclic Redundancy Check (CRC) Error Detection
The CRC error detection feature extends a valid SPI frame by
eight SCLK cycles. These eight extra cycles are needed to send the
CRC byte for that SPI frame. The CRC byte is calculated by the SPI
W
block using the 16-bit payload: the R/ bit, Register Address
ADDRESS MODE
Bits[6:0], and Register Data Bits[7:0]. The CRC polynomial used
in the SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a
timing diagram with CRC enabled, see Figure 47. Register
writes occur at the 24th SCLK rising edge with CRC error
checking enabled.
Address mode is the default mode for the ADGS1208/ADGS1209
on power-up. A single SPI frame in address mode is bounded
CS
CS
by a
falling edge and the succeeding
rising edge. An SPI
frame is comprised of 16 SCLK cycles. The timing diagram for
address mode is shown in Figure 46. The first SDI bit indicates if
the SPI command is a read or write command. When the first
bit is set to 0, a write command is issued, and if the first bit is set
to 1, a read command is issued. The next seven bits determine the
target register address. The remaining eight bits provide the data
to the addressed register. The last eight bits are ignored during a
read command, because during these clock cycles, SDO
During an SPI write, the microcontroller/CPU provides the
CRC byte through SDI. The SPI block checks the CRC byte just
before the 24th SCLK rising edge. On this same edge, the register
write is prevented if an incorrect CRC byte is received by the
SPI interface. In the case that an incorrect CRC byte is detected,
the CRC error flag is asserted in the error flags register.
During an SPI read, the CRC byte is provided to the
microcontroller through SDO.
propagates out the data contained in the addressed register.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
SDI
R/W A6
0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Figure 46. Address Mode Timing Diagram
1
2
8
9
10
16
17
18
19
20
21
22
23
24
CS
SCLK
SDI
R/W A6
0
A0
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
SDO
0
1
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
Figure 47. Timing Diagram with CRC Enabled
Rev. 0 | Page 22 of 33
Data Sheet
ADGS1208/ADGS1209
SCLK Count Error Detection
BURST MODE
SCLK count error detection allows the user to detect if an
incorrect number of SCLK cycles are sent by the microcontroller/
CPU. When in address mode, with CRC disabled, 16 SCLK
cycles are expected. If 16 SCLK cycles are not detected, the
SCLK count error flag asserts in the error flags register. When
less than 16 SCLK cycles are received by the device, a write to
the register map never occurs. When the ADGS1208/ADGS1209
receive more than 16 SCLK cycles, a write to the memory map
still occurs at the 16th SCLK rising edge, and the flag asserts in
the error flags register. With CRC enabled, the expected
number of SCLK cycles is 24. SCLK count error detection is
enabled by default and can be configured by the user through
the error configuration register.
The SPI interface can accept consecutive SPI commands
without the need to de-assert the CS line, which is called burst
mode. Burst mode is enabled through the burst enable register.
This mode uses the same 16-bit command to communicate
with the device. In addition, the response of the device at SDO
is still aligned with the corresponding SPI command. Figure 48
shows an example of SDI and SDO during burst mode.
The invalid read/write address and CRC error checking functions
operate similarly during burst mode as they do during address
mode. However, SCLK count error detection operates in a
slightly different manner. The total number of SCLK cycles
CS
within a given
frame are counted, and if the total is not a
multiple of 16, or a multiple of 24 when CRC is enabled, the
SCLK count error flag asserts.
Invalid Read/Write Address Error Detection
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error occurs.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register never
occurs when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be
disabled by the user through the error configuration register.
CS
SDI
COMMAND0[15:0] COMMAND1[15:0] COMMAND2[15:0] COMMAND3[15:0]
RESPONSE0[15:0] RESPONSE1[15:0] RESPONSE2[15:0] RESPONSE3[15:0]
Figure 48. Burst Mode Frame
SDO
SOFTWARE RESET
When in address mode, the user can initiate a software reset.
To do so, write two consecutive SPI commands, 0xA3 followed
by 0x05, targeting Register 0x0B. After a software reset, all
register values are set to default.
CLEARING THE ERROR FLAGS REGISTER
DAISY-CHAIN MODE
To clear the error flags register, write the special 16-bit SPI
frame, 0x6CA9, to the device. This SPI command does not
trigger the invalid read/write address error. When CRC is
enabled, the user must also send the correct CRC byte for a
successful error clear command. At the 16th or 24th SCLK rising
edge, the error flags register resets to 0.
The connection of several ADGS1208/ADGS1209 devices in a
daisy chain configuration is possible, and Figure 49 shows this
setup. All devices share the same and SCLK line, whereas the
SDO of a device forms a connection to the SDI of the next device,
creating a shift register. In daisy-chain mode, SDO is an eight
cycle delayed version of SDI. When in daisy-chain mode, all
commands target the switch data register. Therefore, it is not
possible to make configuration changes while in daisy-chain mode.
CS
ADGS1208
DEVICE 1
ADGS1208
DEVICE 2
S1
S8
S1
D
D
V
L
S8
SPI
INTERFACE
SDO
SPI
INTERFACE
SDO
SDI
SCLK
CS
RESET/V
L
Figure 49. Two ADGS1208/ADGS1209 Devices Connected in a Daisy-Chain Configuration
Rev. 0 | Page 23 of 33
ADGS1208/ADGS1209
Data Sheet
The ADGS1208/ADGS1209 can only enter daisy-chain mode
when in address mode by sending the 16-bit SPI command,
0x2500 (see Figure 50). When the ADGS1208/ADGS1209
receive this command, the SDO of the device sends out the
same command because the alignment bits at SDO are 0x25,
which allows multiple daisy-connected devices to enter daisy-
chain mode in a single SPI frame. A hardware reset is required to
exit daisy-chain mode.
An SCLK rising edge reads in data on SDI while data is
propagated out of SDO on an SCLK falling edge. The expected
CS
goes high. When this is not the case, the SPI interface sends the
last eight bits received to the switch data register.
number of SCLK cycles must be a multiple of eight before
POWER-ON RESET
The digital section of the ADGS1208/ADGS1209 goes through an
initialization phase during VL power up. This initialization also
occurs after a hardware or software reset. After VL power-up or
a reset, ensure that a minimum of 120 µs from the time of
power-up or reset before any SPI command is issued. Ensure
that VL does not drop out during the 120 µs initialization phase,
because it may result in incorrect operation of the
For the timing diagram of a typical daisy-chain SPI frame, see
CS
Figure 51. When
goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy chain mode, the first eight bits sent out by SDO
ADGS1208/ADGS1209.
CS
on each device in the chain are 0x00. When
goes high, the
internal shift register value does not reset back to 0.
1
0
2
0
3
1
4
0
5
0
6
1
7
0
8
1
9
0
10
0
11
0
12
0
13
0
14
0
15
0
16
0
CS
SCLK
SDI
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Figure 50. SPI Command to Enter Daisy-Chain Mode
CS
SDI
COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0]
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
SDO
8’h00
8’h00
8’h00
COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0]
SDO2
SDO3
8’h00
8’h00
COMMAND3[7:0] COMMAND2[7:0]
8’h00 COMMAND3[7:0]
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 51. Example of an SPI Frame Where Four ADGS1208/ADGS1209 Devices Connect in Daisy-Chain Mode
Rev. 0 | Page 24 of 33
Data Sheet
ADGS1208/ADGS1209
When in round robin mode, the SPI is no longer used to switch
between channels. Instead, to switch from one channel to
another, ensure that a digital signal is present on the CNV pin
ROUND ROBIN MODE
Round robin mode allows the ADGS1208/ADGS1209 to cycle
through the channels faster by reducing the overhead needed
from the digital interface to switch from one channel to the
next. The round robin configuration register selects which
channels are to be included in a cycle, while the CNV edge
select register selects on which edge of CNV the ADGS1208/
ADGS1209 switch to the next channel in the sequence. At the
end of the channel cycle, a resync pulse appears on SDO to
inform the user that the current cycle ended and then it loops
back to the start of the sequence of channels. Figure 52 shows
an example of the round robin mode interface and Figure 53
shows the CNV signal of the analog-to-digital converter (ADC)
being used in conjunction with the ADGS1208 in round robin
mode.
CS
while
is pulled low.
To exit round robin mode, either perform a hardware reset or
send the 16-bit addressable mode SPI frames: 0xA318 followed
by 0xE3B4. These are the only SPI commands recognized by the
SPI interface while in round robin mode.
Round robin mode is significantly faster than addressable mode
to cycle through channels because it removes the 16-bit
overhead required to change input channel. In addition, round
robin mode removes the need for SCLK to be running, which
reduces the digital current consumption (IL). The maximum
CNV frequency is bound by the transition time of the device,
along with the required settling time for the application.
After configuration completes, the round robin enable register
allows the ADGS1208/ADGS1209 to enter round robin mode.
ROUND ROBIN CYCLE
CS
CNV
MUX
X
S1
S2
S(LAST)
RESYNC
CHANNEL
SDO
Figure 52. Round Robin Mode Interface Example
tCYC
VIO
S1
IN1 S2
IN2
IN0
SDI
CNV
SDO
D
AD7980
IN
S3
tACQ
tCONV
ADGS1208
CNV
SCK
IN7 S8
AQUISITION
CONVERSION
AQUISITION
CNV
CS SDI SCK
CONVERT
GPO
CLK
1
2
3
14
15
16
SCK
SDO
DATA IN
GPO
DIGITAL HOST
tDIS
tEN
D15
D14
D13
D1
D0
MUX
N
N + 1
N + 2
CHANNEL
Figure 53. Example of CNV Signal of an ADC Cycling Through Channels in the ADGS1208
Rev. 0 | Page 25 of 33
ADGS1208/ADGS1209
Data Sheet
or low. When the device is in round robin mode, the GPOs are
driven low. The logic low level is GND and VL sets the logic
high level. Figure 54 shows how the ADGS1208 can be used to
control another device, which in this example is the ADG758.
GENERAL-PURPOSE OUTPUTS
The ADGS1208/ADGS1209 have four general-purpose outputs
(GPOs). These digital outputs allow the control of other devices
using the ADGS1208/ADGS1209. The GPOs are controlled
from the SW_DATA register, where they can be either set high
ADGS1208
ADG758
S1
S1
D
D
S8
S8
GPO1
GPO2
GPO3
GPO4
SDO
SPI
1 OF 8
DECODER
INTERFACE
CNV
A0
A1
A2
EN
SDI
SCLK
CS
RESET/V
L
Figure 54. ADGS1208 Device Controlling the ADG758
Rev. 0 | Page 26 of 33
Data Sheet
ADGS1208/ADGS1209
APPLICATIONS INFORMATION
DIGITAL INPUT BUFFERS
POWER SUPPLY RECOMMENDATIONS
There are input buffers present on the digital input pins (
SCLK, and SDI). These buffers are active at all times; as result,
there is current draw from the VL supply if SCLK or SDI are
,
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
CS
toggling, regardless of whether
this current draw, refer to the Specifications section and Figure 31.
is active. For typical values of
CS
An example of a bipolar power solution is shown in Figure 55.
The ADP5070 dual switching regulator generates a positive and
negative supply rail for the ADGS1208/ADGS1209, amplifier,
and/or a precision converter in a typical signal chain. Also
shown in Figure 55 are two optional low dropout (LDO)
regulators, ADP7118 and ADP7182 (positive and negative,
respectively), that can be used to reduce the output ripple of the
ADP5070 in ultralow noise sensitive applications.
SETTLING TIME
Disturbances are apparent on the source/drain when switching
between channels, as is typical with complementary metal-
oxide semiconductor (CMOS) switches and multiplexers. A
sufficient wait time is necessary for these disturbances to settle
before taking a measurement to ensure an accurate reading. The
settling time for a data acquisition system is dependent on the
load on the output of the multiplexer.
The ADM7160 can be used to generate the VL voltage required
to power digital circuitry within the ADGS1208/ADGS1209.
ADM7160
+3.3V
POWER SUPPLY RAILS
LDO
+16.5V
–16.5V
ADP7118
LDO
To guarantee correct operation of the ADGS1208/ADGS1209,
0.1 µF decoupling capacitors are required.
+15V
–15V
+5V
ADP5070
INPUT
ADP7182
LDO
The ADGS1208/ADGS1209 can operate with bipolar supplies
between 4.5 V and 16.5 V. The supplies on VDD and VSS do
not need to be symmetrical. However, the VDD to VSS range must
not exceed 33 V. The ADGS1208/ADGS1209 can also operate
with single supplies between 5 V and 20 V with VSS connected
to GND.
.
Figure 55. Bipolar Power Solution
Table 10. Recommended Power Management Devices
Product
Description
ADP5070
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
ADM7160 5.5 V, 200 mA, ultralow noise LDO linear regulator
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
The device is fully specified at 15 V and +12 V analog supply
voltage ranges.
ADP7118
ADP7182
20 V, 200 mA, low noise CMOS LDO linear regulator
−28 V, −200 mA, low noise LDO linear regulator
Rev. 0 | Page 27 of 33
ADGS1208/ADGS1209
Data Sheet
REGISTER SUMMARIES
Table 11. ADGS1208 Register Summary
Reg. Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default RW
0x01 SW_DATA
0x02 ERR_CONFIG
0x03 ERR_FLAGS
0x05 BURST_EN
0x06 ROUND_ROBIN_EN
GPO4 GPO3
GPO2
GPO1
A2
A1
A0
EN
0x00
0x06
0x00
R/W
R/W
R
Reserved
Reserved
RW_ERR_EN
SCLK_ERR_EN
CRC_ERR_EN
RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG
Reserved
Reserved
S4_EN
BURST_MODE_EN 0x00
ROUND_ROBIN_EN 0x00
R/W
R/W
R/W
R/W
R/W
0x07 RROBIN_CHANNEL_CONFIG S8_EN S7_EN
0x09 CNV_EDGE_SEL
S6_EN
S5_EN
S3_EN
S2_EN
S1_EN
0xFF
0x00
0x00
RESERVED
CNV_EDGE_SEL
0x0B SOFT_RESETB
SOFT_RESETB
Table 12. ADGS1209 Register Summary
Reg. Name
Bit 7 Bit 6
Bit 5
GPO2
Reserved
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default RW
0x01 SW_DATA
GPO4 GPO3
GPO1
Reserved
A1
A0
EN
0x00
0x06
0x00
R/W
R/W
R
0x02 ERR_CONFIG
0x03 ERR_FLAGS
RW_ERR_EN
SCLK_ERR_EN
CRC_ERR_EN
RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG
0x05 BURST_EN
Reserved
Reserved
S4_EN
BURST_MODE_EN 0x00
ROUND_ROBIN_EN 0x00
R/W
R/W
R/W
R/W
R/W
0x06 ROUND_ROBIN_EN
0x07 RROBIN_CHANNEL_CONFIG
0x09 CNV_EDGE_SEL
0x0B SOFT_RESETB
Reserved
S3_EN
S2_EN
S1_EN
0x0F
0x00
0x00
Reserved
CNV_EDGE_SEL
SOFT_RESETB
Rev. 0 | Page 28 of 33
Data Sheet
ADGS1208/ADGS1209
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
The switch data register controls the status of the eight switches of the ADGS1208/ADGS1209 as well as the general-purpose digital
outputs. Use the ADGS1208/ADGS1209 truth tables in conjunction with the bit descriptions.
Table 13. Bit Descriptions for SW_DATA in the ADGS1208
Bits
Bit Name
GPO4
GPO3
GPO2
GPO1
A2
Settings
Description
Default Access
7
Enable bit for GPO4.
Enable bit for GPO3.
Enable bit for GPO2.
Enable bit for GPO1.
Enable bit for A2.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
5
4
3
2
A1
Enable bit for A1.
1
A0
Enable bit for A0.
0
EN
Enable bit for the ADGS1208.
ADGS1208 disabled.
ADGS1208 enabled.
0
1
Table 14. Bit Descriptions for SW_DATA ADGS1209
Bits
Bit Name
GPO4
GPO3
GPO2
GPO1
Reserved
A1
Settings
Description
Default Access
7
Enable bit for GPO4.
Enable bit for GPO3.
Enable bit for GPO2.
Enable bit for GPO1.
This bit is reserved. Set this bit to 0.
Enable bit for A1.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R
6
5
4
3
2
R/W
R/W
R/W
1
A0
Enable bit for A0.
0
EN
Enable bit for ADGS1209.
ADGS1209 disabled.
ADGS1209 enabled.
0
1
Table 15. ADGS1208 Truth Table
A2
X
0
0
0
0
1
1
1
A1
X
0
0
1
1
0
0
1
A0
EN
0
1
1
1
1
1
1
1
On Switch
X
0
1
0
1
0
1
0
1
None
S1
S2
S3
S4
S5
S6
S7
S8
1
1
1
Rev. 0 | Page 29 of 33
ADGS1208/ADGS1209
Data Sheet
Table 16. ADGS1209 Truth Table
A1
A0
EN
0
1
On Switch Pair
X
0
X
0
None
S1
0
1
1
S2
1
0
1
S3
1
1
1
S4
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
The error configuration register allows the user to enable and disable the relevant error features as required.
Table 17. Bit Descriptions for ERR_CONFIG
Bits
[7:3]
2
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
0x0
0x1
R
RW_ERR_EN
Enable bit for detecting an invalid read/write address.
R/W
0
1
Disabled.
Enabled.
1
0
SCLK_ERR_EN
CRC_ERR_EN
Enable bit for detecting the correct number of SCLK cycles in an SPI frame. 0x1
16 SCLK cycles are expected when CRC is disabled and burst mode is
disabled. 24 SCLK cycles are expected when CRC is enabled and burst
mode is disabled. A multiple of 16 SCLK cycles is expected when CRC is
disabled and burst mode is enabled. A multiple of 24 SCLK cycles is
expected when CRC is enabled and burst mode is enabled.
R/W
R/W
0
1
Disabled.
Enabled.
Enable bit for CRC error detection. SPI frames are 24 bits wide when
enabled.
0x0
0
1
Disabled.
Enabled.
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error occurred. To clear the error flags register, write the special 16-bit SPI
command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user
must include the correct CRC byte during the SPI write for the clear error flags register command to succeed.
Table 18. Bit Descriptions for ERR_FLAGS
Bits
[7:3]
2
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
0x0
0x0
R
R
RW_ERR_FLAG
Error flag for invalid read/write address. The error flag asserts during an
SPI read if the target address does not exist. The error flag also asserts
when the target address of an SPI write does not exist or is read only.
0
1
No error.
Error.
1
0
SCLK_ERR_FLAG
CRC_ERR_FLAG
Error flag for the detection of the correct number of SCLK cycles in an SPI
frame.
No error.
0x0
0x0
R
R
0
1
Error.
Error flag that determines if a CRC error occurred during a register write.
0
1
No error.
Error.
Rev. 0 | Page 30 of 33
Data Sheet
ADGS1208/ADGS1209
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
CS
commands without deasserting
.
Table 19. Bit Descriptions for BURST_EN
Bits
[7:1]
0
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
0x0
0x0
R
BURST_MODE_EN
Burst mode enable bit.
Disabled.
Enabled.
R/W
0
1
ROUND ROBIN ENABLE REGISTER
Address: 0x06, Reset: 0x00, Name: ROUND_ROBIN_EN
The round robin register allows the user to enable or disable round robin mode. When enabled, the user can cycle through the channels
enabled in the round robin configuration register by presenting the relevant edge on the CNV pin.
Table 20. Bit Descriptions for ROUND_ROBIN_EN
Bits
[7:1]
0
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
Round robin mode enable bit.
Disabled.
0x0
0x0
R
ROUND_ROBIN_EN
R/W
0
1
Enabled.
ROUND ROBIN CHANNEL CONFIGURATION REGISTER
Address: 0x07, Reset: 0xFF (ADGS1208), 0x0F (ADGS1209), Name: RROBIN_CHANNEL_CONFIG
The round robin channel configuration register controls which channels are included a cycle during round robin mode. During round
robin mode, the channels are cycled through in ascending order.
Table 21. Bit Descriptions for RROBIN_CHANNEL_CONFIG (ADGS1208)
Bits
Bit Name
Settings
Description
Default Access
7
S8_EN
Enable bit for S8.
0x1
0x1
0x1
0x1
0x1
0x1
R/W
R/W
R/W
R/W
R/W
R/W
0
1
S8 disabled during round robin mode.
S8 enabled during round robin mode.
Enable bit for S7.
S7 disabled during round robin mode.
S7 enabled during round robin mode.
Enable bit for S6.
S6 disabled during round robin mode.
S6 enabled during round robin mode.
Enable bit for S5.
S5 disabled during round robin mode.
S5 enabled during round robin mode.
Enable bit for S4.
6
5
4
3
2
S7_EN
S6_EN
S5_EN
S4_EN
S3_EN
0
1
0
1
0
1
0
1
S4 disabled during round robin mode.
S4 enabled during round robin mode.
Enable bit for S3.
0
1
S3 disabled during round robin mode.
S3 enabled during round robin mode.
Rev. 0 | Page 31 of 33
ADGS1208/ADGS1209
Data Sheet
Bits
Bit Name
Settings
Description
Default Access
1
S2_EN
Enable bit for S2.
0x1
R/W
0
1
S2 disabled during round robin mode.
S2 enabled during round robin mode.
Enable bit for S1.
0
S1_EN
0x1
R/W
0
1
S1 disabled during round robin mode.
S1 enabled during round robin mode.
Table 22. Bit Descriptions for RROBIN_CHANNEL_CONFIG (ADGS1209)
Bits
[7:4]
3
Bit Name
Reserved
S4_EN
Settings
Description
Default Access
These bits are reserved. Set these bits to 0.
Enable bit for S4.
0x0
0x1
R
R/W
0
1
S4 disabled during round robin mode.
S4 enabled during round robin mode.
Enable bit for S3.
2
1
0
S3_EN
S2_EN
S1_EN
0x1
0x1
0x1
R/W
R/W
R/W
0
1
S3 disabled during round robin mode.
S3 enabled during round robin mode.
Enable bit for S2.
S2 disabled during round robin mode.
S2 enabled during round robin mode.
Enable bit for S1.
0
1
0
1
S1 disabled during round robin mode.
S1 enabled during round robin mode.
CNV EDGE SELECT REGISTER
Address: 0x09, Reset: 0x00, Name: CNV_EDGE_SEL
The CNV edge select register allows the user to select the active edge of the CNV pin when the device is in round robin mode.
Table 23. Bit Descriptions for CNV_EDGE_SEL
Bits
[7:1]
0
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
CNV active edge select bit.
0x0
0x0
R
CNV_EDGE_SEL
R/W
0
1
Falling edge of CNV is the active edge.
Rising edge of CNV is the active edge.
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
Use the software reset register to perform a software reset. Consecutively, write 0xA3 followed by 0x05 to this register, and the registers of
the device reset to their default state.
Table 24. Bit Descriptions for SOFT_RESETB
Bits
Bit Name
Settings
Description
Default Access
[7:0]
SOFT_RESETB
To perform a software reset, consecutively write 0xA3 followed by 0x05 to 0x0
this register.
R
Rev. 0 | Page 32 of 33
Data Sheet
ADGS1208/ADGS1209
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-24-15
CP-24-15
ADGS1208BCPZ
ADGS1208BCPZ-RL7
ADGS1209BCPZ
ADGS1209BCPZ-RL7
EVAL-ADGS1208SDZ
EVAL-ADGS1209SDZ
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
ADGS1208 Evaluation Board
CP-24-15
CP-24-15
ADGS1209 Evaluation Board
1 Z = RoHS Compliant Part.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16724-0-4/18(0)
Rev. 0 | Page 33 of 33
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