ADGS1412BCPZ-RL7_技术文档

Serially Controlled, 1.5 Ω, On-Resistance,

High Voltage, iCMOS, Quad SPST Switch

ADGS1412

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

SPI interface with error detection

ADGS1412

Includes CRC, invalid read/write address, and SCLK count

error detection

Supports burst and daisy-chain mode

Industry-standard SPI Mode 0 and Mode 3 interface-

compatible

S1

S2

S3

S4

D1

D2

D3

D4

1.5 Ω typical on resistance at 25°C

0.3 Ω typical on-resistance flatness at 25°C

0.1 Ω typical on-resistance match between channels at 25°C

Fully specified at 15 V, 5 V, and +12 V

SPI

INTERFACE

SDO

V

_SSto V_DDanalog signal range

SCLK SDI CS RESET/V

L

APPLICATIONS

Figure 1.

Automated test equipment

Data acquisition systems

Battery-powered systems

Sample-and-hold systems

Audio signal routing

Video signal routing

Communications systems

Relay replacement

GENERAL DESCRIPTION

The ADGS1412 contains four independent single-pole/single-

throw (SPST) switches. An serial peripheral interface (SPI)

controls the switches. The SPI interface has robust error detection

features such as cyclic redundancy check (CRC) error detection,

invalid read/write address detection, and SCLK count error

detection.

PRODUCT HIGHLIGHTS

1. SPI interface removes the need for parallel conversion,

logic traces and reduces GPIO channel count.

2. Daisy-chain mode removes additional logic traces when

multiple devices are used.

3. CRC error detection, invalid read/write address detection,

and SCLK count error detection ensures a robust digital

interface.

It is possible to daisy-chain multiple ADGS1412 devices together.

Daisy-chain mode enables the configuration of multiple devices

with a minimal amount of digital lines. The ADGS1412 can also

operate in burst mode to decrease the time between SPI

commands.

4. Safety integrity level (SIL)-compatible.

5. Minimum distortion.

iCMOS construction ensures ultralow power dissipation, making

the device ideally suited for portable and battery-powered

instruments.

Each switch conducts equally well in both directions when on,

and each switch has an input signal range that extends to the

supplies. In the off condition, signal levels up to the supplies

are blocked.

The on-resistance profile is flat over the full analog input range,

which ensures good linearity and low distortion when switching

audio signals.

Rev. 0

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ADGS1412* Product Page Quick Links

Last Content Update: 11/01/2016

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Voltage, iCMOS, Quad SPST Switch Data Sheet

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ADGS1412

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Address Mode............................................................................. 18

Error Detection Features........................................................... 18

Clearing the Error Flags Register............................................. 19

Burst Mode.................................................................................. 19

Software Reset............................................................................. 19

Daisy-Chain Mode..................................................................... 19

Power-On Reset.......................................................................... 20

Applications Information .............................................................. 21

Power Supply Rails ..................................................................... 21

Power Supply Recommendations............................................. 21

Register Summary .......................................................................... 22

Register Details ............................................................................... 23

Switch Data Register .................................................................. 23

Error Configuration Register.................................................... 23

Error Flags Register.................................................................... 24

Burst Enable Register................................................................. 24

Software Reset Register ............................................................. 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

15 V Dual Supply ....................................................................... 3

5 V Dual Supply ......................................................................... 4

12 V Single Supply........................................................................ 6

Continuous Current per Channel, Sx or Dx............................. 7

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 11

Test Circuits..................................................................................... 15

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 18

REVISION HISTORY

10/2016—Revision 0: Initial Version

Rev. 0 | Page 2 of 25

Data Sheet

ADGS1412

SPECIFICATIONS

15 V DUAL SUPPLY

V_DD= +15 V 10%, V_SS= −15 V 10%, V_L= 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.

Table 1.

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

On Resistance, R_ON

V_DDto V_SS

2.6

V

1.5

1.8

0.1

Ω typ

Ω max

Ω typ

V_S= 10 V, I_S= −10 mA, see Figure 28

V_DD= +13.5 V, V_SS= −13.5 V

V_S= 10 V, I_S= −10 mA

2.3

On-Resistance Match Between

Channels, ∆R_ON

0.18

0.3

0.36

0.19

0.4

0.21

0.45

Ω max

Ω typ

Ω max

On-Resistance Flatness, R_{FLAT (ON)}

V_S= 10 V, I_S= −10 mA

LEAKAGE CURRENTS

V_DD= +16.5 V, V_SS= −16.5 V

Source Off Leakage, I_S(Off)

0.03

nA typ

nA max

nA typ

nA max

nA typ

nA max

V_S= 10 V, V_D=



10 V, see Figure 31

0.55

0.03

0.55

0.15

2

4

12.5

30

Drain Off Leakage, I_D(Off)

V_S= 10 V, V_D=



10 V, see Figure 31

Channel On Leakage, I_D(On), I_S(On)

V_S= V_D= 10 V, see Figure 27

DIGITAL INPUTS

Input Voltage

High, V_INH

2

V min

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

V_IN= V_GNDor V_L

1.35

0.8

Low, V_INL

V max

µA typ

µA max

pF typ

Input Current, I_INLor I_INH

0.001

0.1

Digital Input Capacitance, C_IN

Digital Output Capacitance, C_OUT

DYNAMIC CHARACTERISTICS¹

t_ON

4

115

135

160

190

−20

ns typ

ns max

ns typ

ns max

pC typ

R_L= 300 Ω, C_L= 35 pF

V_S= 10 V, see Figure 34

R_L= 300 Ω, C_L= 35 pF

V_S= 10 V, see Figure 34

V_S= 0 V, R_S= 0 Ω, C_L= 1 nF,

see Figure 35

150

210

160

225

t_OFF

Charge Injection, Q_INJ

Off Isolation

−76

dB typ

% typ

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz,

see Figure 30

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz,

see Figure 29

R_L= 110 Ω, 15 V p-p, f = 20 Hz to

20 kHz, see Figure 32

Channel to Channel Crosstalk

Total Harmonic Distortion + Noise

−100

0.014

−3 dB Bandwidth

Insertion Loss

170

−0.2

MHz typ

dB typ

R_L= 50 Ω, C_L= 5 pF, see Figure 33

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz,

see Figure 33

C_S(Off)

C_D(Off)

C_D(On), C_S(On)

22

23

113

pF typ

V_S= 0 V, f = 1 MHz

Rev. 0 | Page 3 of 25

ADGS1412

Data Sheet

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

POWER REQUIREMENTS

I_DD

V_DD= +16.5 V, V_SS= −16.5 V

All switches open

0.001

220

µA typ

1

µA max

µA typ

µA max

µA typ

µA max

All switches closed, V_L= 5.5 V

All switches closed, V_L= 2.7 V

380

230

I_L

Inactive

6.3

1.8

µA typ

µA max

mA typ

Digital inputs = 0 V or V_L

7

2

8.0

2.1

Active at 50 MHz

Digital inputs toggle between

0 V and V_L, V_L= 5.5 V

mA max

mA typ

0.7

Digital inputs toggle between

0 V and V_L, V_L= 2.7 V

1.0

mA max

µA typ

µA max

I_SS

0.001

Digital inputs = 0 V or V_L

V_DD/V_SS

4.5/ 16.5

V min/V max GND = 0 V

¹Guaranteed by design; not subject to production test.

5 V DUAL SUPPLY

V_DD= +5 V 10%, V_SS= −5 V 10%, V_L= 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.

Table 2.

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

On Resistance, R_ON

V_DDto V_SS

V

3.3

Ω typ

V_S= 4.5 V, I_S= −10 mA,

see Figure 28

4

0.13

4.9

5.4

Ω max

Ω typ

V_DD= +4.5 V, V_SS= −4.5 V

V_S= 4.5 V, I_S= −10 mA

On-Resistance Match Between

Channels, ∆R_ON

0.22

0.9

1.1

0.23

1.24

0.25

1.31

Ω max

Ω typ

Ω max

On-Resistance Flatness, R_{FLAT (ON)}

V_S= 4.5 V, I_S= −10 mA

V_DD= +5.5V, V_SS= −5.5 V

LEAKAGE CURRENTS

Source Off Leakage, I_S(Off)

0.03

nA typ

V_S= 4.5 V, V_D=

see Figure 31



4.5 V,

0.55

0.03

2

12.5

nA max

nA typ

Drain Off Leakage, I_D(Off)

V_S= 4.5 V, V_D=

see Figure 31



4.5 V,

0.55

0.05

1.0

2

4

12.5

30

nA max

nA typ

nA max

Channel On Leakage, I_D(On), I_S(On)

V_S= V_D= 4.5V, see Figure 27

DIGITAL INPUTS

Input Voltage

High, V_INH

2

V min

V max

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

1.35

0.8

Low, V_INL

Rev. 0 | Page 4 of 25

Data Sheet

ADGS1412

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

Input Current, I_INLor I_INH

0.001

µA typ

V_IN= V_GNDor V_L

0.1

µA max

pF typ

Digital Input Capacitance, C_IN

Digital Output Capacitance, C_OUT

DYNAMIC CHARACTERISTICS¹

t_ON

4

265

350

280

365

10

ns typ

ns max

ns typ

ns max

pC typ

R_L= 300 Ω, C_L= 35 pF

V_S= 3 V, see Figure 34

R_L= 300 Ω, C_L= 35 pF

V_S= 3 V, see Figure 34

V_S= 0 V, R_S= 0 Ω, C_L= 1 nF,

see Figure 35

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz,

see Figure 30

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz,

see Figure 29

R_L= 110 Ω, 5 V p-p, f = 20 Hz to

20 kHz, see Figure 32

R_L= 50 Ω, C_L= 5 pF,

see Figure 33

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz,

see Figure 33

390

400

430

435

t_OFF

Charge Injection, Q_INJ

Off Isolation

−76

−100

0.03

130

dB typ

% typ

Channel to Channel Crosstalk

Total Harmonic Distortion + Noise

−3 dB Bandwidth

MHz typ

dB typ

Insertion Loss

−0.3

C_S(Off)

C_D(Off)

C_D(On), C_S(On)

POWER REQUIREMENTS

I_DD

32

33

116

pF typ

V_S= 0 V, f = 1 MHz

V_DD= +5.5 V, V_SS= −5.5 V

Digital inputs = 0 V or

V_L, V_L= 5.5 V

0.001

14

µA typ

1.0

20

µA max

µA typ

µA max

All switches closed, V_L= 2.7 V

Digital inputs = 0 V or V_L

I_L

Inactive

6.3

1.8

µA typ

µA max

mA typ

8.0

2.1

Active at 50 MHz

Digital inputs toggle between

0 V and V_L, V_L= 5.5 V

mA max

mA typ

0.7

Digital inputs toggle between

0 V and V_L, V_L= 2.7 V

1.0

mA max

µA typ

µA max

I_SS

0.001

Digital inputs = 0 V or V_L

V_DD/V_SS

4.5/ 16.5

V min/V max GND = 0 V

¹Guaranteed by design; not subject to production test.

Rev. 0 | Page 5 of 25

ADGS1412

Data Sheet

12 V SINGLE SUPPLY

V_DD= 12 V 10%, V_SS= 0 V, V_L= 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.

Table 3.

Parameter

+25°C −40°C to +85°C

−40°C to +125°C

Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

On Resistance, R_ON

0 V to V_DD

V

2.8

Ω typ

V_S= 0 V to 10 V, I_S= −10 mA,

see Figure 28

3.5

0.13

4.3

4.8

Ω max

Ω typ

V_DD= 10.8 V, V_SS= 0 V

V_S= 0 V to 10 V, I_S= −10 mA

On-Resistance Match Between

Channels, ∆R_ON

0.21

0.6

1.1

0.23

1.2

0.25

1.3

Ω max

Ω typ

Ω max

On-Resistance Flatness, R_{FLAT (ON)}

V_S= 0 V to 10 V, I_S= −10 mA

V_DD= 13.2 V, V_SS= 0 V

LEAKAGE CURRENTS

Source Off Leakage, I_S(Off)

0.02

nA typ

V_S= 1 V/10 V, V_D= 10 V/1 V,

see Figure 31

0.55

0.02

2

12.5

nA max

nA typ

Drain Off Leakage, I_D(Off)

V_S= 1 V/10 V, V_D= 10 V/1 V,

see Figure 31

0.55

0.15

1.5

2

4

12.5

30

nA max

nA typ

nA max

Channel On Leakage, I_D(On), I_S(On)

V_S= V_D= 1 V/10 V, see Figure 27

DIGITAL INPUTS

Input Voltage

High, V_INH

2

V min

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

V_IN= V_GNDor V_L

1.35

0.8

Low, V_INL

V max

µA typ

µA max

pF typ

Input Current, I_INLor I_INH

0.001

0.1

Digital Input Capacitance, C_IN

Digital Output Capacitance, C_OUT

DYNAMIC CHARACTERISTICS¹

t_ON

4

190

240

170

215

10

ns typ

ns max

ns typ

ns max

pC typ

R_L= 300 Ω, C_L= 35 pF

V_S= 8 V, see Figure 34

R_L= 300 Ω, C_L= 35 pF

V_S= 8 V, see Figure 34

V_S= 6 V, R_S= 0 Ω, C_L= 1 nF,

see Figure 35

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz, see Figure 30

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz, see Figure 29

270

240

300

265

t_OFF

Charge Injection, Q_INJ

Off Isolation

−76

−100

0.06

130

dB typ

% typ

Channel to Channel Crosstalk

Total Harmonic Distortion + Noise

−3 dB Bandwidth

R_L= 110 Ω, 6 V p-p, f = 20 Hz to

20 kHz, see Figure 32

R_L= 50 Ω, C_L= 5 pF,

see Figure 33

MHz typ

dB typ

Insertion Loss

−0.3

R_L= 50 Ω, C_L= 5 pF,

f = 1 MHz, see Figure 33

C_S(Off)

C_D(Off)

C_D(On), C_S(On)

29

30

116

pF typ

V_S= 6 V, f = 1 MHz

Rev. 0 | Page 6 of 25

Data Sheet

ADGS1412

Parameter

+25°C −40°C to +85°C

−40°C to +125°C

Unit

Test Conditions/Comments

V_DD= 13.2 V

All switches open

POWER REQUIREMENTS

I_DD

0.001

220

µA typ

µA max

µA typ

µA max

µA typ

µA max

1.0

All switches closed, V_L= 5.5 V

All switches closed, V_L= 2.7 V

380

430

250

I_L

Inactive

6.3

1.8

µA typ

µA max

mA typ

Digital inputs = 0 V or V_L

8.0

2.1

Active at 50 MHz

Digital inputs toggle between

0 V and V_L, V_L= 5.5 V

mA max

mA typ

0.7

Digital inputs toggle between

0 V and V_L, V_L= 2.7 V

1.0

mA max

V_DD

5/20

V min/V max GND = 0 V, V_SS= 0 V

¹Guaranteed by design; not subject to production test.

CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx

Table 4. Four Channels On

Parameter

25°C

85°C

125°C

Unit

CONTINUOUS CURRENT, Sx OR Dx¹

V_DD= 15 V, V_SS= −15 V (θ_JA= 54°C/W)

V_DD= 12 V, V_SS= 0 V (θ_JA= 54°C/W)

V_DD= 5 V, V_SS= −5 V (θ_JA= 54°C/W

297

240

224

165

142

135

79

74

72

mA maximum

¹Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.

Table 5. One Channel On

Parameter

25°C

85°C

125°C

Unit

CONTINUOUS CURRENT, Sx OR Dx¹

V_DD= 15 V, V_SS= −15 V (θ_JA= 54°C/W)

V_DD= 12 V, V_SS= 0 V (θ_JA= 54°C/W)

V_DD= 5 V, V_SS= −5 V (θ_JA= 54°C/W

531

433

404

225

210

202

87

85

84

mA maximum

¹Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.

TIMING CHARACTERISTICS

V_L= 2.7 V to 5.5 V, GND = 0 V, and all specifications T_MINto T_MAX, unless otherwise noted. Guaranteed by design and characterization,

not production tested.

Table 6.

Parameter

Limit

Unit

Test Conditions/Comments

TIMING CHARACTRISTICS

t₁

t₂

t₃

t₄

t₅

t₆

20

8

10

6

8

ns min

SCLK period

SCLK high pulse width

SCLK low pulse width

CS falling edge to SCLK active edge

Data setup time

Data hold time

Rev. 0 | Page 7 of 25

ADGS1412

Data Sheet

Parameter

Limit

10

20

8

Unit

Test Conditions/Comments

t₇

ns min

ns max

ns min

SCLK active edge to CS rising edge

t₈

CS falling edge to SDO data available

SCLK falling edge to SDO data available

CS rising edge to SDO returns to high impedance

CS high time between SPI commands

CS falling edge to SCLK becomes stable

CS rising edge to SCLK becomes stable

1

t₉

t₁₀

t₁₁

t₁₂

t₁₃

8

¹Measured with the 1 kΩ pull-up resistor to V_Land 20 pF load. t₉determines the maximum SCLK frequency when SDO is used.

Timing Diagrams

t₁

SCLK

t₂

t₇

t₄

t₃

CS

t₆

t₅

SDI

R/W

A6

A5

1

D2

D1

D0

t₁₀

t₉

SDO

0

t₈

Figure 2. Address Mode Timing Diagram

t₁

SCLK

CS

t₂

t₃

t₄

t₇

t₆

t₅

SDI

D7

D6

D0

D7

D6

D1

D0

INPUT BYTE FOR DEVICE N

t₉

INPUT BYTE FOR DEVICE N + 1

t₁₀

SDO

0

D7

D6

D1

D0

ZERO BYTE

INPUT BYTE FOR DEVICE N

t₈

Figure 3. Daisy Chain Timing Diagram

t₁₁

CS

SCLK

t₁₃

t₁₂

CS

Figure 4. SCLK/ Timing Relationship

Rev. 0 | Page 8 of 25

Data Sheet

ADGS1412

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 7.

Parameter

Rating

V_DDto V_SS

35 V

V_DDto GND

V_SSto GND

V_Lto GND

−0.3 V to +25 V

+0.3 V to −25 V

−0.3 V to +5.75 V

V_SS− 0.3 V to V_DD+ 0.3 V or

30 mA, whichever occurs first

−0.3 V to +5.75 V

600 mA (pulsed at 1 ms,

10% duty cycle maximum)

Data + 15%

Analog Inputs¹

Only one absolute maximum rating can be applied at any one time.

THERMAL RESISTANCE

Digital Inputs¹

Peak Current, Sx or Dx Pins²

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Continuous Current, Sx or Dx^{2, 3}

Temperature Range

Operating

Storage

Junction Temperature

Table 8. Thermal Resistance

Package Type

CP-24-17²

−40°C to +125°C

−65°C to +150°C

150°C

1

θ_JA

θ_JCB

Unit

54

3

°C/W

Reflow Soldering Peak

Temperature, Pb Free

260(+0/−5)°C

¹θ_JCBis the junction to the bottom of the case value.

²Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board with four thermal vias. See JEDEC JESD51.

¹Overvoltages at the digital Sx and Dx pins are clamped by internal diodes.

Limit current to the maximum ratings given.

²Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.

³See Table 4 and Table 5.

ESD CAUTION

Rev. 0 | Page 9 of 25

ADGS1412

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

18 D2

17

D1

S1

S2

16 NIC

V

ADGS1412

SS

GND

S4

TOP VIEW

15 V

DD

(Not to Scale)

14

13

S3

D3

D4

NOTES

1. NIC = NOT INTERNALLY CONNECTED.

2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR

INCREASED RELIABILITY OF THE SOLDER JOINTS AND

MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED

THAT THE PAD BE SOLDERED TO THE SUBSTRATE, V

.

SS

Figure 5. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic Description

1

2

D1

S1

Drain Terminal 1. This pin can be an input or output.

Source Terminal 1. This pin can be an input or output.

3

4, 11

5

6

7, 8, 10, 12,

16, 19, 24

V_SS

GND

S4

D4

NIC

Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.

Ground (0 V) Reference.

Source Terminal 4. This pin can be an input or output.

Drain Terminal 4. This pin can be an input or output.

Not Internally Connected.

9

RESET/V_L

RESET/Logic Power Supply Input (V_L). Under normal operation, drive the RESET/V_Lpin with a 2.7 V to 5.5 V supply.

Pull the RESET pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers

are set to their default.

13

14

15

17

18

20

D3

S3

V_DD

S2

D2

SDO

Drain Terminal 3. This pin can be an input or output.

Source Terminal 3. This pin can be an input or output.

Most Positive Power Supply Potential.

Source Terminal 2. This pin can be an input or output.

Drain Terminal 2. This pin can be an input or output.

Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading

back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of

SCLK. Pull this open-drain output to V_Lwith an external resistor.

21

22

23

CS

Active Low Control Input. CS is the frame synchronization signal for the input data.

Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.

Serial Data Input. Data is captured on the positive edge of the serial clock input.

SCLK

SDI

EPAD

Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and

maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, V_SS.

Rev. 0 | Page 10 of 25

Data Sheet

ADGS1412

TYPICAL PERFORMANCE CHARACTERISTICS

2.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= +10V,

= –10V

DD

SS

2.0

1.5

1.0

0.5

0

V

= +12V,

= –12V

DD

SS

T

= +125°C

= +85°C

A

T

A

T

= +25°C

= –40°C

A

V

= +16.5V,

= –16.5V

DD

SS

V

= +13.5V,

= –13.5V

DD

SS

V

= +15V,

DD

SS

A

V

= –15V

V

I

= +15V

= –15V

= –10mA

DD

SS

T

I

= 25°C

= –10mA

A

S

–16.5 –12.5 –8.5

–4.5

–0.5

3.5

7.5

11.5

15.5

–15

–10

–5

0

5

10

15

V

OR V (V)

V OR V (V)

S D

S

D

Figure 6. On Resistance vs. V_Sor V_Dfor Various Dual Supplies

Figure 9. On Resistance vs. V_Sor V_Dfor Various Temperatures,

±±5 V Dual Supply

4.0

5.0

4.5

4.0

3.5

V

= +4.5V,

= –4.5V

DD

SS

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= +5V,

= –5V

DD

SS

T

= +85°C

= +25°C

A

3.0

2.5

2.0

1.5

1.0

0.5

0

A

V

= +7V,

= –7V

DD

SS

V

= +5.5V,

DD

SS

V

= –5.5V

T

= –40°C

A

V

= +5V

= –5V

DD

SS

T

= 25°C

= –10mA

A

I

S

I

= –10mA

S

–7 –6 –5 –4 –3 –2 –1

0

1

2

3

4

5

6

7

–5

–4

–3

–2

–1

V

0

1

2

3

4

5

V

OR V (V)

S D

S

D

Figure 7. On Resistance vs. V_Sor V_Dfor Various Dual Supplies

Figure ±0. On Resistance vs. V_Sor V_Dfor Various Temperatures,

±5 V Dual Supply

7

4.5

4.0

3.5

V

= 5V,

= 0V

DD

SS

6

5

4

3

2

1

0

T

= +85°C

= +25°C

3.0

2.5

2.0

1.5

1.0

0.5

0

A

V

= 10.8V,

= 0V

DD

SS

V

= 8V,

= 0V

DD

SS

V

= 12V,

= 0V

DD

SS

T

= –40°C

A

V

= 15V,

V

= 13.2V,

= 0V

DD

SS

= 0V

SS

V

= 12V

= 0V

DD

SS

T

= 25°C

= –10mA

A

I

S

I

= –10mA

S

0

2

4

6

8

10

12

14

0

2

4

6

OR V (V)

8

10

12

V

OR V (V)

D

V

S

D

Figure 8. On Resistance vs. V_Sor V_Dfor Various Single Supplies

Figure ±±. On Resistance vs. V_Sor V_Dfor Various Temperatures,

±2 V Single Supply

Rev. 0 | Page 11 of 25

ADGS1412

Data Sheet

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

9

8

V

= 12V

= 0V

I

(OFF) + –

DD

SS

S

D

S

D

(OFF) + –

(OFF) – +

= 1V/10V

BIAS

T

I

= 125°C

= 100mA

A

7

S

, I (ON) ++

S

6

, I (ON) – –

S

5

4

T

S

= 25°C

= 190mA

A

I

3

2

1

0

V

= +5V

= –5V

DD

SS

–1

0

20

40

60

80

100

120

–5

–4

–3

–2

–1

0

1

2

3

4

5

TEMPERATURE (°C)

V

OR V (V)

S

D

Figure 15. Leakage Current vs. Temperature, 12 V Single Supply

Figure 12. On Resistance vs. V_Sor V_Dfor Various Current Levels and

Temperatures, 5 V Dual Supply

1.5

400

T

= 25°C

I

, I (ON) + +

S

A

D

V

= +15V, V = –15V

SS

DD

1.0

0.5

300

200

I

(OFF) + –

I

(OFF) – +

S

D

0

100

V

= +5V, V = –5V

SS

DD

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

0

I

, I (ON) – –

S

D

–100

–200

–300

–400

–500

V

= +12V, V = 0V

SS

DD

I

(OFF) + –

D

I

(OFF) – +

V

= +15V

= –15V

S

DD

SS

= +10V/–10V

BIAS

–15

–10

–5

0

5

10

15

0

20

40

60

80

100

120

V

(V)

TEMPERATURE (°C)

S

Figure 13. Leakage Current vs. Temperature, 15 V Dual Supply

Figure 16. Charge Injection vs. Source Voltage (V_S)

1.5

350

300

250

200

150

100

50

V

= +5V

= –5V

DD

SS

5V DS, t_OFF

= +4.5V/–4.5V

BIAS

1.0

0.5

5V DS, t_ON

12V SS, t_OFF

12V SS, t_ON

0

15V DS, t_OFF

–0.5

–1.0

–1.5

I

(OFF) + –

(OFF) – +

, I (ON) ++

, I (ON) – –

S

D

S

D

15V DS, t_ON

S

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 17. t_ON/t_OFFTime vs. Temperature for Single Supply (SS) and

Dual Supply (DS)

Figure 14. Leakage Current vs. Temperature, 5 V Dual Supply

Rev. 0 | Page 12 of 25

Data Sheet

ADGS1412

0

–20

V

T

= +15V

= –15V

= 25°C

V

T

= +15V

= –15V

= 25°C

DD

SS

DD

SS

–20

–40

A

–40

100nF DECOUPLING

CAPACITORS

–60

–80

–100

–120

–140

–100

10µF + 100nF DECOUPLING

CAPACITORS

–120

100

1k

10k

100k

1M

10M

100M

1G

100

1k

10k

100k

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply

Figure 21. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency, 15 V

Dual Supply

0

–20

T

= 25°C

A

V

T

= +15V

= –15V

= 25°C

DD

SS

0.025

0.020

0.015

0.010

0.005

0

R

= 110Ω, V = 20V p-p

S

L

A

–40

–60

R

= 110Ω, V = 15V p-p

L

S

–80

R

= 110Ω, V = 10V p-p

S

L

–100

–120

–140

R

= 1kΩ, V = 20V p-p

S

L

R

= 1kΩ, V = 10V p-p

R

= 1kΩ, V = 15V p-p

L

S

L

S

20

200

2k

20k

10k

100k

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 19. Crosstalk vs. Frequency, 15 V Dual Supply

Figure 22. THD + N vs. Frequency, 15 V Dual Supply

0

–1

–2

–3

–4

–5

–6

0.20

0.15

0.10

0.05

0

T = 25°C

A

V

= +15V

= –15V

= 25°C

R

= 110Ω, V = 10V p-p

S

DD

SS

L

T

A

R

= 110Ω, V = 5V p-p

S

L

R

= 1kΩ, V = 10V p-p

= 110Ω, V = 2.5V p-p

= 1kΩ, V = 5V p-p

L

S

R

L

S

R

L

S

R

= 1kΩ, V = 2.5V p-p

L

S

20

200

2k

20k

10k

100k

1M

10M

100M

1G

FREQUENCY (Hz)

Figure 20. Insertion Loss vs. Frequency, 15 V Dual Supply

Figure 23. THD + N vs. Frequency, 5 V Dual Supply

Rev. 0 | Page 13 of 25

ADGS1412

Data Sheet

0.14

80

70

60

50

40

30

20

10

0

T

= 25°C

PER CLOSED SWITCH

T

= 25°C

A

I

DD

0.12

0.10

0.08

0.06

0.04

0.02

0

R

= 110Ω, V = 9V p-p

S

L

V

= +15V

= –15V

DD

SS

= 110Ω, V = 6V p-p

V

= +12V

= 0V

L

S

DD

SS

R

= 110Ω, V = 3V p-p

S

L

R

= 1kΩ, V = 9V p-p

L

S

R

= 1kΩ, V = 6V p-p

L

S

V

= +5V

= –5V

DD

SS

= 1kΩ, V = 3V p-p

L

S

2.7

3.0

3.5

4.0

4.5

5.0

5.5

20

200

2k

20k

V

L

(V)

FREQUENCY (Hz)

Figure 24 . THD + N vs. Frequency, 12 V Single Supply

Figure 26. I_DDvs. V_L

2.0

V

= +15V

= –15V

= 25°C

SCLK = 2.5MHz

SCLK IDLE

DD

SS

1.5

1.0

T

A

0.5

0

–0.5

–1.0

–1.5

–2.0

0

2

4

6

8

TIME (µs)

Figure 25. Digital Feedthrough

Rev. 0 | Page 14 of 25

Data Sheet

ADGS1412

TEST CIRCUITS

I

(OFF)

A

I

(OFF)

A

S

D

Sx

Dx

I

(ON)

A

D

Sx

Dx

V

D

V

S

V

D

Figure 27. On Leakage

Figure 31. Off Leakage

V

DD

SS

0.1µF

AUDIO PRECISION

V

DD

SS

R

S

I

DS

Sx

V

S

V1

V p-p

Dx

V

OUT

Sx

Dx

R

110Ω

L

GND

V

S

R

= V /I

1 DS

ON

Figure 28. On Resistance

Figure 32. THD + Noise

V

DD

SS

V

DD

V

SS

0.1µF

NETWORK

ANALYZER

NETWORK

ANALYZER

V

DD

SS

V

DD

V

SS

V

NC

OUT

S1

S2

R

L

50Ω

Sx

50Ω

V

S

S2

D2

R

50Ω

L

Dx

V

OUT

S

R

50Ω

L

GND

V

WITH SWITCH

V

OUT

INSERTION LOSS = 20 log

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

V

WITHOUT SWITCH

S

V

S

Figure 33. −3 dB Bandwidth

Figure 29. Channel to Channel Crosstalk

V

DD

SS

0.1µF

NETWORK

ANALYZER

V

DD

SS

Sx

50Ω

V

S

Dx

V

OUT

R

L

GND

50Ω

V

OUT

OFF ISOLATION = 20 log

V

S

Figure 30. Off Isolation

Rev. 0 | Page 15 of 25

ADGS1412

Data Sheet

V

DD

SS

0.1µF

DD

SS

SCLK

V

OUT

50%

Sx

Dx

R

300Ω

C

L

35pF

L

90%

V

S

V

INPUT LOGIC

GND

OUT

10%

t_ON

t_OFF

Figure 34. Switching Times, t_ONand t_OFF

V

DD

SS

3V

V

SCLK

R

V

S

Sx

Dx

V

OUT

C

1nF

L

S

Q

= C × ∆V

L OUT

INJ

INPUT LOGIC

GND

V

OUT

∆V

OUT

SWITCH OFF

SWITCH ON

Figure 35. Charge Injection, Q_INJ

Rev. 0 | Page 16 of 25

Data Sheet

ADGS1412

TERMINOLOGY

I_DD

C_D(On), C_S(On)

I

_DDrepresents the positive supply current.

C_D(On) and C_S(On) represent on switch capacitances, which

are measured with reference to ground.

I_SS

I_SSrepresents the negative supply current.

C_IN

C_INis the digital input capacitance.

V_D, V_S

V_Dand V_Srepresent the analog voltage on Terminal Dx and

Terminal Sx, respectively.

t_ON

t_ONrepresents the delay between applying the digital control

input and the output switching on.

R_ON

R_ONrepresents the ohmic resistance between Terminal Dx and

t_OFF

Terminal Sx.

t_OFFrepresents the delay between applying the digital control

input and the output switching off.

∆R_ON

∆R_ONrepresents the difference between the R_ONof any two

channels.

Off Isolation

Off isolation is a measure of unwanted signal coupling through

an off switch.

R_{FLAT (ON)}

Flatness that is defined as the difference between the maximum

and minimum value of on resistance measured over the specified

Charge Injection

Charge injection is a measure of the glitch impulse transferred

from the digital input to the analog output during switching.

analog signal range is represented by R_{FLAT (ON)}

.

I_S(Off)

Crosstalk

I_S(Off) is the source leakage current with the switch off.

Crosstalk is a measure of unwanted signal that is coupled

through from one channel to another as a result of parasitic

capacitance.

I_D(Off)

I_D(Off) is the drain leakage current with the switch off.

−3 dB Bandwidth

Bandwidth is the frequency at which the output is attenuated

by 3 dB.

I_D(On), I_S(On)

I_D(On) and I_S(On) represent the channel leakage currents with

the switch on.

On Response

V_INL

On response is the frequency response of the on switch.

V

_INLis the maximum input voltage for Logic 0.

V_INH

_INHis the minimum input voltage for Logic 1.

_INL, I_INH

_INLand I_INHrepresent the low and high input currents of the

Insertion Loss

Insertion loss is the loss due to the on resistance of the switch.

V

Total Harmonic Distortion + Noise (THD + N)

The ratio of the harmonic amplitude plus noise of the signal to

the fundamental is represented by THD + N.

I

digital inputs.

AC Power Supply Rejection Ratio (ACPSRR)

C_D(Off)

ACPSRR is the ratio of the amplitude of signal on the output to the

amplitude of the modulation. ACPSRR is a measure of the ability of

the device to avoid coupling noise and spurious signals that appear

on the supply voltage pin to the output of the switch. The dc voltage

on the device is modulated by a sine wave of 0.62 V p-p.

C_D(Off) represents the off switch drain capacitance, which is

measured with reference to ground.

C_S(Off)

C_S(Off) represents the off switch source capacitance, which is

measured with reference to ground.

Rev. 0 | Page 17 of 25

ADGS1412

Data Sheet

THEORY OF OPERATION

During any SPI command, SDO sends out eight alignment bits

on the first eight SCLK falling edges. The alignment bits observed

at SDO are 0x25.

The ADGS1412 is a set of serially controlled, quad SPST switches

with error detection features. SPI Mode 0 or SPI Mode 3 can be

used with the device, and it operates with SCLK frequencies up

to 50 MHz The default mode for the ADGS1412 is address mode

in which the registers of the device are accessed by a 16-bit SPI

ERROR DETECTION FEATURES

Protocol and communication errors on the SPI interface are

detectable. There are three detectable errors, which are incorrect

SCLK error detection, invalid read and write address error

detection, and CRC error detection. Each of these errors has a

corresponding enable bit in the error configuration register. In

addition, there is an error flag bit for each of these errors in the

error flags register.

CS

command that is bounded by . The SPI command becomes

24 bit if the user enables CRC error detection. Other error detection

features include SCLK count error and invalid read/write error.

If any of these SPI interface errors occur, they are detectable by

reading the error flags register. The ADGS1412 can also operate

in two other modes, namely burst mode and daisy-chain mode.

CS

The interface pins of the ADGS1412 are , SCLK, SDI, and SDO.

Cyclic Redundancy Check (CRC) Error Detection

CS

Hold

low when using the SPI interface. Data is captured on

The CRC error detection feature extends a valid SPI frame by

8 SCLK cycles. These eight extra cycles are needed to send the CRC

byte for that SPI frame. The CRC byte is calculated by the SPI block

the SDI on the rising edge of SCLK, and data is propagated out on

the SDO on the falling edge of SCLK. SDO has an open-drain

output; thus, connect a pull-up to this output. When not pulled

low by the ADGS1412, SDO is in a high impedance state.

W

using the 16-bit payload: the R/ bit, Register Address Bits[6:0],

and Register Data Bits[7:0]. The CRC polynomial used in the

SPI block is x⁸+ x²+ x¹+ 1 with a seed value of 0. For a timing

diagram with CRC enabled, see Figure 37. Register writes occur

at the 24^thSCLK rising edge with CRC Error Checking enabled.

ADDRESS MODE

Address mode is the default mode for the ADGS1412 upon

power up. A single SPI frame in address mode is bounded by

CS

a

falling edge and the succeeding rising edge. It is comprised

During a SPI write, the microcontroller/CPU provides the CRC

byte through SDI. The SPI block checks the CRC byte just before

the 24^thSCLK rising edge. On this same edge, the register write

is prevented if an incorrect CRC byte is received by the SPI

interface. The CRC error flag is asserted in the error flags

register in the case of the incorrect CRC byte being detected.

of 16 SCLK cycles. The timing diagram for address mode is shown

in Figure 36. The first SDI bit indicates if the SPI command is a

read or write command. When the first bit is set to 0, a write

command is issued, and if the first bit is set to 1, a read command

is issued. The next seven bits determine the target register address.

The remaining eight bits provide the data to the addressed register.

The last eight bits are ignored during a read command, because

during these clock cycles SDO propagates out the data contained

in the addressed register.

During a SPI read, the CRC byte is provided to the microcontroller

through SDO.

The CRC error detection feature is disabled by default and can

be configured by the user through the error configuration register.

The target register address of an SPI command is determined on

the eighth SCLK rising edge. Data from this register propagates out

on SDO from the 9^thto the 16^thSCLK falling edge during SPI

reads. A register write occurs on the 16^thSCLK rising edge

during SPI writes.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SCLK

SDI

R/W A6

0

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDO

0

1

0

1

0

1

D7

D6

D5

D4

D3

D2

D1

D0

Figure 36. Address Mode Timing Diagram

1

2

8

9

10

16

17

18

19

20

21

22

23

24

CS

SCLK

SDI

R/W A6

0

A0

D7

D6

D0

C7

C6

C5

C4

C3

C2

C1

C0

SDO

0

1

D7

D6

D0

C7

C6

C5

C4

C3

C2

C1

C0

Figure 37. Timing Diagram with CRC Enabled

Rev. 0 | Page 18 of 25

Data Sheet

ADGS1412

SCLK Count Error Detection

BURST MODE

SCLK count error detection allows the user to detect if an

incorrect number of SCLK cycles are sent by the microcontroller/

CPU. When in address mode, with CRC disabled, 16 SCLK

cycles are expected. If 16 SCLK cycles are not detected, the

SCLK count error flag asserts in the error flags register. When

less than 16 SCLK cycles are received by the device, a write to

the register map never occurs. When the ADGS1412 receives

more than 16 SCLK cycles, a write to the memory map still

occurs at the 16^thSCLK rising edge, and the flag asserts in the

error flags register. With CRC enabled, the expected number of

SCLK cycles becomes 24. SCLK count error detection is enabled

by default and can be configured by the user through the error

configuration register.

The SPI interface can accept consecutive SPI commands

CS

mode. Burst mode is enabled through the burst enable register.

This mode uses the same 16-bit command to communicate

with the device. In addition, the response of the device at SDO

is still aligned with the corresponding SPI command. Figure 38

shows an example of SDI and SDO during burst mode.

without the need to de-assert the

line, which is called burst

The invalid read/write address and CRC error checking functions

operate similarly during burst mode as they do during address

mode. However, SCLK count error detection operates in a

slightly different manner. The total number of SCLK cycles

CS

within a given

frame are counted, and if the total is not a

multiple of 16, or a multiple of 24 when CRC is enabled, the

SCLK count error flag asserts.

Invalid Read/Write Address Error

An invalid read/write address error detects when a nonexistent

register address is a target for a read or write. In addition, this

error asserts when a write to a read only register is attempted.

The invalid read/write address error flag asserts in the error

flags register when an invalid read/write address error happens.

The invalid read/write address error is detected on the nineth

SCLK rising edge, which means a write to the register never

occurs when an invalid address is targeted. Invalid read/write

address error detection is enabled by default and can be

disabled by the user through the error configuration register.

CS

SDI

COMMAND0[15:0] COMMAND1[15:0] COMMAND2[15:0] COMMAND3[15:0]

SDO

RESPONSE0[15:0] RESPONSE1[15:0] RESPONSE2[15:0] RESPONSE3[15:0]

Figure 38. Burst Mode Frame

SOFTWARE RESET

When in address mode, the user can initiate a software reset.

To do so, write two consecutive SPI commands, namely 0xA3

followed by 0x05, targeting Register 0x0B. After a software

reset, all register values are set to default.

CLEARING THE ERROR FLAGS REGISTER

DAISY-CHAIN MODE

To clear the error flags register, write the special 16-bit SPI

frame, 0x6CA9, to the device. This SPI command does not

trigger the invalid R/W address error. When CRC is enabled,

the user must also send the correct CRC byte for a successful

error clear command. At the 16^thor 24^thSCLK rising edge, the

error flags register resets to zero.

The connection of several ADGS1412 devices in a daisy-chain

configuration is possible, and Figure 39 illustrates this setup. All

devices share the same and SCLK line, whereas the SDO of a

device forms a connection to the SDI of the next device, creating a

shift register. In daisy-chain mode, SDO is an eight-cycle

delayed version of SDI. When in daisy-chain mode, all

commands target the switch data register. Therefore, it is not

possible to make configuration changes while in daisy-chain mode.

CS

ADGS1412

DEVICE 1

ADGS1412

DEVICE 2

S1

S2

S3

S4

D1

S1

D1

D2

D3

D4

D2

S2

S3

S4

D3

V

L

D4

SPI

INTERFACE

SDO

SPI

INTERFACE

SDO

SDI

SCLK

CS

V

L

Figure 39. Two ADGS1412 Devices Connected in a Daisy-Chain Configuration

Rev. 0 | Page 19 of 25

ADGS1412

Data Sheet

The ADGS1412 can only enter daisy-chain mode when in

address mode by sending the 16-bit SPI command, 0x2500

(see Figure 40). When the ADGS1412 receives this command,

the SDO of the device sends out the same command because

the alignment bits at SDO are 0x25, which allows multiple

daisy-connected devices to enter daisy-chain mode in a single

SPI frame. A hardware reset is required to exit daisy-chain mode.

An SCLK rising edge reads in data on SDI while data is

propagated out SDO on an SCLK falling edge. The expected

CS

number of SCLK cycles must be a multiple of eight before

goes high. When this is not the case, the SPI interface sends the

last eight bits received to the switch data register.

POWER-ON RESET

The digital section of the ADGS1412 goes through an initialization

phase during V_Lpower up. This initialization also occurs after a

hardware or software reset. After V_Lpower-up or a reset, ensure

that a minimum of 120 μs from the time of power-up or reset

before any SPI command is issued. Ensure that V_Ldoes not

drop out during the 120 μs initialization phase because it may

result in incorrect operation of the ADGS1412.

For the timing diagram of a typical daisy-chain SPI frame, see

CS

Figure 41. When

goes high, Device 1 writes Command 0,

Bits[7:0] to its switch data register of, Device 2 writes Command 1,

Bits[7:0] to its switches, and so on. The SPI block uses the last

eight bits it received through SDI to update the switches. After

entering daisy-chain mode, the first eight bits sent out by SDO

CS

on each device in the chain are 0x00. When

goes high, the

internal shift register value does not reset back to zero.

1

0

2

0

3

1

4

0

5

0

6

1

7

0

8

1

9

0

10

0

11

0

12

0

13

0

14

0

15

0

16

0

CS

SCLK

SDI

SDO

0

1

0

1

0

1

0

Figure 40. SPI Command to Enter Daisy-Chain Mode

CS

SDI

COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0]

DEVICE 1

DEVICE 2

DEVICE 3

DEVICE 4

SDO

8’h00

COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0]

SDO2

SDO3

8’h00

COMMAND3[7:0] COMMAND2[7:0]

8’h00 COMMAND3[7:0]

NOTES

1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.

Figure 41. Example of a SPI Frame Where Four ADGS1412 Devices Connect in Daisy-Chain Mode

Rev. 0 | Page 20 of 25

Data Sheet

ADGS1412

APPLICATIONS INFORMATION

Figure 42 are two optional LDOs, ADP7118 and ADP7182

POWER SUPPLY RAILS

positive and negative LDOs respectively, that can be used to

reduce the output ripple of the ADPꢀ070 in ultralow noise

sensitive applications.

To guarantee correct operation of the ADGS1412, 0.1 μF

decoupling capacitors are required.

The ADGS1412 can operate with bipolar supplies between

4.ꢀ ꢁ and 1ꢂ.ꢀ ꢁ. The supplies on ꢁ_DDand ꢁ_SSdo not have to

be symmetrical; however, the ꢁ_DDto ꢁ_SSrange must not exceed

33 ꢁ. The ADGS1412 can also operate with single supplies

between ꢀ ꢁ and 20 ꢁ with ꢁ_SSconnected to GND.

The ADM71ꢂ0 can be used to generate ꢁ_Lvoltage that is

required to power digital circuitry within the ADGS1412.

ADM7160

+3.3V

LDO

+16.5V

–16.5V

ADP7118

LDO

+15V

–15V

+5V

INPUT

The voltage range that can be supplied to ꢁ_Lis from 2.7 ꢁ to ꢀ.ꢀ ꢁ.

ADP5070

ADP7182

LDO

The device is fully specified at 1ꢀ ꢁ, +ꢀ ꢁ, and +12 ꢁ analogue

supply voltage ranges.

.

Figure 42. Bipolar Power Solution

POWER SUPPLY RECOMMENDATIONS

Table 10. Recommended Power Management Devices

Product Description

Analog Devices, Inc., has a wide range of power management

products to meet the requirements of most high performance

signal chains.

ADP5070 1 A/0.6 A, dc-to-dc switching regulator with

independent positive and negative outputs

ADM7160 5.5 V, 200 mA, ultralow noise, linear regulator

ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator

ADP7182 −28 V, −200 mA, low noise, LDO linear regulator

An example of a bipolar power solution is shown in Figure 42.

The ADPꢀ070 (dual switching regulator) generates a positive and

negative supply rail for the ADGS1412, amplifier, and/or a

precision converter in a typical signal chain. Also shown in

Rev. 0 | Page 21 of 25

ADGS1412

Data Sheet

REGISTER SUMMARY

Table 11. Register Summary

Register (Hex) Name

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

Reserved SW4_EN SW3_EN

Reserved RW_ERR_EN

Reserved

Bit 2

Bit 1

Bit 0

Default R/W

0x01

0x02

0x03

0x05

0x0B

SW_DATA

SW2_EN

SCLK_ERR_EN

SW1_EN

CRC_ERR_EN

0x00

0x06

0x00

R/W

R

ERR_CONFIG

ERR_FLAGS

BURST_EN

RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG

Reserved

SOFT_RESETB

BURST_MODE_EN 0x00

0x00

R/W

SOFT_RESETB

Rev. 0 | Page 22 of 25

Data Sheet

ADGS1412

REGISTER DETAILS

SWITCH DATA REGISTER

Address: 0x01, Reset: 0x00, Name: SW_DATA

The switch data register controls the status of the four switches of the ADGS1412.

Table 12. Bit Descriptions for SW_DATA

Bits

[7:4]

3

Bit Name

Reserved

SW4_EN

Settings

Description

Default Access

These bits are reserved; set these bits to 0.

Enable bit for SW4.

SW4 open.

0x0

R

R/W

0

1

SW4 closed.

2

1

0

SW3_EN

SW2_EN

SW1_EN

Enable bit for SW3.

SW3 open.

SW3 closed.

0x0

R/W

0

1

Enable bit for SW2.

SW2 open.

SW2 closed.

0

1

Enable bit for SW1.

SW1 open.

SW1 closed.

0

1

ERROR CONFIGURATION REGISTER

Address: 0x02, Reset: 0x06, Name: ERR_CONFIG

The error configuration register allows the user to enable and disable the relevant error features as required.

Table 13. Bit Descriptions for ERR_CONFIG

Bits

[7:3]

2

Bit Name

Settings

Description

Default Access

Reserved

These bits are reserved; set these bits to 0.

0x0

0x1

R

RW_ERR_EN

Enable bit for detecting invalid read/write address.

R/W

0

1

Disabled.

Enabled.

1

0

SCLK_ERR_EN

CRC_ERR_EN

Enable bit for detecting the correct number of SCLK cycles in a SPI frame.

16 SCLK cycles are expected when CRC is disabled and burst mode is

disabled. 24 SCLK cycles are expected when CRC is enabled and burst

mode is disabled. A multiple of 16 SCLK cycles are expected when CRC is

disabled and burst mode is enabled. A multiple of 24 SCLK cycles are

expected when CRC is enabled and burst mode is enabled.

0x1

0x0

R/W

0

1

Disabled.

Enabled.

Enable bit for CRC error detection. SPI frames are 24 bits wide when

enabled.

0

1

Disabled.

Enabled.

Rev. 0 | Page 23 of 25

ADGS1412

Data Sheet

ERROR FLAGS REGISTER

Address: 0x03, Reset: 0x00, Name: ERR_FLAGS

The error flags register allows the user to determine if an error has occurred. To clear the error flags register, write the special 16-bit SPI

command 0x6CA9 to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user must

include the correct CRC byte during the SPI write for the clear error flags register command to succeed.

Table 14. Bit Descriptions for ERR_FLAGS

Bits

[7:3]

2

Bit Name

Settings

Description

Default Access

Reserved

These bits are reserved and are set to 0.

0x0

R

RW_ERR_FLAG

Error flag for invalid read/write address. The error flag asserts during a SPI

read if the target address does not exist. The error flag also asserts when

the target address of a SPI write is does not exist or is read only.

0

1

No error.

Error.

1

0

SCLK_ERR_FLAG

CRC_ERR_FLAG

Error flag for the detection of the correct number of SCLK cycles in a SPI

frame.

No error.

Error.

0x0

R

0

1

Error flag that determines if a CRC error has occurred during a register

write.

0

1

No error.

Error.

BURST ENABLE REGISTER

Address: 0x05, Reset: 0x00, Name: BURST_EN

The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI

CS

commands without deasserting

.

Table 15. Bit Descriptions for BURST_EN

Bits

[7:1]

0

Bit Name

Settings

Description

Default Access

Reserved

These bits are reserved; set these bits to 0.

0x0

R

BURST_MODE_EN

Burst mode enable bit.

Disabled.

Enabled.

R/W

0

1

SOFTWARE RESET REGISTER

Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB

Use the software reset register to perform a software reset. Consecutively, write 0xA3 followed by 0x05 to this register, and the registers of

the device reset to their default state.

Table 16. Bit Descriptions for SOFT_RESETB

Bits

Bit Name

Settings

Description

Default Access

[7:0]

SOFT_RESETB

To perform a software reset, consecutively write 0xA3 followed by 0x05 to 0x0

this register.

R

Rev. 0 | Page 24 of 25

Data Sheet

ADGS1412

OUTLINE DIMENSIONS

4.10

4.00 SQ

3.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

24

19

18

1

0.50

BSC

2.70

2.60 SQ

2.50

EXPOSED

PAD

13

12

6

7

0.50

0.40

0.30

0.20 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

1.00

0.95

0.90

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.

Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.95 mm Package Height

(CP-24-17)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADGS1412BCPZ

ADGS1412BCPZ-RL7

Temperature Range

−40°C to +125°C

Package Description

Package Option

CP-24-17

24-Lead Lead Frame Chip Scale Package [LFCSP]

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D14960-0-10/16(0)

Rev. 0 | Page 25 of 25


型号：	ADGS1412BCPZ-RL7
厂家：	ADI
描述：	Serially Controlled, 1.5 Î©, On-Resistance, High Voltage, iCMOS, Quad SPST Switch
文件：	总26页 (文件大小：722K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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