ADGS5412BCPZ-RL7_技术文档

SPI Interface, 4× SPST Switches,

9.8 Ω R_ON, ± ±2 ꢀV/+3 ꢀ, ꢁMu ꢂCnfiꢃMraꢄbe

ADGS541±

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

SPI interface with error detection

Includes CRC, invalid read/write address, and SCLK count

error detection

Supports burst mode and daisy-chain mode

Industry standard SPI Mode 0 and Mode 3 interface

compatible

ADGS5412

S1

S2

D1

D2

S3

S4

D3

D4

Guaranteed break-before-make switching allowing external

wiring of switches to deliver multiplexer configurations

V_SSto V_DDanalog signal range

Fully specified at 1ꢀ V, 20 V, +12 V, and +36 V

9 V to 22 V dual-supply operation

9 V to 40 V single-supply operation

SPI

INTERFACE

SDO

Latch-up proof analog switch pins

8 kV HBM ESD rating

SCLK

SDI

CS

RESET/V

L

Low on resistance (<10 Ω)

1.8 V logic compatibility with 2.7 V ≤ V_L≤ 3.3 V

Figure 1.

APPLICATIONS

Relay replacement

Automatic test equipment

Data acquisition

Instrumentation

Avionics

Audio and video switching

Communication systems

GENERAL DESCRIPTION

The ADGS5412 contains four independent single-pole/single-

throw (SPST) switches. A serial peripheral interface (SPI) controls

the switches. The SPI interface has robust error detection features,

including cyclic redundancy check (CRC) error detection, invalid

read/write address detection, and serial clock (SCLK) count

error detection.

It is possible to daisy-chain multiple ADGS5412 devices together,

which enables the configuration of multiple devices with a

minimal amount of digital lines. The ADGS5412 can also

operate in burst mode to decrease the time between SPI

commands.

applications with external wiring.

PRODUCT HIGHLIGHTS

1. SPI interface removes the need for parallel conversion and

logic traces and reduces general-purpose input/output

(GPIO) channel count.

2. Daisy-chain mode removes additional logic traces when

multiple devices are used.

3. CRC, invalid read/write address, and SCLK count error

detection ensure a robust digital interface.

4. CRC error detection capabilities allow for the use of the

ADGS5412 in safety critical systems.

Each switch conducts equally well in both directions when on,

and each switch has an input signal range that extends to the

supplies. In the off condition, signal levels up to the supplies are

blocked.

5. Guaranteed break-before-make switching allows the use of

the ADGS5412 in multiplexer configurations with external

wiring.

Trench isolation analog switch section guards against latch-up. A

dielectric trench separates the positive (P) and negative (N) channel

transistors thereby preventing latch-up even under severe

overvoltage conditions.

The on-resistance profile is very flat over the full analog input

range, which ensures good linearity and low distortion when

switching audio signals. The ADGS5412 exhibits break-before-

make switching action, allowing use of the device in multiplexer

Rev. A

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADGS5412

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Error Detection Features........................................................... 22

Clearing the Error Flags Register............................................. 23

Burst Mode.................................................................................. 23

Software Reset............................................................................. 23

Daisy-Chain Mode..................................................................... 23

Power-On Reset.......................................................................... 24

Break-Before-Make Switching.................................................. 25

Trench Isolation.......................................................................... 25

Digital Input Buffers .................................................................. 25

Applications Information .............................................................. 26

Power Supply Rails ..................................................................... 26

Power Supply Recommendations............................................. 26

Register Summary .......................................................................... 27

Register Details ............................................................................... 28

Switch Data Register .................................................................. 28

Error Configuration Register.................................................... 28

Error Flags Register.................................................................... 29

Burst Enable Register................................................................. 29

Software Reset Register ............................................................. 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 30

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

15 V Dual Supply ....................................................................... 3

20 V Dual Supply ....................................................................... 5

12 V Single Supply........................................................................ 7

36 V Single Supply........................................................................ 9

Continuous Current per Channel, S_Xor D_X............................ 11

Timing Characteristics .............................................................. 11

Absolute Maximum Ratings.......................................................... 13

ESD Caution................................................................................ 13

Pin Configurations and Function Descriptions ......................... 14

Typical Performance Characteristics ........................................... 15

Test Circuits..................................................................................... 19

Terminology .................................................................................... 21

Theory of Operation ...................................................................... 22

Address Mode ............................................................................. 22

REVISION HISTORY

7/2018—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to Source Off Leakage, I_S(Off) Parameter and Drain

Off Leakage, I_D(Off) Parameter, Table 1....................................... 3

Changes to Source Off Leakage, I_S(Off) Parameter and Drain

Off Leakage, I_D(Off) Parameter, Table 2....................................... 5

Changes to Source Off Leakage, I_S(Off) Parameter and Drain

Off Leakage, I_D(Off) Parameter, Table 4....................................... 9

Deleted Figure 43 and Figure 44; Renumbered Sequentially..... 24

Added Figure 43 and Figure 44; Renumbered Sequentially ..... 24

5/2017—Revision 0: Initial Version

Rev. A | Page 2 of 30

Data Sheet

ADGS5412

SPECIFICATIONS

15 V DUAL SUPPLY

Positive supply (V_DD) = 15 V 10%, negative supply (V_SS) = −15 V 10%, digital supply (V_L) = 2.7 V to 5.5 V, GND = 0 V, unless

otherwise noted.

Table 1.

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

On Resistance, R_ON

V_DDto V_SS

V

9.8

Ω typ

V_S= 10 V, I_S= −10 mA;

see Figure 29

11

0.35

14

16

Ω max

Ω typ

V_DD= +13.5 V, V_SS= −13.5 V

V_S= 10 V, I_S= −10 mA

On-Resistance Match Between Channels,

∆R_ON

0.7

1.2

1.6

0.9

2

1.1

2.2

Ω max

Ω typ

Ω max

On-Resistance Flatness, R_{FLAT (ON)}

V_S= 10 V, I_S= −10 mA

LEAKAGE CURRENTS

V_DD= +16.5 V, V_SS= −16.5 V

Source Off Leakage, I_S(Off)

0.05

nA typ

V_S= 10 V, V_D= μ 10 V;

see Figure 32

0.25

0.05

0.75

6

nA max

nA typ

Drain Off Leakage, I_D(Off)

V_S= 10 V, V_D= μ 10 V;

see Figure 32

0.25

0.1

0.4

0.75

2

6

nA max

nA typ

nA max

Channel On Leakage, I_D(On), I_S(On)

V_S= V_D= 10 V; see Figure 28

12

DIGITAL OUTPUT

Output Voltage

Low, V_OL

0.4

0.2

V max

µA typ

µA max

pF typ

I_SINK= 5 mA

I_SINK= 1 mA

V_OUT= V_GNDor V_L

High Impedance Leakage Current

0.001

4

0.1

High Impedance Output Capacitance

DIGITAL INPUTS

Input Voltage

High, V_INH

2

V min

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

V_IN= V_GNDor V_L

1.35

0.8

Low, V_INL

V max

µA typ

µA max

pF typ

Input Current, I_INLor I_INH

0.002

4

0.1

Digital Input Capacitance, C_IN

DYNAMIC CHARACTERISTICS¹

t_ON

460

540

185

225

245

ns typ

ns max

ns typ

ns max

ns typ

ns min

R_L= 300 Ω, C_L= 35 pF

V_S= 10 V; see Figure 36

R_L= 300 Ω, C_L= 35 pF

V_S= 10 V; see Figure 36

R_L= 300 Ω, C_L= 35 pF

V_S1= V_S2= 10 V, see Figure 35

560

240

580

270

195

t_OFF

Break-Before-Make Time Delay, t_D

Rev. A | Page 3 of 30

ADGS5412

Data Sheet

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

Charge Injection, Q_INJ

245

−78

−70

0.01

167

−0.7

pC typ

V_S= 0 V, R_S= 0 Ω, C_L= 1 nF;

see Figure 37

R_L= 50 Ω, C_L= 5 pF, f =

100 kHz; see Figure 31

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

see Figure 30

R_L= 1 kΩ, 15 V p-p, f = 20 Hz

to 20 kHz; see Figure 33

R_L= 50 Ω, C_L= 5 pF; see

Figure 34

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

see Figure 34

Off Isolation

dB typ

% typ

Channel to Channel Crosstalk

Total Harmonic Distortion + Noise,

THD + N

−3 dB Bandwidth

MHz typ

dB typ

Insertion Loss

Off Switch Source Capacitance, C_S(Off)

Off Switch Drain Capacitance, C_D(Off)

On Switch Capacitance, C_D(On), C_S(On)

POWER REQUIREMENTS

18

57

pF typ

V_S= 0 V, f = 1 MHz

V_DD= +16.5 V, V_SS= −16.5 V

Digital inputs = 0 V or V_L

Positive Supply Current, I_DD

45

55

45

µA typ

µA max

µA typ

70

All switches closed,

V_L= 5.5 V

110

µA typ

All switches closed,

V_L= 2.7 V

Digital Supply Current, I_L

Inactive

6.3

14

µA typ

µA max

µA typ

Digital inputs = 0 V or V_L

8.0

Inactive, SCLK = 1 MHz

CS = V_Land SDI = 0 V or V_L,

V_L= 5 V

7

µA typ

mA typ

CS = V_Land SDI = 0 V or V_L,

V_L= 3 V

CS = V_Land SDI = 0 V or V_L,

V_L= 5 V

CS = V_Land SDI = 0 V or V_L,

V_L= 3 V

CS and SCLK = 0 V or V_L,

V_L= 5 V

CS and SCLK = 0 V or V_L,

V_L= 3 V

CS and SCLK = 0 V or V_L,

V_L= 5 V

CS and SCLK = 0 V or V_L,

V_L= 3 V

Digital inputs toggle

between 0 V and V_L,

V_L= 5.5 V

SCLK = 50 MHz

390

210

15

Inactive, SDI = 1 MHz

SDI = 25 MHz

7.5

230

120

1.8

Active at 50 MHz

2.1

mA max

mA typ

0.7

Digital inputs toggle

between 0 V and V_L,

V_L= 2.7 V

1.0

mA max

µA typ

µA max

Negative Supply Current, I_SS

0.001

Digital inputs = 0 V or V_L

V_DD/V_SS

9/ 22

V min/V max GND = 0 V

¹Guaranteed by design; not subject to production test.

Rev. A | Page 4 of 30

Data Sheet

ADGS5412

20 V DUAL SUPPLY

V_DD= 20 V 10%, V_SS= −20 V 10%, V_L= 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.

Table 2.

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

On Resistance, R_ON

V_DDto V_SS

V

9

Ω typ

V_S= 15 V, I_S= −10 mA; see

Figure 29

10

0.35

13

15

Ω max

Ω typ

V_DD= +18 V, V_SS= −18 V

V_S= 15 V, I_S= −10 mA

On-Resistance Match Between

Channels, ∆R_ON

0.7

1.6

1.9

0.9

2.3

1.1

2.7

Ω max

Ω typ

Ω max

On-Resistance Flatness, R_{FLAT (ON)}

V_S= 15 V, I_S= −10 mA

V_DD= +22 V, V_SS= −22 V

LEAKAGE CURRENTS

Source Off Leakage, I_S(Off)

0.05

nA typ

V_S= 15 V, V_D= μ 15 V; see

Figure 32

0.25

0.05

0.75

6

nA max

nA typ

Drain Off Leakage, I_D(Off)

V_S= 15 V, V_D= μ 15 V; see

Figure 32

0.25

0.1

0.4

0.75

2

6

nA max

nA typ

nA max

Channel On Leakage, I_D(On), I_S(On)

V_S= V_D= 15 V; see Figure 28

12

DIGITAL OUTPUT

Output Voltage

Low, V_OL

0.4

0.2

V max

µA typ

µA max

pF typ

I_SINK= 5 mA

I_SINK= 1 mA

V_OUT= V_GNDor V_L

High Impedance Leakage Current

0.001

4

0.1

High Impedance Output

Capacitance

DIGITAL INPUTS

Input Voltage

High, V_INH

2

V min

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

V_IN= V_GNDor V_L

1.35

0.8

Low, V_INL

V max

µA typ

µA max

pF typ

Input Current, I_INLor I_INH

Digital Input Capacitance, C_IN

0.002

4

0.1

Rev. A | Page 5 of 30

ADGS5412

Data Sheet

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

DYNAMIC CHARACTERISTICS¹

t_ON

450

530

185

230

235

ns typ

R_L= 300 Ω, C_L= 35 pF

V_S= 10 V; see Figure 36

R_L= 300 Ω, C_L= 35 pF

V_S= 10 V; see Figure 36

R_L= 300 Ω, C_L= 35 pF

V_S1= V_S2= 10 V, see Figure 35

V_S= 0 V, R_S= 0 Ω, C_L= 1 nF; see

Figure 37

R_L= 50 Ω, C_L= 5 pF, f = 100 kHz; see

Figure 31

540

245

555

260

185

ns max

ns typ

ns max

ns typ

ns min

pC typ

t_OFF

Break-Before-Make Time Delay, t_D

Charge Injection, Q_INJ

Off Isolation

310

−78

−70

0.008

dB typ

% typ

Channel-to-Channel Crosstalk

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz; see

Figure 30

R_L= 1 kΩ, 20 V p-p, f = 20 Hz to

20 kHz; see Figure 33

Total Harmonic Distortion + Noise,

THD + N

−3 dB Bandwidth

Insertion Loss

160

−0.6

MHz typ

dB typ

R_L= 50 Ω, C_L= 5 pF; see Figure 34

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz; see

Figure 34

Off Switch Source Capacitance,

C_S(Off)

Off Switch Drain Capacitance,

C_D(Off)

On Switch Capacitance, C_D(On),

C_S(On)

17

56

pF typ

V_S= 0 V, f = 1 MHz

POWER REQUIREMENTS

Positive Supply Current, I_DD

V_DD= +22 V, V_SS= −22 V

Digital inputs = 0 V or V_L

50

70

50

120

µA typ

µA max

µA typ

110

8.0

All switches closed, V_L= 5.5 V

All switches closed, V_L= 2.7 V

I_L

Inactive

6.3

14

µA typ

µA max

µA typ

Digital inputs = 0 V or V_L

Inactive, SCLK = 1 MHz

CS = V_Land SDI = 0 V or V_L,

V_L= 5 V

7

µA typ

CS = V_Land SDI = 0 V or V_L,

V_L= 3 V

CS = V_Land SDI = 0 V or V_L,

V_L= 5 V

CS = V_Land SDI = 0 V or V_L,

V_L= 3 V

SCLK = 50 MHz

390

210

Inactive, SDI = 1 MHz

SDI = 25 MHz

15

µA typ

mA typ

CS and SCLK = 0 V or V_L, V_L= 5 V

7.5

230

120

1.8

CS and SCLK = 0 V or V_L, V_L= 3 V

CS and SCLK = 0 V or V_L, V_L= 5 V

CS and SCLK = 0 V or V_L, V_L= 3 V

Active at 50 MHz

Digital inputs toggle between

0 V and V_L, V_L= 5.5 V

2.1

mA max

mA typ

0.7

Digital inputs toggle between

0 V and V_L, V_L= 2.7 V

1.0

mA max

µA typ

µA max

Negative Supply Current, I_SS

V_DD/V_SS

0.001

Digital inputs = 0 V or V_L

9/ 22

V min/V max GND = 0 V

¹Guaranteed by design; not subject to production test.

Rev. A | Page 6 of 30

Data Sheet

ADGS5412

12 V SINGLE SUPPLY

V_DD= 12 V 10%, V_SS= 0 V, V_L= 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.

Table 3.

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

On-Resistance, R_ON

0 V to V_DD

31

V

19

Ω typ

V_S= 0 V to 10 V, I_S= −10 mA;

see Figure 29

V_DD= 10.8 V, V_SS= 0 V

22

0.4

27

Ω max

Ω typ

On-Resistance Match Between Channels,

∆R_ON

V_S= 0 V to 10 V, I_S= −10 mA

0.8

4.4

5.5

1

1.2

7.5

Ω max

Ω typ

Ω max

On-Resistance Flatness, R_{FLAT (ON)}

V_S= 0 V to 10 V, I_S= −10 mA

V_DD= 13.2 V, V_SS= 0 V

6.5

LEAKAGE CURRENTS

Source Off Leakage, I_S(Off)

0.05

nA typ

V_S= 1 V/10 V, V_D= 10 V/1 V;

see Figure 32

0.25

0.05

0.75

6

nA max

nA typ

Drain Off Leakage, I_D(Off)

V_S= 1 V/10 V, V_D= 10 V/1 V;

see Figure 32

0.25

0.1

0.75

2

6

nA max

nA typ

Channel On Leakage, I_D(On), I_S(On)

V_S= V_D= 1 V/10 V; see

Figure 28

0.4

12

nA max

DIGITAL OUTPUT

Output Voltage

Low, V_OL

0.4

0.2

V max

µA typ

µA max

pF typ

I_SINK= 5 mA

I_SINK= 1 mA

V_OUT= V_GNDor V_L

High Impedance Leakage Current

0.002

4

0.1

High Impedance Output Capacitance

DIGITAL INPUTS

Input Voltage

High, V_INH

2

V min

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

V_IN= V_GNDor V_L

1.35

0.8

Low, V_INL

V max

µA typ

µA max

pF typ

Input Current, I_INLor I_INH

0.001

4

0.1

Digital Input Capacitance, C_IN

DYNAMIC CHARACTERISTICS¹

t_ON

545

665

200

250

320

ns typ

ns max

ns typ

ns max

ns typ

ns min

pC typ

R_L= 300 Ω, C_L= 35 pF

V_S= 8 V; see Figure 36

R_L= 300 Ω, C_L= 35 pF

V_S= 8 V; see Figure 36

R_L= 300 Ω, C_L= 35 pF

V_S1= V_S2= 8 V, see Figure 35

V_S= 6 V, R_S= 0 Ω, C_L= 1 nF;

see Figure 37

R_L= 50 Ω, C_L= 5 pF,

f = 100 kHz; see Figure 31

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

see Figure 30

R_L= 1 kΩ, 6 V p-p, f = 20 Hz

to 20 kHz; see Figure 33

720

275

775

305

235

t_OFF

Break-Before-Make Time Delay, t_D

Charge Injection, Q_INJ

Off Isolation

105

−78

−70

0.08

dB typ

% typ

Channel-to-Channel Crosstalk

Total Harmonic Distortion + Noise,

THD + N

Rev. A | Page 7 of 30

ADGS5412

Data Sheet

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

−3 dB Bandwidth

180

MHz typ

R_L= 50 Ω, C_L= 5 pF; see

Figure 34

Insertion Loss

−1.3

dB typ

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

see Figure 34

Off Switch Source Capacitance, C_S(Off)

Off Switch Drain Capacitance, C_D(Off)

On Switch Capacitance, C_D(On), C_S(On)

POWER REQUIREMENTS

22

56

pF typ

V_S= 6 V, f = 1 MHz

V_DD= 13.2 V

Positive Supply Current, I_DD

40

µA typ

µA max

µA typ

Digital inputs = 0 V or V_L

65

40

105

All switches closed, V_L= 5.5 V

All switches closed, V_L= 2.7 V

I_L

Inactive

6.3

14

µA typ

µA max

µA typ

Digital inputs = 0 V or V_L

8.0

Inactive, SCLK = 1 MHz

CS = V_Land SDI = 0 V or V_L,

V_L= 5 V

7

µA typ

mA typ

CS = V_Land SDI = 0 V or V_L,

V_L= 3 V

CS = V_Land SDI = 0 V or V_L,

V_L= 5 V

CS = V_Land SDI = 0 V or V_L,

V_L= 3 V

CS and SCLK = 0 V or V_L,

V_L= 5 V

CS and SCLK = 0 V or V_L,

V_L= 3 V

CS and SCLK = 0 V or V_L,

V_L= 5 V

CS and SCLK = 0 V or V_L,

V_L= 3 V

Digital inputs toggle

between 0 V and V_L,

V_L= 5.5 V

SCLK = 50 MHz

390

210

15

Inactive, SDI = 1 MHz

SDI = 25 MHz

7.5

230

120

1.8

Active at 50 MHz

2.1

mA max

mA typ

0.7

Digital inputs toggle

between 0 V and V_L,

V_L= 2.7 V

1.0

mA max

V_DD

9/40

V min/V max GND = 0 V, V_SS= 0 V

¹Guaranteed by design; not subject to production test.

Rev. A | Page 8 of 30

Data Sheet

ADGS5412

36 V SINGLE SUPPLY

V_DD= 36 V 10%, V_SS= 0 V, V_L= 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.

Table 4.

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

On Resistance, R_ON

0 V to V_DD

17

V

10.6

Ω typ

V_S= 0 V to 30 V, I_S= −10 mA; see

Figure 29

V_DD= 32.4 V, V_SS= 0 V

12

0.35

15

Ω max

Ω typ

On-Resistance Match Between

Channels, ∆R_ON

V_S= 0 V to 30 V, I_S= −10 mA

0.7

2.9

3.4

0.9

4

1.1

4.7

Ω max

Ω typ

Ω max

On-Resistance Flatness, R_FLAT(ON)

V_S= 0 V to 30 V, I_S= −10 mA

V_DD= 39.6 V, V_SS= 0 V

LEAKAGE CURRENTS

Source Off Leakage, I_S(Off)

0.05

nA typ

V_S= 1 V/30 V, V_D= 30 V/1 V; see

Figure 32

0.25

0.05

0.75

6

nA max

nA typ

Drain Off Leakage, I_D(Off)

V_S= 1 V/30 V, V_D= 30 V/1 V; see

Figure 32

0.25

0.1

0.4

0.75

2

6

nA max

nA typ

nA max

Channel On Leakage, I_D(On), I_S(On)

V_S= V_D= 1 V/30 V; see Figure 28

12

DIGITAL OUTPUT

Output Voltage

Low, V_OL

0.4

0.2

V max

µA typ

µA max

pF typ

I_SINK= 5 mA

I_SINK= 1 mA

V_OUT= V_GNDor V_L

High Impedance Leakage Current

0.001

4

0.1

High Impedance Output

Capacitance

DIGITAL INPUTS

Input Voltage

High, V_INH

2

V min

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

3.3 V < V_L≤ 5.5 V

2.7 V ≤ V_L≤ 3.3 V

V_IN= V_GNDor V_L

1.35

0.8

Low, V_INL

V max

µA typ

µA max

pF typ

Input Current, I_INLor I_INH

Digital Input Capacitance, C_IN

0.002

4

0.1

Rev. A | Page 9 of 30

ADGS5412

Data Sheet

Parameter

+25°C −40°C to +85°C −40°C to +125°C Unit

Test Conditions/Comments

DYNAMIC CHARACTERISTICS¹

t_ON

470

555

195

245

ns typ

R_L= 300 Ω, C_L= 35 pF

V_S= 18 V; see Figure 36

R_L= 300 Ω, C_L= 35 pF

V_S= 18 V; see Figure 36

R_L= 300 Ω, C_L= 35 pF

V_S1= V_S2= 18 V, see Figure 35

V_S= 18 V, R_S= 0 Ω, C_L= 1 nF; see

Figure 37

R_L= 50 Ω, C_L= 5 pF, f = 100 kHz; see

Figure 31

565

250

580

260

185

ns max

ns typ

ns max

ns typ

ns min

pC typ

t_OFF

Break-Before-Make Time Delay, t_D

Charge Injection, Q_INJ

Off Isolation

285

−78

−70

0.03

dB typ

% typ

Channel-to-Channel Crosstalk

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz; see

Figure 30

R_L= 1 kΩ, 18 V p-p, f = 20 Hz to

20 kHz; see Figure 33

Total Harmonic Distortion + Noise,

THD + N

−3 dB Bandwidth

Insertion Loss

174

−0.7

MHz typ

dB typ

R_L= 50 Ω, C_L= 5 pF; see Figure 34

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz; see

Figure 34

Off Switch Source Capacitance,

C_S(Off)

Off Switch Drain Capacitance,

C_D(Off)

On Switch Capacitance, C_D(On),

C_S(On)

17

55

pF typ

V_S= 18 V, f = 1 MHz

POWER REQUIREMENTS

V_DD= 39.6 V

Positive Supply Current, I_DD

80

100

80

µA typ

µA max

µA typ

Digital inputs = 0 V or V_L

130

8.0

All switches closed, V_L= 5.5 V

All switches closed, V_L= 2.7 V

135

I_L

Inactive

6.3

14

µA typ

µA max

µA typ

Digital inputs = 0 V or V_L

Inactive, SCLK = 1 MHz

CS = V_Land SDI = 0 V or V_L,

V_L= 5 V

7

µA typ

CS = V_Land SDI = 0 V or V_L,

V_L= 3 V

CS = V_Land SDI = 0 V or V_L,

V_L= 5 V

CS = V_Land SDI = 0 V or V_L,

V_L= 3 V

SCLK = 50 MHz

390

210

Inactive, SDI = 1 MHz

SDI = 25 MHz

15

µA typ

mA typ

CS and SCLK = 0 V or V_L, V_L= 5 V

7.5

230

120

1.8

CS and SCLK = 0 V or V_L, V_L= 3 V

CS and SCLK = 0 V or V_L, V_L= 5 V

CS and SCLK = 0 V or V_L, V_L= 3 V

Active at 50 MHz

Digital inputs toggle between

0 V and V_L, V_L= 5.5 V

2.1

mA max

mA typ

0.7

Digital inputs toggle between

0 V and V_L, V_L= 2.7 V

1.0

mA max

V_DD

9/40

V min/V max GND = 0 V, V_SS= 0 V

¹Guaranteed by design; not subject to production test.

Rev. A | Page 10 of 30

Data Sheet

ADGS5412

CONTINUOUS CURRENT PER CHANNEL, S_XOR D_X

Table 5. Four Channels On

Parameter

25°C

85°C

125°C

Unit

CONTINUOUS CURRENT, S_XOR D_X

V_DD= +15 V, V_SS= −15 V

LFCSP (θ_JA= 50°C/W)

V_DD= +20 V, V_SS= −20 V

LFCSP (θ_JA= 50°C/W)

V_DD= 12 V, V_SS= 0 V

LFCSP (θ_JA= 50°C/W)

V_DD= 36 V, V_SS= 0 V

LFCSP (θ_JA= 50°C/W)

126

133

97

94

98

71

97

59

63

44

62

mA max

131

Table 6. One Channel On

Parameter

25°C

85°C

125°C

Unit

CONTINUOUS CURRENT, S_XOR D_X

V_DD= +15 V, V_SS= −15 V

LFCSP (θ_JA= 50°C/W)

V_DD= +20 V, V_SS= −20 V

LFCSP (θ_JA= 50°C/W)

V_DD= 12 V, V_SS= 0 V

LFCSP (θ_JA= 50°C/W)

V_DD= 36 V, V_SS= 0 V

LFCSP (θ_JA= 50°C/W)

230

241

180

239

154

160

126

158

102

104

88

mA max

104

TIMING CHARACTERISTICS

V_L= 2.7 V to 5.5 V; GND = 0 V; all specifications T_MINto T_MAX, unless otherwise noted. Guaranteed by design and characterization, not

production tested.

Table 7.

Parameter

Limit at T_MIN, T_MAX

Unit

Test Conditions/Comments

SCLK period

SCLK high pulse width

SCLK low pulse width

CS falling edge to SCLK rising edge

Data setup time

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

20

8

10

6

8

10

20

8

ns min

ns max

ns min

Data hold time

SCLK rising edge to CS rising edge

CS falling edge to SDO data available

SCLK falling edge to SDO data available

CS rising edge to SDO returns to high impedance

CS high time between SPI commands

CS falling edge to SCLK becomes stable

CS rising edge to SCLK becomes stable

1

t₉

t₁₀

t₁₁

t₁₂

t₁₃

8

¹Measured with the 1 kΩ pull-up resistor to V_Land 20 pF load. The parameter t₉determines the maximum SCLK frequency when SDO is used.

Rev. A | Page 11 of 30

ADGS5412

Data Sheet

t₁

SCLK

CS

t₂

t₇

t₄

t₃

t₆

t₅

SDI

R/W

A6

A5

1

D2

D1

D0

t₁₀

t₉

SDO

0

t₈

Figure 2. Addressable Mode Timing Diagram

t₁

SCLK

CS

t₂

t₃

t₄

t₇

t₆

t₅

SDI

D7

D6

D0

D7

D6

D1

D0

INPUT BYTE FOR DEVICE N

t₉

INPUT BYTE FOR DEVICE N + 1

t₁₀

SDO

0

D7

D6

D1

D0

ZERO BYTE

INPUT BYTE FOR DEVICE N

t₈

Figure 3. Daisy Chain Timing Diagram

t₁₁

CS

SCLK

t₁₃

t₁₂

CS

Figure 4. SCLK/ Timing Relationship

Rev. A | Page 12 of 30

Data Sheet

ADGS5412

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 8.

Parameter

Rating

V_DDto V_SS

48 V

V_DDto GND

V_SSto GND

V_Lto GND

−0.3 V to +48 V

+0.3 V to −48 V

−0.3 V to +6 V

Analog Inputs¹

V_SS− 0.3 V to V_DD+ 0.3 V or

Only one absolute maximum rating can be applied at any one time.

30 mA, whichever occurs first

−0.3 V to +6 V

ESD CAUTION

Digital Inputs¹

Peak Current, S_Xor D_X

261 mA (pulsed at 1 ms, 10%

duty cycle maximum)

Data + 15%

2

Continuous Current, S_Xor D_X

Temperature Ranges

Operating

Storage

Junction Temperature

Thermal Impedance, θ_JA

−40°C to +125°C

−65°C to +150°C

150°C

50°C/W

Reflow Soldering Peak

Temperature, Pb Free

260 (+0/−5)°C

Human Body Model (HBM) ESD 8 kV

Rating

¹Overvoltages at the S_Xpins and D_Xpins are clamped by internal diodes. Limit

the current to the maximum ratings given.

²See Table 5.

Rev. A | Page 13 of 30

ADGS5412

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

18

17

16

15

14

13

1

2

3

4

5

6

D2

D1

S1

S2

ADGS5412

NIC

V

SS

TOP VIEW

V

GND

DD

(Not to Scale)

S4

D4

S3

D3

NOTES

1. THE EXPOSED PAD IS CONNECTED

INTERNALLY. FOR INCREASED RELIABILITY

OF THE SOLDER JOINTS AND MAXIMUM

THERMAL CAPABILITY, IT IS RECOMMENDED

THAT THE EXPOSED PAD BE SOLDEREDTO

THE SUBSTRATE, V

.

SS

2. NIC = NOT INTERNALLY CONNECTED.

Figure 5. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic Description

1

2

3

4, 11

5

6

7, 8, 10,

12, 16, 19,

24

D1

S1

V_SS

GND

S4

Drain Terminal 1. This pin can be an input or an output.

Source Terminal 1. This pin can be an input or an output.

Most Negative Power Supply Potential. In single-supply applications, tie this pin to GND.

Ground (0 V) Reference.

Source Terminal 4. This pin can be an input or an output.

Drain Terminal 4. This pin can be an input or an output.

Not Internally Connected.

D4

NIC

9

RESET/V_L

RESET/Logic Power Supply Input (V_L). Under normal operation, drive the RESET/V_Lpin with a 2.7 V to 5.5 V supply.

Pull the pin low to complete a hardware reset. All switches are opened, and the appropriate registers are set to

their default values.

13

14

15

17

18

20

D3

S3

V_DD

S2

D2

SDO

Drain Terminal 3. This pin can be an input or an output.

Source Terminal 3. This pin can be an input or an output.

Most Positive Power Supply Potential.

Source Terminal 2. This pin can be an input or an output.

Drain Terminal 2. This pin can be an input or an output.

Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading

back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of SCLK.

Pull this open-drain output to V_Lwith an external resistor.

21

CS

Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it

powers on the SCLK buffers and enables the input shift register. Data is transferred in on the falling edges of the

following clocks. Taking CS high updates the switch condition.

22

23

SCLK

SDI

Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.

Serial Data Input. Data is captured on the positive edge of the serial clock input.

EPAD

Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum

thermal capability, it is recommended that the pad be soldered to the substrate, V_SS.

Rev. A | Page 14 of 30

Data Sheet

ADGS5412

TYPICAL PERFORMANCE CHARACTERISTICS

16

12

10

8

T

= 25°C

V

= +10V

= –10V

T = 25°C

A

DD

SS

V

= +9V

= –9V

DD

SS

14

12

10

8

V

= 32.4V

= 0V

DD

SS

V

= 36V

= 0V

DD

SS

V

= +11V

= –11V

DD

SS

6

V

= 39.6V

= 0V

DD

SS

V

1=0+13.2V

= –13.2V

DD

SS

V

= +16.5V

= –16.5V

DD

SS

V

= +15V

= –15V

6

DD

SS

4

2

0

–20

–15

–10

–5

0

V , V (V)

5

10

15

20

0

5

10

15

20

25

30

35

40

45

V , V (V)

S

D

S

D

Figure 6. On Resistance (R_ON) as a Function of V_S, V_D(Dual Supply)

Figure 9. On Resistance (R_ON) as a Function of V_S, V_D(Single Supply)

12

18

16

14

V

= +18V

= –18V

DD

SS

10

8

T

= +125°C

A

12

10

8

V

= +22V

= –22V

T

= +85°C

DD

SS

A

V

= +20V

= –20V

DD

SS

V

6

T

= +25°C

= –40°C

T

A

4

6

4

2

V

= +15V

= –15V

DD

SS

T

= 25°C

A

0

–15

–25 –20 –15 –10

–5

0

5

10

15

20

25

–10

–5

0

5

10

15

V , V (V)

S

D

S

D

Figure 7. On Resistance (R_ON) as a Function of V_S, V_D(Dual Supply)

Figure 10. On Resistance (R_ON) as a Function of V_S, V_Dfor Various Temperatures,

15 V Dual Supply

25

16

14

12

T

= 25°C

A

V

= +10V

= 0V

DD

SS

V

= 10.8V

= 0V

DD

SS

V

= +9V

= 0V

DD

SS

20

15

10

5

T

= +125°C

A

10

8

T

= +85°C

= +25°C

= –40°C

A

T

V

= 11V

= 0V

DD

SS

V

= 12V

= 0V

DD

SS

6

T

A

V

= 13.2V

= 0V

DD

SS

4

2

V

= +20V

= –20V

DD

SS

0

–20

0

2

4

6

8

10

12

14

–15

–10

–5

0

5

10

15

20

V , V (V)

S

D

S

D

Figure 8. On Resistance (R_ON) as a Function of V_S, V_D(Single Supply)

Figure 11. On Resistance (R_ON) as a Function of V_S, V_Dfor Various Temperatures,

20 V Dual Supply

Rev. A | Page 15 of 30

ADGS5412

Data Sheet

30

0.8

0.6

V

= 12V

= 0V

V

= +20V

= –20V

BIAS

DD

SS

DD

SS

= +15V/–15V

I

, I (ON) + +

S

D

25

20

15

10

5

I

, I (ON) – –

S

D

T

= +125°C

0.4

A

I

(OFF) + –

S

T

= +85°C

A

0.2

I

(OFF) – +

D

T

= +25°C

= –40°C

0

T

A

–0.2

–0.4

–0.6

I

(OFF) – +

S

I

(OFF) + –

D

0

2

4

6

8

10

12

0

25

50

75

100

125

V , V (V)

TEMPERATURE (°C)

S

D

Figure 15. Leakage Currents vs. Temperature, 20 V Dual Supply

Figure 12. On Resistance (R_ON) as a Function of V_S, V_Dfor Various

Temperatures, 12 V Single Supply

0.6

16

14

12

V

= 12V

= 0V

BIAS

DD

SS

I

, I (ON) + +

S

D

= 1V/10V

0.4

0.2

0

T

= +125°C

A

T

= +85°C

I

, I (ON) – –

S

A

D

10

8

I

(OFF) + –

S

T

= +25°C

= –40°C

A

I

(OFF) – +

D

T

6

A

4

2

I

(OFF) + –

D

V

= 36V

= 0V

DD

SS

I

(OFF) – +

S

–0.2

0

25

50

75

100

125

0

5

10

15

20

25

30

35

40

TEMPERATURE (°C)

V , V (V)

S

D

Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply

Figure 13. R_ONas a Function of V_S,V_Dfor Various Temperatures,

36 V Single Supply

0.8

V

= 36V

= 0V

BIAS

DD

SS

V

= +15V

= –15V

BIAS

DD

SS

I

, I (ON) + +

S

D

= 1V/30V

= +10V/–10V

0.6

0.4

I

, I (ON) + +

S

D

0.6

0.4

0.2

0

I

, I (ON) – –

S

D

I

, I (ON) – –

S

D

I

(OFF) – +

D

I

(OFF) + –

S

0.2

0

I

(OFF) + –

S

–0.2

–0.4

–0.6

I

(OFF) – +

S

I

(OFF) – +

D

–0.2

–0.4

I

(OFF) + –

D

I

(OFF) – +

S

I

(OFF) + –

D

0

25

50

75

100

125

0

25

50

75

100

125

TEMPERATURE (°C)

Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply

Figure 14. Leakage Currents vs. Temperature, 15 V Dual Supply

Rev. A | Page 16 of 30

Data Sheet

ADGS5412

0

–20

T

V

= 25°C

= +15V

DD

T

V

= 25°C

A

100nF DECOUPLING CAP

10µF + 100nF DECOUPLING CAP

NO DECOUPLING

A

= +15V

= –15V

DD

SS

= –15V

–20

–40

SS

–40

–60

–80

–100

–120

–140

–100

–120

100

1k

10k

100k

1M

10M

100M

1G

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 21. AC Power Supply Rejection Ration (PSRR) vs. Frequency, 15 V

Dual Supply

Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply

0

–10

0.09

T

V

= 25°C

= +15V

SS

T = 25°C

A

DD

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

= –15V

–20

–30

–40

20V , V = 20V p-p

DS

S

–50

15V , V = 15V p-p

DS

12V , V = 6V p-p

SS

–60

, V = 18V p-p

S

36V

–70

–80

–90

–100

–110

–120

10k

100k

1M

10M

100M

1G

20

200

2k

20k

FREQUENCY (Hz)

Figure 22. THD + N vs. Frequency, 15 V Dual Supply

Figure 19. Crosstalk vs. Frequency, 15 V Dual Supply

0

–0.5

–1.0

–1.5

–0.2

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

400

350

300

250

200

150

100

50

T

= 25°C

A

V

= 20V, V = –20V

SS

DD

T

= 25°C

= +15V

= 15V, V = –15V

SS

A

DD

= –15V

SS

V

= 12V, V = 0V

SS

= 36V, V = 0V

SS

0

–20

10k

100k

1M

10M

100M

1G

–10

0

10

20

30

40

FREQUENCY (Hz)

Vs (V)

Figure 23. Bandwidth

Figure 20. Charge Injection vs. Source Voltage, V_S

Rev. A | Page 17 of 30

ADGS5412

Data Sheet

700

15V

450

400

350

300

250

200

150

100

50

,

t_ON

15V

20V

12V

36V

,

t_OFF

DS

T

= 25°C

A

20V

12V

36V

DS

SS

600

500

400

300

200

100

0

SS

,

SS

V

= 5V

= 3V

L

0

–40

–20

0

20

40

60

80

100

120

1

10

20

30

40

50

TEMPERATURE (°C)

SCLK FREQUENCY (MHz)

Figure 24. t_ON, t_OFFTimes vs. Temperature

CS

Figure 26. I_Lvs. SCLK Frequency When Is High

100

2.0

T

DD

= 25°C

SCLK = 2.5MHz

SCLK IDLE

T

V

= 25°C

A

DD

SS

A

I

WITH ONE SWITCH CLOSED

= +15V

= –15V

90

80

70

60

50

40

30

20

10

0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

12V

15V

20V

36V

0

2

4

6

8

2.7

3.0

3.5

4.0

4.5

5.0

5.5

TIME (µs)

V

(V)

L

Figure 25. I_DDvs. V_L

Figure 27. Digital Feedthrough

Rev. A | Page 18 of 30

Data Sheet

ADGS5412

TEST CIRCUITS

I

(OFF)

A

I

(OFF)

A

(ON)

S

D

Sx

Dx

Sx

Dx

V

S

V

D

V

D

S

Figure 28. On Leakage

Figure 32. Off Leakage

I

DS

V

SS

DD

0.1µF

V1

AUDIO PRECISION

Sx

Dx

V

SS

DD

R

S

Sx

R

= V /I

DS

ON

1

V

S

V p-p

Figure 29. On Resistance

Dx

V

OUT

R

1kΩ

L

V

DD

SS

GND

0.1µF

NETWORK

ANALYZER

V

Figure 33. THD + N

DD

SS

V

NIC

OUT

S1

D1

R

L

V

DD

SS

50Ω

0.1µF

S2

D2

R

L

NETWORK

ANALYZER

50Ω

V

DD

SS

V

S

GND

Sx

Dx

50Ω

V

S

V

OUT

CHANNEL TO CHANNEL CROSSTALK = 20 log

V

OUT

S

R

L

50Ω

Figure 30. Channel to Channel Crosstalk

GND

V

SS

DD

0.1µF

V

WITH SWITCH

OUT

INSERTION LOSS = 20 log

V

WITHOUT SWITCH

OUT

NETWORK

ANALYZER

Figure 34. Bandwidth

V

DD

SS

Sx

50Ω

V

S

Dx

V

OUT

R

L

50Ω

GND

V

OUT

OFF ISOLATION = 20 log

V

S

Figure 31. Off Isolation

Rev. A | Page 19 of 30

ADGS5412

Data Sheet

Figure 35. Break-Before-Make Time Delay, t_D

V

DD

SS

0.1µF

SCLK

V

OUT

50%

S

D

R

300Ω

C

L

35pF

L

90%

10%

V

S

V

INPUT LOGIC

GND

OUT

t_ON

t_OFF

Figure 36. Switching Times

V

DD

SS

3V

DD

SCLK

R

V

S

D

V

OUT

C

1nF

L

S

Q

= C × ∆V

OUT

INJ

L

INPUT LOGIC

GND

V

OUT

∆V

OUT

SWITCH OFF

SWITCH ON

Figure 37. Charge Injection

V

SS

NETWORK

ANALYZER

V

DD

SS

INTERNAL

BIAS

R

L

50Ω

V

S

V

NIC

OUT

R

S1

D1

L

50Ω

GND

V

OUT

AC PSRR = 20 log

V

S

NOTES

1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED

FROM THE AC PSRR MEASUREMENT.

Figure 38. AC PSRR

Rev. A | Page 20 of 30

Data Sheet

ADGS5412

TERMINOLOGY

I_DD

C_IN

I

_DDis the positive supply current.

C_INis the digital input capacitance.

I_SS

t_ON

I_SSis the negative supply current.

t_ONis the delay between applying the digital control input and

the output switching on.

V_D, V_S

V_Dand V_Sare the analog voltages on Terminal D and Terminal

S, respectively.

t_OFF

t_OFFis the delay between applying the digital control input and

the output switching off.

R_ON

R_ONis the ohmic resistance between Terminal D and Terminal

t_D

S.

t_Dis the off time measured between the 80% point of both

switches when switching from one address state to another.

∆R_ON

∆R_ONis the difference between the R_ONof any two channels.

Off Isolation

Off isolation is a measure of unwanted signal coupling through

an off switch.

R_{FLAT (ON)}

R_{FLAT (ON)}is flatness that is defined as the difference between the

Charge Injection

Charge injection is a measure of the glitch impulse transferred

from the digital input to the analog output during switching.

maximum and minimum value of on resistance measured over

the specified analog signal range.

I_S(Off)

Crosstalk

I_S(Off) is the source leakage current with the switch off.

Crosstalk is a measure of unwanted signal that is coupled

through from one channel to another as a result of parasitic

capacitance.

I_D(Off)

I_D(Off) is the drain leakage current with the switch off.

I_D(On), I_S(On)

I_D(On) and I_S(On) are the channel leakage currents with the

switch on.

Bandwidth

Bandwidth is the frequency at which the output is attenuated by

3 dB.

V_INL

On Response

V

_INLis the maximum input voltage for Logic 0.

V_INH

_INHis the minimum input voltage for Logic 1.

_INL, I_INH

_INLand I_INHare the low and high input currents of the digital

On response is the frequency response of the on switch.

Insertion Loss

V

Insertion loss is the loss due to the on resistance of the switch.

I

Total Harmonic Distortion + Noise (THD + N)

THD + N is the ratio of the harmonic amplitude plus the noise

of the signal to the fundamental.

inputs.

C_D(Off)

AC Power Supply Rejection Ratio (AC PSRR)

C_D(Off) is the off switch drain capacitance, which is measured

with reference to the GND pin.

AC PSRR is the ratio of the amplitude of signal on the output to

the amplitude of the modulation. This is a measure of the ability

of the device to avoid coupling noise and spurious signals that

appear on the supply voltage pin to the output of the switch. The dc

voltage on the device is modulated by a sine wave of 0.62 V p-p.

C_S(Off)

C_S(Off) is the off switch source capacitance, which is measured

with reference to the GND pin.

C_D(On), C_S(On)

C_D(On) and C_S(On) are the on switch capacitances, which are

measured with reference to the GND pin

Rev. A | Page 21 of 30

ADGS5412

Data Sheet

THEORY OF OPERATION

The ADGS5412 is a set of serially controlled, quad SPST

switches with error detection features. SPI Mode 0 and Mode 3

can be used with the device, and it operates with SCLK frequen-

cies up to 50 MHz. The default mode for the ADGS5412 is

address mode, in which the registers of the device are accessed

reads. A register write occurs on the 16^thSCLK rising edge

during SPI writes.

During any SPI command, SDO sends out eight alignment bits

on the first eight SCLK falling edges. The alignment bits observed

at SDO are 0x25.

CS

by a 16-bit SPI command that is bounded by . The SPI

ERROR DETECTION FEATURES

command becomes 24-bit if the user enables CRC error detection.

Other error detection features include SCLK count error and

invalid read/write error. If any of these SPI interface errors occur,

they are detectable by reading the error flags register. The

ADGS5412 can also operate in two other modes: burst mode

and daisy-chain mode.

Protocol and communication errors on the SPI interface are

detectable. There are three detectable errors, which are incorrect

SCLK error detection, invalid read and write address error

detection, and CRC error detection. Each of these errors has a

corresponding enable bit in the error configuration register. In

addition, there is an error flag bit for each of these errors in the

error flags register.

CS

The interface pins of the ADGS5412 are , SCLK, SDI, and

CS

SDO. Hold low when using the SPI interface. Data is captured

Cyclic Redundancy Check (CRC) Error Detection

on the SDI pin on the rising edge of SCLK, and data is propagated

out on the SDO pin on the falling edge of SCLK. SDO has an

open-drain output; thus, connect a pull-up to this output. When

not pulled low by the ADGS5412, SDO is in a high impedance

state.

The CRC error detection feature extends a valid SPI frame by

eight SCLK cycles. These eight extra cycles are needed to send the

CRC byte for that SPI frame. The CRC byte is calculated by the SPI

W

block using the 16-bit payload: the R/ bit, Register Address

Bits[6:0], and Register Data Bits[7:0]. The CRC polynomial used

in the SPI block is x⁸+ x²+ x¹+ 1 with a seed value of 0. For a

timing diagram with CRC enabled, see Figure 40. Register

writes occur at the 24^thSCLK rising edge with CRC error

checking enabled.

ADDRESS MODE

Address mode is the default mode for the ADGS5412 on power-up.

A single SPI frame in address mode is bounded by a

CS

falling

CS

edge and the succeeding rising edge. It is comprised of 16 SCLK

cycles. The timing diagram for address mode is shown in Figure 39.

The first SDI bit indicates if the SPI command is a read or write

command. When the first bit is set to 0, a write command is issued,

and if the first bit is set to 1, a read command is issued. The next

seven bits determine the target register address. The remaining

eight bits provide the data to the addressed register. The last eight

bits are ignored during a read command, because during these

clock cycles, SDO propagates out the data contained in the

addressed register.

During an SPI write, the microcontroller or CPU provides the

CRC byte through SDI. The SPI block checks the CRC byte just

before the 24^thSCLK rising edge. On this same edge, the register

write is prevented if an incorrect CRC byte is received by the

SPI interface. The CRC error flag is asserted in the error flags

register in the case of the incorrect CRC byte being detected.

During an SPI read, the CRC byte is provided to the microcon-

troller through SDO.

The CRC error detection feature is disabled by default and can

be configured by the user through the error configuration register.

The target register address of an SPI command is determined on

the eighth SCLK rising edge. Data from this register propagates out

on SDO from the ninth to the 16^thSCLK falling edge during SPI

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

CS

SCLK

SDI

R/W A6

0

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SDO

0

1

0

1

0

1

D7

D6

D5

D4

D3

D2

D1

D0

Figure 39. Address Mode Timing Diagram

1

2

8

9

10

16

17

18

19

20

21

22

23

24

CS

SCLK

SDI

R/W A6

0

A0

D7

D6

D0

C7

C6

C5

C4

C3

C2

C1

C0

0

1

D7

D6

D0

C7

C6

C5

C4

C3

C2

C1

C0

SDO

Figure 40. Timing Diagram with CRC Enabled

Rev. A | Page 22 of 30

Data Sheet

ADGS5412

SCLK Count Error Detection

BURST MODE

SCLK count error detection allows the user to detect if an incorrect

number of SCLK cycles are sent by the microcontroller or CPU.

When in address mode, with CRC disabled, 16 SCLK cycles are

expected. If 16 SCLK cycles are not detected, the SCLK count

error flag asserts in the error flags register. When less than

16 SCLK cycles are received by the device, a write to the register

map never occurs. When the ADGS5412 receives more than

16 SCLK cycles, a write to the memory map still occurs at the

16^thSCLK rising edge, and the flag asserts in the error flags

register. With CRC enabled, the expected number of SCLK

cycles becomes 24. SCLK count error detection is enabled by

default and can be configured by the user through the error

configuration register.

The SPI interface can accept consecutive SPI commands

without the need to deassert the CS line, which is called burst

mode. Burst mode is enabled through the burst enable register.

This mode uses the same 16-bit command to communicate

with the device. In addition, the response of the device at SDO

is still aligned with the corresponding SPI command. Figure 41

shows an example of SDI and SDO during burst mode.

The invalid read/write address and CRC error checking functions

operate similarly during burst mode as they do during address

mode. However, SCLK count error detection operates in a

slightly different manner. The total number of SCLK cycles

CS

within a given

frame are counted, and if the total is not a

multiple of 16 or a multiple of 24 when CRC is enabled, the

SCLK count error flag asserts.

Invalid Read/Write Address Error

An invalid read/write address error detects when a nonexistent

register address is a target for a read or write. In addition, this

error asserts when a write to a read only register is attempted.

The invalid read/write address error flag asserts in the error

flags register when an invalid read/write address error occurs.

The invalid read/write address error is detected on the ninth

SCLK rising edge, which means a write to the register never

occurs when an invalid address is targeted. Invalid read/write

address error detection is enabled by default and can be

disabled by the user through the error configuration register.

CS

SDI

COMMAND0[15:0] COMMAND1[15:0] COMMAND2[15:0] COMMAND3[15:0]

RESPONSE0[15:0] RESPONSE1[15:0] RESPONSE2[15:0] RESPONSE3[15:0]

Figure 41. Burst Mode Frame

SDO

SOFTWARE RESET

When in address mode, the user can initiate a software reset. To

do so, write two consecutive SPI commands, namely 0xA3 fol-

lowed by 0x05, targeting Register 0x0B. After a software reset,

all register values are set to default.

CLEARING THE ERROR FLAGS REGISTER

DAISY-CHAIN MODE

To clear the error flags register, write the special 16-bit SPI

frame, 0x6CA9, to the device. This SPI command does not

The connection of several ADGS5412 devices in a daisy-chain

configuration is possible, and Figure 42 shows this setup. All

devices share the same and SCLK line, whereas the SDO of a

device forms a connection to the SDI of the next device, creating a

shift register. In daisy-chain mode, SDO is an eight cycle delayed

version of SDI. When in daisy-chain mode, all commands target

the switch data register. Therefore, it is not possible to make

configuration changes while in daisy-chain mode.

DEVICE 2

W

trigger the invalid R/ address error. When CRC is enabled,

CS

the user must also send the correct CRC byte for a successful

error clear command. At the 16^thor 24^thSCLK rising edge, the

error flags register resets to zero.

DEVICE 1

ADGS5412

S1

S2

S3

S4

D1

S1

S2

S3

S4

D1

D2

D3

D4

D2

D3

RESET/V

D4

L

SDO

SPI

INTERFACE

SPI

INTERFACE

SDO

SDI

SCLK

CS

RESET/V

L

Figure 42. Two SPI Controlled Switches Connected in a Daisy-Chain Configuration

Rev. A | Page 23 of 30

ADGS5412

Data Sheet

The ADGS5412 can only enter daisy-chain mode when in

address mode by sending the 16-bit SPI command, 0x2500

(see Figure 43). When the ADGS5412 receives this command,

the SDO of the device sends out the same command because

the alignment bits at SDO are 0x25, which allows multiple

daisy-connected devices to enter daisy-chain mode in a single

SPI frame. A hardware reset is required to exit daisy-chain mode.

An SCLK rising edge reads in data on SDI while data is

propagated out SDO on an SCLK falling edge. The expected

CS

number of SCLK cycles must be a multiple of eight before

goes high. When this is not the case, the SPI interface sends the

last eight bits received to the switch data register

POWER-ON RESET

The digital section of the ADGS5412 goes through an initialization

phase during V_Lpower up. This initialization also occurs after a

hardware or software reset. After V_Lpower-up or a reset, ensure

that a minimum of 120 μs from the time of power-up or reset

before any SPI command is issued. Ensure that V_Ldoes not

drop out during the 120 μs initialization phase because it may

result in incorrect operation of the ADGS5412.

For the timing diagram of a typical daisy-chain SPI frame, see

CS

Figure 44. When

goes high, Device 1 writes Command 0,

Bits[7:0] to its switch data register, Device 2 writes Command 1,

Bits[7:0] to its switches, and so on. The SPI block uses the last

eight bits it received through SDI to update the switches. After

entering daisy-chain mode, the first eight bits sent out by SDO

CS

on each device in the chain are 0x00. When

goes high, the

internal shift register value does not reset back to zero.

1

0

2

0

3

4

5

6

7

0

8

1

9

10

11

12

13

14

15

16

CS

SCLK

SDI

1

0

1

0

SDO

0

1

0

1

0

1

0

Figure 43. SPI Command to Enter Daisy-Chain Mode

CS

SDI

COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0]

DEVICE 1

DEVICE 2

DEVICE 3

DEVICE 4

SDO

8’h00

COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0]

SDO2

SDO3

8’h00

COMMAND3[7:0] COMMAND2[7:0]

8’h00 COMMAND3[7:0]

NOTES

1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.

Figure 44. Example of an SPI Frame When Four ADGS5412 Devices are Connected in Daisy-Chain Mode

Rev. A | Page 24 of 30

Data Sheet

ADGS5412

switch pins pass the maximum rating in the JESD78D standard

in which they are stressed with a 5ꢀꢀ mA pulse for 1 second.

BREAK-BEFORE-MAKE SWITCHING

The ADGS5412 exhibits break-before-make switching action,

which allows the use of the device in multiplexer applications.

This configuration can be achieved by externally hardwiring the

device in the mux configuration that is required, as shown in

Figure 45.

The high voltage latch-up proof family of switches and multiplexers

provide a robust solution for instrumentation, industrial, automo-

tive, aerospace, and other harsh environments that are prone to

latch-up, which is an undesirable high current state that can

lead to device failure and which persists until the power supply

is turned off. The ADGS5412 high voltage switches allow

single-supply operation from 9 V to 4ꢀ V and dual-supply

operation from 9 V to 22 V.

4:1 MUX

4 × SPST

S1

NMOS

PMOS

S2

Dx

S3

S4

SPI

INTERFACE

CS

SCLK SDI

RESET/V

L

P-WELL

N-WELL

Figure 45. An SPI Controlled Switch Configured into a 4:1 Mux

TRENCH ISOLATION

In the analog switch section of the ADGS5412, an insulating

oxide layer (trench) is placed between the negative channel metal-

oxide semiconductor (NMOS) and the positive channel metal-

oxide semiconductor (PMOS) transistors of each complementary

metal oxide semiconductor switch (CMOS). Parasitic junctions,

which occur between the transistors in junction isolated

switches, are eliminated, and the result is a completely latch-up

proof switch.

TRENCH

BURIED OXIDE LAYER

HANDLE WAFER

Figure 46. Trench Isolation

DIGITAL INPUT BUFFERS

There are input buffers present on the digital inputs pins

SCLK, and SDI. These buffers are active at all times. As result of

this, there will be current draw from the V_Lsupply if SCLK or SDI

are toggling, regardless whether

this current draw, refer to the specification tables and Figure 26.

,

CS

In junction isolation, the negative (N) and positive (P) wells of the

PMOS and NMOS transistors form a diode that is reverse-biased

under normal operation. However, during overvoltage

conditions, this diode can become forward-biased. A silicon

controlled rectifier (SCR) circuit is formed by the two transistors,

causing a significant amplification of the current that, in turn,

leads to latch-up. With trench isolation, this diode is removed,

and the result is a latch-up proof switch. The ADGS5412 analog

is active. For typical values of

CS

Rev. A | Page 25 of 30

ADGS5412

Data Sheet

APPLICATIONS INFORMATION

positive and negative low dropout regulators (LDOs), respectively,

that can be used to reduce the output ripple of the ADP5070 in

ultralow noise sensitive applications.

POWER SUPPLY RAILS

To guarantee correct operation of the ADGS5412, 0.1 µF

decoupling capacitors are required.

The ADM7160 can be used to generate the

that is required to power digital circuitry within the ADGS5412.

/V_Lvoltage

RESET

The ADGS5412 can operate with bipolar supplies between 9 V

and 22 V. The supplies on V_DDand V_SSdo not have to be

symmetrical; however, the V_DDto V_SSrange must not exceed 44 V.

The ADGS5412 can also operate with single supplies between

9 V and 40 V with V_SSconnected to GND.

ADM7160

+3.3V

LDO

+16.5V

–16.5V

ADP7118

LDO

+15V

–15V

+5V

INPUT

ADP5070

The voltage range that can be supplied to

to 5.5 V.

/V_Lis from 2.7 V

ADP7182

LDO

RESET

Figure 47. Bipolar Power Solution

The device is fully specified at 15 V, 20 V, +12 V, and +36 V

analog supply voltage ranges.

Table 10. Recommended Power Management Devices

Product Description

ADP5070 1 A/0.6 A, dc-to-dc switching regulator with

independent positive and negative outputs

ADM7160 5.5 V, 200 mA, ultralow noise, linear regulator

ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator

ADP7182 −28 V, −200 mA, low noise, LDO linear regulator

POWER SUPPLY RECOMMENDATIONS

Analog Devices, Inc. has a wide range of power management

products to meet the requirements of most high performance

signal chains.

An example of a bipolar power solution is shown in Figure 47.

The ADP5070 (dual switching regulator) generates a positive and

negative supply rail for the ADGS5412, amplifier, and/or a

precision converter in a typical signal chain. Also shown in

Figure 47 are two optional LDOs, ADP7118 and ADP7182,

Rev. A | Page 26 of 30

Data Sheet

ADGS5412

REGISTER SUMMARY

Table 11. Register Summary

Reg. Name

Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

Default

0x00

RW

R/W

R

0x01 SW_DATA

0x02 ERR_CONFIG

0x03 ERR_FLAGS

0x05 BURST_EN

0x0B SOFT_RESETB

[7:0]

Reserved

SW4_EN SW3_EN

SW2_EN

SW1_EN

RW_ERR_EN

RW_ERR_FLAG

Reserved

SCLK_ERR_EN

SCLK_ERR_FLAG

CRC_ERR_EN

CRC_ERR_FLAG

BURST_MODE_EN

0x06

0x00

R/W

SOFT_RESETB

0x00

Rev. A | Page 27 of 30

ADGS5412

Data Sheet

REGISTER DETAILS

SWITCH DATA REGISTER

Address: 0x01, Reset: 0x00, Name: SW_DATA

The switch data register controls the status of the four switches of the ADGS5412.

Table 12. Bit Descriptions for SW_DATA

Bits

[7:4]

3

Bit Name

Reserved

SW4_EN

Settings

Description

Default

0x0

Access

R

These bits are reserved; set these bits to 0.

Enable bit for SW4.

SW4 open.

0x0

R/W

0

1

SW4 closed.

2

1

0

SW3_EN

SW2_EN

SW1_EN

Enable bit for SW3.

SW3 open.

SW3 closed.

0x0

R/W

0

1

Enable bit for SW2.

SW2 open.

SW2 closed.

0

1

Enable bit for SW1.

SW1 open.

SW1 closed.

0

1

ERROR CONFIGURATION REGISTER

Address: 0x02, Reset: 0x06, Name: ERR_CONFIG

The error configuration register allows the user to enable/disable the relevant error features as required.

Table 13. Bit Descriptions for ERR_CONFIG

Bits Bit Name

Settings Description

Default Access

[7:3] Reserved

These bits are reserved; set these bits to 0.

0x0

0x1

R

2

1

RW_ERR_EN

Enable bit for detecting an invalid read/write address.

Disabled.

Enabled.

R/W

0

1

SCLK_ERR_EN

Enable bit for detecting the correct number of SCLK cycles in an SPI frame. When

CRC is disabled and burst mode is disabled, 16 SCLK cycles are expected. When

CRC is enabled and burst mode is disabled, 24 SCLK cycles are expected. A multiple

of 16 SCLK cycles is expected when CRC is disabled and burst mode is enabled. A

multiple of 24 SCLK cycles is expected when CRC is enabled and burst mode is

enabled.

0x1

0x0

R/W

0

1

Disabled.

Enabled.

0

CRC_ERR_EN

Enable bit for CRC error detection. SPI frames must be 24 bits wide when enabled.

0

1

Disabled.

Enabled.

Rev. A | Page 28 of 30

Data Sheet

ADGS5412

ERROR FLAGS REGISTER

Address: 0x03, Reset: 0x00, Name: ERR_FLAGS

The error flags register allows the user to determine if an error occurred. To clear the error flags register, write the special 16-bit SPI

W

command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/ address error. When CRC is enabled then the user

must include the correct CRC byte during the SPI write in order for the clear error flags register command to be successful.

Table 14. Bit Descriptions for ERR_FLAGS

Bits Bit Name

Settings Description

Default Access

[7:3] Reserved

These bits are reserved and are set to 0.

0x0

R

2

RW_ERR_FLAG

Error flag for invalid read/write address. The error flag asserts during an SPI read

if the target address does not exist. The error flag also asserts when the target

address of an SPI write does not exist or is read only.

0

1

No error.

Error.

1

0

SCLK_ERR_FLAG

CRC_ERR_FLAG

Error flag for the detection of the correct number of SCLK cycles in an SPI frame.

No error.

Error.

0x0

R

0

1

Error flag that determines if a CRC error occurred during a register write.

0

1

No error.

Error.

BURST ENABLE REGISTER

Address: 0x05, Reset: 0x00, Name: BURST_EN

The burst enable register allows the user to enable or disable the burst mode. When enabled, the user can send multiple consecutive SPI

commands without de-asserting

.

CS

Table 15. Bit Descriptions for BURST_EN

Bits

[7:1]

0

Bit Name

Settings

Description

Default

0x0

Access

R

Reserved

These bits are reserved; set these bits to 0.

BURST_MODE_EN

Burst mode enable bit.

Disabled.

Enabled.

0x0

R/W

0

1

SOFTWARE RESET REGISTER

Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB

This register is used to perform a software reset. Consecutively write 0xA3 and 0x05 to this register and the device registers reset to their

default states.

Table 16. Bit Descriptions for SOFT_RESETB

Bits Bit Name

Settings Description

To perform a software reset, consecutively write 0xA3 followed by 0x05 to this

register.

Default Access

0x0 R/W

[7:0] SOFT_RESETB

Rev. A | Page 29 of 30

ADGS5412

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

4.10

4.00 SQ

3.90

0.30

0.25

0.18

PIN 1

INDICATOR

1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

24

19

18

1

0.50

BSC

2.70

2.60 SQ

2.50

EXPOSED

PAD

13

12

6

7

0.50

0.40

0.30

0.20 MIN

TOP VIEW

BOTTOM VIEW

1.00

0.95

0.90

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.

Figure 48. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.95 mm Package Height

(CP-24-17)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADGS5412BCPZ

ADGS5412BCPZ-RL7

EVAL-ADGS5412SDZ

Temperature Range

−40°C to +125°C

Package Description

Package Option

CP-24-17

24-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D15234-0-7/18(A)

Rev. A | Page 30 of 30


型号：	ADGS5412BCPZ-RL7
厂家：	ADI
描述：	SPI Interface, 4Ã SPST Switches, 9.8 Î© RON, Â±20 V/36 V, Mux Configurable
文件：	总30页 (文件大小：608K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADGS5412BCPZ-RL7 [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E