ADIS16467 [ADI]
Precision MEMS IMU Module;
| 型号： | ADIS16467 |
| 厂家： | 
ADI |
| 描述： | Precision MEMS IMU Module |
| 文件： | 总34页 (文件大小：758K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision MEMS IMU Module
Data Sheet
ADIS16467
FEATURES
GENERAL DESCRIPTION
Triaxial, digital gyroscope
The ADIS16467 is a precision, microelectric mechanical system
(MEMS), inertial measurement unit (IMU) that includes a triaxial
gyroscope and a triaxial accelerometer. Each inertial sensor in
the ADIS16467 combines with signal conditioning to optimize
dynamic performance. The factory calibration characterizes
each sensor for sensitivity, bias, alignment, linear acceleration
(gyroscope bias), and point of percussion (accelerometer location).
Therefore, each sensor has dynamic compensation formulas
that provide accurate sensor measurements over a broad set of
conditions.
12ꢀ°/sec, ꢀ00°/sec, 2000°/sec dynamic range models
2°/hr in-run bias stability (ADIS16467-1)
0.1ꢀ°/√hr angular random walk (ADIS16467-1 and
ADIS16467-2)
0.0ꢀ° axis to axis misalignment error
Triaxial, digital accelerometer, 40 g
13 μg in-run bias stability
Triaxial, delta angle, and delta velocity outputs
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +8ꢀ°C
SPI-compatible data communications
Programmable operation and control
Automatic and manual bias correction controls
Data ready indicator for synchronous data acquisition
External sync modes: direct, pulse, scaled, and output
On demand self test of inertial sensors
On demand self test of flash memory
The ADIS16467 provides a simple, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared to the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation
systems. The serial peripheral interface (SPI) and register structure
provide a simple interface for data collection and configuration
control.
Single-supply operation (VDD): 3.0 V to 3.6 V
2000 g mechanical shock survivability
Operating temperature range: −40°C to +10ꢀ°C
The ADIS16467 is in an aluminum module package that is
approximately 22.4 mm × 24.3 mm × 9 mm with a 14-lead
connector interface.
APPLICATIONS
Navigation, stabilization, and instrumentation
Unmanned and autonomous vehicles
Smart agriculture and construction machinery
Factory/industrial automation, robotics
Virtual/augmented reality
Internet of Moving Things
FUNCTIONAL BLOCK DIAGRAM
DR
RST
VDD
POWER
GND
CS
SELF TEST
INPUT/OUTPUT
MANAGEMENT
OUTPUT
DATA
REGISTERS
TRIAXIAL
GYROSCOPE
SCLK
DIN
CALIBRATION
TRIAXIAL
ACCELEROMETER
SPI
CONTROLLER
AND
FILTERS
USER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
DOUT
CLOCK
ADIS16467
SYNC
Figure 1.
Rev. C
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ADIS16467
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Device Configuration ................................................................ 15
User Register Memory Map.......................................................... 16
User Register Defintions ............................................................... 18
Gyroscope Data .......................................................................... 18
Delta Angles................................................................................ 21
Delta Velocity ............................................................................. 22
Calibration .................................................................................. 24
Applications Information ............................................................. 31
Assembly and Handling Tips ................................................... 31
Power Supply Considerations .................................................. 31
Breakout Board........................................................................... 31
Serial Port Operation................................................................. 32
Digital Resolution of Gyroscopes and Accelerometers ........ 32
PC-Based Evaluation Tools ...................................................... 33
Packaging and Ordering Information......................................... 34
Outline Dimensions................................................................... 34
Ordering Guide .......................................................................... 34
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings....................................................... 7
Thermal Resistance...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions ............................ 8
Typical Performance Characteristics............................................. 9
Theory of Operation ...................................................................... 11
Introduction................................................................................ 11
Inertial Sensor Signal Chain ..................................................... 11
Register Structure....................................................................... 12
Serial Peripheral Interface (SPI)............................................... 13
Data Ready (DR) ........................................................................ 13
Reading Sensor Data.................................................................. 14
REVISION HISTORY
2/2020—Rev. B to Rev. C
2/2019—Rev. 0 to Rev. A
Changes to Table 1 ........................................................................... 3
Added Figure 18 ............................................................................. 10
Changes to Reading Sensor Data Section and Burst Read
Function Section............................................................................. 14
Changes to Table 1............................................................................3
Changes to Table 2............................................................................5
Changes to Figure 5 ..........................................................................6
Added Figure 11, Figure 12, and Figure 13; Renumbered
Sequentially ........................................................................................9
Added Figure 14, Figure 15, Figure 16, and Figure 17.............. 10
Changes to Figure 18, Figure 19, and Figure 20 ........................ 11
Changes to Figure 22 and Figure 23............................................ 12
Added Gyroscope Data Width (Digital Resolution) Section... 18
Changes to Gyroscope Measurement Range/Scale Factor Section,
Table 11, Table 12, Table 13, Table 17, Table 21, and Table 25 19
Added Accelerometer Data Width (Digital Resolution) Section
........................................................................................................... 20
Change to Calibration, Accelerometer Bias (XA_BIAS_LOW
and XA_BIAS_HIGH) Section..................................................... 25
Change to Filter Control Register (FILT_CTRL) Section........ 26
Changes to Direct Sync Mode Section ........................................ 27
Changes to Pulse Sync Mode Section.......................................... 28
Changes to Sensor Self Test Section ............................................ 29
Changes to Figure 52 ..................................................................... 31
Changes to Outline Dimensions.................................................. 33
4/2019—Rev. A to Rev. B
Changes to Serial Peripheral Interface (SPI) Section ................ 13
Changes to Figure 32 ..................................................................... 14
Changes to Table 10....................................................................... 18
Changes to Gyroscope Data Section............................................ 18
Changes to Acceleration Data Section ........................................ 19
Added Accelerometer Data Formatting Section........................ 20
Deleted Accelerometer Resolution Section ................................ 20
Added Serial Port Operation Section, Maximum Throughput
Section, and Serial Port SCLK Underrun/Overrun Conditions
Section.............................................................................................. 32
Added Digital Resolution of Gyroscopes and Accelerometers
Section.............................................................................................. 32
Moved Gyroscope Data Width (Digital Resolution) Section........ 32
Moved Accelerometer Data Width (Digital Resolution) Section. 32
12/2017—Revision 0: Initial Version
Rev. C | Page 2 of 34
Data Sheet
ADIS16467
SPECIFICATIONS
Case temperature (TC) = 25°C, VDD = 3.3 V, angular rate = 0°/sec, and dynamic range = 2000°/sec 1 g, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
GYROSCOPES
Dynamic Range
ADIS16467-1
ADIS16467-2
ADIS16467-3
125
500
2000
°/sec
°/sec
°/sec
Sensitivity
ADIS16467-1, 16-bit
ADIS16467-2, 16-bit
ADIS16467-3, 16-bit
ADIS16467-1, 32-bit
ADIS16467-2, 32-bit
ADIS16467-3, 32-bit
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
Axis to axis, 1 σ
160
40
10
10,485,760
2,621,440
655,360
0.3
0.1
0.05
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
LSB/°/sec
%
Repeatability1
Error over Temperature
Misalignment Error
Nonlinearity2
%
Degrees
% FS
% FS
ADIS16467-1, full scale (FS) = 125°/sec
ADIS16467-2, FS = 500°/sec
ADIS16467-3, FS = 2000°/sec
0.2
0.2
0.25
% FS
Bias
In-Run Bias Stability
ADIS16467-1, 1 σ
2
°/hr
ADIS16467-2, 1 σ
2.5
°/hr
ADIS16467-3, 1 σ
6
°/hr
Angular Random Walk
ADIS16467-1, 1 σ
ADIS16467-2, 1 σ
ADIS16467-3, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
0.15
0.15
0.26
0.4
°/√hr
°/√hr
°/√hr
°/sec
Repeatability1
Error over Temperature
Linear Acceleration Effect
Vibration Rectification Effect
Output Noise
−40°C ≤ TC ≤ +85°C, 1 σ
Any direction, 1 σ
0.2
°/sec
°/sec/g
0.009
0.0005
0.05
0.07
0.05
0.08
0.11
0.16
0.002
0.003
0.002
0.003
0.004
0.0065
550
Random vibration, 2 g rms, bandwidth = 50 Hz to 2 kHz
ADIS16467-1, 1 σ, no filtering, x-axis
ADIS16467-1, 1 σ, no filtering, y-axis and z-axis
ADIS16467-2, 1 σ, no filtering, x-axis
ADIS16467-2, 1 σ, no filtering, y-axis and z-axis
ADIS16467-3, 1 σ, no filtering, x-axis
ADIS16467-3, 1 σ, no filtering, y-axis and z-axis
ADIS16467-1, 10 Hz to 40 Hz, x-axis
ADIS16467-1, 10 Hz to 40 Hz, y-axis and z-axis
ADIS16467-2, 10 Hz to 40 Hz, x-axis
ADIS16467-2, 10 Hz to 40 Hz, y-axis and z-axis
ADIS16467-3, 10 Hz to 40 Hz, x-axis
ADIS16467-3, 10 Hz to 40 Hz, y-axis and z-axis
°/sec/g2
°/sec rms
°/sec rms
°/sec rms
°/sec rms
°/sec rms
°/sec rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
Hz
Rate Noise Density
3 dB Bandwidth
Sensor Resonant Frequency
ACCELEROMETERS3
Dynamic Range
66
kHz
Each axis
40
g
Sensitivity
32-bit data format
52,428,800
0.2
0.1
0.05
0.02
0.4
LSB/g
%
%
Degrees
% FS
% FS
% FS
Repeatability1
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
Axis to axis
Best fit straight line, 10 g
Best fit straight line, 20 g
Best fit straight line, 40 g
Rev. C | Page 3 of 34
Error over temperature
Misalignment Error
Nonlinearity
1.5
ADIS16467
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
Bias
In-Run Bias Stability
Velocity Random Walk
Repeatability1
Error over Temperature
Output Noise
Noise Density
1 σ, y-axis and z-axis
1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
−40°C ≤ TC ≤ +85°C, 1 σ
No filtering
13
0.037
6
μg
m/sec/√hr
mg
mg
mg rms
μg/√Hz rms
Hz
3
2.3
100
600
5.65
5.25
Bandwidth = 10 Hz to 40 Hz, no filtering
3 dB Bandwidth
Sensor Resonant Frequency
Y-axis and z-axis
X-axis
kHz
kHz
TEMPERATURE SENSOR
Scale Factor
Output = 0x0000 at 0°C ( 5°C)
0.1
°C/LSB
LOGIC INPUTS4
Input Voltage
High, VIH
2.0
V
Low, VIL
0.8
V
RST Pulse Width
CS Wake-Up Pulse Width
Input Current
1
μs
μs
20
Logic 1, IIH
Logic 0, IIL
All Pins Except RST
RST Pin
VIH = 3.3 V
VIL = 0 V
10
10
μA
μA
mA
pF
0.33
10
Input Capacitance, CIN
DIGITAL OUTPUTS
Output Voltage
High, VOH
ISOURCE = 0.5 mA
ISINK = 2.0 mA
2.4
V
V
Low, VOL
0.4
FLASH MEMORY
Data Retention6
FUNCTIONAL TIMES7
Power-On Start-Up Time
Reset Recovery Time
Endurance5
TJ = 85°C
10000
20
Cycles
Years
Time until data is available
259
198
198
142
72
ms
ms
ms
ms
ms
ms
ms
SPS
%
Register GLOB_CMD, Bit 7 = 1 (see Table 113)
RST pulled low, then restored to high8
Factory Calibration Restore
Flash Memory Backup
Flash Memory Test Time
Self Test Time9
Register GLOB_CMD, Bit 1 = 1 (see Table 113)
Register GLOB_CMD, Bit 3 = 1 (see Table 113)
Register GLOB_CMD, Bit 4 = 1 (see Table 113)
Register GLOB_CMD, Bit 2 = 1 (see Table 113)
32
14
CONVERSION RATE
Initial Clock Accuracy
Sync Input Clock
2000
3
1.9
3.0
2.1
3.6
55
kHz
V
mA
POWER SUPPLY, VDD
Power Supply Current10
Operating voltage range
Normal mode, VDD = 3.3 V
44
1 Bias repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of High-Temperature Operating Life (HTOL) at +105°C.
2 This measurement is based on the deviation from a best fit linear model.
3 All specifications associated with the accelerometers relate to the full-scale range of 40 g, unless otherwise noted.
4 The digital input/output signals use a 3.3 V system.
5 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C.
6 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.
7 These times do not include thermal settling and internal filter response times, which may affect overall accuracy.
8
RST
The
line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery.
9 The self test time can extend when using external clock rates lower than 2000 Hz.
10 Power supply current transients can reach 100 mA during initial startup or reset recovery.
Rev. C | Page 4 of 34
Data Sheet
ADIS16467
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
Burst Read Mode
Parameter Description
Min Typ Max Min1 Typ Max Unit
fSCLK
Serial clock
Stall period between data
Read rate
0.1
16
24
2
0.1
N/A
1
MHz
μs
μs
tSTALL
tREADRATE
tCS
Chip select to SCLK edge
200
200
ns
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise/fall times
DOUT rise/fall times
CS high after SCLK edge
25
25
ns
ns
ns
25
50
25
50
5
5
12.5
12.5
5
5
12.5 ns
12.5 ns
ns
0
5
0
5
t1
Input sync positive pulse width; pulse sync mode,
Register MSC_CTRL, Bits[4:1] (binary, see Table 105)
μs
tSTDR
Input sync to data ready valid transition
Direct sync mode, Register MSC_CTRL, Bits[4:2] (binary, see Table 105)
Pulse sync mode, Register MSC_CTRL, Bits[4:2] (binary, see Table 105)
Data invalid time
256
256
20
256
256
20
μs
μs
μs
μs
tNV
t2
Input sync period2
477
477
1 N/A means not applicable.
2 This specification is rounded up from the cycle time that comes from the maximum input clock frequency (2100 Hz).
Timing Diagrams
CS
tSCLKR
tSCLKF
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
DOUT
tDAV
tDR
MSB
R/W
DB14
tDSU
DB13
A5
DB12
DB11
A3
DB10
tDF
DB2
DB1
LSB
LSB
tDHD
DIN
A6
A4
A2
D2
D1
Figure 2. SPI Timing and Sequence Diagram
tREADRATE
tSTALL
CS
SCLK
Figure 3. Stall Time and Data Rate Timing Diagram
Rev. C | Page 5 of 34
ADIS16467
Data Sheet
t2
tSTDR
t1
SYNC
DR
tNV
Figure 4. Input Clock Timing Diagram, Pulse Sync Mode, Register MSC_CTRL, Bits[4:2] = 101 (Binary)
t2
t1
SYNC
DR
tNV
tSTDR
Figure 5. Input Clock Timing Diagram, Direct Sync Mode, Register MSC_CTRL, Bits[4:2] = 001 (Binary)
Rev. C | Page 6 of 34
Data Sheet
ADIS16467
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Mechanical Shock Survivability
Any Axis, Unpowered
2000 g
The ADIS16467 is a multichip module that includes many active
components. The values in Table 4 identify the thermal
response of the hottest component inside of the ADIS16467,
with respect to the overall power dissipation of the module.
This approach enables a simple method for predicting the
temperature of the hottest junction, based on either ambient or
case temperature.
Any Axis, Powered
VDD to GND
2000 g
−0.3 V to +3.6 V
−0.3 V to VDD + 0.2 V
−0.3 V to VDD + 0.2 V
−40°C to +85°C
−40°C to +105°C
−65°C to +150°C
2-bar
Digital Input Voltage to GND
Digital Output Voltage to GND
Calibration Temperature Range
Operating Temperature Range
Storage Temperature Range1
Barometric Pressure
For example, when the ambient temperature is 70°C, the hottest
junction temperature (TJ) inside of the ADIS16467 is 75.3°C.
1 Extended exposure to temperatures that are lower than −40°C or higher
than +105°C can adversely affect the accuracy of the factory calibration.
TJ = θJA × VDD × IDD + 70°C
TJ = 36.5°C/W × 3.3 V × 0.044 A + 70°C
TJ = 75.3°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 4. Thermal Resistance
1
2
Package Type
θJA
θJC
16.9C/W
Mass (g)
ML-14-63
36.5°C/W
15
1 θJA is the natural convection junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure.
2 θJC is the junction to case thermal resistance.
3 Thermal impedance values come from direct observation of the hottest
temperature inside of the ADIS16467, when it is attached to an FR4-08 PCB
that has two metal layers and has a thickness of 0.063 inches.
ESD CAUTION
Rev. C | Page 7 of 34
ADIS16467
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
ADIS16467
TOP VIEW
(Not to Scale)
PIN 14
13 11
9
7
8
5
6
3
4
1
2
14 12 10
NOTES
1. THIS REPRESENTS THE PIN ASSIGNMENTS WHEN
LOOKING DOWNAT THE CONNECTOR. SEE FIGURE 7.
2. MATING CONNECTOR:
SAMTEC CLM-107-02 SERIES OR EQUIVALENT.
3. DNC = DO NOT CONNECT.
Figure 6. Pin Assignments, Bottom View
Figure 7. Pin Assignments, Package Level View
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1
DR
Output
Data Ready Indicator.
2
3
4
5
SYNC
SCLK
DOUT
DIN
Input/output
Input
Output
Input
Input
External Sync Input/Output, per MSC_CTRL. See Table 105.
SPI Serial Clock.
SPI Data Output. This pin clocks the output on the SCLK falling edge.
SPI Data Input. This pin clocks the input on the SCLK rising edge.
SPI Chip Select.
6
CS
7
8
DNC
RST
Not applicable
Input
Do Not Connect. Do not connect to this pin.
Reset.
9
DNC
DNC
VDD
DNC
GND
DNC
Not applicable
Not applicable
Supply
Not applicable
Supply
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Power Supply.
Do Not Connect. Do not connect to this pin.
Power Ground.
10
11
12
13
14
Not applicable
Do Not Connect. Do not connect to this pin.
Rev. C | Page 8 of 34
Data Sheet
ADIS16467
TYPICAL PERFORMANCE CHARACTERISTICS
1000
X-AXIS
Y-AXIS
Z-AXIS
X-AXIS
Y-AXIS
Z-AXIS
100
10
1
0.1
0.001
0.001
0.01
0.1
1
10
100
1000 10000 100000
0.01
0.1
1
10
100
1000 10000 100000
INTEGRATION PERIOD (Seconds)
INTEGRATION PERIOD (Seconds)
Figure 8. Gyroscope Allan Deviation, TC = 25°C, ADIS16467-1
Figure 11. Accelerometer Allan Deviation, TC = 25°C
0.4
0.3
1000
X-AXIS
Y-AXIS
Z-AXIS
0.2
100
10
1
0.1
µ + 1σ
0
–0.1
–0.2
–0.3
–0.4
µ
µ – 1σ
0.1
0.001 0.01
0.1
1
10
100
1000 10000 100000
–60
–40
–20
0
20
40
60
80
100
INTEGRATION PERIOD (Seconds)
AMBIENT TEMPERATURE (°C)
Figure 9. Gyroscope Allan Deviation, TC = 25°C, ADIS16467-2
Figure 12. ADIS16467-1 Gyroscope Sensitivity Error vs. Ambient Temperature
0.4
0.3
0.2
0.1
1000
X-AXIS
Y-AXIS
Z-AXIS
100
10
1
µ + 1σ
0
–0.1
µ
–0.2
µ – 1σ
–0.3
–0.4
–60
0.1
0.001
–40
–20
0
20
40
60
80
100
0.01
0.1
1
10
100
1000 10000 100000
AMBIENT TEMPERATURE (°C)
INTEGRATION PERIOD (Seconds)
Figure 13. ADIS16467-2 Gyroscope Sensitivity Error vs. Ambient Temperature
Figure 10. Gyroscope Allan Deviation, TC = 25°C, ADIS16467-3
Rev. C | Page 9 of 34
ADIS16467
Data Sheet
0.4
0.5
0.4
0.3
0.3
0.2
0.2
µ + 1σ
0.1
0.1
0
0
µ + 1σ
µ – 1σ
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
µ
µ – 1σ
µ
–60
–40
–20
0
20
40
60
80
100
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 17. ADIS16467-3 Gyroscope Bias Error vs. Ambient Temperature
Figure 14. ADIS16467-3 Gyroscope Sensitivity Error vs. Ambient Temperature
0.5
0.4
0.3
0.2
µ + 1σ
0.1
0
–0.1
–0.2
µ
µ – 1σ
–0.3
–0.4
–0.5
0
5
10
15
20
25
30
35
–60
–40
–20
0
20
40
60
80
100
POWER-ON TIME (Minutes)
AMBIENT TEMPERATURE (°C)
Figure 15. ADIS16467-1 Gyroscope Bias Error vs. Ambient Temperature
Figure 18. ADIS16467-3 Gyroscope Bias Error vs. Power-On Time at 25°C.
(Applicable to All ADIS16467 Models)
0.5
0.4
0.3
0.2
µ + 1σ
0.1
0
–0.1
µ
–0.2
µ – 1σ
–0.3
–0.4
–0.5
–60
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE (°C)
Figure 16. ADIS16467-2 Gyroscope Bias Error vs. Ambient Temperature
Rev. C | Page 10 of 34
Data Sheet
ADIS16467
THEORY OF OPERATION
External Clock Options
INTRODUCTION
The ADIS16467 provides three different modes of operation
that support the device using an external clock to control the
internal processing rate (fSM in Figure 20 and Figure 21)
through the SYNC pin. Register MSC_CTRL (see Table 105)
provides the configuration options for these external clock
modes in Bits[4:2].
When using the factory default configuration for all user
configurable control registers, the ADIS16467 initializes and
automatically starts a continuous process of sampling, processing,
and loading calibrated sensor data into the output registers at a
rate of 2000 SPS.
INERTIAL SENSOR SIGNAL CHAIN
Inertial Sensor Calibration
Figure 19 shows the basic signal chain for the inertial sensors in the
ADIS16467. This signal chain produces an update rate of 2000
SPS in the output data registers when it operates in internal clock
mode (default, see Register MSC_CTRL, Bits[4:2] in Table 105).
The inertial sensor calibration function for the gyroscopes and the
accelerometers has two components: factory calibration and
user calibration (see Figure 22).
FROM
TO
BARTLETT
WINDOW
FIR FILTER
FACTORY
CALIBRATION
USER
CALIBRATION
AVERAGING
DECIMATING
FILTER
BARTLETT
OUTPUT
DATA
REGISTERS
AVERAGING
DECIMATING
FILTER
MEMS
SENSORS
WINDOW
FIR
CALIBRATION
FILTER
Figure 22. Inertial Sensor Calibration Processing
Figure 19. Signal Processing Diagram, Inertial Sensors
The factory calibration of the gyroscope applies the following
correction formulas to the data of each gyroscope:
Gyroscope Data Sampling
The three gyroscopes produce angular rate measurements around
three orthogonal axes (x, y, and z). Figure 20 shows the data
sampling plan for each gyroscope when the ADIS16467 operates in
internal clock mode (default, see Register MSC_CTRL, Bits[4:2] in
Table 105). Each gyroscope has an analog-to-digital converter
(ADC) and sample clock (fSG) that drives data sampling at a rate
of 4100 Hz ( 5ꢀ). The internal processor reads and processes
this data from each gyroscope at a rate of 2000 Hz (fSM).
bX
ω
m11 m12
m
ω
XC
13
X
ωYC m21 m22 m23
ωY bY
ωZC
m31 m32 m33
ωZ
bZ
l
l12
l
a
11
13
XC
l21 l22 l23 aYC
l31 l32 l33
aZC
TO
INTERNAL
BARTLETT
WINDOW
MEMS
GYROSCOPE
where:
DATA
ADC
REGISTER
FIR FILTER
ωXC, ωYC, and ωZC are the gyroscope outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
fSG = 4100Hz
fSM = 2000Hz
Figure 20. Gyroscope Data Sampling
ωX, ωY, and ωZ are the gyroscope outputs (precalibration).
bX, bY, and bZ provide bias correction.
l11, l12, l13, l21, l22, l23, l31, l32, and l33 provide linear g correction
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
Accelerometer Data Sampling
The three accelerometers produce linear acceleration measurements
along the same orthogonal axes (x, y, and z) as the gyroscopes.
Figure 21 shows the data sampling plan for each accelerometer
when the ADIS16467 operates in internal clock mode (default,
see Register MSC_CTRL, Bits[4:2] in Table 105).
All correction factors in this relationship come from direct
observation of the response of each gyroscope at multiple
temperatures over the calibration temperature range (−40°C ≤
TC ≤ +85°C). These correction factors are stored in the flash
memory bank, but they are not available for observation or
configuration. Register MSC_CTRL, Bit 7 (see Table 105) provides
the only user configuration option for the factory calibration of
the gyroscopes: an on/off control for the linear g compensation.
See Figure 45 for more details on the user calibration options
available for the gyroscopes.
TO
2
1
2
MEMS
ACCELEROMETER
BARTLETT
WINDOW
a(n)
ADC
n = 1
÷2
FIR FILTER
2 × fSM = 4000Hz
Figure 21. Accelerometer Data Sampling
Rev. C | Page 11 of 34
ADIS16467
Data Sheet
The factory calibration of the accelerometer applies the following
correction formulas to the data of each accelerometer:
Bartlett Window FIR Filter
The Bartlett window finite impulse response (FIR) filter (see
Figure 23) contains two averaging filter stages, in a cascade
configuration. The FILT_CTRL register (see Table 101) provides
the configuration controls for this filter.
bX
a
m11 m12
m
a
XC
13
X
aYC m21 m22 m23
aY bY
aZC
m31 m32 m33
aZ
bZ
2
XC
N
N
TO
FROM
MEMS
SENSOR
1
N
1
N
ω(n)
ω(n)
FACTORY
CALIBRATION
0
p12
p
ω
13
n = 1
n = 1
p21
0
p23 ωY2C
2
Figure 23. Bartlett Window FIR Filter Signal Path
p31 p32
0
ωZC
Averaging/Decimating Filter
where:
The second digital filter averages multiple samples together to
produce each register update. In this type of filter structure, the
number of samples in the average is equal to the reduction in the
update rate for the output data registers. The DEC_RATE register
(see Table 109) provides the configuration controls for this filter.
aXC, aYC, and aZC are the accelerometer outputs (post calibration).
m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and
alignment correction.
aX, aY, and aZ are the accelerometer outputs (precalibration).
bX, bY, and bZ provide bias correction.
p12, p13, p21, p23, p31 and p32 provide a point of percussion
alignment correction (see Figure 48).
FROM
USER
N
1
N
TO OUTPUT
REGISTERS
ω(n)
Σ
n = 1
CALIBRATION
÷N
ω2XC, ω2YC, and ω2ZC are the square of the gyroscope outputs
(post calibration).
Figure 24. Averaging/Decimating Filter Diagram
All of the correction factors in this relationship come from direct
observation of the response of each accelerometer at multiple
temperatures, over the calibration temperature range (−40°C ≤
TC ≤ +85°C). These correction factors are stored in the flash
memory bank, but they are not available for observation or
configuration. Register MSC_CTRL, Bit 6 (see Table 105) provides
the only user configuration option for the factory calibration of
the accelerometers: an on/off control for the point of percussion,
alignment function. See Figure 46 for more details on the user
calibration options available for the accelerometers.
REGISTER STRUCTURE
All communication between the ADIS16467 and an external
processor involves either reading the contents of an output register
or writing configuration or command information to a control
register. The output data registers include the latest sensor data,
error flags, and identification information. The control registers
include sample rate, filtering, calibration, and diagnostic options.
Each user accessible register has two bytes (upper and lower),
each of which has a unique address. See Table 8 for a detailed
list of all user registers and the corresponding addresses.
TRIAXIAL
SENSOR
OUTPUT
REGISTERS
GYROSCOPE
SIGNAL
PROCESSING
TRIAXIAL
ACCELEROMETER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
CONTROLLER
Figure 25. Basic Operation of the ADIS16467
Rev. C | Page 12 of 34
Data Sheet
ADIS16467
SERIAL PERIPHERAL INTERFACE (SPI)
DATA READY (DR)
The SPI provides access to the user registers (see Table 8).
Figure 26 shows the most common connections between the
ADIS16467 and a SPI master device, which is often an embedded
processor that has an SPI-compatible interface. In this example,
the SPI master uses an interrupt service routine to collect data
every time the data ready (DR) signal pulses.
The factory default configuration provides users with a DR signal
on the DR pin (see Table 5) that pulses when the output data
registers update. Connect the DR pin to a pin on the embedded
processor to trigger data collection, on the second edge of this
pulse. Register MSC_CTRL, Bit 0 (see Table 105), controls the
polarity of this signal. In Figure 27, Register MSC_CTRL, Bit 0 = 1,
which means that data collection must start on the rising edges
of the DR pulses.
Additional information on ADIS16467 SPI can be found in the
Applications Information section of this datasheet.
INPUT/OUTPUT LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
DR
+3.3V
INACTIVE
ACTIVE
VDD
Figure 27. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)
SYSTEM
PROCESSOR
SPI MASTER
ADIS16467
SS
SCLK
MOSI
MISO
IRQ
CS
During the start-up and reset recovery processes, the DR signal
may exhibit some transient behavior before data production
begins. Figure 28 shows an example of the DR behavior during
startup, and Figure 29 and Figure 30 provide examples of the
DR behavior during recovery from reset commands.
SCLK
DIN
DOUT
DR
TIME THAT VDD > 3V
VDD
Figure 26. Electrical Connection Diagram
PULSING INDICATES
DATA PRODUCTION
Table 6. Generic SPI Master Pin Mnemonics and Functions
Mnemonic
Function
DR
SS
Slave select
SCLK
MOSI
MISO
IRQ
Serial clock
START-UP TIME
Master output, slave input
Master input, slave output
Interrupt request
Figure 28. Data Ready Response During Startup
SOFTWARE RESET COMMAND
GLOB_CMD[7] = 1
Embedded processors typically use control registers to configure
serial ports for communicating with SPI slave devices, such as
the ADIS16467. Table 7 provides a list of settings that describe
the SPI protocol of the ADIS16467. The initialization routine
of the master processor typically establishes these settings using
firmware commands to write them into the control registers.
DR PULSING
RESUMES
DR
RESET RECOVERY TIME
Figure 29. Data Ready Response During Reset
(Register GLOB_CMD, Bit 7 = 1) Recovery
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
RST PIN
RELEASED
Master
ADIS16467 operates as slave
SCLK ≤ 2 MHz1
SPI Mode 3
MSB First Mode
16-Bit Mode
Maximum serial clock rate
RST
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence, see Figure 31 for coding
Shift register and data length
DR PULSING
RESUMES
DR
1 A burst mode read requires this value to be ≤1 MHz (see Table 2 for more
information).
RESET RECOVERY TIME
RST
Figure 30. Data Ready Response During Reset (
= 0) Recovery
Rev. C | Page 13 of 34
ADIS16467
Data Sheet
CS
SCLK
DIN
R/W A6
A5
R/W A6
A5
A4
A3
A2
A1
A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS INA THREE-STATE, HIGH IMPEDANCE MODE, WHICHALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 31. SPI Communication Bit Sequence
1
2
3
11
CS
SCLK
0x6800
DIN
DIAG_STAT
XGYRO_OUT
CHECKSUM
DOUT
Figure 32. Burst Read Sequence
CS
SCLK
DIN
DIN = 0x7200 = 0111 0010 0000 0000
HIGH-Z
HIGH-Z
DOUT
DOUT = 0100 0000 0101 0011 = 0x4053 = 16467 (PROD_ID)
Figure 33. SPI Signal Pattern, Repeating Read of the PROD_ID Register
Burst Read Function
READING SENSOR DATA
The burst read function provides a way to read the same group
of output data registers using a continuous stream of bits at an
SCLK rate of up to 1 MHz. This method does not require a stall
time between each 16-bit segment (see Figure 3). To start this
mode, set DIN = 0x6800 to read register 0x6800, and then read
Reading a single register requires two 16-bit cycles on the SPI:
one to request the contents of a register and another to receive
those contents. The 16-bit command code (see Figure 31) for a
R
read request on the SPI has three parts: the read bit ( /W = 0),
either address of the register, [A6:A0], and eight don’t care bits,
[DC7:DC0]. Figure 34 shows an example that includes two register
reads in succession. This example starts with DIN = 0x0C00, to
request the contents of the Z_GYRO_LOW register, and follows
with 0x0E00, to request the contents of the Z_GYRO_OUT
register. The sequence in Figure 34 also shows full duplex mode
of operation, which means that the ADIS16467 can receive
requests on DIN while also transmitting data out on DOUT
within the same 16-bit SPI cycle.
CS
each register in the sequence out of DOUT while keeping
low for the entire 176-bit sequence (see Figure 32). It is critical
CS
to read all 176 bits before the
pin goes high.
The sequence of registers (and checksum value) in the burst
read response depends on which sample clock mode that the
ADIS16467 is operating in (Register MSC_CTRL, Bits[4:2], see
Table 105). In all clock modes, except when operating in scaled
sync mode (Register MSC_CTRL, Bits[4:2] = 010), the burst
read response includes the following registers and value:
DIAG_STAT, X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT,
X_ACCL_OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT,
DATA_CNTR, and the checksum value. In these cases, use the
following formula to verify the checksum value, treating each
byte in the formula as an independent, unsigned, 8-bit number:
NEXT
ADDRESS
DIN
0x0C00
0x0E00
DOUT
Z_GYRO_LOW
Z_GYRO_OUT
Figure 34. SPI Read Example
Figure 33 shows an example of the four SPI signals when reading
the PROD_ID register (see Table 121) in a repeating pattern.
This pattern can be helpful when troubleshooting the SPI
interface setup and communications because the signals are
the same for each 16-bit sequence, except during the first cycle.
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]
Note that the read and write functions using the SPI interface
are always 16-bits long. The only exception is the burst read
function described in the Burst Read Function section.
Rev. C | Page 14 of 34
Data Sheet
ADIS16467
When operating in scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010), the burst read response includes the following
registers and value: DIAG_STAT, X_GYRO_OUT, Y_GYRO_
OUT, Z_GYRO_OUT, X_ACCL_OUT, Y_ACCL_OUT,
Z_ACCL_OUT, TEMP_OUT, TIME_STAMP, and the checksum
value. In this case, use the following formula to verify the
checksum value, treating each byte in the formula as an
independent, unsigned, 8-bit number:
Memory Structure
Figure 36 shows a functional diagram for the memory structure of
the ADIS16467. The flash memory bank contains the operational
code, unit specific calibration coefficients and user configuration
settings. During initialization (power application or reset recover),
this information loads from the flash memory into the static
random access memory (SRAM), which supports all normal
operation, including register access through the SPI port. Writing
to a configuration register using the SPI updates the SRAM
location of the register but does not automatically update the
settings in the flash memory bank. The manual flash memory
update command (Register GLOB_CMD, Bit 3, see Table 113)
provides a convenient method for saving all of these settings to
the flash memory bank at one time. A yes in the Flash Backup
column of Table 8 identifies the registers that have storage
support in the flash memory bank.
Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +
X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +
Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +
Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +
X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +
Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +
Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +
TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +
TIME_STAMP, Bits[15:8] + TIME_STAMP, Bits[7:0]
MANUAL
FLASH
BACKUP
DEVICE CONFIGURATION
Each configuration register contains 16 bits (two bytes). Bits[7:0]
contain the low byte, and Bits[15:8] contain the high byte of each
register. Each byte has a unique address in the user register map
(see Table 8). Updating the contents of a register requires writing
to both bytes in the following sequence: low byte first, high byte
second. There are three parts to coding an SPI command (see
Figure 31) that write a new byte of data to a register: the write bit
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
SPI ACCESS
(NO SPI ACCESS)
START-UP
RESET
Figure 36. SRAM and Flash Memory Diagram
R
( /W = 1), the address of the byte, [A6:A0], and the new data for
that location, [DC7:DC0]. Figure 35 shows a coding example
for writing 0x0004 to the FILT_CTRL register (see Table 101).
In Figure 35, the 0xDC04 command writes 0x04 to Address
0x5C (lower byte) and the 0xDD00 command writes 0x00 to
Address 0x5D (upper byte).
CS
SCLK
DIN
0xDC04
0xDD00
Figure 35. SPI Sequence for Writing 0x0004 to FILT_CTRL
Rev. C | Page 15 of 34
ADIS16467
Data Sheet
USER REGISTER MEMORY MAP
Table 8. User Register Memory Map (N/A Means Not Applicable)
Name
R/W
N/A
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
N/A
R
R
R
R
R
R
R
R
R
R
R
R
Flash Backup
N/A
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
N/A
No
No
No
No
No
No
No
No
No
No
No
No
Address
Default
Register Description
Reserved
DIAG_STAT
0x00, 0x01
0x02, 0x03
0x04, 0x05
0x06, 0x07
0x08, 0x09
0x0A, 0x0B
0x0C, 0x0D
0x0E, 0x0F
0x10, 0x11
0x12, 0x13
0x14, 0x15
0x16, 0x17
0x18, 0x19
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x20, 0x21
0x22, 0x23
0x24, 0x25
0x26, 0x27
0x28, 0x29
0x2A, 0x2B
0x2C, 0x2D
0x2E, 0x2F
0x30, 0x31
0x32, 0x33
0x34, 0x35
0x36, 0x37
0x38, 0x39
0x3A, 0x3B
0x3C to 0x3F
0x40, 0x41
0x42, 0x43
0x44, 0x45
0x46, 0x47
0x48, 0x49
0x4A, 0x4B
0x4C, 0x4D
0x4E, 0x4F
0x50, 0x51
0x52, 0x53
0x54, 0x55
0x56, 0x57
0x58 to 0x5B
0x5C, 0x5D
0x5E, 0x5F
0x60, 0x61
0x62, 0x63
N/A
0x0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
N/A
Reserved
Output, system error flags
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TEMP_OUT
Output, x-axis gyroscope, low word
Output, x-axis gyroscope, high word
Output, y-axis gyroscope, low word
Output, y-axis gyroscope, high word
Output, z-axis gyroscope, low word
Output, z-axis gyroscope, high word
Output, x-axis accelerometer, low word
Output, x-axis accelerometer, high word
Output, y-axis accelerometer, low word
Output, y-axis accelerometer, high word
Output, z-axis accelerometer, low word
Output, z-axis accelerometer, high word
Output, temperature
TIME_STAMP
Reserved
DATA_CNTR
Output, time stamp
Reserved
New data counter
X_DELTANG_LOW
X_DELTANG_OUT
Y_DELTANG_LOW
Y_DELTANG_OUT
Z_DELTANG_LOW
Z_DELTANG_OUT
X_DELTVEL_LOW
X_DELTVEL_OUT
Y_DELTVEL_LOW
Y_DELTVEL_OUT
Z_DELTVEL_LOW
Z_DELTVEL_OUT
Reserved
XG_BIAS_LOW
XG_BIAS_HIGH
YG_BIAS_LOW
YG_BIAS_HIGH
ZG_BIAS_LOW
ZG_BIAS_HIGH
XA_BIAS_LOW
XA_BIAS_HIGH
YA_BIAS_LOW
YA_BIAS_HIGH
ZA_BIAS_LOW
ZA_BIAS_HIGH
Reserved
Output, x-axis delta angle, low word
Output, x-axis delta angle, high word
Output, y-axis delta angle, low word
Output, y-axis delta angle, high word
Output, z-axis delta angle, low word
Output, z-axis delta angle, high word
Output, x-axis delta velocity, low word
Output, x-axis delta velocity, high word
Output, y-axis delta velocity, low word
Output, y-axis delta velocity, high word
Output, z-axis delta velocity, low word
Output, z-axis delta velocity, high word
Reserved
Calibration, offset, gyroscope, x-axis, low word
Calibration, offset, gyroscope, x-axis, high word
Calibration, offset, gyroscope, y-axis, low word
Calibration, offset, gyroscope, y-axis, high word
Calibration, offset, gyroscope, z-axis, low word
Calibration, offset, gyroscope, z-axis, high word
Calibration, offset, accelerometer, x-axis, low word
Calibration, offset, accelerometer, x-axis, high word
Calibration, offset, accelerometer, y-axis, low word
Calibration, offset, accelerometer, y-axis, high word
Calibration, offset, accelerometer, z-axis, low word
Calibration, offset, accelerometer, z-axis, high word
Reserved
R
No
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
R/W
R
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
N/A
Yes
No
FILT_CTRL
RANG_MDL
MSC_CTRL
UP_SCALE
0x0000
N/A1
0x00C1
0x07D0
Control, Bartlett window FIR filter
Measurement range (model specific) identifier
Control, input/output and other miscellaneous options
Control, scale factor for input clock, pulse per second (PPS)
mode
R/W
R/W
Yes
Yes
DEC_RATE
R/W
Yes
0x64, 0x65
0x0000
Control, decimation filter (output data rate)
Rev. C | Page 16 of 34
Data Sheet
ADIS16467
Name
R/W
R/W
W
N/A
R
R
R
R
R
R/W
R/W
R/W
R
Flash Backup
Address
Default
0x070A
N/A
N/A
N/A
N/A
N/A
0x4053
N/A
N/A
Register Description
NULL_CNFG
GLOB_CMD
Reserved
FIRM_REV
FIRM_DM
Yes
No
N/A
No
No
No
No
No
Yes
Yes
Yes
No
No
0x66, 0x67
0x68, 0x69
0x6A to 0x6B
0x6C, 0x6D
0x6E, 0x6F
0x70, 0x71
0x72, 0x73
0x74, 0x75
0x76, 0x77
0x78, 0x79
0x7A, 0x7B
0x7C, 0x7D
0x7E, 0x7E
Control, bias estimation period
Control, global commands
Reserved
Identification, firmware revision
Identification, date code, day and month
Identification, date code, year
Identification, device number
Identification, serial number
User Scratch Register 1
User Scratch Register 2
User Scratch Register 3
Output, flash memory write cycle counter, lower word
Output, flash memory write cycle counter, upper word
FIRM_Y
PROD_ID
SERIAL_NUM
USER_SCR_1
USER_SCR_2
USER_SCR_3
FLSHCNT_LOW
FLSHCNT_HIGH
N/A
N/A
N/A
N/A
R
1 See Table 102 for the default value in this register, which is model specific.
Rev. C | Page 17 of 34
ADIS16467
Data Sheet
USER REGISTER DEFINTIONS
Status/Error Flag Indicators (DIAG_STAT)
Table 9. DIAG_STAT Register Definition
GYROSCOPE DATA
The gyroscopes in the ADIS16467 measure the angular rate of
rotation around three orthogonal axes (x, y, and z). Figure 37
shows the orientation of each gyroscope axis, along with the
direction of rotation that produces a positive response in each
measurement.
Addresses
Default
Access
Flash Backup
0x02, 0x03
0x0000
R
No
Table 10. DIAG_STAT Bit Assignments
Bits Description
[15:8] Reserved.
Z-AXIS
ω
z
7
6
Clock error. A 1 indicates that the internal data sampling
clock (fSM, see Figure 20 and Figure 21) does not
synchronize with the external clock, which only applies
when using scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010, see Table 105. When this error occurs,
adjust the frequency of the clock signal on the SYNC pin
to operate within the appropriate range.
Y-AXIS
X-AXIS
ω
ω
x
y
Memory failure. A 1 indicates a failure in the flash memory
test (Register GLOB_CMD, Bit 4, see Table 113), which
involves a comparison between a cyclic redundancy
check (CRC) calculation of the present flash memory and
a CRC calculation from the same memory locations at
the time of initial programming (during the production
process). If this error occurs, repeat the same test. If this
error persists, replace the ADIS16467.
Figure 37. Gyroscope Axis and Polarity Assignments
Each gyroscope has two output data registers. Figure 38 shows how
these two registers combine to support a 32-bit, twos complement
data format for the x-axis gyroscope measurements. This format
also applies to the y- and z-axes. Additional information on the
resolution of the accelerometers can be found in the Gyroscope
Data Width (Digital Resolution) section.
5
Sensor failure. A 1 indicates failure of at least one sensor,
at the conclusion of the self test (Register GLOB_CMD,
Bit 2, see Table 113). If this error occurs, repeat the same
test. If this error persists, replace the ADIS16467. Motion,
during the execution of this test, can cause a false failure.
X_GYRO_OUT
X_GYRO_LOW
BIT 15
BIT 0 BIT 15
BIT 0
4
3
Standby mode. A 1 indicates that the voltage across
VDD and GND is <2.8 V, which causes data processing to
stop. When VDD ≥ 2.8 V for 250 ms, the ADIS16467
reinitializes and starts producing data again.
X-AXIS GYROSCOPE DATA
Figure 38. Gyroscope Output Data Structure
SPI communication error. A 1 indicates that the total
number of SCLK cycles is not equal to an integer multiple
of 16. When this error occurs, repeat the previous
communication sequence. Persistence in this error may
indicate a weakness in the SPI service that the ADIS16467
is receiving from the system it is supporting.
Gyroscope Measurement Range/Scale Factor
Table 11 provides the measurement range ( ωMAX) and scale
factor (KG) for the gyroscopes in each ADIS16467 model.
Table 11. Gyroscope Measurement Range and Scale Factors
Range, ±±MAX
(°/sec)
Scale Factor, KG
(LSB/°/sec)
2
1
Flash memory update failure. A 1 indicates that the most
recent flash memory update (Register GLOB_CMD, Bit 3,
see Table 113) failed. If this error occurs, ensure that
VDD ≥ 3 V and repeat the update attempt. If this error
persists, replace the ADIS16467.
Model
ADIS16467-1BMLZ
ADIS16467-2BMLZ
ADIS16467-3BMLZ
125
500
2000
160
40
10
Datapath overrun. A 1 indicates that one of the datapaths
experienced an overrun condition. If this error occurs,
initiate a reset using the RST pin (see Table 5, Pin 8) or
Register GLOB_CMD, Bit 7 (see Table 113). See the Serial
Port Operation section for more details on conditions
that may cause this bit to be set to 1.
Gyroscope Data Formatting
Table 12 and Table 13 offer various numerical examples that
demonstrate the format of the rotation rate data in both 16-bit
and 32-bit formats.
Table 12. 16-Bit Gyroscope Data Format Examples
0
Reserved.
Rotation Rate
Decimal Hex.
Binary
The DIAG_STAT register (see Table 9 and Table 10) provides
error flags for monitoring the integrity and operation of the
ADIS16467. Reading this register causes all bits to return to 0.
The error flags in DIAG_STAT are sticky, meaning that, when
the flags raise to 1, the flags remain there until a read request
clears the flags. If an error condition persists, the flag (bit)
automatically returns to an alarm value of 1.
+ωMAX
+2/KG
+1/KG
0°/sec
−1/KG
−2/KG
−ωMAX
+20,000
0x4E20
0100 1110 0010 0000
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1011 0001 1110 0000
+2
+1
0
−1
−2
−20,000
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0xB1E0
Rev. C | Page 18 of 34
Data Sheet
ADIS16467
Table 13. 32-Bit Gyroscope Data Format Examples
Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT)
Rotation Rate (°/sec)
Decimal
Hex.
Table 22. Z_GYRO_LOW Register Definition
+ωMAX
+1,310,720,000 0x4E200000
Addresses
Default
Access
Flash Backup
+2/(KG × 216)
+1/(KG × 216)
0
+2
+1
0
−1
−2
0x00000002
0x00000001
0x0000000
0xFFFFFFFF
0xFFFFFFFE
0x0C, 0x0D
Not applicable
R
No
Table 23. Z_GYRO_LOW Bit Definitions
−1/(KG × 216)
−2/(KG × 216)
−ωMAX
Bits
Description
[15:0]
Z-axis gyroscope data; additional resolution bits
−1,310,720,000 0xB1E00000
Table 24. Z_GYRO_OUT Register Definition
X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT)
Addresses
Default
Access
Flash Backup
Table 14. X_GYRO_LOW Register Definition
0x0E, 0x0F
Not applicable
R
No
Addresses
Default
Access
Flash Backup
Table 25. Z_GYRO_OUT Bit Definitions
0x04, 0x05
Not applicable
R
No
Bits
Description
Table 15. X_GYRO_LOW Bit Definitions
[15:0]
Z-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG)
Bits
Description
[15:0]
X-axis gyroscope data; additional resolution bits
The Z_GYRO_LOW (see Table 22 and Table 23) and Z_GYRO_
OUT (see Table 24 and Table 25) registers contain the gyroscope
data for the z-axis.
Table 16. X_GYRO_OUT Register Definition
Addresses
Default
Access
Flash Backup
Acceleration Data
0x06, 0x07
Not applicable
R
No
The accelerometers in the ADIS16467 measure both dynamic
and static (response to gravity) acceleration along the same three
orthogonal axes that define the axes of rotation for the gyroscopes
(x, y, and z). Figure 39 shows the orientation of each accelerometer
axis, along with the direction of acceleration that produces a
positive response in each measurement.
Table 17. X_GYRO_OUT Bit Definitions
Bits
Description
[15:0]
X-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG)
The X_GYRO_LOW (see Table 14 and Table 15) and X_GYRO_
OUT (see Table 16 and Table 17) registers contain the gyroscope
data for the x-axis.
Z-AXIS
a
z
Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT)
Y-AXIS
X-AXIS
Table 18. Y_GYRO_LOW Register Definition
a
a
x
y
Addresses
Default
Access
Flash Backup
0x08, 0x09
Not applicable
R
No
Table 19. Y_GYRO_LOW Bit Definitions
Bits
Description
[15:0]
Y-axis gyroscope data; additional resolution bits
Figure 39. Accelerometer Axis and Polarity Assignments
Each accelerometer has two output data registers. Figure 40
shows how these two registers combine to support a 32-bit,
twos complement data format for the x-axis accelerometer
measurements. This format also applies to the y- and z-axes.
Additional information on the resolution of the accelerometers
can be found in the Accelerometer Data Width (Digital
Resolution) section.
Table 20. Y_GYRO_OUT Register Definition
Addresses
Default
Access
Flash Backup
0x0A, 0x0B
Not applicable
R
No
Table 21. Y_GYRO_OUT Bit Definitions
Bits
Description
[15:0]
Y-axis gyroscope data; high word; twos complement,
0°/sec = 0x0000, 1 LSB = 1/KG (see Table 11 for KG)
X_ACCL_OUT
X_ACCL_LOW
The Y_GYRO_LOW (see Table 18 and Table 19) and Y_GYRO_
OUT (see Table 20 and Table 21) registers contain the gyroscope
data for the y-axis.
BIT 15
BIT 0 BIT 15
X-AXIS ACCELEROMETER DATA
BIT 0
Figure 40. Accelerometer Output Data Structure
Rev. C | Page 19 of 34
ADIS16467
Data Sheet
Table 33. Y_ACCL_LOW Bit Definitions
Bits Description
Accelerometer Data Formatting
Table 26 and Table 27 show various numerical examples that
demonstrate the format of the linear acceleration data in both
16-bit and 32-bit formats.
[15:0] Y-axis accelerometer data; additional resolution bits
Table 34. Y_ACCL_OUT Register Definition
Addresses Default
Access
Flash Backup
Table 26. 16-Bit Accelerometer Data Format Examples
0x16, 0x17 Not applicable
R
No
Acceleration
Decimal
+32,000
+2
+1
0
−1
−2
−32,000
Hex.
Binary
+40 g
0x7D00 0111 1101 0000 0000
Table 35. Y_ACCL_OUT Bit Definitions
Bits Description
+2.5 mg
+1.25 mg
0 mg
−1.25 mg
−2.5 mg
−40 g
0x0002
0x0001
0x0000
0xFFFF
0xFFFE
0x8300
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1000 0011 0000 0000
[15:0] Y-axis accelerometer data, high word; twos complement,
40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg
The Y_ACCL_LOW (see Table 32 and Table 33) and Y_ACCL_
OUT (see Table 34 and Table 35) registers contain the
accelerometer data for the y-axis.
Table 27. 32-Bit Accelerometer Data Format Examples
Acceleration
Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT)
Decimal
Hex.
+40 g
+2,097,152,000
+2
+1
0
−1
−2
0x7D000000
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x83000000
Table 36. Z_ACCL_LOW Register Definition
+1.25/215 mg
+1.25/216 mg
0
Addresses
Default
Access
Flash Backup
0x18, 0x19
Not applicable
R
No
−1.25/216 mg
−1.25/215 mg
−40 g
Table 37. Z_ACCL_LOW Bit Definitions
Bits Description
−2,097,152,000
[15:0] Z-axis accelerometer data; additional resolution bits
X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT)
Table 38. Z_ACCL_OUT Register Definition
Addresses
Default
Access
Flash Backup
Table 28. X_ACCL_LOW Register Definition
0x1A, 0x1B
Not applicable
R
No
Addresses
Default
Access
Flash Backup
0x10, 0x11
Not applicable
R
No
Table 39. Z_ACCL_OUT Bit Definitions
Bits Description
Table 29. X_ACCL_LOW Bit Definitions
Bits Description
[15:0] Z-axis accelerometer data, high word; twos complement,
40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg
[15:0] X-axis accelerometer data; additional resolution bits
The Z_ACCL_LOW (see Table 36 and Table 37) and Z_ACCL_
OUT (see Table 38 and Table 39) registers contain the
accelerometer data for the z-axis.
Table 30. X_ACCL_OUT Register Definition
Addresses
Default
Access
Flash Backup
0x12, 0x13
Not applicable
R
No
Internal Temperature (TEMP_OUT)
Table 31. X_ACCL_OUT Bit Definitions
Bits Description
Table 40. TEMP_OUT Register Definition
Addresses
Default
Access
Flash Backup
[15:0] X-axis accelerometer data, high word; twos complement,
0x1C, 0x1D
Not applicable
R
No
40 g range; 0 g = 0x0000, 1 LSB = 1.25 mg
Table 41. TEMP_OUT Bit Definitions
The X_ACCL_LOW (see Table 28 and Table 29) and X_ACCL_
OUT (see Table 30 and Table 31) registers contain the
accelerometer data for the x-axis.
Bits
Description
[15:0]
Temperature data; twos complement,
1 LSB = 0.1°C, 0°C = 0x0000
Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT)
The TEMP_OUT register (see Table 40 and Table 41) provides
a coarse measurement of the temperature inside of the ADIS16467.
This data is most useful for monitoring relative changes in the
thermal environment.
Table 32. Y_ACCL_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x14, 0x15
Not applicable
R
No
Rev. C | Page 20 of 34
Data Sheet
ADIS16467
Table 42. TEMP_OUT Data Format Examples
DELTA ANGLES
Temperature (°C)
Decimal Hex.
Binary
In addition to the angular rate of rotation (gyroscope)
measurements around each axis (x, y, and z), the ADIS16467 also
provides delta angle measurements that represent a calculation
of angular displacement between each sample update.
+105
+25
+0.2
+0.1
+0
+0.1
+0.2
−40
+1050
+250
+2
+1
0
−1
−2
−400
0x041A 0000 0100 0001 1010
0x00FA 0000 0000 1111 1010
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0xFE70 1111 1110 0111 0000
Z-AXIS
Δθ
z
Y-AXIS
X-AXIS
Δθ
Δθ
x
Time Stamp (TIME_STAMP)
Table 43. TIME_STAMP Register Definition
y
Addresses
Default
Access
Flash Backup
0x1E, 0x1F
Not applicable
R
No
Figure 41. Delta Angle Axis and Polarity Assignments
Table 44. TIME_STAMP Bit Definitions
The delta angle outputs represent an integration of the gyroscope
measurements and use the following formula for all three axes
(x-axis displayed):
Bits
Description
[15:0]
Time from the last pulse on the SYNC pin; offset binary
format, 1 LSB = 49.02 μs
D 1
1
The TIME_STAMP register (see Table 43 and Table 44) works
in conjunction with scaled sync mode (Register MSC_CTRL,
Bits[4:2] = 010, see Table 105). The 16-bit number in TIME_
STAMP contains the time associated with the last sample in
each data update relative to the most recent edge of the clock
signal in the SYNC pin. For example, when the value in the
UP_SCALE register (see Table 107) represents a scale factor of
20, DEC_RATE = 0, and the external SYNC rate = 100 Hz, the
following time stamp sequence results: 0 LSB, 10 LSB, 21 LSB,
31 LSB, 41 LSB, 51 LSB, 61 LSB, 72 LSB, …, 194 LSB for the 20th
sample, which translates to 0 μs, 490 μs, …, 9510 μs, the time
from the first SYNC edge.
x, nD
x, nDd x, nDd 1
2 fS
d 0
where:
x is the x-axis.
n is the sample time, prior to the decimation filter.
D is the decimation rate (DEC_RATE + 1, see Table 109).
fS is the sample rate.
d is the incremental variable in the summation formula.
ωX is the x-axis rate of rotation (gyroscope).
When using the internal sample clock, fS is equal to a nominal
rate of 2000 SPS. For better precision in this measurement,
measure the internal sample rate (fS) using the data ready signal
on the DR pin (DEC_RATE = 0x0000, see Table 108), divide
each delta angle result (from the delta angle output registers) by
the data ready frequency and multiply it by 2000. Each axis of
the delta angle measurements has two output data registers.
Figure 42 shows how these two registers combine to support a
32-bit, twos complement data format for the x-axis delta angle
measurements. This format also applies to the y- and z-axes.
Data Update Counter (DATA_CNTR)
Table 45. DATA_CNTR Register Definition
Addresses
Default
Access
Flash Backup
0x22, 0x23
Not applicable
R
No
Table 46. DATA_CNTR Bit Definitions
Bits
Description
[15:0]
Data update counter, offset binary format
X_DELTANG_OUT
X_DELTANG_LOW
BIT 0 BIT 15
When the ADIS16467 goes through the power-on sequence or
when it recovers from a reset command, DATA_CNTR (see
Table 45 and Table 46) starts with a value of 0x0000 and
increments every time new data loads into the output registers.
When the DATA_CNTR value reaches 0xFFFF, the next data
update causes it to wrap back around to 0x0000, where it
continues to increment every time new data loads into the
output registers.
BIT 15
BIT 0
X-AXIS DELTA ANGLE DATA
Figure 42. Delta Angle Output Data Structure
Delta Angle Measurement Range
Table 47 shows the measurement range and scale factor for
each ADIS16467 model.
Table 47. Delta Angle Measurement Range and Scale Factor
Model
Measurement Range, ±±ΔMAX (°)
ADIS16467-1BMLZ
ADIS16467-2BMLZ
ADIS16467-3BMLZ
360
720
2160
Rev. C | Page 21 of 34
ADIS16467
Data Sheet
Table 58. Z_DELTANG_OUT Register Definitions
X-Axis Delta Angle (X_DELTANG_LOW and
X_DELTANG_OUT)
Addresses
Default
Access
Flash Backup
0x2E, 0x2F
Not applicable
R
No
Table 48. X_DELTANG_LOW Register Definitions
Addresses
Default
Access
Flash Backup
Table 59. Z_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Z-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX
0x24, 0x25
Not applicable
R
No
Table 49. X_DELTANG_LOW Bit Definitions
)
Bits
Description
The Z_DELTANG_LOW (see Table 56 and Table 57) and
Z_DELTANG_OUT (see Table 58 and Table 59) registers
contain the delta angle data for the z-axis.
[15:0]
X-axis delta angle data; low word
Table 50. X_DELTANG_OUT Register Definitions
Addresses
Default
Access
Flash Backup
Delta Angle Resolution
0x26, 0x27
Not applicable
R
No
Table 60 and Table 61 show various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
Table 51. X_DELTANG_OUT Bit Definitions
Bits Description
[15:0] X-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX
Table 60. 16-Bit Delta Angle Data Format Examples
)
Delta Angle (°)
Decimal Hex.
Binary
The X_DELTANG_LOW (see Table 48 and Table 49) and
X_DELTANG_OUT (see Table 50 and Table 51) registers
contain the delta angle data for the x-axis.
ΔθMAX × (215−1)/215 +32,767
0x7FFF 0111 1111 1110 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
+ΔθMAX/214
+ΔθMAX/215
0
+2
+1
0
Y-Axis Delta Angle (Y_DELTANG_LOW and
Y_DELTANG_OUT)
−ΔθMAX/215
−ΔθMAX/214
−ΔθMAX
−1
−2
−32,768
Table 52. Y_DELTANG_LOW Register Definitions
Addresses
Default
Access
Flash Backup
0x28, 0x29
Not applicable
R
No
Table 61. 32-Bit Delta Angle Data Format Examples
Delta Angle (°)
+ΔθMAX × (231 − 1)/231
+ΔθMAX/230
+ΔθMAX/231
0
−ΔθMAX/231
−ΔθMAX/230
−ΔθMAX
Decimal
Hex.
Table 53. Y_DELTANG_LOW Bit Definitions
+2,147,483,647 0x7FFFFFFF
Bits
Description
+2
+1
0
−1
−2
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
[15:0]
Y-axis delta angle data; low word
Table 54. Y_DELTANG_OUT Register Definitions
Addresses
Default
Access
Flash Backup
0x2A, 0x2B
Not applicable
R
No
−2,147,483,648 0x80000000
Table 55. Y_DELTANG_OUT Bit Definitions
Bits Description
[15:0] Y-axis delta angle data; twos complement, 0° = 0x0000,
1 LSB = ΔθMAX/215 (see Table 47 for ΔθMAX
DELTA VELOCITY
In addition to the linear acceleration measurements along each
axis (x, y, and z), the ADIS16467 also provides delta velocity
measurements that represent a calculation of linear velocity
change between each sample update.
)
The Y_DELTANG_LOW (see Table 52 and Table 53) and
Y_DELTANG_OUT (see Table 54 and Table 55) registers
contain the delta angle data for the y-axis.
Z-AXIS
ΔV
z
Z-Axis Delta Angle (Z_DELTANG_LOW and
Z_DELTANG_OUT)
Y-AXIS
X-AXIS
Table 56. Z_DELTANG_LOW Register Definitions
ΔV
x
ΔV
y
Addresses
Default
Access
Flash Backup
0x2C, 0x2D
Not applicable
R
No
Table 57. Z_DELTANG_LOW Bit Definitions
Bits
Description
Figure 43. Delta Velocity Axis and Polarity Assignments
[15:0]
Z-axis delta angle data; low word
Rev. C | Page 22 of 34
Data Sheet
ADIS16467
The delta velocity outputs represent an integration of the
acceleration measurements and use the following formula for
all three axes (x-axis displayed):
Y-Axis Delta Velocity (Y_DELTVEL_LOW and
Y_DELTVEL_OUT)
Table 66. Y_DELTVEL_LOW Register Definition
D1
1
Addresses
Default
Access
Flash Backup
Vx, nD
a
x, nDd ax, nD d 1
2 fS
0x34, 0x35
Not applicable
R
No
d 0
where:
x is the x-axis.
Table 67. Y_DELTVEL_LOW Bit Definitions
Bits
Description
n is the sample time, prior to the decimation filter.
D is the decimation rate (DEC_RATE + 1, see Table 109).
fS is the sample rate.
[15:0]
Y-axis delta velocity data; additional resolution bits
Table 68. Y_DELTVEL_OUT Register Definition
d is the incremental variable in the summation formula.
aX is the x-axis acceleration.
Addresses
Default
Access
Flash Backup
0x36, 0x37
Not applicable
R
No
When using the internal sample clock, fS is equal to a nominal rate
of 2000 SPS. For better precision in this measurement, measure the
internal sample rate (fS) using the data ready signal on the DR pin
(DEC_RATE = 0x0000, see Table 108), divide each delta angle
result (from the delta angle output registers) by the data ready
frequency and multiply it by 2000. Each axis of the delta velocity
measurements has two output data registers. Figure 44 shows how
these two registers combine to support a 32-bit, twos complement
data format for the delta velocity measurements along the x-axis.
This format also applies to the y- and z-axes.
Table 69. Y_DELTVEL_OUT Bit Definitions
Bits Description
[15:0] Y-axis delta velocity data; twos complement,
400 m/sec range, 0 m/sec = 0x0000;
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
The Y_DELTVEL_LOW (see Table 66 and Table 67) and
Y_DELTVEL_OUT (see Table 68 and Table 69) registers
contain the delta velocity data for the y-axis.
Z-Axis Delta Velocity (Z_DELTVEL_LOW and
Z_DELTVEL_OUT)
X_DELTVEL_OUT
X_DELTVEL_LOW
BIT 0 BIT 15
Table 70. Z_DELTVEL_LOW Register Definition
BIT 15
BIT 0
Addresses
Default
Access
Flash Backup
X-AXIS DELTA VELOCITY DATA
0x38, 0x39
Not applicable
R
No
Figure 44. Delta Velocity Output Data Structure
Table 71. Z_DELTVEL_LOW Bit Definitions
X-Axis Delta Velocity (X_DELTVEL_LOW and
X_DELTVEL_OUT)
Bits
Description
[15:0]
Z-axis delta velocity data; additional resolution bits
Table 62. X_DELTVEL_LOW Register Definition
Addresses
Default
Access
Flash Backup
Table 72. Z_DELTVEL_OUT Register Definition
0x30, 0x31
Not applicable
R
No
Addresses
Default
Access
Flash Backup
0x3A, 0x3B
Not applicable
R
No
Table 63. X_DELTVEL_LOW Bit Definitions
Bits
Description
Table 73. Z_DELTVEL_OUT Bit Definitions
Bits Description
[15:0]
X-axis delta velocity data; additional resolution bits
[15:0] Z-axis delta velocity data; twos complement,
400 m/sec range, 0 m/sec = 0x0000;
Table 64. X_DELTVEL_OUT Register Definition
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
Addresses
Default
Access
Flash Backup
0x32, 0x33
Not applicable
R
No
The Z_DELTVEL_LOW (see Table 70 and Table 71) and
Z_DELTVEL_OUT (see Table 72 and Table 73) registers
contain the delta velocity data for the z-axis.
Table 65. X_DELTVEL_OUT Bit Definitions
Bits
Description
[15:0]
X-axis delta velocity data; twos complement,
400 m/sec range, 0 m/sec = 0x0000;
Delta Velocity Resolution
Table 74 and Table 75 offer various numerical examples that
demonstrate the format of the delta velocity data in both 16-bit
and 32-bit formats.
1 LSB = 400 m/sec ÷ 215 = ~0.01221 m/sec
The X_DELTVEL_LOW (see Table 62 and Table 63) and
X_DELTVEL_OUT (see Table 64 and Table 65) registers
contain the delta velocity data for the x-axis.
Rev. C | Page 23 of 34
ADIS16467
Data Sheet
Table 74. 16-Bit Delta Velocity Data Format Examples
and the data format examples in Table 13 apply to the 32-bit
combination of the XG_BIAS_LOW and XG_BIAS_HIGH
registers. See Figure 45 for an illustration of how these two registers
combine and influence the x-axis gyroscope measurements.
Velocity (m/sec)
+400 × (215 − 1)/215 +32,767
Decimal Hex.
Binary
0x7FFF 0111 1111 1111 1111
0x0002 0000 0000 0000 0010
0x0001 0000 0000 0000 0001
0x0000 0000 0000 0000 0000
0xFFFF 1111 1111 1111 1111
0xFFFE 1111 1111 1111 1110
0x8000 1000 0000 0000 0000
+400/214
+400/215
0
−400/215
−400/214
−400
+2
+1
0
−1
−2
−32,768
FACTORY
X-AXIS
GYRO
CALIBRATION
AND
X_GYRO_OUT X_GYRO_LOW
FILTERING
XG_BIAS_HIGH XG_BIAS_LOW
Figure 45. User Calibration Signal Path, Gyroscopes
Table 75. 32-Bit Delta Velocity Data Format Examples
Calibration, Gyroscope Bias (YG_BIAS_LOW and
YG_BIAS_HIGH)
Velocity (m/sec)
+400 × (231 − 1)/231
+400/230
+400/231
0
Decimal
Hex.
+2,147,483,647
+2
+1
0
0x7FFFFFFF
0x00000002
0x00000001
0x00000000
0xFFFFFFFF
0xFFFFFFFE
0x80000000
Table 80. YG_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x44, 0x45
0x0000
R/W
Yes
−400/231
−400/230
−400
−1
−2
Table 81. YG_BIAS_LOW Bit Definitions
Bits Description
+2,147,483,648
[15:0] Y-axis gyroscope offset correction; lower word
CALIBRATION
Table 82. YG_BIAS_HIGH Register Definition
The signal chain of each inertial sensor (accelerometers and
gyroscopes) includes the application of unique correction
formulas, which are derived from extensive characterization of
bias, sensitivity, alignment, response to linear acceleration
(gyroscopes), and point of percussion (accelerometer location)
over a temperature range of −40°C to +85°C, for each ADIS16467.
These correction formulas are not accessible, but users do have
the opportunity to adjust the bias for each sensor individually
through user accessible registers. These correction factors
follow immediately after the factory derived correction formulas
in the signal chain, which processes at a rate of 2000 Hz when
using the internal sample clock.
Addresses
Default
Access
Flash Backup
0x46, 0x47
0x0000
R/W
Yes
Table 83. YG_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis gyroscope offset correction factor, upper word
The YG_BIAS_LOW (see Table 80 and Table 81) and YG_BIAS_
HIGH (see Table 82 and Table 83) registers combine to allow
users to adjust the bias of the y-axis gyroscopes. The data format
examples in Table 12 also apply to the YG_BIAS_HIGH register,
and the data format examples in Table 13 apply to the 32-bit
combination of the YG_BIAS_LOW and YG_BIAS_HIGH
registers. These registers influence the y-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 45).
Calibration, Gyroscope Bias (XG_BIAS_LOW and
XG_BIAS_HIGH)
Table 76. XG_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
0x40, 0x41
0x0000
R/W
Yes
Calibration, Gyroscope Bias (ZG_BIAS_LOW and
ZG_BIAS_HIGH)
Table 77. XG_BIAS_LOW Bit Definitions
Bits
Description
Table 84. ZG_BIAS_LOW Register Definition
[15:0]
X-axis gyroscope offset correction; lower word
Addresses
Default
Access
Flash Backup
0x48, 0x49
0x0000
R/W
Yes
Table 78. XG_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
Table 85. ZG_BIAS_LOW Bit Definitions
Bits Description
0x42, 0x43
0x0000
R/W
Yes
[15:0] Z-axis gyroscope offset correction; lower word
Table 79. XG_BIAS_HIGH Bit Definitions
Bits Description
Table 86. ZG_BIAS_HIGH Register Definition
[15:0] X-axis gyroscope offset correction factor, upper word
Addresses
Default
Access
Flash Backup
0x4A, 0x4B
0x0000
R/W
Yes
The XG_BIAS_LOW (see Table 76 and Table 77) and XG_BIAS_
HIGH (see Table 78 and Table 79) registers combine to allow
users to adjust the bias of the x-axis gyroscopes. The data format
examples in Table 12 also apply to the XG_BIAS_HIGH register,
Rev. C | Page 24 of 34
Data Sheet
ADIS16467
Table 87. ZG_BIAS_HIGH Bit Definitions
Table 94. YA_BIAS_HIGH Register Definition
Bits
Description
Addresses
Default
Access
Flash Backup
[15:0] Z-axis gyroscope offset correction factor, upper word
0x52, 0x53
0x0000
R/W
Yes
The ZG_BIAS_LOW (see Table 84 and Table 85) and ZG_BIAS_
HIGH (see Table 86 and Table 87) registers combine to allow
users to adjust the bias of the z-axis gyroscopes. The data format
examples in Table 12 also apply to the ZG_BIAS_HIGH register,
and the data format examples in Table 13 apply to the 32-bit
combination of the ZG_BIAS_LOW and ZG_BIAS_HIGH
registers. These registers influence the z-axis gyroscope
measurements in the same manner that the XG_BIAS_LOW
and XG_BIAS_HIGH registers influence the x-axis gyroscope
measurements (see Figure 45).
Table 95. YA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Y-axis accelerometer offset correction, upper word
The YA_BIAS_LOW (see Table 92 and Table 93) and YA_BIAS_
HIGH (see Table 94 and Table 95) registers combine to allow users
to adjust the bias of the y-axis accelerometers. The data format
examples in Table 26 also apply to the YA_BIAS_HIGH register,
and the data format examples in Table 27 apply to the 32-bit
combination of the YA_BIAS_LOW and YA_BIAS_HIGH
registers. These registers influence the y-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW and
XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 46).
Calibration, Accelerometer Bias (XA_BIAS_LOW and
XA_BIAS_HIGH)
Table 88. XA_BIAS_LOW Register Definition
Addresses
Default
Access
Flash Backup
Calibration, Accelerometer Bias (ZA_BIAS_LOW and
ZA_BIAS_HIGH)
0x4C, 0x4D
0x0000
R/W
Yes
Table 89. XA_BIAS_LOW Bit Definitions
Table 96. ZA_BIAS_LOW Register Definition
Bits
Description
Addresses
Default
Access
Flash Backup
[15:0]
X-axis accelerometer offset correction; lower word
0x54, 0x55
0x0000
R/W
Yes
Table 90. XA_BIAS_HIGH Register Definition
Table 97. ZA_BIAS_LOW Bit Definitions
Bits Description
Addresses
Default
Access
Flash Backup
0x4E, 0x4F
0x0000
R/W
Yes
[15:0] Z-axis accelerometer offset correction; lower word
Table 91. XA_BIAS_HIGH Bit Definitions
Bits Description
Table 98. ZA_BIAS_HIGH Register Definition
Addresses
Default
Access
Flash Backup
[15:0] X-axis accelerometer offset correction, upper word
0x56, 0x57
0x0000
R/W
Yes
The XA_BIAS_LOW (see Table 88 and Table 89) and XA_BIAS_
HIGH (see Table 90 and Table 91) registers combine to allow users
to adjust the bias of the x-axis accelerometers. The data format
examples in Table 26 also apply to the XA_BIAS_HIGH register,
and the data format examples in Table 27 apply to the 32-bit
combination of the XA_BIAS_LOW and XA_BIAS_HIGH
registers. See Figure 46 for an illustration of how these two registers
combine and influence the x-axis accelerometer measurements.
Table 99. ZA_BIAS_HIGH Bit Definitions
Bits Description
[15:0] Z-axis accelerometer offset correction, upper word
The ZA_BIAS_LOW (see Table 96 and Table 97) and ZA_BIAS_
HIGH (see Table 98 and Table 99) registers combine to allow
users to adjust the bias of the z-axis accelerometers. The data
format examples in Table 26 also apply to the ZA_BIAS_HIGH
register, and the data format examples in Table 27 apply to the
32-bit combination of the ZA_BIAS_LOW and ZA_BIAS_HIGH
registers. These registers influence the z-axis accelerometer
measurements in the same manner that the XA_BIAS_LOW and
XA_BIAS_HIGH registers influence the x-axis accelerometer
measurements (see Figure 46).
FACTORY
X-AXIS
ACCL
CALIBRATION
AND
X_ACCL_OUT X_ACCL_LOW
FILTERING
XA_BIAS_HIGH XA_BIAS_LOW
Figure 46. User Calibration Signal Path, Accelerometers
Filter Control Register (FILT_CTRL)
Calibration, Accelerometer Bias (YA_BIAS_LOW and
YA_BIAS_HIGH)
Table 100. FILT_CTRL Register Definition
Addresses
Default
Access
Flash Backup
Table 92. YA_BIAS_LOW Register Definition
0x5C, 0x5D
0x0000
R/W
Yes
Addresses
Default
Access
Flash Backup
0x50, 0x51
0x0000
R/W
Yes
Table 101. FILT_CTRL Bit Definitions
Bits
Description
Table 93. YA_BIAS_LOW Bit Definitions
[15:3]
[2:0]
Not used
Bits
Description
Filter Size Variable B, number of taps in each stage; N = 2B
[15:0]
Y-axis accelerometer offset correction; lower word
Rev. C | Page 25 of 34
ADIS16467
Data Sheet
The FILT_CTRL register (see Table 100 and Table 101)
provides user controls for the Bartlett window FIR filter (see
Figure 23), which contains two cascaded averaging filters. For
example, use the following sequence to set Register FILT_CTRL,
Bits[2:0] = 100, which sets each stage to have 16 taps: 0xCC04 and
0xCD00. Figure 47 provides the frequency response for several
settings in the FILT_CTRL register.
Table 105. MSC_CTRL Bit Definitions
Bits Description
[15:8] Not used
7
Linear g compensation for gyroscopes (1 = enabled)
Point of percussion alignment (1 = enabled)
Not used, always set to zero
SYNC function setting
6
5
[4:2]
0
–20
–40
–60
–80
111 = reserved (do not use)
110 = reserved (do not use)
101 = pulse sync mode
100 = reserved (do not use)
011 = output sync mode
010 = scaled sync mode
001 = direct sync mode
000 = internal clock mode (default)
SYNC polarity (input or output)
1 = rising edge triggers sampling
0 = falling edge triggers sampling
DR polarity
–100
1
0
N = 2
–120
N = 4
N = 16
N = 64
–140
0.001
0.01
FREQUENCY (f/fS
0.1
1
1 = active high when data is valid
0 = active low when data is valid
Figure 47. Bartlett Window, FIR Filter Frequency Response
(Phase Delay = N Samples)
Point of Percussion
Register MSC_CTRL, Bit 6 (see Table 105) offers an on/off control
for the point of percussion alignment function, which maps the
accelerometer sensors to the corner of the package shown in
Figure 48. The factory default setting in the MSC_CTRL register
activates this function. To turn this function off while retaining
the rest of the factory default settings in the MSC_CTRL register,
set Register MSC_CTRL, Bit 6 = 0, using the following command
sequence on the DIN pin: 0xE081, then 0xE100.
Range Identifier (RANG_MDL)
Table 102. RANG_MDL Register Definition
Addresses
Default
Access
Flash Backup
0x5E, 0x5F
Not applicable
R
No
Table 103. RANG_MDL Bit Definitions
Bits
Description
[15:3]
[3:2]
Not used
Gyroscope measurement range
00 = 125°/sec (ADIS16467-1BMLZ)
01 = 500°/sec (ADIS16467-2BMLZ)
10 = reserved
11 = 2000°/sec (ADIS16467-3BMLZ)
Reserved, binary value = 11
[1:0]
Miscellaneous Control Register (MSC_CTRL)
Table 104. MSC_CTRL Register Definition
POINT OF PERCUSSION
ALIGNMENT REFERENCE POINT
SEE MSC_CTRL[6]
Addresses
Default
Access
Flash Backup
0x60, 0x61
0x00C1
R/W
Yes
Figure 48. Point of Percussion Reference Point
Linear Acceleration Effect on Gyroscope Bias
Register MSC_CTRL, Bit 7 (see Table 105) provides an on/off
control for the linear g compensation in the signal calibration
routines of the gyroscope. The factory default contents in the
MSC_CTRL register enable this compensation. To turn the
compensation off, set Register MSC_CTRL, Bit 7 = 0, using
the following sequence on the DIN pin: 0xE041, 0xE100.
Rev. C | Page 26 of 34
Data Sheet
ADIS16467
Internal Clock Mode
Output Sync Mode
Register MSC_CTRL, Bits[4:2] (see Table 105), provide five
different configuration options for controlling the clock (fSM; see
Figure 20 and Figure 21), which controls data acquisition and
processing for the inertial sensors. The default setting for Register
MSC_CTRL, Bits[4:2] is 000 (binary), which places the ADIS16467
in internal clock mode. In this mode, an internal clock controls
inertial sensor data acquisition and processing at a nominal rate
of 2000 Hz. In this mode, each accelerometer data update comes
from an average of two data samples (sample rate = 4000 Hz).
When Register MSC_CTRL, Bits[4:2] = 011, the ADIS16467
operates in output sync mode, which is the same as internal
clock mode with one exception: the SYNC pin pulses when
the internal processor collects data from the inertial sensors.
Figure 49 provides an example of this signal.
GYROSCOPE AND
ACCELEROMETER
DATA ACQUISITION
ACCELEROMETER
DATA ACQUISITION
SYNC
Direct Sync Mode
250µs
500µs
When Register MSC_CTRL, Bits[4:2] = 001, the ADIS16467
operates in direct sync mode. The signal on the SYNC pin directly
controls the sample clock. In this mode, the internal processor
collects gyroscope data samples on the rising edge of the clock
signal (SYNC pin) and collects accelerometer data samples on both
rising and falling edges of the clock signal. The internal processor
averages both accelerometer samples (from rising and falling edge
of the clock signal) together to produce a single data sample.
Therefore, when operating the ADIS16467 in this mode, the clock
signal (SYNC pin) must have a duty cycle of 50ꢀ and a frequency
that is within the range of 1900 Hz to 2100 Hz. The ADIS16467 is
capable of operating when the clock frequency (SYNC pin) is less
than 1900 Hz, but with risk of performance degradation, especially
when tracking dynamic inertial conditions (including vibration).
Figure 49. Sync Output Signal, Register MSC_CTRL, Bits[4:2] = 011
Pulse Sync Mode
When operating in pulse sync mode (Register MSC_CTRL,
Bits[4:2] = 101), the internal processor only collects accelerometer
samples on the leading edge of the clock signal, which enables the
use of a narrow pulse width (see Table 2) in the clock signal on
the SYNC pin. Using pulse sync mode also lowers the bandwidth
on the inertial sensors to 370 Hz. When operating in the pulse
sync mode, the ADIS16467 provides the best performance when
the frequency of the clock signal (SYNC pin) is within the range
of 1000 Hz to 2100 Hz. The ADIS16467 is capable of operating
when the clock frequency (SYNC pin) is less than 1000 Hz, but
with risk of performance degradation, especially when tracking
dynamic inertial conditions (including vibration).
Scaled Sync Mode
When Register MSC_CTRL, Bits[4:2] = 010, the ADIS16467
operates in scaled sync mode that supports a frequency range of
1 Hz to 128 Hz for the clock signal on the SYNC pin. This
mode of operation is particularly useful when synchronizing
the data processing with a PPS signal from a global positioning
system (GPS) receiver or with a synchronization signal from a
video processing system. When operating in scaled sync mode,
the frequency of the sample clock is equal to the product of the
external clock scale factor, KECSF (from the UP_SCALE register,
see Table 106 and Table 107), and the frequency of the clock
signal on the SYNC pin.
Decimation Filter (DEC_RATE)
Table 108. DEC_RATE Register Definition
Addresses
Default
Access
Flash Backup
0x64, 0x65
0x0000
R/W
Yes
Table 109. DEC_RATE Bit Definitions
Bits
Description
[15:11]
[10:0]
Don’t care
Decimation rate, binary format, maximum = 1999
The DEC_RATE register (see Table 108 and Table 109) provides
user control for the averaging decimating filter, which averages
and decimates the gyroscope and accelerometer data; it also
extends the time that the delta angle and the delta velocity track
between each update. When the ADIS16467 operates in internal
clock mode (see Register MSC_CTRL, Bits[4:2], in Table 105),
the nominal output data rate is equal to 2000/(DEC_RATE + 1).
For example, set DEC_RATE = 0x0013 to reduce the output
sample rate to 100 SPS (2000 ÷ 20), using the following DIN pin
sequence: 0xE413, then 0xE500.
For example, when using a 1 Hz input signal, set UP_SCALE =
0x07D0 (KECSF = 2000 (decimal)) to establish a sample rate of
2000 SPS for the inertial sensors and the signal processing. Use
the following sequence on the DIN pin to configure UP_SCALE
for this scenario: 0xE2D0, then 0xE307.
Table 106. UP_SCALE Register Definition
Addresses
Default
Access
Flash Backup
0x62, 0x63
0x07D0
R/W
Yes
Table 107. UP_SCALE Bit Definitions
Data Update Rate in External Sync Modes
Bits
Description
When using the input sync option, in scaled sync mode
(Register MSC_CTRL, Bits[4:2] = 010, see Table 105), the
output data rate is equal to
[15:0]
KECSF; binary format
(fSYNC × KECSF)/(DEC_RATE + 1)
Rev. C | Page 27 of 34
ADIS16467
Data Sheet
where:
Table 1 provides the execution time for each GLOB_CMD
command.
f
SYNC is the frequency of the clock signal on the SYNC pin.
K
ESCF is the value from the UP_SCALE register (see Table 107).
Software Reset
When using direct sync mode and pulse sync mode, KESCF = 1.
Use the following DIN sequence to set Register GLOB_CMD,
Bit 7 = 1, which triggers a reset: 0xE880, then 0xE900. This reset
clears all data, and then restarts data sampling and processing.
This function provides a firmware alternative to toggling the
Continuous Bias Estimation (NULL_CNFG)
Table 110. NULL_CNFG Register Definition
Addresses
Default
Access
Flash Backup
RST
pin (see Table 5, Pin 8).
0x66, 0x67
0x070A
R/W
Yes
Flash Memory Test
Table 111. NULL_CNFG Bit Definitions
Bits Description
[15:14] Not used
Use the following DIN sequence to set Register GLOB_CMD,
Bit 4 = 1, which tests the flash memory: 0xE810, then 0xE900.
The command performs a CRC computation on the flash memory
(excluding user register locations) and compares it to the original
CRC value, which comes from the factory configuration process.
If the current CRC value does not match the original CRC
value, Register DIAG_STAT, Bit 6 (see Table 10), rises to 1,
indicating a failing result.
13
12
11
10
9
Z-axis accelerometer bias correction enable (1 = enabled)
Y-axis accelerometer bias correction enable (1 = enabled)
X-axis accelerometer bias correction enable (1 = enabled)
Z-axis gyroscope bias correction enable (1 = enabled)
Y-axis gyroscope bias correction enable (1 = enabled)
X-axis gyroscope bias correction enable (1 = enabled)
Not used
8
Flash Memory Update
[7:4]
[3:0]
Use the following DIN sequence to set Register GLOB_CMD,
Bit 3 = 1, which triggers a backup of all user configurable registers
in the flash memory: 0xE808, then 0xE900. Register DIAG_STAT,
Bit 2 (see Table 10), identifies success (0) or failure (1) in
completing this process.
Time base control (TBC), range: 0 to 12 (default = 10);
tB = 2TBC/2000, time base; tA = 64 × tB, average time
The NULL_CNFG register (see Table 110 and Table 111) provides
the configuration controls for the continuous bias estimator (CBE),
which associates with the bias correction update command in
Register GLOB_CMD, Bit 0 (see Table 113). Register NULL_
CNFG, Bits[3:0], establishes the total average time (tA) for the
bias estimates and Register NULL_CNFG, Bits[13:8], provide the
on/off controls for each sensor. The factory default configuration
for the NULL_CNFG register enables the bias null command
for the gyroscopes, disables the bias null command for the
accelerometers, and sets the average null time to ~32 sec.
Sensor Self Test
Use the following DIN sequence to set Register GLOB_CMD,
Bit 2 = 1, which triggers the self test routine for the inertial sensors:
0xE804, then 0xE900. The self test routine uses the following
steps to validate the integrity of each inertial sensor:
1. Measure the output on each sensor.
2. Activate an internal stimulus on the mechanical elements of
each sensor to move them in a predictable manner and
create an observable response in the sensors.
3. Measure the output response on each sensor.
4. Deactivate the internal stimulus on each sensor.
5. Calculate the difference between the sensor measurements
from Step 1 (stimulus is off) and from Step 3 (stimulus is on).
6. Compare the difference with internal pass and fail criteria.
7. Report the pass and fail result to Register DIAG_STAT, Bit 5
(see Table 10).
Global Commands (GLOB_CMD)
Table 112. GLOB_CMD Register Definition
Addresses
Default
Access
Flash Backup
0x68, 0x69
Not applicable
W
No
Table 113. GLOB_CMD Bit Definitions
Bits
Description
[15:8]
Not used
7
Software reset
[6:5]
4
Not used
Motion during the execution of this test can indicate a false failure.
Flash memory test
Flash memory update
Sensor self test
Factory Calibration Restore
3
2
Use the following DIN sequence to set Register GLOB_CMD,
Bit 1 = 1 to restore the factory default settings for the MSC_
CTRL, DEC_RATE, and FILT_CTRL registers and to clear all
user configurable bias correction settings: 0xE802, then 0xE900.
Executing this command results in writing 0x0000 to the following
registers: XG_BIAS_LOW, XG_BIAS_HIGH, YG_BIAS_LOW,
YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_HIGH,
1
Factory calibration restore
Bias correction update
0
The GLOB_CMD register (see Table 112 and Table 113) provides
trigger bits for several operations. Write a 1 to the appropriate bit
in GLOB_CMD to start a particular function. During the
execution of these commands, data production stops, pulsing stops
on the DR pin, and the SPI interface does not respond to requests.
XA_BIAS_LOW, XA_BIAS_HIGH, YA_BIAS_LOW,
YA_BIAS_HIGH, ZA_BIAS_LOW, and ZA_BIAS_HIGH.
Rev. C | Page 28 of 34
Data Sheet
ADIS16467
Table 121. PROD_ID Bit Definitions
Bias Correction Update
Bits
Description
Use the following DIN pin sequence to set Register GLOB_CMD,
Bit 0 = 1 to trigger a bias correction, using the correction factors
from the CBE (see Table 111): 0xE801, then 0xE900.
[15:0]
Product identification = 0x4053
The PROD_ID register (see Table 120 and Table 121) contains
the numerical portion of the device number (16,467). See Figure 33
for an example of how to use a looping read of this register to
validate the integrity of the communication.
Firmware Revision (FIRM_REV)
Table 114. FIRM_REV Register Definition
Addresses
Default
Access
Flash Backup
Serial Number (SERIAL_NUM)
0x6C, 0x6D
Not applicable
R
No
Table 122. SERIAL_NUM Register Definition
Table 115. FIRM_REV Bit Definitions
Addresses
Default
Access
Flash Backup
Bits
Description
0x74, 0x75
Not applicable
R
No
[15:0]
Firmware revision, binary coded decimal (BCD) format
Table 123. SERIAL_NUM Bit Definitions
Bits Description
[15:0] Lot specific serial number
The FIRM_REV register (see Table 114 and Table 115) provides
the firmware revision for the internal firmware. This register uses a
BCD format, where each nibble represents a digit. For example,
if FIRM_REV = 0x0104, the firmware revision is 1.04.
Scratch Registers (USER_SCR_1 to USER_SCR_3)
Firmware Revision Day and Month (FIRM_DM)
Table 124. USER_SCR_1 Register Definition
Table 116. FIRM_DM Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x76, 0x77
Not applicable
R/W
Yes
0x6E, 0x6F
Not applicable
R
No
Table 125. USER_SCR_1 Bit Definitions
Bits Description
Table 117. FIRM_DM Bit Definitions
Bits
Description
[15:0] User defined
[15:8]
[7:0]
Factory configuration month, BCD format
Factory configuration day, BCD format
Table 126. USER_SCR_2 Register Definition
Addresses
Default
Access
Flash Backup
The FIRM_DM register (see Table 116 and Table 117) contains
the month and day of the factory configuration date. Register
FIRM_DM, Bits[15:8], contain digits that represent the month
of the factory configuration. For example, November is the 11th
month in a year and is represented by Register FIRM_DM,
Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:0], contain the
day of factory configuration. For example, the 27th day of the
month is represented by Register FIRM_DM, Bits[7:0] = 0x27.
0x78, 0x79
Not applicable
R/W
Yes
Table 127. USER_SCR_2 Bit Definitions
Bits Description
[15:0] User defined
Table 128. USER_SCR_3 Register Definition
Addresses
Default
Access
Flash Backup
0x7A, 0x7B
Not applicable
R/W
Yes
Firmware Revision Year (FIRM_Y)
Table 129. USER_SCR_3 Bit Definitions
Bits Description
[15:0] User defined
Table 118. FIRM_Y Register Definition
Addresses
Default
Access
Flash Backup
0x70, 0x71
Not applicable
R
No
The USER_SCR_1 (see Table 124 and Table 125), USER_SCR_2
(see Table 126 and Table 127), and USER_SCR_3 (see Table 128
and Table 129) registers provide three locations for the user to
store information. For nonvolatile storage, use the manual flash
memory update command (Register GLOB_CMD, Bit 3, see
Table 113), after writing information to these registers.
Table 119. FIRM_Y Bit Definitions
Bits
Description
[15:0]
Factory configuration year, BCD format
The FIRM_Y register (see Table 118 and Table 119) contains
the year of the factory configuration date. For example, the
year, 2017, is represented by FIRM_Y = 0x2017.
Flash Memory Endurance Counter (FLSHCNT_LOW and
FLSHCNT_HIGH)
Product Identification (PROD_ID)
Table 130. FLSHCNT_LOW Register Definition
Table 120. PROD_ID Register Definition
Addresses
Default
Access
Flash Backup
Addresses
Default
Access
Flash Backup
0x7C, 0x7D
Not applicable
R
No
0x72, 0x73
0x4053
R
No
Rev. C | Page 29 of 34
ADIS16467
Data Sheet
Table 131. FLSHCNT_LOW Bit Definitions
Bits
Description
600
450
300
[15:0] Flash memory write counter, low word
Table 132. FLSHCNT_HIGH Register Definition
Addresses
Default
Access
Flash Backup
0x7E, 0x7F
Not applicable
R
No
Table 133. FLSHCNT_HIGH Bit Definitions
Bits Description
[15:0] Flash memory write counter, high word
150
0
The FLSHCNT_LOW (see Table 130 and Table 131) and
FLSHCNT_HIGH (see Table 132 and Table 133) registers
combine to provide a 32-bit, binary counter that tracks the
number of flash memory write cycles. In addition to the
number of write cycles, the flash memory has a finite service
lifetime, which depends on the junction temperature. Figure 50
provides guidance for estimating the retention life for the flash
memory at specific junction temperatures. The junction
temperature is approximately 7°C above the case temperature.
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
Figure 50. Flash Memory Retention
Rev. C | Page 30 of 34
Data Sheet
ADIS16467
APPLICATIONS INFORMATION
ASSEMBLY AND HANDLING TIPS
Mounting Tips
BREAKOUT BOARD
The ADIS16IMU4/PCBZ breakout board provides a ribbon
cable interface for simple connection to an embedded processor
development system. Figure 52 shows the electrical schematic,
and Figure 53 shows a top view for this breakout board. J2 mates
directly to the electrical connector on the ADIS16467, and J1 easily
mates to a 1 mm ribbon cable system.
The ADIS16467 package supports installation onto a PCB or
rigid enclosure, using three M2 or 2-56 machine screws, using
a torque that is between 20 inch ounces and 40 inch ounces.
When designing a mechanical interface for the ADIS16467,
avoid placing unnecessary translational stress on the electrical
connector because this can influence the bias repeatability
behaviors of the inertial sensors. When the same PCB also has
the mating connector, the use of passthrough holes for the
mounting screws may be required. Figure 51 shows a detailed
view of the PCB pad design when using one of the connector
variants in the CLM-107-02 family.
J2
J1
1
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DR
SYNC
SCLK
DOUT
DIN
CS
DNC
RST
DNC
DNC
VDD
DNC
GND
DNC
3
4
5
6
7
8
9
10
11
12
13
14
0.2364 [6.0]
0.019685
[0.5000]
(TYP)
0.0240 [0.610]
C1
0805
10µF
C2
0603
1µF
0.054 [1.37]
0.1800
[4.57]
0.0394 [1.00]
Figure 52. ADIS16IMU4/PCBZ Electrical Schematic
0.0394 [1.00]
0.022±
DIA (TYP)
NONPLATED
0.022 DIA THROUGH HOLE (TYP)
THROUGH HOLE 2× NONPLATED THROUGH HOLE
Figure 51. Mating Connector Design Detail
POWER SUPPLY CONSIDERATIONS
The ADIS16467 contains 6 μF of decoupling capacitance across
the VDD and GND pins. When the VDD voltage raises from 0 V
to 3.3 V, the charging current for this capacitor bank imposes the
following current profile (in amperes):
dVDD
dt
dVDD
dt
t
IDD
t
C
6106
where:
IDD(t)is the current demand on the VDD pin during the initial
power supply ramp, with respect to time.
C is the internal capacitance across the VDD and GND pins (6 μF).
VDD(t) is the voltage on the VDD pin, with respect to time.
Figure 53. ADIS16IMU4/PCBZ Top View
For example, if VDD follows a linear ramp from 0 V to 3.3 V, in
66 μs, the charging current is 300 mA for that timeframe. The
ADIS16467 also contains embedded processing functions that
present transient current demands during initialization or reset
recovery operations. During these processes, the peak current
demand reaches 250 mA and occurs at a time that is approximately
40 ms after VDD reaches 3.0 V (or ~40 ms after initiating a
reset sequence).
J1
RST
CS
1
3
5
7
9
2
4
6
8
SCLK
DOUT
DNC
GND
GND
DIN
GND
10 VDD
12 VDD
14 SYNC
16 NC
VDD 11
DR 13
NC 15
Figure 54. ADIS16IMU4/PCBZ J1 Pin Assignments
Rev. C | Page 31 of 34
ADIS16467
Data Sheet
SERIAL PORT OPERATION
Maximum Throughput
DIGITAL RESOLUTION OF GYROSCOPES AND
ACCELEROMETERS
When operating with the maximum output data (DEC_RATE =
0x0000, as described in Table 109), the maximum SCLK rate
(defined in Table 2) and minimum stall time, the SPI port can
support up to 12, 16-bit register reads in between each pulse of
the data ready signal. Attempting to read more than 12 registers
can result in a datapath overrun error in the DIAG_STAT register
(see Table 10). The serial port stall time (tSTALL) to meet these
requirements must be no more than 10% greater than the
minimum specification for tSTALL in Table 2.
Gyroscope Data Width (Digital Resolution)
The decimation filter (DEC_RATE register, see Table 109) and
Bartlett window filter (FILT_CTRL register, see Table 101) have
direct influence over the total number of bits in the output data
registers, which contain relevant information. When using the
factory default settings (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) for these filters, the data width for the gyroscope data
width is 16 bits, which means that application processors can
acquire all relevant information through the X_GYRO_OUT,
Y_GYRO_OUT, and Z_GYRO_OUT registers.
The number of allowable registers reads between each pulse on
the data ready line increases proportionally with the decimation
rate (set by the DEC_RATE register, see Table 109). For example,
when the decimation rate equals 3 (DEC_RATE = 0x0002), the
SPI is able to support up to 36 register reads, assuming maximum
SCLK rate and minimum stall times in the protocol. Decreasing
the SCLK rate and increasing the stall time lowers the total
number of register reads supported by the ADIS16467 before a
datapath overrun error occurs.
The X_GYRO_LOW, Y_GYRO_LOW, and Z_GYRO_
LOW registers capture the bit growth that comes from each
accumulation operation in the decimation and Bartlett window
filters. When using these filters (DEC_RATE ≠ 0x0000 and/or
FILT_CTRL ≠ 0x0000), the bit growth is equal to the square root
of the number of summations in each filter stage. For example,
when DEC_RATE = 0x0007, the decimation filter adds eight (7 +
1 = 8, see Table 109) successful samples together, which causes
the data width to increase by 3 bits (80.5 = 3). When FILT_CTRL =
0x0002, both stages in the Bartlett window filter use four (22 = 4,
see Table 101) summation operations, which increases the data
width by two bits (40.5 = 2). When using both DEC_RATE =
0x0007 and FILT_CTRL = 0x0002, the total bit growth is 7 bits,
which increases the overall data width to 23 bits.
This limitation of reading 12, 16-bit registers does not impact the
ability of the user to access the full precision of the gyroscopes and
accelerometers if the factory default settings of DEC_RATE =
0x0000 and FILT_CTRL = 0x0000 are used. In this case, the
data width for the gyroscope and accelerometer data is 16 bits,
and application processors can acquire all relevant information
through the X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT,
X_ACCEL_OUT, Y_ACCEL_OUT, and Z_ACCEL_OUT
registers. Thirty-two bit reads of the sensor data do not provide
additional precision in this case. See the Gyroscope Data Width
(Digital Resolution) section and the Accelerometer Data Width
(Digital Resolution) section for more information.
Accelerometer Data Width (Digital Resolution)
The decimation filter (DEC_RATE register, see Table 109) and
Bartlett window filter (FILT_CTRL register, see Table 101) have
direct influence over the total number of bits in the output data
registers, which contain relevant information. When using the
factory default settings (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) for these filters, the data width for the accelerometer
data will be 20 bits. The X_ACCL_OUT, Y_ACCL_OUT, and
Z_ACCL_OUT registers contain the most significant 16 bits of this
data, while the remaining (least significant) bits are in the upper 4
bits of the X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW
registers. Because the total noise (0.6 mg rms, see Table 1) in
the accelerometer data (DEC_RATE = 0x0000, FILT_CTRL =
0x0000) is greater than the 16-bit quantization noise (0.25 mg ÷
120.5 = 0.072 mg), application processors can acquire all relevant
information through the X_ACCL_OUT, Y_ACCL_OUT, and
Z_ACCL_OUT registers. This setup enables applications to
preserve optimal performance, while using the burst read (see
Figure 32), which only provides 16-bit data for the accelerometers.
Serial Port SCLK Underrun/Overrun Conditions
The serial port operates in 16-bit segments and it is critical that
the number of SCLK cycles be equal to an integer multiple of 16
CS
when the
pin is low. Failure to meet this condition causes
the serial port controller inside of the ADIS16467 to be unable
to correctly receive and respond to new requests.
CS
If too many SCLK cycles are received before the
deasserted, the user can recover serial port operation by asserting
CS CS
pin is
, providing 17 rising edges on the SCLK line, deasserting
,
and then attempting to correctly read the PROD_ID (or other
read-only) register on the ADIS16467. The user should repeat
these steps up to a maximum of 15 times until the correct data
is read.
The X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW
registers also capture the bit growth that comes from each
accumulation operation in the decimation and Bartlett window
filters. When using these filters (DEC_RATE ≠ 0x0000 and/or
FILT_CTRL ≠ 0x0000), the bit growth is proportional to the
square root of the number of summations in each filter stage.
For example, when DEC_RATE = 0x0001, the decimation filter
CS
If
user must either power cycle or issue a hard reset (using the
RST
is deasserted before enough SCLK cycles are received, the
pin) to regain SPI port access.
Rev. C | Page 32 of 34
Data Sheet
ADIS16467
adds two (1 + 1 = 2, see Table 109) successful samples together,
which causes the data width to increase by 1 bit (20.5 = 1). When
FILT_CTRL = 0x0001, both stages in the Bartlett window filter
use two (21 = 2, see Table 101) summation operations, which
increases the data width by 1 bit (20.5 = 1). When using both
DEC_RATE = 0x0001 and FILT_CTRL = 0x0001, the total bit
growth is 3 bits, which increases the overall data width to 23 bits.
PC-BASED EVALUATION TOOLS
The ADIS16IMU4/PCBZ provides a simple way to connect the
ADIS16467 to the EVAL-ADIS2 evaluation system, which
provides a PC-based method for evaluation of basic function
and performance. For more information, visit the EVAL-
ADIS2 Wiki Guide.
Rev. C | Page 33 of 34
ADIS16467
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
22.47
22.40
22.33
R 2.75
Ø 2.40
22.47
22.40
22.33
18.25 BSC
24.37
24.30
24.23
0.19
TOP VIEW
7.10
REF
14.20 BSC
1.00 BSC
PITCH
1.50°
0.57
END VIEW
9.07
9.00
8.93
Figure 55. 14-Lead Module with Connector Interface [MODULE]
(ML-14-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ML-14-6
ML-14-6
ADIS16467-1BMLZ
ADIS16467-2BMLZ
ADIS16467-3BMLZ
ADIS16IMU4/PCBZ
EVAL-ADIS2Z
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
14-Lead Module with Connector Interface [MODULE]
14-Lead Module with Connector Interface [MODULE]
14-Lead Module with Connector Interface [MODULE]
Breakout Board
ML-14-6
Evaluation System
1 Z = RoHS Compliant Part.
©2017–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15439-2/20(C)
Rev. C | Page 34 of 34
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