ADIS16477-3PCBZ_技术文档

Precision, Miniature MEMs IMU

Data Sheet

ADIS16477

FEATURES

GENERAL DESCRIPTION

Triaxial, digital gyroscope

The ADIS16477 is a precision, miniature MEMS inertial measure-

ment unit (IMU) that includes a triaxial gyroscope and a triaxial

accelerometer. Each inertial sensor in the ADIS16477 combines

with signal conditioning that optimizes dynamic performance.

The factory calibration characterizes each sensor for sensitivity,

bias, alignment, linear acceleration (gyroscope bias), and point

of percussion (accelerometer location). As a result, each sensor

has dynamic compensation formulas that provide accurate

sensor measurements over a broad set of conditions.

±12ꢀ°/sec, ±ꢀ00°/sec, ±2000°/sec range models

2°/hr in-run bias stability (ADIS16477-1)

0.1ꢀ°/√hr angle random walk (ADIS16477-1 and

ADIS16477-2)

±0.1° axis-to-axis misalignment error

Triaxial, digital accelerometer, ±40 g

13 μg in-run bias stability

Triaxial, delta angle and delta velocity outputs

Factory calibrated sensitivity, bias, and axial alignment

Calibration temperature range: −40°C to +8ꢀ°C

SPI compatible data communications

Programmable operation and control

Automatic and manual bias correction controls

Data ready indicator for synchronous data acquisition

External sync modes: direct, pulse, scaled, and output

On demand self test of inertial sensors

On demand self test of flash memory

The ADIS16477 provides a simple, cost effective method for

integrating accurate, multiaxis inertial sensing into industrial

systems, especially when compared with the complexity and

investment associated with discrete designs. All necessary motion

testing and calibration are part of the production process at the

factory, greatly reducing system integration time. Tight orthogonal

alignment simplifies inertial frame alignment in navigation

systems. The serial peripheral interface (SPI) and register

structure provide a simple interface for data collection and

configuration control.

Single-supply operation (VDD): 3.0 V to 3.6 V

2000 g mechanical shock survivability

Operating temperature range: −40°C to +10ꢀ°C

The ADIS16477 is available in a 44-ball, ball grid array (BGA)

package that is approximately 11 mm × 15 mm × 11 mm.

APPLICATIONS

Navigation, stabilization, and instrumentation

Unmanned and autonomous vehicles

Smart agriculture/construction machinery

Factory/industrial automation, robotics

Virtual/augmented reality

Internet of Moving Things

FUNCTIONAL BLOCK DIAGRAM

DR

RST

VDD

POWER

MANAGEMENT

GND

SELF TEST

I/O

OUTPUT

DATA

CS

TRIAXIAL

GYROSCOPE

REGISTERS

SCLK

DIN

CALIBRATION

TRIAXIAL

ACCELEROMETER

SPI

CONTROLLER

AND

FILTERS

USER

CONTROL

REGISTERS

TEMPERATURE

SENSOR

DOUT

CLOCK

ADIS16477

SYNC

Figure 1.

Rev. D

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ADIS16477

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Device Configuration ................................................................ 16

User Register Memory Map.......................................................... 17

User Register Defintions ............................................................... 19

Gyroscope Data .......................................................................... 19

Delta Angles................................................................................ 22

Delta Velocity ............................................................................. 23

Calibration .................................................................................. 25

Applications Information ............................................................. 32

Assembly and Handling Tips ................................................... 32

Power Supply Considerations .................................................. 33

Serial Port Operation................................................................. 33

Digital Resolution of Gyroscopes and Accelerometers ........ 33

Evaluation Tools......................................................................... 34

Tray Drawing.................................................................................. 36

Packaging and Ordering Information......................................... 37

Outline Dimensions................................................................... 37

Ordering Guide .......................................................................... 37

Applications ...................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications .................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings....................................................... 7

Thermal Resistance...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions ............................ 8

Typical Performance Characteristics........................................... 10

Theory of Operation ...................................................................... 12

Introduction................................................................................ 12

Inertial Sensor Signal Chain ..................................................... 12

Register Structure....................................................................... 13

Serial Peripheral Interface (SPI)............................................... 14

Data Ready (DR) ........................................................................ 14

Reading Sensor Data.................................................................. 15

REVISION HISTORY

4/2020—Rev. C to Rev. D

Change to Logic Inputs Parameter, Table 1 ................................. 4

Changes to Endnote 1, Table 3....................................................... 7

Changes to Figure 5 ..........................................................................6

Changes to Figure 11 ..................................................................... 10

Added Figure 12 and Figure 13; Renumbered Sequentially..... 10

Added Figure 14, Figure 15, Figure 16, and Figure 17.............. 11

Changes to Figure 18, Figure 19, and Figure 20 ........................ 12

Changes to Figure 22 and Figure 23............................................ 13

Added Gyroscope Data Width (Digital Resolution) Section... 19

Changes to Gyroscope Measurement Range/Scale Factor Section,

Table 11, Table 12, Table 13, Table 17, Table 21, and Table 25 .... 20

Added Accelerometer Data Width (Digital Resolution)

Section.............................................................................................. 21

Change to Calibration, Accelerometer Bias (XA_BIAS_LOW

and XA_BIAS_HIGH) Section..................................................... 26

Change to Filter Control Register (FILT_CTRL) Section........ 27

Changes to Direct Sync Mode Section and to Pulse Sync Mode

Section.............................................................................................. 28

Changes to Sensor Self Test Section ............................................ 30

5/2019—Rev. B to Rev. C

Changes to Serial Peripheral Interface (SPI) Section ................ 14

Changes to Figure 32 ..................................................................... 15

Changes to Table 10 and Gyroscope Data Section.................... 19

Changes to Acceleration Data Section ........................................ 21

Added Accelerometer Data Formatting Section Header.......... 21

Deleted Accelerometer Resolution Header ................................ 21

Added Serial Port Operation Section, Maximum Throughput

Section, Serial Port SCLK Underrun/Overrun Conditions

Section, and Digital Resolution of Gyroscopes and

Accelerometers Section ................................................................. 33

Moved Gyroscope Data Width (Digital Resolution) Section... 33

Moved Accelerometer Data Width (Digital Resolution) Section. 33

Moved Figure 52 and Figure 53.................................................... 35

Added Tray Drawing Section and Figure 54; Renumbered

Sequentially ..................................................................................... 36

11/2017—Rev. 0 to Rev. A

Changes to Table 1............................................................................3

Changes to Figure 26 ..................................................................... 14

2/2019—Rev. A to Rev. B

Changes to Table 1 ........................................................................... 3

10/2017—Revision 0: Initial Version

Changes to Table 2 ........................................................................... 5

Rev. D | Page 2 of 37

Data Sheet

ADIS16477

SPECIFICATIONS

Case temperature (T_C) = 25°C, VDD = 3.3 V, angular rate = 0°/sec, dynamic range = 2000°/sec 1 g, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

1ꢀ2

Typ

Max

Unit

GYROSCOPES

Dynamic Range

ADIS16477-1

°/sec

ADIS16477-ꢀ

255

°/sec

ADIS16477-3

ꢀ555

°/sec

Sensitivity

ADIS16477-1, 16-bit

ADIS16477-ꢀ, 16-bit

ADIS16477-3, 16-bit

ADIS16477-1, 3ꢀ-bit

ADIS16477-ꢀ, 3ꢀ-bit

ADIS16477-3, 3ꢀ-bit

−45°C ≤ T_C≤ +82°C, 1 σ

Axis to axis, −45°C ≤ T_C≤ +82°C, 1 σ

ADIS16477-1, full scale (FS) = 1ꢀ2°/sec

ADIS16477-ꢀ, FS = 255°/sec

ADIS16477-3, FS = ꢀ555°/sec

165

45

15

15,482,765

ꢀ,6ꢀ1,445

622,365

5.3

5.1

LSB/°/sec

%

Error over Temperature

Repeatability ¹

Misalignment Error

Nonlinearity^ꢀ

%

Degrees

% FS

5.ꢀ

% FS

5.ꢀ2

% FS

Bias

Repeatability¹

In-Run Bias Stability

−45°C ≤ T_C≤ +82°C, 1 σ

ADIS16477-1, 1 σ

5.7

ꢀ

°/sec

°/hr

ADIS16477-ꢀ, 1 σ

ꢀ.2

°/hr

ADIS16477-3, 1 σ

7

°/hr

Angular Random Walk

ADIS16477-1, 1 σ

ADIS16477-ꢀ, 1 σ

ADIS16477-3, 1 σ

5.12

5.3

°/√hr

Error over Temperature

Linear Acceleration Effect

Vibration Rectified Error (VRE)

Output Noise

−45°C ≤ T_C≤ +82°C, 1 σ

Any direction, 1 σ

5.ꢀ

°/sec

5.51

5.5552

5.57

5.58

5.17

5.553

5.557

225

66

°/sec/g

°/sec/g²

°/sec rms

°/sec/√Hz rms

Hz

Random vibration, ꢀ g_rms, 25 Hz to ꢀ kHz

ADIS16477-1, 1 σ, no filtering

ADIS16477-ꢀ, 1 σ, no filtering

ADIS16477-3, 1 σ, no filtering

ADIS16477-1, f = 15 Hz to 45 Hz

ADIS16477-ꢀ, f = 15 Hz to 45 Hz

ADIS16477-3, f = 15 Hz to 45 Hz

Rate Noise Density

3 dB Bandwidth

Sensor Resonant Frequency

ACCELEROMETERS³

Dynamic Range

kHz

Each axis

45

g

Sensitivity

Error over temperature

Repeatability¹

Misalignment Error

Nonlinearity

3ꢀ-bit data format

2ꢀ,4ꢀ8,855

5.1

5.52

5.5ꢀ

5.4

LSB/g

%

Degrees

% FS

−45°C ≤ T_C≤ +82°C, 1 σ

Axis to axis, −45°C ≤ T_C≤ +82°C, 1 σ

Best fit straight line, 15 g

Best fit straight line, ꢀ5 g

Best fit straight line, 45 g

1.2

Bias

Repeatability¹

−45°C ≤ T_C≤ +82°C, 1 σ

6

mg

In-Run Bias Stability

Velocity Random Walk

Error over Temperature

1 σ

13

5.537

3

μg

m/sec/√hr

mg

−45°C ≤ T_C≤ +82°C, 1 σ

Rev. D | Page 3 of 37

ADIS16477

Data Sheet

Parameter

Test Conditions/Comments

No filtering

f = 15 Hz to 45 Hz, no filtering

Min

Typ

ꢀ.3

155

655

2.62

2.ꢀ2

Max

Unit

Output Noise

Noise Density

3 dB Bandwidth

Sensor Resonant Frequency

mg rms

μg/√Hz rms

Hz

kHz

Y-axis and z-axis

X-axis

TEMPERATURE SENSOR

Scale Factor

Output = 5x5555 at 5°C ( 2°C)

5.1

°C/LSB

LOGIC INPUTS⁴

Input Voltage

High, V_IH

Low, V_IL

RST Pulse Width

Input Current

ꢀ.5

1

V

ꢁs

5.8

Logic 1, I_IH

Logic 5, I_IL

All Pins Except RST

RST Pin

V_IH= 3.3 V

V_IL= 5 V

15

ꢁA

mA

pF

5.33

15

Input Capacitance, C_IN

DIGITAL OUTPUTS

Output Voltage

High, V_OH

I_SOURCE= 5.2 mA

I_SINK= ꢀ.5 mA

ꢀ.4

V

Low, V_OL

5.4

FLASH MEMORY

Data Retention⁶

FUNCTIONAL TIMES⁷

Power-On Start-Up Time

Reset Recovery Time⁸

Factory Calibration Restore

Flash Memory Backup

Flash Memory Test Time

Self Test Time⁹

Endurance²

T_J= 82°C

15555

ꢀ5

Cycles

Years

Time until data is available

ꢀ2ꢀ

193

14ꢀ

7ꢀ

3ꢀ

14

ms

SPS

%

GLOB_CMD, Bit 7 = 1 (see Table 113)

GLOB_CMD, Bit 1 = 1 (see Table 113)

GLOB_CMD, Bit 3 = 1 (see Table 113)

GLOB_CMD, Bit 4 = 1 (see Table 113)

GLOB_CMD, Bit ꢀ = 1 (see Table 113)

CONVERSION RATE

Initial Clock Accuracy

Sync Input Clock

POWER SUPPLY, VDD

Power Supply Current¹⁵

ꢀ555

3

1.9

3.5

ꢀ.1

3.6

22

kHz

V

mA

Operating voltage range

Normal mode, VDD = 3.3 V

44

¹Bias repeatability provides an estimate for long-term drift in the bias, as observed during 255 hours of high temperature operating life (HTOL) at 152°C.

^ꢀThis measurement is based on the deviation from a best fit linear model.

³All specifications associated with the accelerometers relate to the full-scale range of 8 g, unless otherwise noted.

⁴The digital input/output signals use a 3.3 V system.

²Endurance is qualified as per JEDEC Standard ꢀꢀ, Method A117, measured at −45°C, +ꢀ2°C, +82°C, and +1ꢀ2°C.

⁶The data retention specification assumes a junction temperature (T_J) of 82°C per JEDEC Standard ꢀꢀ, Method A117. Data retention lifetime decreases with T_J.

⁷These times do not include thermal settling and internal filter response times, which may affect overall accuracy.

8

RST

The

line must be in a low state for at least 15 μs to ensure a proper reset initiation and recovery.

⁹The self test time can extend when using external clock rates lower than ꢀ555 Hz.

¹⁵Power supply current transients can reach 155 mA during initial startup or reset recovery.

Rev. D | Page 4 of 37

Data Sheet

ADIS16477

TIMING SPECIFICATIONS

T_A= 25°C, VDD = 3.3 V, unless otherwise noted.

Table 2.

Normal Mode

Burst Read Mode

Parameter Description

Min Typ Max Min¹Typ Max Unit

f_SCLK

Serial clock

Stall period between data

Read rate

5.1

16

ꢀ4

ꢀ

5.1

N/A

1

MHz

ꢁs

t_STALL

t_READRATE

t_CS

Chip select to SCLK edge

ꢀ55

ns

t_DAV

t_DSU

t_DHD

t_SCLKR, t_SCLKF

t_DR, t_DF

t_SFS

DOUT valid after SCLK edge

DIN setup time before SCLK rising edge

DIN hold time after SCLK rising edge

SCLK rise/fall times

DOUT rise/fall times

CS high after SCLK edge

ꢀ2

ns

ꢀ2

25

ꢀ2

25

2

1ꢀ.2

2

1ꢀ.2 ns

ns

5

2

5

2

t₁

Input sync positive pulse width; pulse sync mode, MSC_CTRL = 151

(binary, see Table 152)

ꢁs

t_STDR

Input sync to data ready valid transition

Direct sync mode, MSC_CTRL = 551 (binary, see Table 152)

Pulse sync mode, MSC_CTRL = 151 (binary, see Table 152)

Data invalid time

ꢀ26

ꢀ5

ꢀ26

ꢀ5

ꢁs

t_NV

t_ꢀ

Input sync period^ꢀ

477

¹N/A means not applicable.

^ꢀThis specification is rounded up from the cycle time that comes from the maximum input clock frequency (ꢀ155 Hz).

Timing Diagrams

CS

t_SCLKR

t_SCLKF

t_CS

t_SFS

1

2

3

4

5

6

15

16

SCLK

DOUT

t_DAV

t_DR

MSB

R/W

DB14

t_DSU

DB13

A5

DB12

DB11

A3

DB10

t_DF

DB2

DB1

LSB

t_DHD

DIN

A6

A4

A2

D2

D1

Figure 2. SPI Timing and Sequence Diagram

READRATE

STALL

Figure 3. Stall Time and Data Rate Timing Diagram

Rev. D | Page 2 of 37

ADIS16477

Data Sheet

t₂

t_STDR

t₁

SYNC

DR

t_NV

Figure 4. Input Clock Timing Diagram, Pulse Sync Mode, Register MSC_CTRL, Bits[4:2] = 101 (Binary)

t₂

t₁

SYNC

DR

t_NV

t_STDR

Figure 5. Input Clock Timing Diagram, Direct Sync Mode, Register MSC_CTRL, Bits[4:2] = 001 (Binary)

Rev. D | Page 6 of 37

Data Sheet

ADIS16477

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 3.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Parameter

Rating

Mechanical Shock Survivability

Any Axis, Unpowered

ꢀ555 g

The ADIS16477 is a multichip module that includes many

active components. The values in Table 4 identify the thermal

response of the hottest component inside of the ADIS16477,

with respect to the overall power dissipation of the module.

This approach enables a simple method for predicting the

temperature of the hottest junction, based on either ambient or

case temperature.

Any Axis, Powered

VDD to GND

ꢀ555 g

−5.3 V to +3.6 V

−5.3 V to VDD + 5.ꢀ V

−45°C to +82°C

−45°C to +152°C

−62°C to +125°C

ꢀ bar

Digital Input Voltage to GND

Digital Output Voltage to GND

Calibration Temperature Range

Operating Temperature Range

Storage Temperature Range¹

Barometric Pressure

For example, when the ambient temperature is 70°C, the

hottest junction temperature (T_J) inside of the ADIS16477 is

76.7°C.

¹Extended exposure to temperatures that are lower than −45°C or higher

than +152°C may adversely affect the accuracy of the factory calibration.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the

operational section of this specification is not implied.

Operation beyond the maximum operating conditions for

extended periods may affect product reliability.

T_J= θ_JA× VDD × I_DD+ 70°C

T_J= 158.2°C/W × 3.3 V × 0.044 A + 70°C

T_J= 93°C

Table 4. Package Characteristics

1

2

Package Type θ_JA

ML-44-1³

128.ꢀ°C/W

θ_JC

Device Weight

156.1°C/W

1.3 g

¹θ_JAis the natural convection junction to ambient thermal resistance

measured in a one cubic foot sealed enclosure.

^ꢀθ_JCis the junction to case thermal resistance.

³Thermal impedance values come from direct observation of the hottest

temperature inside of the ADIS16477, when it is attached to an FR4-58 PCB

that has two metal layers and has a thickness of 5.563 inches.

ESD CAUTION

Rev. D | Page 7 of 37

ADIS16477

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADIS16477

A

B

C

D

E

F

G

H

J

K

1

2

3

4

5

6

7

8

PIN A1

PIN A8

PIN K8

BOTTOM VIEW OF PACKAGE

Figure 7. Pin Assignments, Package Level View

Figure 6. Pin Assignments, Bottom View

Table 5. Pin Function Descriptions

Pin No.

A1

Aꢀ

A3

A4

A2

A6

A7

A8

B3

B4

B2

B6

Cꢀ

C3

C6

C7

D3

D6

Eꢀ

Mnemonic

GND

DNC

GND

VDD

GND

VDD

GND

VDD

GND

RST

Type

Description

Supply

Not applicable

Supply

Input

Power Ground

Do Not Connect

Power Ground

Power Supply

Power Ground

Power Supply

Power Ground

Power Supply

Power Ground

Reset

E3

E6

E7

F1

F3

F6

F8

GND

CS

Supply

Input

Power Ground

SPI, Chip Select

SPI, Data Input

Power Supply

SPI, Data Output

SPI, Serial Clock

Power Ground

Gꢀ

G3

G6

G7

H1

H3

H6

H8

DIN

Input

GND

VDD

DOUT

SCLK

GND

Supply

Output

Input

Supply

Rev. D | Page 8 of 37

Data Sheet

ADIS16477

Pin No.

Jꢀ

J3

J4

J2

J6

J7

K1

K3

K6

K8

Mnemonic

GND

SYNC

VDD

DR

GND

VDD

Type

Description

Supply

Input

Power Ground

Sync (External Clock)

Power Supply

Data Ready

Power Ground

Power Supply

Power Ground

Supply

Output

Supply

GND

Rev. D | Page 9 of 37

ADIS16477

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

X-AXIS

Y-AXIS

Z-AXIS

X-AXIS

Y-AXIS

Z-AXIS

0.001

0.01

0.1

1

10

100

1000 10000 100000

0.001

0.01

0.1

1

10

100

1000 10000 100000

INTEGRATION PERIOD (Seconds)

Figure 11. Accelerometer Allan Deviation, T_C= 25°C

Figure 8. Gyroscope Allan Deviation, T_C= 25°C, ADIS16477-1

0.5

0.4

X-AXIS

Y-AXIS

Z-AXIS

0.3

0.2

0.1

µ + 1σ

0

–0.1

–0.2

–0.3

–0.4

–0.5

µ

µ – 1σ

0.001 0.01

0.1

1

10

100

1000 10000 100000

–60

–40

–20

0

20

40

60

80

100

AMBIENT TEMPERATURE (°C)

INTEGRATION PERIOD (Seconds)

Figure 12. ADIS16477-1 Gyroscope Sensitivity Error vs. Ambient Temperature

Figure 9. Gyroscope Allan Deviation, T_C= 25°C, ADIS16477-2

0.5

0.4

0.3

0.2

X-AXIS

Y-AXIS

Z-AXIS

µ + 1σ

µ – 1σ

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

µ

0.001

0.01

0.1

1

10

100

1000 10000 100000

–60

–40

–20

0

20

40

60

80

100

INTEGRATION PERIOD (Seconds)

AMBIENT TEMPERATURE (°C)

Figure 13. ADIS16477-2 Gyroscope Sensitivity Error vs. Ambient Temperature

Figure 10. Gyroscope Allan Deviation, T_C= 25°C, ADIS16477-3

Rev. D | Page 15 of 37

Data Sheet

ADIS16477

0.5

0.4

0.5

0.4

0.3

µ + 1σ

0.2

0.1

0

µ + 1σ

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

µ

µ – 1σ

µ

µ – 1σ

–60

–40

–20

0

20

40

60

80

100

–60

–40

–20

0

20

40

60

80

100

AMBIENT TEMPERATURE (°C)

Figure 14. ADIS16477-3 Gyroscope Sensitivity Error vs. Ambient Temperature

Figure 16. ADIS16477-2 Gyroscope Bias Error vs. Ambient Temperature

0.5

0.4

0.3

0.2

0.5

0.4

0.3

0.2

µ + 1σ

0.1

0

µ

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

µ – 1σ

–0.2

–0.3

–0.4

–0.5

–60

–40

–20

0

20

40

60

80

100

–60

–40

–20

0

20

40

60

80

100

AMBIENT TEMPERATURE (°C)

Figure 15. ADIS16477-1 Gyroscope Bias Error vs. Ambient Temperature

Figure 17. ADIS16477-3 Gyroscope Bias Error vs. Ambient Temperature

Rev. D | Page 11 of 37

ADIS16477

Data Sheet

THEORY OF OPERATION

External Clock Options

INTRODUCTION

The ADIS16477 provides three different modes of operation

that support the device using an external clock to control the

internal processing rate (f_SMin Figure 19 and Figure 20) through

the SYNC pin. The MSC_CTRL register (see Table 105) provides

the configuration options for these external clock modes in

Bits[4:2].

When using the factory default configuration for all user

configurable control registers, the ADIS16477 initializes itself

and automatically starts a continuous process of sampling,

processing, and loading calibrated sensor data into its output

registers at a rate of 2000 SPS.

INERTIAL SENSOR SIGNAL CHAIN

Inertial Sensor Calibration

Figure 18 provides the basic signal chain for the inertial sensors

in the ADIS16477. This signal chain produces an update rate

of 2000 SPS in the output data registers when it operates in

internal clock mode (default, see Register MSC_CTRL, Bits[4:2]

in Table 105).

The inertial sensor calibration function for the gyroscopes and the

accelerometers has two components: factory calibration and

user calibration (see Figure 21).

FROM

TO

BARTLETT

WINDOW

FIR FILTER

FACTORY

CALIBRATION

USER

CALIBRATION

AVERAGING

DECIMATING

FILTER

BARTLETT

OUTPUT

DATA

REGISTERS

AVERAGING

DECIMATING

FILTER

MEMS

SENSORS

WINDOW

FIR

CALIBRATION

FILTER

Figure 21. Inertial Sensor Calibration Processing

Figure 18. Signal Processing Diagram, Inertial Sensors

The factory calibration of the gyroscope applies the following

correction formulas to the data of each gyroscope:

Gyroscope Data Sampling













The three gyroscopes produce angular rate measurements around

three orthogonal axes (x, y, and z). Figure 19 shows the data

sampling plan for each gyroscope when the ADIS16477 operates in

internal clock mode (default, see Register MSC_CTRL, Bits[4:2]

in Table 105). Each gyroscope has an analog-to-digital

converter (ADC) and sample clock (f_SG) that drives data sampling

at a rate of 4100 Hz ( 5ꢀ). The internal processor reads and

processes this data from each gyroscope at a rate of 2000 Hz (f_SM).





















b_X





ω

m₁₁m₁₂

m

ω

^XC

¹³

^X



ω_YC m₂₁m₂₂m₂₃



ω_Y b_Y

























ω_ZC

m₃₁m₃₂m₃₃

ω_Z

b_Z

























l

l₁₂

l

a

 ¹¹

¹³



^XC

l₂₁l₂₂l₂₃ a_YC

















l₃₁l₃₂l₃₃

a_ZC









where:

TO

INTERNAL

BARTLETT

WINDOW

MEMS

GYROSCOPE

DATA

ADC

ω_XC, ω_YC, and ω_ZCare the gyroscope outputs (post calibration).

m₁₁, m₁₂, m₁₃, m₂₁, m₂₂, m₂₃, m₃₁, m₃₂, and m₃₃provide scale and

alignment correction.

ω_X, ω_Y, and ω_Zare the gyroscope outputs (precalibration).

b_X, b_Y, and b_Zprovide bias correction.

l₁₁, l₁₂, l₁₃, l₂₁, l₂₂, l₂₃, l₃₁, l₃₂, and l₃₃provide linear g correction

a_XC, a_YC, and a_ZCare the accelerometer outputs (post calibration).

REGISTER

FIR FILTER

f_SG= 4100Hz

f_SM= 2000Hz

Figure 19. Gyroscope Data Sampling

Accelerometer Data Sampling

The three accelerometers produce linear acceleration measurements

along the same orthogonal axes (x, y, and z) as the gyroscopes.

Figure 20 shows the data sampling plan for each accelerometer

when the ADIS16477 operates in internal clock mode (default,

see Register MSC_CTRL, Bits[4:2] in Table 105).

All of the correction factors in this relationship come from

direct observation of the response of each gyroscope at multiple

temperatures over the calibration temperature range (−40°C ≤

T_C≤ +85°C). These correction factors are stored in the flash

memory bank, but they are not available for observation or

configuration. Register MSC_CTRL, Bit 7 (see Table 105)

provides the only user configuration option for the factory

calibration of the gyroscopes: an on/off control for the linear g

compensation. See Figure 44 for more details on the user

calibration options available for the gyroscopes.

TO

2

1

2

MEMS

BARTLETT

WINDOW

a(n)

ADC

ACCELEROMETER

n = 1

÷2

FIR FILTER

2 × f_SM= 4000Hz

Figure 20. Accelerometer Data Sampling

Rev. D | Page 1ꢀ of 37

Data Sheet

ADIS16477

The factory calibration of the accelerometer applies the following

correction formulas to the data of each accelerometer:

Bartlett Window FIR Filter

The Bartlett window finite impulse response (FIR) filter (see

Figure 22) contains two averaging filter stages, in a cascade

configuration. The FILT_CTRL register (see Table 101) provides

the configuration controls for this filter.

































b_X





a

m₁₁m₁₂

m

a

^XC

¹³

^X



a_YC m₂₁m₂₂m₂₃



a_Y b_Y

























a_ZC

m₃₁m₃₂m₃₃

a_Z

b_Z











2

^XC







FROM

MEMS

SENSOR

N

TO

1

N

1

N

ω(n)

FACTORY

CALIBRATION













0

p₁₂

p

¹³



n = 1

p₂₁

0

p₂₃ _Y²_C







2









Figure 22. Bartlett Window FIR Filter Signal Path

p₃₁p₃₂

0

_ZC









Averaging/Decimating Filter

where:

The second digital filter averages multiple samples together to

produce each register update. In this type of filter structure, the

number of samples in the average is equal to the reduction in

the update rate for the output data registers. The DEC_RATE

register (see Table 109) provides the configuration controls for

this filter.

a_XC, a_YC, and a_ZCare the accelerometer outputs (post calibration).

m₁₁, m₁₂, m₁₃, m₂₁, m₂₂, m₂₃, m₃₁, m₃₂, and m₃₃provide scale and

alignment correction.

a_X, a_Y, and a_Zare the accelerometer outputs (precalibration).

b_X, b_Y, and b_Zprovide bias correction.

p₁₂, p₁₃, p₂₁, p₂₃, p₃₁and p₃₂provide a point of percussion

alignment correction (see Figure 47).

FROM

USER

N

ω²_XC, ω²_YC, and ω²_ZCare the square of the gyroscope outputs

(post calibration).

1

N

TO OUTPUT

REGISTERS

ω(n)

Σ

n = 1

CALIBRATION

÷N

All of the correction factors in this relationship come from

direct observation of the response of each accelerometer at

multiple temperatures, over the calibration temperature range

(−40°C ≤ T_C≤ +85°C). These correction factors are stored

in the flash memory bank, but they are not available for

observation or configuration. MSC_CTRL, Bit 6 (see Table 105)

provides the only user configuration option for the factory

calibration of the accelerometers: an on/off control for the point of

percussion, alignment function. See Figure 45 for more details

on the user calibration options available for the accelerometers.

Figure 23. Averaging/Decimating Filter Diagram

REGISTER STRUCTURE

All communication between the ADIS16477 and an external

processor involves either reading the contents of an output

register or writing configuration/command information to a

control register. The output data registers include the latest

sensor data, error flags, and identification information. The

control registers include sample rate, filtering, calibration, and

diagnostic options. Each user accessible register has two bytes

(upper and lower), each of which has its own unique address.

See Table 8 for a detailed list of all user registers, along with

their addresses.

TRIAXIAL

SENSOR

OUTPUT

REGISTERS

GYROSCOPE

SIGNAL

PROCESSING

TRIAXIAL

ACCELLEROMETER

CONTROL

REGISTERS

TEMPERATURE

SENSOR

CONTROLLER

Figure 24. Basic Operation of the ADIS16477

Rev. D | Page 13 of 37

ADIS16477

Data Sheet

SERIAL PERIPHERAL INTERFACE (SPI)

DATA READY (DR)

The SPI provides access to the user registers (see Table 8).

Figure 25 shows the most common connections between the

ADIS16477 and a SPI master device, which is often an

embedded processor that has a SPI-compatible interface. In this

example, the SPI master uses an interrupt service routine to

collect data every time the data ready (DR) signal pulses.

The factory default configuration provides users with a DR

signal on the DR pin (see Table 5), which pulses when the

output data registers are updating. Connect the DR pin to a pin

on the embedded processor, which triggers data collection, on the

second edge of this pulse. The MSC_CTRL register, Bit 0 (see

Table 105), controls the polarity of this signal. In Figure 26,

Register MSC_CTRL, Bit 0 = 1, which means that data

collection must start on the rising edges of the DR pulses.

Additional information on the ADIS16477 SPI can be found in

the Serial Port Operation section of this data sheet.

I/O LINES ARE COMPATIBLE WITH

3.3V LOGIC LEVELS

DR

+3.3V

INACTIVE

ACTIVE

VDD

Figure 26. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)

SYSTEM

PROCESSOR

SPI MASTER

ADIS16477

During the start-up and reset recovery processes, the DR signal

may exhibit some transient behavior before data production

begins. Figure 27 shows an example of the DR behavior during

startup, and Figure 28 and Figure 29 provide examples of the

DR behavior during recovery from reset commands.

SS

SCLK

MOSI

MISO

IRQ

CS

SCLK

DIN

DOUT

DR

TIME THAT VDD > 3V

VDD

Figure 25. Electrical Connection Diagram

PULSING INDICATES

DATA PRODUCTION

Table 6. Generic SPI Master Pin Names and Functions

Mnemonic

Function

DR

SS

Slave select

SCLK

MOSI

MISO

IRQ

Serial clock

START-UP TIME

Master output, slave input

Master input, slave output

Interrupt request

Figure 27. Data Ready Response During Startup

SOFTWARE RESET COMMAND

GLOB_CMD[7] = 1

Embedded processors typically use control registers to

configure their serial ports for communicating with SPI slave

devices such as the ADIS16477. Table 7 provides a list of settings

that describe the SPI protocol of the ADIS16477. The

initialization routine of the master processor typically

establishes these settings using firmware commands to write

them into the control registers.

DR PULSING

RESUMES

DR

RESET RECOVERY TIME

Figure 28. Data Ready Response During Reset

(Register GLOB_CMD, Bit 7 = 1) Recovery

Table 7. Generic Master Processor SPI Settings

RST PIN

RELEASED

Processor Setting Description

Master

ADIS16477 operates as slave

Maximum serial clock rate

CPOL = 1 (polarity), CPHA = 1 (phase)

Bit sequence, see Figure 35 for coding

Shift register and data length

RST

SCLK ≤ ꢀ MHz¹

SPI Mode 3

MSB First Mode

16-Bit Mode

DR PULSING

RESUMES

DR

¹A burst mode read requires this value to be ≤1 MHz (see Table ꢀ for more

information).

RESET RECOVERY TIME

RST

Figure 29. Data Ready Response During Reset (

= 0) Recovery

Rev. D | Page 14 of 37

Data Sheet

ADIS16477

CS

SCLK

DIN

R/W A6

A5

R/W A6

A5

A4

A3

A2

A1

A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

D8 D7 D6 D5 D4 D3 D2 D1 D0

DOUT

D15 D14 D13 D12 D11 D10 D9

D15 D14 D13

NOTES

1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.

2. WHEN CS IS HIGH, DOUT IS INA THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE

FOR OTHER DEVICES.

Figure 30. SPI Communication Bit Sequence

1

2

3

11

CS

SCLK

0x6800

DIN

DIAG_STAT

XGYRO_OUT

CHECKSUM

DOUT

Figure 31. Burst Read Sequence

CS

SCLK

DIN

DIN = 0x7200 = 0111 0010 0000 0000

DOUT HIGH-Z

HIGH-Z

DOUT = 0100 0000 0101 1101 = 0x405D = 16477 (PROD_ID)

Figure 32. SPI Signal Pattern Showing a Read of the PROD_ID Register

Burst Read Function

READING SENSOR DATA

The burst read function provides a way to read a batch of

output data registers, using a continuous stream of bits, at a

rate of up to 1 MHz (SCLK). This method does not require a

stall time between each 16-bit segment (see Figure 3). As shown

in Figure 31, start this mode by setting DIN = 0x6800, and then

read each of the registers in the sequence out of DOUT while

Reading a single register requires two 16-bit cycles on the SPI:

one to request the contents of a register and another to receive

those contents. The 16-bit command code (see Figure 30) for a

R

read request on the SPI has three parts: the read bit ( /W = 0),

either address of the register, [A6:A0], and eight don’t care bits,

[DC7:DC0]. Figure 33 shows an example that includes two

register reads in succession. This example starts with DIN =

0x0C00, to request the contents of the Z_GYRO_LOW

register, and follows with 0x0E00, to request the contents of

the Z_GYRO_OUT register. The sequence in Figure 33 also

shows full duplex mode of operation, which means that the

ADIS16477 can receive requests on DIN while also

transmitting data out on DOUT within the same 16-bit SPI

cycle.

CS

keeping

low for the entire 176-bit sequence.

The sequence of registers (and checksum value) in the burst read

response depends on which sample clock mode that the ADIS16477

is operating in (Register MSC_CTRL, Bits[4:2], see Table 105).

In all clock modes, except when operating in scaled sync mode

(Register MSC_CTRL, Bits[4:2] = 010), the burst read response

includes the following registers and value: DIAG_STAT,

X_GYRO_OUT, Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_

OUT, Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, DATA_

CNTR, and the checksum value. In these cases, use the following

formula to verify the checksum value, treating each byte in the

formula as an independent, unsigned, 8-bit number:

DIN

0x0C00

0x0E00

DOUT

Z_GYRO_LOW

Z_GYRO_OUT

Figure 33. SPI Read Example

Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +

X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +

Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +

Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +

X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +

Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +

Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +

TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +

DATA_CNTR, Bits[15:8] + DATA_CNTR, Bits[7:0]

Figure 32 provides an example of the four SPI signals when

reading the PROD_ID register (see Table 121) in a repeating

pattern. This pattern can be helpful when troubleshooting the

SPI interface setup and communications because the signals are

the same for each 16-bit sequence, except during the first cycle.

Rev. D | Page 12 of 37

ADIS16477

Data Sheet

When operating in scaled sync mode (Register MSC_CTRL,

Bits[4:2] = 010), the burst read response includes the following

registers and value: DIAG_STAT, X_GYRO_OUT,

Memory Structure

Figure 35 provides a functional diagram for the memory

structure of the ADIS16477. The flash memory bank contains

the operational code, unit specific calibration coefficients and

user configuration settings. During initialization (power

application or reset recover), this information loads from the

flash memory into the static random access memory (SRAM),

which supports all normal operation, including register access

through the SPI port. Writing to a configuration register using

the SPI updates the SRAM location of the register but does not

automatically update its settings in the flash memory bank. The

manual flash memory update command (Register GLOB_CMD,

Bit 3, see Table 113) provides a convenient method for saving

all of these settings to the flash memory bank at one time. A yes

in the flash backup column of Table 8 identifies the registers

that have storage support in the flash memory bank.

Y_GYRO_OUT, Z_GYRO_OUT, X_ACCL_OUT,

Y_ACCL_OUT, Z_ACCL_OUT, TEMP_OUT, TIME_STAMP,

and the checksum value. In this case, use the following formula

to verify the checksum value, treating each byte in the formula

as an independent, unsigned, 8-bit number.

Checksum = DIAG_STAT, Bits[15:8] + DIAG_STAT, Bits[7:0] +

X_GYRO_OUT, Bits[15:8] + X_GYRO_OUT, Bits[7:0] +

Y_GYRO_OUT, Bits[15:8] + Y_GYRO_OUT, Bits[7:0] +

Z_GYRO_OUT, Bits[15:8] + Z_GYRO_OUT, Bits[7:0] +

X_ACCL_OUT, Bits[15:8] + X_ACCL_OUT, Bits[7:0] +

Y_ACCL_OUT, Bits[15:8] + Y_ACCL_OUT, Bits[7:0] +

Z_ACCL_OUT, Bits[15:8] + Z_ACCL_OUT, Bits[7:0] +

TEMP_OUT, Bits[15:8] + TEMP_OUT, Bits[7:0] +

TIME_STAMP, Bits[15:8] + TIME_STAMP, Bits[7:0]

MANUAL

FLASH

BACKUP

DEVICE CONFIGURATION

Each configuration register contains 16 bits (two bytes). Bits[7:0]

contain the low byte, and Bits[15:8] contain the high byte of

each register. Each byte has its own unique address in the user

register map (see Table 8). Updating the contents of a register

requires writing to both of its bytes in the following sequence:

low byte first, high byte second. There are three parts to coding

a SPI command (see Figure 30) that write a new byte of data to

NONVOLATILE

FLASH MEMORY

VOLATILE

SRAM

SPI ACCESS

(NO SPI ACCESS)

START-UP

RESET

Figure 35. SRAM and Flash Memory Diagram

R

a register: the write bit ( /W = 1), the address of the byte, [A6:A0],

and the new data for that location, [DC7:DC0]. Figure 34

shows a coding example for writing 0x0004 to the FILT_CTRL

register (see Table 101). In Figure 34, the 0xDC04 command

writes 0x04 to Address 0x5C (lower byte) and the 0xDD00

command writes 0x00 to Address 0x5D (upper byte).

CS

SCLK

DIN

0xDC04

0xDD00

Figure 34. SPI Sequence for Writing 0x0004 to FILT_CTRL

Rev. D | Page 16 of 37

Data Sheet

ADIS16477

USER REGISTER MEMORY MAP

Table 8. User Register Memory Map (N/A Means Not Applicable)

Name

R/W

N/A

R

N/A

R

Flash Backup

N/A

No

N/A

No

Address

Default

Register Description

Reserved

DIAG_STAT

5x55, 5x51

5x5ꢀ, 5x53

5x54, 5x52

5x56, 5x57

5x58, 5x59

5x5A, 5x5B

5x5C, 5x5D

5x5E, 5x5F

5x15, 5x11

5x1ꢀ, 5x13

5x14, 5x12

5x16, 5x17

5x18, 5x19

5x1A, 5x1B

5x1C, 5x1D

5x1E, 5x1F

5xꢀ5, 5xꢀ1

5xꢀꢀ, 5xꢀ3

5xꢀ4, 5xꢀ2

5xꢀ6, 5xꢀ7

5xꢀ8, 5xꢀ9

5xꢀA, 5xꢀB

5xꢀC, 5xꢀD

5xꢀE, 5xꢀF

5x35, 5x31

5x3ꢀ, 5x33

5x34, 5x32

5x36, 5x37

5x38, 5x39

5x3A, 5x3B

5x3C to 5x3F

5x45, 5x41

5x4ꢀ, 5x43

5x44, 5x42

5x46, 5x47

5x48, 5x49

5x4A, 5x4B

5x4C, 5x4D

5x4E, 5x4F

5x25, 5x21

5x2ꢀ, 5x23

5x24, 5x22

5x26, 5x27

5x28 to 5x2B

5x2C, 5x2D

5x2E, 5x2F

5x65, 5x61

5x6ꢀ, 5x63

N/A

5x5555

N/A

5x5555

N/A

Reserved

Output, system error flags

X_GYRO_LOW

X_GYRO_OUT

Y_GYRO_LOW

Y_GYRO_OUT

Z_GYRO_LOW

Z_GYRO_OUT

X_ACCL_LOW

X_ACCL_OUT

Y_ACCL_LOW

Y_ACCL_OUT

Z_ACCL_LOW

Z_ACCL_OUT

TEMP_OUT

Output, x-axis gyroscope, low word

Output, x-axis gyroscope, high word

Output, y-axis gyroscope, low word

Output, y-axis gyroscope, high word

Output, z-axis gyroscope, low word

Output, z-axis gyroscope, high word

Output, x-axis accelerometer, low word

Output, x-axis accelerometer, high word

Output, y-axis accelerometer, low word

Output, y-axis accelerometer, high word

Output, z-axis accelerometer, low word

Output, z-axis accelerometer, high word

Output, temperature

TIME_STAMP

Reserved

DATA_CNTR

Output, time stamp

Reserved

New data counter

X_DELTANG_LOW

X_DELTANG_OUT

Y_DELTANG_LOW

Y_DELTANG_OUT

Z_DELTANG_LOW

Z_DELTANG_OUT

X_DELTVEL_LOW

X_DELTVEL_OUT

Y_DELTVEL_LOW

Y_DELTVEL_OUT

Z_DELTVEL_LOW

Z_DELTVEL_OUT

Reserved

XG_BIAS_LOW

XG_BIAS_HIGH

YG_BIAS_LOW

YG_BIAS_HIGH

ZG_BIAS_LOW

ZG_BIAS_HIGH

XA_BIAS_LOW

XA_BIAS_HIGH

YA_BIAS_LOW

YA_BIAS_HIGH

ZA_BIAS_LOW

ZA_BIAS_HIGH

Reserved

Output, x-axis delta angle, low word

Output, x-axis delta angle, high word

Output, y-axis delta angle, low word

Output, y-axis delta angle, high word

Output, z-axis delta angle, low word

Output, z-axis delta angle, high word

Output, x-axis delta velocity, low word

Output, x-axis delta velocity, high word

Output, y-axis delta velocity, low word

Output, y-axis delta velocity, high word

Output, z-axis delta velocity, low word

Output, z-axis delta velocity, high word

Reserved

Calibration, offset, gyroscope, x-axis, low word

Calibration, offset, gyroscope, x-axis, high word

Calibration, offset, gyroscope, y-axis, low word

Calibration, offset, gyroscope, y-axis, high word

Calibration, offset, gyroscope, z-axis, low word

Calibration, offset, gyroscope, z-axis, high word

Calibration, offset, accelerometer, x-axis, low word

Calibration, offset, accelerometer, x-axis, high word

Calibration, offset, accelerometer, y-axis, low word

Calibration, offset, accelerometer, y-axis, high word

Calibration, offset, accelerometer, z-axis, low word

Calibration, offset, accelerometer, z-axis, high word

Reserved

R

No

N/A

R/W

N/A

R/W

R

N/A

Yes

N/A

Yes

No

FILT_CTRL

RANG_MDL

MSC_CTRL

UP_SCALE

5x5555

N/A¹

5x55C1

5x57D5

Control, Bartlett window FIR filter

Measurement range (model specific) identifier

Control, input/output and other miscellaneous options

Control, scale factor for input clock, pulse per second (PPS)

mode

R/W

Yes

DEC_RATE

R/W

Yes

5x64, 5x62

5x5555

Control, decimation filter (output data rate)

Rev. D | Page 17 of 37

ADIS16477

Data Sheet

Name

R/W

W

N/A

R

R/W

R

Flash Backup

Address

Default

5x575A

N/A

5x452D

N/A

Register Description

NULL_CNFG

GLOB_CMD

Reserved

FIRM_REV

FIRM_DM

Yes

No

N/A

No

Yes

No

5x66, 5x67

5x68, 5x69

5x6A to 5x6B

5x6C, 5x6D

5x6E, 5x6F

5x75, 5x71

5x7ꢀ, 5x73

5x74, 5x72

5x76, 5x77

5x78, 5x79

5x7A, 5x7B

5x7C, 5x7D

5x7E, 5x7E

Control, bias estimation period

Control, global commands

Reserved

Identification, firmware revision

Identification, date code, day and month

Identification, date code, year

Identification, device number

Identification, serial number

User Scratch Register 1

User Scratch Register ꢀ

User Scratch Register 3

Output, flash memory write cycle counter, lower word

Output, flash memory write cycle counter, upper word

FIRM_Y

PROD_ID

SERIAL_NUM

USER_SCR_1

USER_SCR_ꢀ

USER_SCR_3

FLSHCNT_LOW

FLSHCNT_HIGH

N/A

R

¹See Table 15ꢀ for the default value in this register, which is model specific.

Rev. D | Page 18 of 37

Data Sheet

ADIS16477

USER REGISTER DEFINTIONS

clears them. If an error condition persists, the flag (bit)

automatically returns to an alarm value of 1.

Status/Error Flag Indicators (DIAG_STAT)

Table 9. DIAG_STAT Register Definition

GYROSCOPE DATA

Addresses

Default

Access

Flash Backup

The gyroscopes in the ADIS16477 measure the angular rate of

rotation around three orthogonal axes (x, y, and z). Figure 36

shows the orientation of each gyroscope axis, along with the

direction of rotation that produces a positive response in each

of their measurements.

5x5ꢀ, 5x53

5x5555

R

No

Table 10. DIAG_STAT Bit Assignments

Bits Description

[12:8] Reserved.

7

6

Clock error. A 1 indicates that the internal data sampling

clock (f_SM, see Figure 19 and Figure ꢀ5) does not

synchronize with the external clock, which only applies

when using scaled sync mode (Register MSC_CTRL,

Bits[4:ꢀ] = 515, see Table 152). When this error occurs,

adjust the frequency of the clock signal on the SYNC pin

to operate within the appropriate range.

Z

ω

Z

X

Y

Memory failure. A 1 indicates a failure in the flash memory

test (Register GLOB_CMD, Bit 4, see Table 113), which

involves a comparison between a cyclic redundancy

check (CRC) calculation of the present flash memory and

a CRC calculation from the same memory locations at

the time of initial programming (during the production

process). If this error occurs, repeat the same test. If this

error persists, replace the ADIS16477 device.

ω

X

Y

PIN K1

PIN A8

Figure 36. Gyroscope Axis and Polarity Assignments

Each gyroscope has two output data registers. Figure 37 shows

how these two registers combine to support a 32-bit, twos

complement data format for the x-axis gyroscope measurements.

This format also applies to the y- and z-axes.

2

Sensor failure. A 1 indicates failure of at least one sensor,

at the conclusion of the self test (Register GLOB_CMD,

Bit ꢀ, see Table 113). If this error occurs, repeat the same

test. If this error persists, replace the ADIS16477. Motion,

during the execution of this test, can cause a false

failure.

Additional information on the precision and resolution of the

accelerometers can be found in the Digital Resolution of

Gyroscopes and Accelerometers section of this data sheet.

X_GYRO_OUT

X_GYRO_LOW

4

3

Standby mode. A 1 indicates that the voltage across

VDD and GND is <ꢀ.8 V, which causes data processing to

stop. When VDD ≥ ꢀ.8 V for ꢀ25 ms, the ADIS16477

reinitializes itself and starts producing data again.

BIT 15

BIT 0 BIT 15

BIT 0

X-AXIS GYROSCOPE DATA

Figure 37. Gyroscope Output Data Structure

SPI communication error. A 1 indicates that the total

number of SCLK cycles is not equal to an integer multiple

of 16. When this error occurs, repeat the previous

communication sequence. Persistence in this error may

indicate a weakness in the SPI service that the ADIS16477

is receiving from the system it is supporting.

Gyroscope Measurement Range/Scale Factor

Table 11 provides the measurement range ( ω_MAX) and scale

factor (K_G) for the gyroscope in each ADIS16477 model.

Table 11. Gyroscope Measurement Range and Scale Factors

ꢀ

1

Flash memory update failure. A 1 indicates that the most

recent flash memory update (Register GLOB_CMD, Bit 3,

see Table 113) failed. If this error occurs, ensure that

VDD ≥ 3 V and repeat the update attempt. If this error

persists, replace the ADIS16477.

Scale Factor, K_G

(LSB/°/sec)

Model

Range, ±±_MAX(°/sec)

ADIS16477-1

ADIS16477-ꢀ

ADIS16477-3

1ꢀ2

255

ꢀ555

165

45

15

Data path overrun. A 1 indicates that one of the data

paths experienced an overrun condition. If this error

occurs, initiate a reset using the RST pin (see Table 2,

Pin F3) or Register GLOB_CMD, Bit 7 (see Table 113). See

the Serial Port Operation section for more details on

conditions that may cause this bit to be set to 1.

5

Reserved

The DIAG_STAT register (see Table 9 and Table 10) provides

error flags for monitoring the integrity and operation of the

ADIS16477. Reading this register causes all of its bits to return

to 0. The error flags in DIAG_STAT are sticky, meaning that,

when they raise to a 1, they remain there until a read request

Rev. D | Page 19 of 37

ADIS16477

Data Sheet

Table 20. Y_GYRO_OUT Register Definition

Gyroscope Data Formatting

Addresses

Default

Access

Flash Backup

Table 12 and Table 13 offer various numerical examples that

demonstrate the format of the rotation rate data in both 16-bit

and 32-bit formats.

5x5A, 5x5B

Not applicable

R

No

Table 21. Y_GYRO_OUT Bit Definitions

Bits

Description

Table 12. 16-Bit Gyroscope Data Format Examples

[12:5]

Y-axis gyroscope data; high word; twos complement,

5°/sec = 5x5555, 1 LSB = 1/K_G(see Table 11 for K_G)

Rotation Rate

Decimal Hex

Binary

+ω_MAX

+ꢀ/K_G

+1/K_G

5°/sec

−1/K_G

−ꢀ/K_G

−ω_MAX

+ꢀ5,555

+ꢀ

+1

5

−1

−ꢀ

−ꢀ5,555

5x4Eꢀ5

5155 1115 5515 5555

5555 5555 5555 5515

5555 5555 5555 5551

5555 5555 5555 5555

1111 1111 1111 1111

1111 1111 1111 1115

1511 5551 1115 5555

The Y_GYRO_LOW (see Table 18 and Table 19) and Y_GYRO_

OUT (see Table 20 and Table 21) registers contain the gyroscope

data for the y-axis.

5x555ꢀ

5x5551

5x5555

5xFFFF

5xFFFE

5xB1E5

Z-Axis Gyroscope (Z_GYRO_LOW and Z_GYRO_OUT)

Table 22. Z_GYRO_LOW Register Definition

Addresses

Default

Access

Flash Backup

5x5C, 5x5D

Not applicable

R

No

Table 13. 32-Bit Gyroscope Data Format Examples

Rotation Rate (°/sec)

Decimal

Hex

Table 23. Z_GYRO_LOW Bit Definitions

+ω_MAX

+1,315,7ꢀ5,555 5x4Eꢀ55555

Bits

Description

+ꢀ/(K_G× ꢀ¹⁶)

+1/(K_G× ꢀ¹⁶)

5

+ꢀ

+1

5

−1

−ꢀ

5x5555555ꢀ

5x55555551

5x5555555

5xFFFFFFFF

5xFFFFFFFE

[12:5]

Z-axis gyroscope data; additional resolution bits

Table 24. Z_GYRO_OUT Register Definition

−1/(K_G× ꢀ¹⁶)

−ꢀ/(K_G× ꢀ¹⁶)

−ω_MAX

Addresses

Default

Access

Flash Backup

5x5E, 5x5F

Not applicable

R

No

−1,315,7ꢀ5,555 5xB1E55555

Table 25. Z_GYRO_OUT Bit Definitions

X-Axis Gyroscope (X_GYRO_LOW and X_GYRO_OUT)

Bits

Description

[12:5]

Z-axis gyroscope data; high word; twos complement,

5°/sec = 5x5555, 1 LSB = 1/K_G(see Table 11 for K_G)

Table 14. X_GYRO_LOW Register Definition

Addresses

Default

Access

Flash Backup

The Z_GYRO_LOW (see Table 22 and Table 23) and Z_GYRO_

OUT (see Table 24 and Table 25) registers contain the gyroscope

data for the z-axis.

5x54, 5x52

Not applicable

R

No

Table 15. X_GYRO_LOW Bit Definitions

Bits

Description

Acceleration Data

[12:5]

X-axis gyroscope data; additional resolution bits

The accelerometers in the ADIS16477 measure both dynamic

and static (response to gravity) acceleration along the same three

orthogonal axes that define the axes of rotation for the gyroscopes

(x, y, and z). Figure 38 shows the orientation of each

Table 16. X_GYRO_OUT Register Definition

Addresses

Default

Access

Flash Backup

5x56, 5x57

Not applicable

R

No

accelerometer axis, along with the direction of acceleration

that produces a positive response in each of their measurements.

Table 17. X_GYRO_OUT Bit Definitions

Bits

Description

Z

[12:5]

X-axis gyroscope data; high word; twos complement,

5°/sec = 5x5555, 1 LSB = 1/K_G(See Table 11 for K_G)

a

z

The X_GYRO_LOW (see Table 14 and Table 15) and X_GYRO_

OUT (see Table 16 and Table 17) registers contain the gyroscope

data for the x-axis.

PIN K1

PIN A8

Y-Axis Gyroscope (Y_GYRO_LOW and Y_GYRO_OUT)

Table 18. Y_GYRO_LOW Register Definition

X

a

x

a

y

Y

Addresses

Default

Access

Flash Backup

Figure 38. Accelerometer Axis and Polarity Assignments

5x58, 5x59

Not applicable

R

No

Each accelerometer has two output data registers. Figure 39

shows how these two registers combine to support a 32-bit,

twos complement data format for the x-axis accelerometer

measurements. This format also applies to the y- and z-axes.

Table 19. Y_GYRO_LOW Bit Definitions

Bits

Description

[12:5]

Y-axis gyroscope data; additional resolution bits

Rev. D | Page ꢀ5 of 37

Data Sheet

ADIS16477

Additional information on the precision and resolution of the

accelerometers can be found in the Digital Resolution of

Gyroscopes and Accelerometers section of this data sheet.

Y-Axis Accelerometer (Y_ACCL_LOW and Y_ACCL_OUT)

Table 32. Y_ACCL_LOW Register Definition

Addresses

Default

Access

Flash Backup

X_ACCL_OUT

X_ACCL_LOW

5x14, 5x12

Not applicable

R

No

BIT 15

BIT 0 BIT 15

X-AXIS ACCELEROMETER DATA

BIT 0

Table 33. Y_ACCL_LOW Bit Definitions

Bits Description

Figure 39. Accelerometer Output Data Structure

[12:5] Y-axis accelerometer data; additional resolution bits

Accelerometer Data Formatting

Table 34. Y_ACCL_OUT Register Definition

Table 26 and Table 27 offer various numerical examples that

demonstrate the format of the linear acceleration data in both

16-bit and 32-bit formats.

Addresses Default

Access

Flash Backup

5x16, 5x17 Not applicable

R

No

Table 35. Y_ACCL_OUT Bit Definitions

Bits Description

Table 26. 16-Bit Accelerometer Data Format Examples

Acceleration

Decimal

+3ꢀ,555

+ꢀ

Hex

Binary

[12:5] Y-axis accelerometer data, high word; twos complement,

+45 g

5x7D55 5111 1151 5555 5555

45 g range; 5 g = 5x5555, 1 LSB = 1.ꢀ2 mg

+ꢀ.2 mg

+1.ꢀ2 mg

5 mg

5x555ꢀ

5x5551

5x5555

5xFFFF

5xFFFE

5x8355

5555 5555 5555 5515

5555 5555 5555 5551

5555 5555 5555 5555

1111 1111 1111 1111

1111 1111 1111 1115

1555 5511 5555 5555

The Y_ACCL_LOW (see Table 32 and Table 33) and

Y_ACCL_ OUT (see Table 34 and Table 35) registers contain

the accelerometer data for the y-axis.

+1

5

−1

−ꢀ

−1.ꢀ2 mg

−ꢀ.2 mg

−45 g

Z-Axis Accelerometer (Z_ACCL_LOW and Z_ACCL_OUT)

−3ꢀ,555

Table 36. Z_ACCL_LOW Register Definition

Table 27. 32-Bit Accelerometer Data Format Examples

Addresses

Default

Access

Flash Backup

Acceleration

Decimal

Hex

5x18, 5x19

Not applicable

R

No

+45 g

+ꢀ,597,12ꢀ,555

+ꢀ

+1

5

−1

−ꢀ

5x7D555555

5x5555555ꢀ

5x55555551

5x55555555

5xFFFFFFFF

5xFFFFFFFE

5x83555555

+1.ꢀ2/ꢀ¹²mg

+1.ꢀ2/ꢀ¹⁶mg

5

Table 37. Z_ACCL_LOW Bit Definitions

Bits Description

[12:5] Z-axis accelerometer data; additional resolution bits

−1.ꢀ2/ꢀ¹⁶mg

−1.ꢀ2/ꢀ¹²mg

−45 g

Table 38. Z_ACCL_OUT Register Definition

Addresses

Default

Access

Flash Backup

−ꢀ,597,12ꢀ,555

5x1A, 5x1B

Not applicable

R

No

X-Axis Accelerometer (X_ACCL_LOW and X_ACCL_OUT)

Table 39. Z_ACCL_OUT Bit Definitions

Bits Description

Table 28. X_ACCL_LOW Register Definition

Addresses

Default

Access

Flash Backup

[12:5] Z-axis accelerometer data, high word; twos complement,

5x15, 5x11

Not applicable

R

No

45 g range; 5 g = 5x5555, 1 LSB = 1.ꢀ2 mg

The Z_ACCL_LOW (see Table 36 and Table 37) and Z_ACCL_

OUT (see Table 38 and Table 39) registers contain the

accelerometer data for the z-axis.

Table 29. X_ACCL_LOW Bit Definitions

Bits Description

[12:5] X-axis accelerometer data; additional resolution bits

Table 30. X_ACCL_OUT Register Definition

Addresses

Default

Access

Flash Backup

5x1ꢀ, 5x13

Not applicable

R

No

Table 31. X_ACCL_OUT Bit Definitions

Bits Description

[12:5] X-axis accelerometer data, high word; twos complement,

45 g range; 5 g = 5x5555, 1 LSB = 1.ꢀ2 mg

The X_ACCL_LOW (see Table 28 and Table 29) and X_ACCL_

OUT (see Table 30 and Table 31) registers contain the

accelerometer data for the x-axis.

Rev. D | Page ꢀ1 of 37

ADIS16477

Data Sheet

Internal Temperature (TEMP_OUT)

Data Update Counter (DATA_CNTR)

Table 40. TEMP_OUT Register Definition

Table 45. DATA_CNTR Register Definition

Addresses

Default

Access

Flash Backup

Addresses

Default

Access

Flash Backup

5x1C, 5x1D

Not applicable

R

No

5xꢀꢀ, 5xꢀ3

Not applicable

R

No

Table 41. TEMP_OUT Bit Definitions

Table 46. DATA_CNTR Bit Definitions

Bits

Description

Bits

Description

[12:5]

Temperature data; twos complement,

1 LSB = 5.1°C, 5°C = 5x5555

[12:5]

Data update counter, offset binary format

When the ADIS16477 goes through its power-on sequence or

when it recovers from a reset command, DATA_CNTR (see

Table 45 and Table 46) starts with a value of 0x0000 and

increments every time new data loads into the output registers.

When the DATA_CNTR value reaches 0xFFFF, the next data

update causes it to wrap back around to 0x0000, where it continues

to increment every time new data loads into the output registers.

The TEMP_OUT register (see Table 40 and Table 41) provides

a coarse measurement of the temperature inside of the ADIS16477.

This data is most useful for monitoring relative changes in the

thermal environment.

Table 42. TEMP_OUT Data Format Examples

Temperature (°C)

Decimal Hex

Binary

+152

+ꢀ2

+5.ꢀ

+5.1

+5

+5.1

+5.ꢀ

−45

+1525

+ꢀ25

+ꢀ

+1

5

−1

−ꢀ

−455

5x541A 5555 5155 5551 1515

5x55FA 5555 5555 1111 1515

5x555ꢀ 5555 5555 5555 5515

5x5551 5555 5555 5555 5551

5x5555 5555 5555 5555 5555

5xFFFF 1111 1111 1111 1111

5xFFFE 1111 1111 1111 1115

5xFE75 1111 1115 5111 5555

DELTA ANGLES

In addition to the angular rate of rotation (gyroscope)

measurements around each axis (x, y, and z), the ADIS16477 also

provides delta angle measurements that represent a calculation

of angular displacement between each sample update.

Z

Δθ

Z

Time Stamp (TIME_STAMP)

Table 43. TIME_STAMP Register Definition

X

Y

Addresses

Default

Access

Flash Backup

Δθ

X

Y

5x1E, 5x1F

Not applicable

R

No

PIN K1

PIN A8

Figure 40. Delta Angle Axis and Polarity Assignments

Table 44. TIME_STAMP Bit Definitions

The delta angle outputs represent an integration of the gyroscope

measurements and use the following formula for all three axes (x-

axis displayed):

Bits

Description

[12:5]

Time from the last pulse on the SYNC pin; offset binary

format, 1 LSB = 49.5ꢀ ꢁs

D  1

The TIME_STAMP register (see Table 43 and Table 44) works

in conjunction with scaled sync mode (Register MSC_CTRL,

Bits[4:2] = 010, see Table 105). The 16-bit number in TIME_

STAMP contains the time associated with the last sample in

each data update relative to the most recent edge of the clock

signal in the SYNC pin. For example, when the value in the

UP_SCALE register (see Table 107) represents a scale factor of

20, DEC_RATE = 0, and the external SYNC rate = 100 Hz, the

following time stamp sequence results: 0 LSB, 10 LSB, 21 LSB,

31 LSB, 41 LSB, 51 LSB, 61 LSB, 72 LSB, …, 194 LSB for the 20th

sample, which translates to 0 μs, 490 μs, …, 9510 μs, the time

from the first SYNC edge.

1

 ^

_{x, nD}





_{x, nDd} _{x, nDd 1}



2 f_S

d 0

where:

D is the decimation rate (DEC_RATE + 1, see Table 109).

f_Sis the sample rate.

d is the incremental variable in the summation formula.

ω_Xis the x-axis rate of rotation (gyroscope).

n is the sample time, prior to the decimation filter.

When using the internal sample clock, f_Sis equal to a nominal

rate of 2000 SPS. For better precision in this measurement,

measure the internal sample rate (f_S) using the data ready signal

on the DR pin (DEC_RATE = 0x0000, see Table 108), divide

each delta angle result (from the delta angle output registers) by

the data ready frequency and multiply it by 2000. Each axis of

the delta angle measurements has two output data registers.

Figure 41 shows how these two registers combine to support a

32-bit, twos complement data format for the x-axis delta angle

measurements. This format also applies to the y- and z-axes.

Rev. D | Page ꢀꢀ of 37

Data Sheet

ADIS16477

The Y_DELTANG_LOW (see Table 52 and Table 53) and

Y_DELTANG_OUT (see Table 54 and Table 55) registers

contain the delta angle data for the y-axis.

X_DELTANG_OUT

X_DELTANG_LOW

BIT 0 BIT 15

BIT 15

BIT 0

X-AXIS DELTA ANGLE DATA

Z-Axis Delta Angle (Z_DELTANG_LOW and

Z_DELTANG_OUT)

Figure 41. Delta Angle Output Data Structure

Delta Angle Measurement Range

Table 56. Z_DELTANG_LOW Register Definitions

Table 47 shows the measurement range and scale factor for

each ADIS16477 model.

Addresses

Default

Access

Flash Backup

5xꢀC, 5xꢀD

Not applicable

R

No

Table 47. Delta Angle Measurement Range and Scale Factor

Table 57. Z_DELTANG_LOW Bit Definitions

Model

Measurement Range, ±ꢁθ_MAX(°)

Bits

Description

ADIS16477-1BMLZ

ADIS16477-ꢀBMLZ

ADIS16477-3BMLZ

365

7ꢀ5

ꢀ165

[12:5]

Z-axis delta angle data; low word

Table 58. Z_DELTANG_OUT Register Definitions

Addresses

Default

Access

Flash Backup

X-Axis Delta Angle (X_DELTANG_LOW and

X_DELTANG_OUT)

5xꢀE, 5xꢀF

Not applicable

R

No

Table 48. X_DELTANG_LOW Register Definitions

Table 59. Z_DELTANG_OUT Bit Definitions

Bits Description

[12:5] Z-axis delta angle data; twos complement, 5° = 5x5555,

1 LSB = Δθ_MAX/ꢀ¹²(see Table 47 for Δθ_MAX

Addresses Default

Access Flash Backup

5xꢀ4, 5xꢀ2 Not applicable

R

No

)

Table 49. X_DELTANG_LOW Bit Definitions

The Z_DELTANG_LOW (see Table 56 and Table 57) and

Z_DELTANG_OUT (see Table 58 and Table 59) registers

contain the delta angle data for the z-axis.

Bits

Description

[12:5]

X-axis delta angle data; low word

Table 50. X_DELTANG_OUT Register Definitions

Delta Angle Resolution

Addresses Default

Access Flash Backup

Table 60 and Table 61 show various numerical examples that

demonstrate the format of the delta angle data in both 16-bit

and 32-bit formats.

5xꢀ6, 5xꢀ7 Not applicable

R

No

Table 51. X_DELTANG_OUT Bit Definitions

Bits Description

[12:5] X-axis delta angle data; twos complement, 5° = 5x5555,

1 LSB = Δθ_MAX/ꢀ¹²(see Table 47 for Δθ_MAX

Table 60. 16-Bit Delta Angle Data Format Examples

Delta Angle (°)

Decimal Hex

Binary

)

Δθ_MAX× (ꢀ¹²−1)/ꢀ¹²+3ꢀ,767

5x7FFF 5111 1111 1115 1111

5x555ꢀ 5555 5555 5555 5515

5x5551 5555 5555 5555 5551

5x5555 5555 5555 5555 5555

5xFFFF 1111 1111 1111 1111

5xFFFE 1111 1111 1111 1115

5x8555 1555 5555 5555 5555

The X_DELTANG_LOW (see Table 48 and Table 49) and

X_DELTANG_OUT (see Table 50 and Table 51) registers

contain the delta angle data for the x-axis.

+Δθ_MAX/ꢀ¹⁴

+Δθ_MAX/ꢀ¹²

5

+ꢀ

+1

5

−Δθ_MAX/ꢀ¹²

−Δθ_MAX/ꢀ¹⁴

−Δθ_MAX

−1

−ꢀ

−3ꢀ,768

Y-Axis Delta Angle (Y_DELTANG_LOW and

Y_DELTANG_OUT)

Table 52. Y_DELTANG_LOW Register Definitions

Addresses

Default

Access

Flash Backup

Table 61. 32-Bit Delta Angle Data Format Examples

5xꢀ8, 5xꢀ9

Not applicable

R

No

Delta Angle (°)

+Δθ_MAX× (ꢀ³¹− 1)/ꢀ³¹

+Δθ_MAX/ꢀ³⁵

+Δθ_MAX/ꢀ³¹

5

−Δθ_MAX/ꢀ³¹

−Δθ_MAX/ꢀ³⁵

−Δθ_MAX

Decimal

Hex

+ꢀ,147,483,647 5x7FFFFFFF

Table 53. Y_DELTANG_LOW Bit Definitions

+ꢀ

+1

5

−1

−ꢀ

5x5555555ꢀ

5x55555551

5x55555555

5xFFFFFFFF

5xFFFFFFFE

Bits

Description

[12:5]

Y-axis delta angle data; low word

Table 54. Y_DELTANG_OUT Register Definitions

Addresses

Default

Access

Flash Backup

−ꢀ,147,483,648 5x85555555

5xꢀA, 5xꢀB

Not applicable

R

No

DELTA VELOCITY

Table 55. Y_DELTANG_OUT Bit Definitions

Bits Description

[12:5] Y-axis delta angle data; twos complement, 5° = 5x5555,

1 LSB = Δθ_MAX/ꢀ¹²(see Table 47 for Δθ_MAX

In addition to the linear acceleration measurements along each

axis (x, y, and z), the ADIS16477 also provides delta velocity

measurements that represent a calculation of linear velocity

change between each sample update.

)

Rev. D | Page ꢀ3 of 37

ADIS16477

Data Sheet

Z

Table 65. X_DELTVEL_OUT Bit Definitions

Bits

Description

ΔV

Z

[12:5]

X-axis delta velocity data; twos complement,

455 m/sec range, 5 m/sec = 5x5555;

1 LSB = 455 m/sec ÷ ꢀ¹²= ~5.51ꢀꢀ1 m/sec

The X_DELTVEL_LOW (see Table 62 and Table 63) and

X_DELTVEL_OUT (see Table 64 and Table 65) registers

contain the delta velocity data for the x-axis.

PIN K1

PIN A8

ΔV

Y

X

Y-Axis Delta Velocity (Y_DELTVEL_LOW and

Y_DELTVEL_OUT)

Y

Figure 42. Delta Velocity Axis and Polarity Assignments

Table 66. Y_DELTVEL_LOW Register Definition

The delta velocity outputs represent an integration of the

acceleration measurements and use the following formula for

all three axes (x-axis displayed):

Addresses

Default

Access

Flash Backup

5x34, 5x32

Not applicable

R

No

D1

1

Table 67. Y_DELTVEL_LOW Bit Definitions

^

V_{x, nD}





a

_{x, nDd} a_{x, nD d 1}



2 f_S

d 0

Bits

Description

[12:5]

Y-axis delta velocity data; additional resolution bits

where:

x is the x-axis.

Table 68. Y_DELTVEL_OUT Register Definition

Addresses

n is the sample time, prior to the decimation filter.

D is the decimation rate (DEC_RATE + 1, see Table 109).

f_Sis the sample rate.

Default

Access

Flash Backup

5x36, 5x37

Not applicable

R

No

d is the incremental variable in the summation formula.

a_Xis the x-axis acceleration.

Table 69. Y_DELTVEL_OUT Bit Definitions

Bits

Description

When using the internal sample clock, f_Sis equal to a nominal

rate of 2000 SPS. For better precision in this measurement,

measure the internal sample rate (f_S) using the data ready signal

on the DR pin (DEC_RATE = 0x0000, see Table 108), divide

each delta angle result (from the delta angle output registers) by

the data ready frequency and multiply it by 2000. Each axis of

the delta velocity measurements has two output data registers.

Figure 43 shows how these two registers combine to support

32-bit, twos complement data format for the delta velocity

measurements along the x-axis. This format also applies to the

y- and z-axes.

[12:5]

Y-axis delta velocity data; twos complement,

455 m/sec range, 5 m/sec = 5x5555;

1 LSB = 455 m/sec ÷ ꢀ¹²= ~5.51ꢀꢀ1 m/sec

The Y_DELTVEL_LOW (see Table 66 and Table 67) and

Y_DELTVEL_OUT (see Table 68 and Table 69) registers

contain the delta velocity data for the y-axis.

Z-Axis Delta Velocity (Z_DELTVEL_LOW and

Z_DELTVEL_OUT)

Table 70. Z_DELTVEL_LOW Register Definition

Addresses

Default

Access

Flash Backup

5x38, 5x39

Not applicable

R

No

X_ DELTVEL_OUT

BIT 0 BIT 15

X_ DELTVEL_LOW

BIT 0

BIT 15

Table 71. Z_DELTVEL_LOW Bit Definitions

X-AXIS DELTA VELOCITY DATA

Bits

Description

[12:5]

Z-axis delta velocity data; additional resolution bits

Figure 43. Delta Angle Output Data Structure

X-Axis Delta Velocity (X_DELTVEL_LOW and

X_DELTVEL_OUT)

Table 72. Z_DELTVEL_OUT Register Definition

Addresses

Default

Access

Flash Backup

5x3A, 5x3B

Not applicable

R

No

Table 62. X_DELTVEL_LOW Register Definition

Addresses

Default

Access

Flash Backup

Table 73. Z_DELTVEL_OUT Bit Definitions

Bits Description

5x35, 5x31

Not applicable

R

No

[12:5] Z-axis delta velocity data; twos complement,

455 m/sec range, 5 m/sec = 5x5555;

Table 63. X_DELTVEL_LOW Bit Definitions

Bits

Description

1 LSB = 455 m/sec ÷ ꢀ¹²= ~5.51ꢀꢀ1 m/sec

[12:5]

X-axis delta velocity data; additional resolution bits

The Z_DELTVEL_LOW (see Table 70 and Table 71) and

Z_DELTVEL_OUT (see Table 72 and Table 73) registers

contain the delta velocity data for the z-axis.

Table 64. X_DELTVEL_OUT Register Definition

Addresses

Default

Access

Flash Backup

5x3ꢀ, 5x33

Not applicable

R

No

Rev. D | Page ꢀ4 of 37

Data Sheet

ADIS16477

Delta Velocity Resolution

The XG_BIAS_LOW (see Table 76 and Table 77) and XG_BIAS_

HIGH (see Table 78 and Table 79) registers combine to allow users

to adjust the bias of the x-axis gyroscopes. The data format

examples in Table 12 also apply to the XG_BIAS_HIGH register,

and the data format examples in Table 13 apply to the 32-bit

combination of the XG_BIAS_LOW and XG_BIAS_HIGH

registers. See Figure 44 for an illustration of how these two registers

combine and influence the x-axis gyroscope measurements.

Table 74 and Table 75 offer various numerical examples that

demonstrate the format of the delta velocity data in both 16-bit

and 32-bit formats.

Table 74. 16-Bit Delta Velocity Data Format Examples

Velocity (m/sec)

Decimal Hex

Binary

+455 × (ꢀ¹²− 1)/ꢀ¹²+3ꢀ,767

5x7FFF 5111 1111 1111 1111

5x555ꢀ 5555 5555 5555 5515

5x5551 5555 5555 5555 5551

5x5555 5555 5555 5555 5555

5xFFFF 1111 1111 1111 1111

5xFFFE 1111 1111 1111 1115

5x8555 1555 5555 5555 5555

+455/ꢀ¹⁴

+455/ꢀ¹²

5

+ꢀ

+1

5

FACTORY

X-AXIS

GYRO

CALIBRATION

AND

X_GYRO_OUT X_GYRO_LOW

FILTERING

−455/ꢀ¹²

−455/ꢀ¹⁴

−455

−1

−ꢀ

−3ꢀ,768

XG_BIAS_HIGH XG_BIAS_LOW

Figure 44. User Calibration Signal Path, Gyroscopes

Calibration, Gyroscope Bias (YG_BIAS_LOW and

YG_BIAS_HIGH)

Table 75. 32-Bit Delta Velocity Data Format Examples

Velocity (m/sec)

+455 × (ꢀ³¹− 1)/ꢀ³¹

+455/ꢀ³⁵

+455/ꢀ³¹

5

−455/ꢀ³¹

−455/ꢀ³⁵

−455

Decimal

Hex

Table 80. YG_BIAS_LOW Register Definition

+ꢀ,147,483,647

+ꢀ

+1

5

−1

−ꢀ

5x7FFFFFFF

5x5555555ꢀ

5x55555551

5x55555555

5xFFFFFFFF

5xFFFFFFFE

5x85555555

Addresses

Default

Access

Flash Backup

5x44, 5x42

5x5555

R/W

Yes

Table 81. YG_BIAS_LOW Bit Definitions

Bits Description

[12:5] Y-axis gyroscope offset correction; lower word

+ꢀ,147,483,648

Table 82. YG_BIAS_HIGH Register Definition

CALIBRATION

Addresses

Default

Access

Flash Backup

The signal chain of each inertial sensor (accelerometers and

gyroscopes) includes the application of unique correction

formulas, which are derived from extensive characterization of

bias, sensitivity, alignment, response to linear acceleration

(gyroscopes), and point of percussion (accelerometer location)

over a temperature range of −40°C to +85°C, for each ADIS16477.

These correction formulas are not accessible, but users do have

the opportunity to adjust the bias for each sensor individually

through user accessible registers. These correction factors

follow immediately after the factory derived correction formulas

in the signal chain, which processes at a rate of 2000 Hz when

using the internal sample clock.

5x46, 5x47

5x5555

R/W

Yes

Table 83. YG_BIAS_HIGH Bit Definitions

Bits Description

[12:5] Y-axis gyroscope offset correction factor, upper word

The YG_BIAS_LOW (see Table 80 and Table 81) and YG_BIAS_

HIGH (see Table 82 and Table 83) registers combine to allow

users to adjust the bias of the y-axis gyroscopes. The data format

examples in Table 12 also apply to the YG_BIAS_HIGH register,

and the data format examples in Table 13 apply to the 32-bit

combination of the YG_BIAS_LOW and YG_BIAS_HIGH

registers. These registers influence the y-axis gyroscope

measurements in the same manner that the XG_BIAS_LOW

and XG_BIAS_HIGH registers influence the x-axis gyroscope

measurements (see Figure 44).

Calibration, Gyroscope Bias (XG_BIAS_LOW and

XG_BIAS_HIGH)

Table 76. XG_BIAS_LOW Register Definition

Calibration, Gyroscope Bias (ZG_BIAS_LOW and

ZG_BIAS_HIGH)

Addresses

Default

Access

Flash Backup

5x45, 5x41

5x5555

R/W

Yes

Table 84. ZG_BIAS_LOW Register Definition

Addresses

Default

Access

Flash Backup

Table 77. XG_BIAS_LOW Bit Definitions

5x48, 5x49

5x5555

R/W

Yes

Bits

Description

[12:5]

X-axis gyroscope offset correction; lower word

Table 85. ZG_BIAS_LOW Bit Definitions

Bits Description

Table 78. XG_BIAS_HIGH Register Definition

Addresses

[12:5] Z-axis gyroscope offset correction; lower word

Default

Access

Flash Backup

Table 86. ZG_BIAS_HIGH Register Definition

5x4ꢀ, 5x43

5x5555

R/W

Yes

Addresses

Default

Access

Flash Backup

Table 79. XG_BIAS_HIGH Bit Definitions

Bits Description

[12:5] X-axis gyroscope offset correction factor, upper word

5x4A, 5x4B

5x5555

R/W

Yes

Rev. D | Page ꢀ2 of 37

ADIS16477

Data Sheet

Table 87. ZG_BIAS_HIGH Bit Definitions

Table 93. YA_BIAS_LOW Bit Definitions

Bits

Description

Bits

Description

[12:5] Z-axis gyroscope offset correction factor, upper word

[12:5]

Y-axis accelerometer offset correction; lower word

The ZG_BIAS_LOW (see Table 84 and Table 85) and ZG_BIAS_

HIGH (see Table 86 and Table 87) registers combine to allow

users to adjust the bias of the z-axis gyroscopes. The data

format examples in Table 12 also apply to the ZG_BIAS_HIGH

register, and the data format examples in Table 13 apply to the

32-bit combination of the ZG_BIAS_LOW and ZG_BIAS_HIGH

registers. These registers influence the z-axis gyroscope

measurements in the same manner that the XG_BIAS_LOW

and XG_BIAS_HIGH registers influence the x-axis gyroscope

measurements (see Figure 44).

Table 94. YA_BIAS_HIGH Register Definition

Addresses

Default

Access

Flash Backup

5x2ꢀ, 5x23

5x5555

R/W

Yes

Table 95. YA_BIAS_HIGH Bit Definitions

Bits Description

[12:5] Y-axis accelerometer offset correction, upper word

The YA_BIAS_LOW (see Table 92 and Table 93) and

YA_BIAS_HIGH (see Table 94 and Table 95) registers combine

to allow users to adjust the bias of the y-axis accelerometers.

The data format examples in Table 26 also apply to the

YA_BIAS_HIGH register, and the data format examples in

Table 27 apply to the 32-bit combination of the YA_BIAS_LOW

and YA_BIAS_HIGH registers. These registers influence the y-

axis accelerometer measurements in the same manner that the

XA_BIAS_LOW and XA_BIAS_HIGH registers influence the

x-axis accelerometer measurements (see Figure 45).

Calibration, Accelerometer Bias (XA_BIAS_LOW and

XA_BIAS_HIGH)

Table 88. XA_BIAS_LOW Register Definition

Addresses

Default

Access

Flash Backup

5x4C, 5x4D

5x5555

R/W

Yes

Table 89. XA_BIAS_LOW Bit Definitions

Bits

Description

Calibration, Accelerometer Bias (ZA_BIAS_LOW and

ZA_BIAS_HIGH)

[12:5]

X-axis accelerometer offset correction; lower word

Table 90. XA_BIAS_HIGH Register Definition

Table 96. ZA_BIAS_LOW Register Definition

Addresses

Default

Access

Flash Backup

Addresses

Default

Access

Flash Backup

5x4E, 5x4F

5x5555

R/W

Yes

5x24, 5x22

5x5555

R/W

Yes

Table 91. XA_BIAS_HIGH Bit Definitions

Bits Description

Table 97. ZA_BIAS_LOW Bit Definitions

Bits Description

[12:5] X-axis accelerometer offset correction, upper word

[12:5] Z-axis accelerometer offset correction; lower word

The XA_BIAS_LOW (see Table 88 and Table 89) and XA_BIAS_

HIGH (see Table 90 and Table 91) registers combine to allow

users to adjust the bias of the x-axis accelerometers. The data

format examples in Table 26 also apply to the XA_BIAS_HIGH

register, and the data format examples in Table 27 apply to the

32-bit combination of the XA_BIAS_LOW and XA_BIAS_HIGH

registers. See Figure 45 for an illustration of how these two

registers combine and influence the x-axis accelerometer

measurements.

Table 98. ZA_BIAS_HIGH Register Definition

Addresses

Default

Access

Flash Backup

5x26, 5x27

5x5555

R/W

Yes

Table 99. ZA_BIAS_HIGH Bit Definitions

Bits Description

[12:5] Z-axis accelerometer offset correction, upper word

The ZA_BIAS_LOW (see Table 96 and Table 97) and ZA_BIAS_

HIGH (see Table 98 and Table 99) registers combine to allow

users to adjust the bias of the z-axis accelerometers. The data

format examples in Table 26 also apply to the ZA_BIAS_HIGH

register, and the data format examples in Table 27 apply to the 32-

bit combination of the ZA_BIAS_LOW and ZA_BIAS_HIGH

registers. These registers influence the z-axis accelerometer

measurements in the same manner that the XA_BIAS_LOW

and XA_BIAS_HIGH registers influence the x-axis accelerometer

measurements (see Figure 45).

FACTORY

X-AXIS

ACCL

CALIBRATION

AND

X_ACCL_OUT X_ACCL_LOW

FILTERING

XA_BIAS_HIGH XA_BIAS_LOW

Figure 45. User Calibration Signal Path, Accelerometers

Calibration, Accelerometer Bias (YA_BIAS_LOW and

YA_BIAS_HIGH)

Table 92. YA_BIAS_LOW Register Definition

Filter Control Register (FILT_CTRL)

Addresses

Default

Access

Flash Backup

Table 100. FILT_CTRL Register Definition

5x25, 5x21

5x5555

R/W

Yes

Addresses

Default

Access

Flash Backup

5x2C, 5x2D

5x5555

R/W

Yes

Rev. D | Page ꢀ6 of 37

Data Sheet

ADIS16477

Table 101. FILT_CTRL Bit Definitions

Bits

Description

Bits

Description

[4:ꢀ]

SYNC function setting

[12:3]

[ꢀ:5]

Not used

111 = reserved (do not use)

115 = reserved (do not use)

151 = pulse sync mode

Filter Size Variable B, number of taps in each stage; N = ꢀ^B

The FILT_CTRL register (see Table 100 and Table 101) provides

user controls for the Bartlett window FIR filter (see Figure 22),

which contains two cascaded averaging filters. For example, use

the following sequence to set Register FILT_CTRL, Bits[2:0] = 100,

which sets each stage to have 16 taps: 0xCC04 and 0xCD00.

Figure 46 provides the frequency response for several settings

in the FILT_CTRL register.

155 = reserved (do not use)

511 = output sync mode

515 = scaled sync mode

551 = direct sync mode

555 = internal clock mode (default)

SYNC polarity (input or output)

1 = rising edge triggers sampling

5 = falling edge triggers sampling

DR polarity

1

5

0

–20

–40

–60

–80

1 = active high when data is valid

5 = active low when data is valid

Point of Percussion

Register MSC_CTRL, Bit 6 (see Table 105) offers an on/off control

for the point of percussion alignment function, which maps the

accelerometer sensors to the corner of the package that is

closest to Pin A1 (see Figure 47). The factory default setting in

the MSC_CTRL register activates this function. To turn this

function off while retaining the rest of the factory default

settings in the MSC_CTRL register, set Register MSC_CTRL,

Bit 6 = 0, using the following command sequence on the DIN

pin: 0xE081, then 0xE100.

–100

N = 2

–120

N = 4

N = 16

N = 64

–140

0.001

0.01

FREQUENCY (f/f_S

0.1

1

Figure 46. Bartlett Window, FIR Filter Frequency Response

(Phase Delay = N Samples)

Range Identifier (RANG_MDL)

Table 102. RANG_MDL Register Definition

Addresses

Default

Access

Flash Backup

5x2E, 5x2F

Not applicable

R

No

PIN A8

PIN A1

POINT OF

PERCUSSION

Table 103. RANG_MDL Bit Definitions

Figure 47. Point of Percussion Reference Point

Bits

Description

[12:3]

[3:ꢀ]

Not used

Linear Acceleration Effect on Gyroscope Bias

Gyroscope measurement range

55 = 1ꢀ2°/sec (ADIS16477-1BMLZ)

51 = 255°/sec (ADIS16477-ꢀBMLZ)

15 = reserved

11 = ꢀ555°/sec (ADIS16477-3BMLZ)

Reserved, binary value = 11

Register MSC_CTRL, Bit 7 (see Table 105) provides an on/off

control for the linear g compensation in the signal calibration

routines of the gyroscope. The factory default contents in the

MSC_CTRL register enable this compensation. To turn the

compensation off, set Register MSC_CTRL, Bit 7 = 0, using the

following sequence on the DIN pin: 0xE04, then 0xEF00.

[1:5]

Miscellaneous Control Register (MSC_CTRL)

Internal Clock Mode

Table 104. MSC_CTRL Register Definition

Register MSC_CTRL, Bits[4:2] (see Table 105), provide five

different configuration options for controlling the clock (f_SM;

see Figure 19 and Figure 20), which controls data acquisition

and processing for the inertial sensors. The default setting for

Register MSC_CTRL, Bits[4:2] is 000 (binary), which places the

ADIS16477 in the internal clock mode. In this mode, an internal

clock controls inertial sensor data acquisition and processing at a

nominal rate of 2000 Hz. In this mode, each accelerometer data

update comes from an average of two data samples (sample rate =

4000 Hz).

Addresses

Default

Access

Flash Backup

5x65, 5x61

5x55C1

R/W

Yes

Table 105. MSC_CTRL Bit Definitions

Bits Description

[12:8] Not used

7

6

2

Linear g compensation for gyroscopes (1 = enabled)

Point of percussion alignment (1 = enabled)

Not used, always set to zero

Rev. D | Page ꢀ7 of 37

ADIS16477

Data Sheet

external clock scale factor, K_ECSF, (from the UP_SCALE register,

see Table 106 and Table 107) and the frequency of the clock

signal on the SYNC pin.

Output Sync Mode

When Register MSC_CTRL, Bits[4:2] = 011, the ADIS16477

operates in output sync mode, which is the same as internal

clock mode with one exception, the SYNC pin pulses when

the internal processor collects data from the inertial sensors.

Figure 48 provides an example of this signal.

For example, when using a 1 Hz input signal, set UP_SCALE =

0x07D0 (K_ECSF= 2000 (decimal)) to establish a sample rate of

2000 SPS for the inertial sensors and their signal processing.

Use the following sequence on the DIN pin to configure

UP_SCALE for this scenario: 0xE2D0, then 0xE307.

GYROSCOPE AND

ACCELEROMETER

DATA ACQUISITION

ACCELEROMETER

DATA ACQUISITION

Table 106. UP_SCALE Register Definition

SYNC

Addresses

Default

Access

Flash Backup

250µs

5x6ꢀ, 5x63

5x57D5

R/W

Yes

500µs

Table 107. UP_SCALE Bit Definitions

Figure 48. Sync Output Signal, Register MSC_CTRL, Bits[4:2] = 011

Bits

Description

Direct Sync Mode

[12:5]

K_ECSF; binary format

When Register MSC_CTRL, Bits[4:2] = 001, the ADIS16477

operates in direct sync mode. The signal on the SYNC pin

directly controls the sample clock. In this mode, the internal

processor collects gyroscope data samples on the rising edge of

the clock signal (SYNC pin) and collects accelerometer data

samples on both rising and falling edges of the clock signal. The

internal processor averages both accelerometer samples (from

rising and falling edges of the clock signal) together to produce

a single data sample. Therefore, when operating the ADIS16477

in this mode, the clock signal (SYNC pin) must have a duty

cycle of 50ꢀ and a frequency that is within the range of 1900 Hz

to 2100 Hz. The ADIS16477 is capable of operating when the

clock frequency (SYNC pin) is less than 1900 Hz, but with risk

of performance degradation, especially when tracking dynamic

inertial conditions (including vibration).

Decimation Filter (DEC_RATE)

Table 108. DEC_RATE Register Definition

Addresses

Default

Access

Flash Backup

5x64, 5x62

5x5555

R/W

Yes

Table 109. DEC_RATE Bit Definitions

Bits

Description

[12:11]

[15:5]

Don’t care

Decimation rate, binary format, maximum = 1999

The DEC_RATE register (see Table 108 and Table 109)

provides user control for the averaging decimating filter, which

averages and decimates the gyroscope and accelerometer data; it

also extends the time that the delta angle and the delta velocity

track between each update. When the ADIS16477 operates in

internal clock mode (see Register MSC_CTRL, Bits [4:2], in

Table 105), the nominal output data rate is equal to

Pulse Sync Mode

When operating in pulse sync mode (Register MSC_CTRL,

Bits[4:2] = 101), the internal processor only collects accelerometer

samples on the leading edge of the clock signal, which enables

the use of a narrow pulse width (see Table 2) in the clock signal on

the SYNC pin. Using pulse sync mode also lowers the bandwidth

on the inertial sensors to 370 Hz. When operating in pulse sync

mode, the ADIS16477 provides the best performance when the

frequency of the clock signal (SYNC pin) is within the range of

1000 Hz to 2100 Hz. The ADIS16477 is capable of operating

when the clock frequency (SYNC pin) is less than 1000 Hz, but

with risk of performance degradation, especially when tracking

dynamic inertial conditions (including vibration).

2000/(DEC_RATE + 1). For example, set DEC_RATE = 0x0013

to reduce the output sample rate to 100 SPS (2000 ÷ 20), using

the following DIN pin sequence: 0xE413, then 0xE500.

Data Update Rate in External Sync Modes

When using the input sync option, in scaled sync mode

(Register MSC_CTRL, Bits[4:2] = 010, see Table 105), the

output data rate is equal to

(f_SYNC× K_ECSF)/(DEC_RATE + 1)

where:

f

K

_SYNCis the frequency of the clock signal on the SYNC pin.

_ESCFis the value from the UP_SCALE register (see Table 107).

Scaled Sync Mode

When using direct sync mode and pulse sync mode, K_ESCF= 1.

When Register MSC_CTRL, Bits[4:2] = 010, the ADIS16477

operates in scaled sync mode that supports a frequency range of

1 Hz to 128 Hz for the clock signal on the SYNC pin. This

mode of operation is particularly useful when synchronizing

the data processing with a PPS signal from a global positioning

system (GPS) receiver or with a synchronization signal from a

video processing system. When operating in scaled sync mode,

the frequency of the sample clock is equal to the product of the

Continuous Bias Estimation (NULL_CNFG)

Table 110. NULL_CNFG Register Definition

Addresses

Default

Access

Flash Backup

5x66, 5x67

5x575A

R/W

Yes

Rev. D | Page ꢀ8 of 37

Data Sheet

ADIS16477

Table 111. NULL_CNFG Bit Definitions

Flash Memory Test

Bits

Description

Use the following DIN sequence to set Register GLOB_CMD,

Bit 4 = 1, which tests the flash memory: 0xE810, then 0xE900.

The command performs a CRC computation on the flash

memory (excluding user register locations) and compares it to

the original CRC value, which comes from the factory configura-

tion process. If the current CRC value does not match the

original CRC value, Register DIAG_STAT, Bit 6 (see Table 10),

rises to 1, indicating a failing result.

[15:14] Not used

13

12

11

10

9

8

[7:4]

[3:0]

Z-axis accelerometer bias correction enable (1 = enabled)

Y-axis accelerometer bias correction enable (1 = enabled)

X-axis accelerometer bias correction enable (1 = enabled)

Z-axis gyroscope bias correction enable (1 = enabled)

Y-axis gyroscope bias correction enable (1 = enabled)

X-axis gyroscope bias correction enable (1 = enabled)

Not used

Flash Memory Update

Time base control (TBC), range: 0 to 12 (default = 10);

t_B= 2^TBC/2000, time base; t_A= 64 × t_B, average time

Use the following DIN sequence to set Register GLOB_CMD,

Bit 3 = 1, which triggers a backup of all user configurable registers

in the flash memory: 0xE808, then 0xE900. Register

DIAG_STAT, Bit 2 (see Table 10) identifies success (0) or

failure (1) in completing this process.

The NULL_CNFG register (see Table 110 and Table 111)

provides the configuration controls for the continuous bias

estimator (CBE), which associates with the bias correction

update command in Register GLOB_CMD, Bit 0 (see Table 113).

Register NULL_ CNFG, Bits[3:0], establishes the total average

time (t_A) for the bias estimates and Register NULL_CNFG,

Bits[13:8], provide the on/off controls for each sensor. The factory

default configuration for the NULL_CNFG register enables the

bias null command for the gyroscopes, disables the bias null

command for the accelerometers, and sets the average time

to ~32 sec.

Sensor Self Test

Use the following DIN sequence to set Register GLOB_CMD,

Bit 2 = 1, which triggers the self test routine for the inertial sensors:

0xE804 and 0xE900. The self test routine uses the following steps

to validate the integrity of each inertial sensor:

1. Measure the output on each sensor.

2. Activate an internal stimulus on the mechanical elements of

each sensor to move them in a predictable manner and

create an observable response in the sensors.

3. Measure the output response on each sensor.

4. Deactivate the internal stimulus on each sensor.

5. Calculate the difference between the sensor measurements

from Step 1 (stimulus is off) and from Step 3 (stimulus is on).

6. Compare the difference with internal pass and fail criteria.

7. Report the pass and fail result to Register DIAG_STAT, Bit 5

(see Table 10).

Global Commands (GLOB_CMD)

Table 112. GLOB_CMD Register Definition

Addresses

Default

Access

Flash Backup

0x68, 0x69

Not applicable

W

No

Table 113. GLOB_CMD Bit Definitions

Bits

Description

[15:8]

7

Not used

Software reset

Motion, during the execution of this test, can indicate a false

failure.

[6:5]

4

3

Not used

Flash memory test

Flash memory update

Sensor self test

Factory Calibration Restore

2

Use the following DIN sequence to set Register GLOB_CMD,

Bit 1 = 1 to restore the factory default settings for the MSC_

CTRL, DEC_RATE, and FILT_CTRL registers and to clear all

user configurable bias correction settings: 0xE802, then 0xE900.

Executing this command results in writing 0x0000 to the

following registers: XG_BIAS_LOW, XG_BIAS_HIGH,

YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW,

ZG_BIAS_ HIGH, XA_BIAS_LOW, XA_BIAS_HIGH,

YA_BIAS_LOW, YA_BIAS_HIGH, ZA_BIAS_LOW, and

ZA_BIAS_HIGH.

1

0

Factory calibration restore

Bias correction update

The GLOB_CMD register (see Table 112 and Table 113)

provides trigger bits for several operations. Write a 1 to the

appropriate bit in GLOB_CMD to start a particular function.

During the execution of these commands, data production

stops, pulsing stops on the DR pin, and the SPI interface does

not respond to requests. Table 1 provides the execution time

for each GLOB_CMD command.

Software Reset

Bias Correction Update

Use the following DIN sequence to set Register GLOB_CMD,

Bit 7 = 1, which triggers a reset: 0xE880, then 0xE900. This reset

clears all data, and then restarts data sampling and processing.

This function provides a firmware alternative to toggling the

Use the following DIN pin sequence to set Register GLOB_CMD,

Bit 0 = 1 to trigger a bias correction, using the correction

factors from the CBE (see Table 111): 0xE801, then 0xE900.

RST

pin (see Table 5, Pin F3).

Rev. D | Page 29 of 37

ADIS16477

Data Sheet

The PROD_ID register (see Table 120 and Table 121) contains

the numerical portion of the device number (16,477). See Figure 32

for an example of how to use a looping read of this register to

validate the integrity of the communication.

Firmware Revision (FIRM_REV)

Table 114. FIRM_REV Register Definition

Addresses

Default

Access

Flash Backup

5x6C, 5x6D

Not applicable

R

No

Serial Number (SERIAL_NUM)

Table 115. FIRM_REV Bit Definitions

Table 122. SERIAL_NUM Register Definition

Bits

Description

Addresses

Default

Access

Flash Backup

[12:5]

Firmware revision, binary coded decimal (BCD) format

5x74, 5x72

Not applicable

R

No

The FIRM_REV register (see Table 114 and Table 115)

provides the firmware revision for the internal firmware. This

register uses a BCD format, where each nibble represents a

digit. For example, if FIRM_REV = 0x0104, the firmware revision

is 1.04.

Table 123. SERIAL_NUM Bit Definitions

Bits Description

[12:5] Lot specific serial number

Scratch Registers (USER_SCR_1 to USER_SCR_3)

Firmware Revision Day and Month (FIRM_DM)

Table 124. USER_SCR_1 Register Definition

Table 116. FIRM_DM Register Definition

Addresses

Default

Access

Flash Backup

Addresses

Default

Access

Flash Backup

5x76, 5x77

Not applicable

R/W

Yes

5x6E, 5x6F

Not applicable

R

No

Table 125. USER_SCR_1 Bit Definitions

Bits Description

Table 117. FIRM_DM Bit Definitions

Bits

Description

[12:5] User defined

[12:8]

[7:5]

Factory configuration month, BCD format

Factory configuration day, BCD format

Table 126. USER_SCR_2 Register Definition

Addresses

Default

Access

Flash Backup

The FIRM_DM register (see Table 116 and Table 117)

contains the month and day of the factory configuration date.

Register FIRM_DM, Bits[15:8], contain digits that represent the

month of the factory configuration. For example, November is

the 11^thmonth in a year and is represented by Register

FIRM_DM, Bits[15:8] = 0x11. Register FIRM_DM, Bits[7:0],

contain the day of factory configuration. For example, the 27^th

day of the month is represented by Register FIRM_DM,

Bits[7:0] = 0x27.

5x78, 5x79

Not applicable

R/W

Yes

Table 127. USER_SCR_2 Bit Definitions

Bits Description

[12:5] User defined

Table 128. USER_SCR_3 Register Definition

Addresses

Default

Access

Flash Backup

5x7A, 5x7B

Not applicable

R/W

Yes

Firmware Revision Year (FIRM_Y)

Table 129. USER_SCR_3 Bit Definitions

Bits Description

[12:5] User defined

Table 118. FIRM_Y Register Definition

Addresses

Default

Access

Flash Backup

5x75, 5x71

Not applicable

R

No

The USER_SCR_1 (see Table 124 and Table 125), USER_SCR_2

(see Table 126 and Table 127), and USER_SCR_3 (see Table 128

and Table 129) registers provide three locations for the user to

store information. For nonvolatile storage, use the manual flash

memory update command (Register GLOB_CMD, Bit 3, see

Table 113), after writing information to these registers.

Table 119. FIRM_Y Bit Definitions

Bits

Description

[12:5]

Factory configuration year, BCD format

The FIRM_Y register (see Table 118 and Table 119) contains

the year of the factory configuration date. For example, the

year, 2017, is represented by FIRM_Y = 0x2017.

Product Identification (PROD_ID)

Table 120. PROD_ID Register Definition

Addresses

Default

Access

Flash Backup

5x7ꢀ, 5x73

5x452D

R

No

Table 121. PROD_ID Bit Definitions

Bits

Description

[12:5]

Product identification = 5x452D

Rev. D | Page 35 of 37

Data Sheet

ADIS16477

number of write cycles, the flash memory has a finite service

lifetime, which depends on the junction temperature. Figure 49

provides guidance for estimating the retention life for the flash

memory at specific junction temperatures. The junction

temperature is approximately 7°C above the case temperature.

Flash Memory Endurance Counter (FLSHCNT_LOW and

FLSHCNT_HIGH)

Table 130. FLSHCNT_LOW Register Definition

Addresses

Default

Access

Flash Backup

5x7C, 5x7D

Not applicable

R

No

Table 131. FLSHCNT_LOW Bit Definitions

Bits Description

[12:5] Flash memory write counter, low word

600

450

300

Table 132. FLSHCNT_HIGH Register Definition

Addresses

Default

Access

Flash Backup

5x7E, 5x7F

Not applicable

R

No

Table 133. FLSHCNT_HIGH Bit Definitions

Bits Description

[12:5] Flash memory write counter, high word

150

0

30

40

55

70

85

100

125

135

150

The FLSHCNT_LOW (see Table 130 and Table 131) and

FLSHCNT_HIGH (see Table 132 and Table 133) registers

combine to provide a 32-bit, binary counter that tracks the

number of flash memory write cycles. In addition to the

JUNCTION TEMPERATURE (°C)

Figure 49. Flash Memory Retention

Rev. D | Page 31 of 37

ADIS16477

Data Sheet

APPLICATIONS INFORMATION

ASSEMBLY AND HANDLING TIPS

Package Attributes

PCB Layout Suggestions

Figure 51 shows an example of the pad design and layout for

the ADIS16477 on a PCB. This example uses a solder mask

opening, with a diameter of 0.73 mm, around a metal pad that

has a diameter of 0.56 mm. When using a material for the system

PCB, which has similar thermal expansion properties as the

substrate material of the ADIS16477, the system PCB can also

use the solder mask to define the pads that support attachment

to the balls of the ADIS16477. The coefficient of thermal

expansion (CTE) in the substrate of the ADIS16477 is

approximately 14 ppm/°C.

The ADIS16477 is a multichip module package that has a 44-ball

BGA interface. This package has three basic attributes that

influence its handling and assembly to the PCB of the system:

the lid, the substrate, and the BGA pattern. The material of the

lid is a liquid crystal polymer (LCP), and its nominal thickness

is 0.5 mm. The substrate is a laminate composition that has a

nominal thickness of 1.57 mm. The solder ball material is

SAC305, and each ball has a nominal diameter of 0.75 mm

( 0.15 mm). The BGA pattern follows an 8 × 10 array, with

36 unpopulated positions, which simplifies the escape pattern

for the power, ground, and signal traces on the system PCB.

0.73

(MASK OPENING)

0.56

(COPPER PAD)

Assembly Tips

When developing a process to attach the ADIS16477 to a PCB,

consider the following guidelines and insights:



The ADIS16477 is capable of supporting solder reflow

attachment processes, which are in accordance with

J-STD-020E.



Limit device exposure to one pass through the solder

reflow process (no rework).

The hole in the top of the lid (see Figure 50) provides

venting and pressure relief during the assembly process of

the ADIS16477. Keep this hole clear of obstruction while

attaching the ADIS16477 to a PCB.

1.27

ALL DIMENSIONS IN MILLIMETERS

Figure 51. Recommend PCB Pattern, Solder Mask Defined Pads

Underfill

Underfill can be a useful technique in managing certain threats

to the integrity of the solder joints of the ADIS16477, including

peeling stress and extended exposure to vibration. When selecting

underfill material and developing an application and curing

process, ensure that the material fills the gap between each

surface (the ADIS16477 substrate and system PCB) and adheres

to both surfaces. The ADIS16477 does not require the use of

underfill materials in applications that do not anticipate

exposure to these types of mechanical stresses and when the

CTE of the system PCB is close to the same value as the CTE

of the substrate of the ADIS16477 (~14 ppm/°C).

OPENING IN

PACKAGE LID

Figure 50. Pressure Relief Hole



Use no clean flux to avoid exposing the device to cleaning

solvents, which can penetrate the inside of the ADIS16477

through the hole in the lid and be difficult to remove.

When the assembly process requires the use of liquids that

can reach the hole in the lid, use a temporary seal to

prevent entrapment of those liquids inside the cavity.

Manage moisture exposure prior to the solder reflow

processing, in accordance with J-STD-033, Moisture

Sensitivity Level 5.

Avoid exposing the ADIS16477 to mechanical shock

survivability that exceeds the maximum rating of 2000 g

(see Table 3). In standard PCB processing, high speed

handling equipment and panel separation processes often

present the most risk of introducing harmful levels of

mechanical shock survivability.

Process Validation and Control

These guidelines provide a starting point for developing a process

for attaching the ADIS16477 to a system PCB. Because each

system and situation may present unique requirements for this

attachment process, ensure that the process supports optimal

solder joint integrity, verify that the final system meets all

environmental test requirements, and establish observation and

control strategies for all key process attributes (for example, peak

temperatures, dwell times, and ramp rates).



Rev. D | Page 3ꢀ of 37

Data Sheet

ADIS16477

Accelerometer Data Width (Digital Resolution) section for

more information.

POWER SUPPLY CONSIDERATIONS

The ADIS16477 contains 6 μF of decoupling capacitance across

the VDD and GND pins. When the VDD voltage rises from 0 V

to 3.3 V, the charging current for this capacitor bank imposes

the following current profile (in amperes):

Serial Port SCLK Underrun/Overrun Conditions

The serial port operates in 16-bit segments, and it is critical that

the number of SCLK cycles be equal to an integer multiple of 16

CS

when the

pin is low. Failure to meet this condition causes

dVDD

dt

dVDD

dt

t

 

I_DD



t



 C

 610^6

the serial port controller inside of the ADIS16477 to be unable

to correctly receive and respond to new requests.

where:

CS

pin is

I_DD(t) is the current demand on the VDD pin during the initial

power supply ramp, with respect to time.

C is the internal capacitance across the VDD and GND pins (6 μF).

VDD(t) is the voltage on the VDD pin, with respect to time.

If too many SCLK cycles are received before the

deasserted, the user can recover serial port operation by asserting

CS CS

, providing 17 rising edges on the SCLK line, deasserting

and then attempting to correctly read the PROD_ID (or other

read-only) register on the ADIS16477. The user should repeat

these steps up to a maximum of 15 times until the correct data is

read.

,

For example, if VDD follows a linear ramp from 0 V to 3.3 V,

in 66 μs, the charging current is 300 mA for that timeframe.

The ADIS16477 also contains embedded processing functions

that present transient current demands during initialization or

reset recovery operations. During these processes, the peak

current demand reaches 250 mA and occurs at a time that is

approximately 40 ms after VDD reaches 3.0 V (or ~40 ms after

initiating a reset sequence).

CS

If

user must either power cycle or issue a hard reset (using the

RST

is deasserted before enough SCLK cycles are received, the

pin) to regain SPI port access.

DIGITAL RESOLUTION OF GYROSCOPES AND

ACCELEROMETERS

SERIAL PORT OPERATION

Maximum Throughput

Gyroscope Data Width (Digital Resolution)

The decimation filter (DEC_RATE register, see Table 109) and

Bartlett window filter (FILT_CTRL register, see Table 101)

have direct influence over the total number of bits in the output

data registers, which contain relevant information. When using

the factory default settings (DEC_RATE = 0x0000, FILT_CTRL =

0x0000) for these filters, the gyroscope data width is 16 bits,

which means that application processors can acquire all relevant

information through the X_GYRO_OUT, Y_GYRO_OUT, and

Z_GYRO_OUT registers.

When operating with the maximum output data (DEC_RATE =

0x0000, as described in Table 109), the maximum SCLK rate

(defined in Table 2) and minimum stall time, the SPI port can

support up to 12, 16-bit register reads in between each pulse of

the data ready signal. Attempting to read more than 12 registers

can result in a datapath overrun error in the DIAG_STAT

register (see Table 10). The serial port stall time (t_STALL) to meet

these requirements must be no more than 10ꢀ greater than the

minimum specification for t_STALLin Table 2.

The X_GYRO_LOW, Y_GYRO_LOW, and Z_GYRO_LOW

registers capture the bit growth that comes from each

accumulation operation in the decimation and Bartlett window

filters. When using these filters (DEC_RATE ≠ 0x0000 and/or

FILT_CTRL ≠ 0x0000), the data width increases by one bit

every time the number of summations (in a filter stage)

increases by a factor of two. For example, when DEC_RATE =

0x0007, the decimation filter adds eight (7 + 1 = 8, see Table 109)

successive samples together, which causes the data width to

increase by 3 bits (log₂8 = 3). When FILT_CTRL = 0x0002, both

stages in the Bartlett window filter use four (2²= 4, see Table 101)

summation operations, which increases the data width by 2 bits

(log₂4 = 2). When using both DEC_RATE = 0x0007 and

FILT_CTRL = 0x0002, the total bit growth is 7 bits, which

increases the overall data width to 23 bits.

The number of allowable registers reads between each pulse on

the data ready line increases proportionally with the decimation

rate (set by the DEC_RATE register, see Table 109). For example,

when the decimation rate equals 3 (DEC_RATE = 0x0002), the

SPI is able to support up to 36 register reads, assuming maximum

SCLK rate and minimum stall times in the protocol. Decreasing

the SCLK rate and increasing the stall time lowers the total

number of register reads supported by the ADIS16477 before a

datapath overrun error occurs.

This limitation of reading 12, 16-bit registers does not impact

the ability of the user to access the full precision of the

gyroscopes and accelerometers if the factory default settings of

DEC_RATE = 0x0000 and FILT_CTRL = 0x0000 are used. In

this case, the data width for the gyroscope and accelerometer

data is 16 bits, and application processors can acquire all

relevant information through the X_GYRO_OUT, Y_GYRO_

OUT, Z_GYRO_OUT, X_ACCEL_OUT, Y_ACCEL_OUT,

and Z_ACCEL_OUT registers. Thirty-two bit reads of the

sensor data do not provide additional precision in this case. See

the Gyroscope Data Width (Digital Resolution) section and the

Accelerometer Data Width (Digital Resolution)

The decimation filter (DEC_RATE register, see Table 109) and

Bartlett window filter (FILT_CTRL register, see Table 101)

have direct influence over the total number of bits in the output

data registers, which contain relevant information. When using

the factory default settings (DEC_RATE = 0x0000, FILT_CTRL

Rev. D | Page 33 of 37

ADIS16477

Data Sheet

= 0x0000) for these filters, the accelerometer data width is 20 bits.

The X_ACCL_OUT, Y_ACCL_OUT, and Z_ACCL_OUT

registers contain the most significant 16 bits of this data, while

the remaining (least significant) bits are in the upper 4 bits of

the X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW

registers. Since the total noise (0.6 mg rms, see Table 1) in the

accelerometer data (DEC_RATE = 0x0000, FILT_CTRL =

0x0000) is greater than the 16-bit quantization noise (0.25 mg ÷

12^0.5= 0.072 mg), application processors can acquire all relevant

information through the X_ACCL_OUT, Y_ACCL_OUT, and

Z_ACCL_OUT registers. This enables applications to preserve

optimal performance, while using the burst read (see Figure 31),

which only provides 16-bit data for the accelerometers.

EVALUATION TOOLS

Breakout Boards

The ADIS16477 has three difference breakout boards, which

provide a simple way to connect an ADIS16477 model and an

existing embedded processor platform. Table 134 provides a list

of the model numbers for each breakout board, along with the

ADIS16477 model that is on each breakout board.

Table 134. Breakout Board Models

Breakout Board Model

ADIS16477-1/PCBZ

ADIS16477-ꢀ/PCBZ

ADIS16477-3/PCBZ

ADIS16477 Model

ADIS16477-1BMLZ

ADIS16477-ꢀBMLZ

ADIS16477-3BMLZ

The X_ACCL_LOW, Y_ACCL_LOW, and Z_ACCL_LOW

registers also capture the bit growth that comes from each

accumulation operation in the decimation and Bartlett window

filters. When using these filters (DEC_RATE ≠ 0x0000 and/or

FILT_CTRL ≠ 0x0000), the data width increases by one bit

every time the number of summations (in a filter stage)

increases by a factor of two. For example, when DEC_RATE =

0x0001, the decimation filter adds two (1 + 1 = 2, see Table 109)

successive samples together, which causes the data width to

increase by 1 bit (log₂2 = 1). When FILT_CTRL = 0x0001, both

stages in the Bartlett window filter add two (2¹= 2, see Table 101)

successive samples together, which increases the data width by 1 bit

(log₂2 = 1) as well. When using both DEC_RATE = 0x0001 and

FILT_CTRL = 0x0001, the total bit growth is 3 bits, which

increases the overall data width to 23 bits.

The electrical interface (J1) on each breakout board comes from

a dual row, 2 mm pitch, 16-pin interface, which supports standard

ribbon cabling (1 mm pitch). Table 135 provides the J1 pin assign-

ments, which support direct connection with an embedded

processor board, using standard ribbon cables. Although each

case may present its own set of sensitivities (such as electromag-

netic interference (EMI)), these boards can typically support

reliable communication over ribbon cables up to 20 cm in length.

Table 135. J1 Pin Assignments, Breakout Board

J1 Pin Number

Signal

Function

1

RST

Reset

ꢀ

3

SCLK

CS

SPI

4

2

6

DOUT

NC

DIN

SPI

No connect

SPI

7

8

9

15

11

1ꢀ

13

14

12

16

GND

VDD

DR

SYNC

NC

Ground

Power, 3.3 V

Data ready

Input clock

No connect

Figure 52 provides a top level view of the breakout board,

including dimensional locations for all the key mechanical

features, such as the mounting holes and the 16-pin header.

Figure 53 provides an electrical schematic for this breakout

board. For additional information, refer to the ADIS1647x/PCB

Wiki Guide.

Rev. D | Page 34 of 37

Data Sheet

ADIS16477

30.07mm

ADIS1647X/PCB

BREAKOUT BOARD

08-045113rA

5.125mm

J1

16.99mm

*

33.25mm

16.26mm

5.125mm

6.03mm

3.625mm

Figure 52. Top Level View of the Breakout Board

VDD

DUT1

C7

K6

VDD

J5

VDD

D6

VDD

H1

VDD

J4

VDD

D3

C3

GND

CS

GND

NC

F3

E3

RST

DIN

RST

VDD

F6

H6

H3

GND

SCLK

DR

J1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

RST

CS

G6

DIN

DOUT

SYNC

SCLK

DOUT

G3

CS

J6

J3

DR

SYNC

DIN

ADIS16477AMLZ

K8

K3

K1

J7

GND

VDD

A1

GND

A2

GND

A3

J2

GND

A4

H8

G7

G2

F8

F1

E7

E6

E2

C6

C2

GND

A5

DR

NC

GND

A6

SYNC

GND

A7

GND

A8

GND

B8

HIROSE

A3-16-PA-2SV(71)

GND

B3

GND

B4

GND

B5

GND

B6

GND

Figure 53. Breakout Board Schematic

IMU Evaluation Software for the EVAL-ADISX Platforms, the

EVAL-ADIS2 provides a simple, functional test platform that

allows users to configure and collect data from the ADIS16477

models.

PC-Based Evaluation, EVAL-ADIS2

In addition to supporting quick prototype connections between

the ADIS16477 and an embedded processing system, J1 on the

breakout board also connects directly to J1 on the EVAL-ADIS2

evaluation system. When used in conjunction with the

Rev. D | Page 32 of 37

ADIS16477

Data Sheet

TRAY DRAWING

The ADIS16477 parts are shipped in the tray shown in Figure 54.

322.60 REF

315.00

112.25

112.00

111.75

92.10

135.90

16.00

BSC

TOP VIEW

12.70

DETAIL A

11.95 BSC

22.00 BSC

14.50 BSC

DETAIL C

272.05

271.80

271.55

0.76

R 4.75

DETAIL C

DETAIL B

SIDE VIEW

21.40

3.80

1.30

2.54

2.50

17.90

34.30

25.40

2.00

255.30

30°

±1°

3.50

B

A

DETAIL B

15.43

15.35

15.27

11.43

11.35

11.27

A

11.10

NOTES:

1. MATERIAL IS MPPO.

2. TOLERANCES ARE x.x = ± 0.25

7.90

x.xx = ± 0.13

UNLESS OTHERWISE SPECITIED.

3. ESD

–

SURFACE RESISTIVITY

SECTION A-A

SECTION B-B

10⁵TO 10¹¹Ω/SQ.

C 3.00 × 0.45°

DETAIL A

B

Figure 54. Drawing of Shipping Tray

Rev. D | Page 36 of 37

Data Sheet

ADIS16477

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

11.25

11.00

10.75

1.055

BSC

1.270

BSC

A1 BALL

CORNER INDICATOR

1.785

BSC

1.270

BSC

15.25

15.00

14.75

0.900

Ø 0.750

0.600

TOP VIEW

END VIEW

BOTTOM VIEW

11.350

11.000

*10.475

0.90

MAX

*Including Lable

Thickness

SEATING

PLANE

Figure 55. 44-Ball Ball Grid Array Module [BGA]

(ML-44-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−45°C to +152°C

Package Description

Package Option

ADIS16477-1BMLZ

ADIS16477-ꢀBMLZ

ADIS16477-3BMLZ

ADIS16477-1/PCBZ

ADIS16477-ꢀ/PCBZ

ADIS16477-3/PCBZ

44-Ball Ball Grid Array Module [BGA]

ADIS16477-1 Breakout Board

ADIS16477-ꢀ Breakout Board

ADIS16477-3 Breakout Board

ML-44-1

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D1ꢀ437-4/20(D)

www.analog.com/ADIS16477

Rev. D | Page 37 of 37


型号：	ADIS16477-3PCBZ
厂家：	ADI
描述：	Precision, Miniature MEMs IMU
文件：	总37页 (文件大小：970K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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