ADIS16497 [ADI]
Tactical Grade, Six Degrees of Freedom Inertial Sensor;
| 型号： | ADIS16497 |
| 厂家： | 
ADI |
| 描述： | Tactical Grade, Six Degrees of Freedom Inertial Sensor |
| 文件： | 总43页 (文件大小：769K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Tactical Grade, Six Degrees of Freedom
Inertial Sensor
Data Sheet
ADIS16497
FEATURES
GENERAL DESCRIPTION
Triaxial, digital gyroscope
±12ꢀ°/sec, ±4ꢀ0°/sec, ±2000°/sec range options
±0.0ꢀ° axis to axis misalignment error
The ADIS16497 is a complete inertial system that includes a
triaxis gyroscope and a triaxis accelerometer. Each inertial sensor
in the ADIS16497 combines industry leading iMEMS® technology
±0.2ꢀ° (maximum) axis to package misalignment error
0.8°/hr in-run bias stability (ADIS16497-1)
0.09°/√hr angular random walk (ADIS16497-1)
Triaxial, digital accelerometer, ±40 g
with signal conditioning that optimizes dynamic performance.
The factory calibration characterizes each sensor for sensitivity,
bias, alignment, and linear acceleration (gyroscope bias). As a
result, each sensor has its own dynamic compensation formulas that
provide accurate sensor measurements.
13 μg in run bias stability
Triaxial, delta angle and delta velocity outputs
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +8ꢀ°C
SPI compatible
Programmable operation and control
Automatic and manual bias correction controls
Configurable FIR filters
Digital I/O: data ready, external clock
Sample clock options: internal, external, or scaled
On demand self test of inertial sensors
Single-supply operation: 3.0 V to 3.6 V
1ꢀ00 g mechanical shock survivability
Operating temperature range: −40°C to +10ꢀ°C
The ADIS16497 provides a simple, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at
the factory, greatly reducing system integration time. Tight
orthogonal alignment simplifies inertial frame alignment in
navigation systems. The serial peripheral interface (SPI) and
register structure provide a simple interface for data collection
and configuration control.
The footprint and connector system of the ADIS16497 enable a
simple upgrade from the ADIS16375, ADIS16480, ADIS16485,
ADIS16488A, and ADIS16490. The ADIS16497 is available in an
aluminum package that is approximately 47 mm × 44 mm ×
14 mm and includes a standard connector interface.
APPLICATIONS
Precision instrumentation, stabilization
Guidance, navigation, control
Avionics, unmanned vehicles
Precision autonomous machines, robotics
FUNCTIONAL BLOCK DIAGRAM
DIO1 DIO2 DIO3 DIO4 RST
VDD
POWER
MANAGEMENT
GND
SELF TEST
I/O
OUTPUT
DATA
CS
TRIAXIAL
GYROSCOPE
REGISTERS
SCLK
DIN
CALIBRATION
AND
FILTERS
TRIAXIAL
ACCELEROMETER
SPI
CONTROLLER
USER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
DOUT
CLOCK
ADIS16497
Figure 1.
Rev. D
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017-2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADIS16497
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Cyclical Redundancy Check (CRC-32)................................... 25
Delta Angles................................................................................ 26
Delta Velocity ............................................................................. 27
User Bias/Scale Adjustment...................................................... 29
Scratch Registers, USER_SCR_x.............................................. 32
Applications ...................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications .................................................................................... 4
Timing Specifications .................................................................. 6
Absolute Maximum Ratings ........................................................... 9
Thermal Resistance...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions .......................... 10
Typical Performance Characteristics........................................... 11
Theory of Operation ...................................................................... 13
Inertial Sensor Signal Chain ..................................................... 13
Register Structure....................................................................... 14
Serial Peripheral Interface......................................................... 15
Data Ready .................................................................................. 15
Reading Sensor Data.................................................................. 16
Device Configuration ................................................................ 17
User Register Memory Map.......................................................... 18
User Register Defintions ............................................................... 21
Page Number (PAGE_ID) ........................................................ 21
Data/Sample Counter (DATA_CNT)..................................... 21
Status/Error Flag Indicators (SYS_E_FLAG)......................... 21
Self Test Error Flags (DIAG_STS)........................................... 22
Internal Temperature (TEMP_OUT) ..................................... 22
Gyroscope Data .......................................................................... 22
Acceleration Data....................................................................... 24
Time Stamp................................................................................. 25
Flash Memory Endurance Counter, FLSHCNT_LOW,
FLSHCNT_HIGH...................................................................... 32
Global Commands, GLOB_CMD ........................................... 33
Auxiliary I/O Line Configuration, FNCTIO_CTRL............. 34
General-Purpose I/O Control, GPIO_CTRL......................... 35
Miscellaneous Configuration, CONFIG................................. 35
Linear Acceleration on Effect on Gyroscope Bias ................. 35
Decimation Filter, DEC_RATE ............................................... 35
Continuous Bias Estimation (CBE), NULL_CNFG.............. 36
Scaling the Input Clock (PPS Mode), SYNC_SCALE........... 36
FIR Filters.................................................................................... 37
Firmware Revision, FIRM_REV.............................................. 39
Firmware Revision Year, FIRM_Y .......................................... 39
Boot Revision Number, BOOT_REV...................................... 39
Continuous SRAM Testing....................................................... 39
Applications Information ............................................................. 41
Mounting Best Practices ........................................................... 41
Preventing Misinsertion............................................................ 41
Evaluation Tools......................................................................... 41
Power Supply Considerations .................................................. 41
CRC32 Coding Example ........................................................... 42
Outline Dimensions....................................................................... 43
Ordering Guide .......................................................................... 43
REVISION HISTORY
7/2020—Rev. C to Rev. D
1/2020—Rev. B to Rev. C
Changes to Table 1 ........................................................................... 5
Changes to Table 2 ........................................................................... 6
Changes to Flash Memory Update Section and On Demand Self
Test (ODST) Section...................................................................... 33
Changes to Data Ready Indicator Section .................................. 34
Changes to Scaling the Input Clock (PPS Mode),
Changes to Accelerometers, Sensitivity Parameter, Table 1.......1
6/2019—Rev. A to Rev. B
Changes to Features Section............................................................1
Changes to Specifications Section and Table 1.............................4
Changes to Figure 5 and Figure 6 ...................................................7
Changes to Table 6............................................................................9
Changes to Figure 12 ..................................................................... 10
SYNC_SCALE................................................................................. 36
Rev. D | Page 2 of 43
Data Sheet
ADIS16497
Added Figure 13 and Figure 14; Renumbered Sequentially .....10
Added Figure 15, Figure 16, Figure 17, Figure 18, Figure 19,
and Figure 20 ...................................................................................11
Changes to Theory of Operation Section ....................................12
Change to Serial Peripheral Interface Section.............................14
Changes to Burst Read Function Section and Table 10.............15
Changes to Table 11........................................................................16
Changes to Table 12........................................................................17
Changes to Model Column, Table 24...........................................21
Change to Delta Angle Measurement Range Section and Model
Column, Table 60............................................................................25
Changes to Delta Velocity Section................................................26
Changes to Continuous Bias Estimation (CBE), NULL_CNFG
Section and Description Column, Table 156..............................35
Added CRC32 Coding Example, Table 195, and Table 196;
Renumbered Sequentially..............................................................41
11/2017—Rev. 0 to Rev. A
Changes to Table 1............................................................................3
Changed t2 Parameter, Table 2; GLOB_CMD, Bit 3 Parameter,
GLOB_CMD, Bit 6 Parameter, and GLOB_CMD, Bit 7 Parameter,
Table 3 ................................................................................................5
10/2017—Revision 0: Initial Version
Rev. D | Page 3 of 43
ADIS16497
Data Sheet
SPECIFICATIONS
TC = 25°C, VDD = 3.3 V, angular rate = 0°/sec, ADIS16497-1 model, 1 g, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
12ꢀ
Typ
Max
Unit
GYROSCOPES
Dynamic Range
ADIS16497-1
°/sec
ADIS16497-2
4ꢀ5
4ꢁ5
°/sec
ADIS16497-3
2555
°/sec
Sensitivity
ADIS16497-1, 32-bit
ADIS16497-2, 32-bit
ADIS16497-3, 32-bit
154ꢁꢀ765
2621445
6ꢀꢀ365
5.1
5.2
5.2
LSB/°/sec
LSB/°/sec
LSB/°/sec
%
%
%
Degrees
Degrees
% FS
% FS
% FS
Error Over Temperature
ADIS16497-1, −45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
ADIS16497-2, −45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
ADIS16497-3, −45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
Axis to axis, −45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
Axis to package, −45°C ≤ TC ≤ +ꢁꢀ°C
1 σ, ADIS16497-1, FS = 12ꢀ°/sec
1 σ, ADIS16497-2, FS = 4ꢀ5°/sec
1 σ, ADIS16497-3, FS = 2555°/sec
Misalignment
Nonlinearity1
5.5ꢀ
5.2ꢀ
5.2
5.2
5.2ꢀ
Bias
Repeatability 2
In Run Bias Stability
−45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
1 σ, ADIS16497-1
5.57
5.ꢁ
°/sec
°/hr
1 σ, ADIS16497-2
1.6
°/hr
1 σ, ADIS16497-3
3.3
°/hr
Angular Random Walk
1 σ, ADIS16497-1
1 σ, ADIS16497-2
5.59
5.1
°/√hr
°/√hr
1 σ, ADIS16497-3
5.1ꢁ
5.1
°/√hr
°/sec
Error over Temperature
Linear Acceleration Effect
−45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
Any axis, 1 σ (CONFIG register, Bit 7 = 1)
Any axis, 1 σ (CONFIG register, Bit 7 = 5)
1 σ, ADIS16497-1
1 σ, ADIS16497-2
1 σ, ADIS16497-3
5.556
5.51ꢀ
5.5553
5.5554
5.5559
°/sec/g
°/sec/g
°/sec/g2
°/sec/g2
°/sec/g2
Vibration Rectification Error
Noise
Output Noise
No filtering, ADIS16497-1
No filtering, ADIS16497-2
No filtering, ADIS16497-3
1 σ, ADIS16497-1
1 σ, ADIS16497-2
1 σ, ADIS16497-3
5.5ꢀ1
5.5ꢀꢁ
5.112
5.552
5.5522
5.5542
4ꢁ5
°/sec rms
°/sec rms
°/sec rms
°/sec/√Hz rms
°/sec/√Hz rms
°/sec/√Hz rms
Hz
Rate Noise Density3
−3 dB Bandwidth
ADIS16497-1
ADIS16497-2, ADIS16497-3
ꢀꢀ5
Hz
Sensor Resonant Frequency
6ꢀ
kHz
Rev. D | Page 4 of 43
Data Sheet
ADIS16497
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ACCELEROMETERS4
Dynamic Range
Sensitivity
Each axis
45
g
32-bit data format
−45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
ꢀ2,42ꢁ,ꢁ55
5.51
LSB/g
%
Error Over Temperature
Misalignment
Nonlinearity
Axis to axis, −45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
Axis to package, −45°C ≤ TC ≤ +ꢁꢀ°C
Best fit straight line, 15 g
Best fit straight line, 25 g
Best fit straight line, 45 g
5.5ꢀ
Degrees
Degrees
% FS
% FS
% FS
5.2ꢀ
5.52
5.4
1.ꢀ
Bias
In Run Bias Stability
Velocity Random Walk
Error over Temperature
Repeatability
1 σ
1 σ
13
5.54
5.ꢀ
6
μg
m/sec/√hr
mg
mg
−45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
−45°C ≤ TC ≤ +ꢁꢀ°C, 1 σ
Noise
Output Noise
Noise Density
−3 dB Bandwidth
Sensor Resonant Frequency
TEMPERATURE SENSOR
Scale Factor
No filtering
15 Hz to 45 Hz, no filtering
2.6
ꢁꢁ
7ꢀ5
ꢀ.ꢀ
mg rms
μg/√Hz rms
Hz
kHz
Output = 5x5555 at 2ꢀ°C ( ꢀ°C)
5.512ꢀ
°C/LSB
LOGIC INPUTSꢀ
Input Voltage
High, VIH
Low, VIL
RST Pulse Width
Input Current
2.5
1
V
V
ꢂs
5.ꢁ
Logic 1, IIH
Logic 5, IIL
All Pins Except RST, CS
RST, CS Pins6
VIH = 3.3 V
VIL = 5 V
15
15
ꢂA
ꢂA
mA
pF
5.33
15
Input Capacitance, CIN
DIGITAL OUTPUTSꢀ
Output Voltage
High, VOH
ISOURCE = 5.ꢀ mA
ISINK = 2.5 mA
Endurance7
TJ = ꢁꢀ°C
2.4
V
V
Low, VOL
5.4
FLASH MEMORY
Data Retentionꢁ
FUNCTIONAL TIMES9
155,555
25
Cycles
Years
Time until data is available, −45°C ≤ TC ≤
+ꢁꢀ°C, 1 σ
Power-On Start-Up Time
Reset Recovery Time15
26ꢀ
22ꢀ
26ꢀ
ms
ms
ms
GLOB_CMD, Bit 7 = 1 (see Table 142)
RST pulled low, then restored to high
Flash Memory
Update Time
Clear User Calibration
Self Test Time
GLOB_CMD, Bit 3 = 1 (see Table 142)
GLOB_CMD, Bit 6 = 1 (see Table 142)
GLOB_CMD, Bit 1 = 1 (see Table 142)
1355
3ꢀ5
35
ms
ꢂs
ms
Rev. D | Page ꢀ of 43
ADIS16497
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
4.2ꢀ
5.52
45
Max
Unit
kSPS
%
ppm/°C
kHz
Hz
CONVERSION RATE
Initial Clock Accuracy
Temperature Coefficient
Sync Input Clock
Pulse Per Second (PPS) Mode
POWER SUPPLY, VDD
Power Supply Current11
3.5
1
4.ꢀ
12ꢁ
3.6
Operating voltage range
Normal mode, VDD = 3.3 V, ꢂ + σ
3.5
V
mA
ꢁ9
1 FS = full scale, FS = 12ꢀ°/sec (ADIS16497-1), FS = 4ꢀ5°/sec (ADIS16497-2), FS = 2555°/sec (ADIS16497-3).
2 Bias repeatability provides an estimate for long-term drift in the bias, as observed during ꢀ55 hours of high temperature operating life (HTOL) at +15ꢀC.
3 Magnitude between 15 and 45 Hz, sample rate is 42ꢀ5 SPS (nominal), no digital filtering.
4 All specifications associated with the accelerometers relate to the full-scale range of 45 g.
ꢀ The digital I/O signals use a 3.3 V system.
6 RST
CS
and
pins are connected to the VDD pin through 15 kΩ pull-up resistors.
7 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −45°C, +2ꢀ°C, +ꢁꢀ°C, and +12ꢀ°C.
ꢁ The data retention specification assumes a junction temperature (TJ) of ꢁꢀ°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ.
9 These times do not include thermal settling and internal filter response times, which can affect overall accuracy.
15
RST
The
line must be in a low state for at least 15 μs to ensure a proper reset initiation and recovery.
11 Supply current transients can reach 2ꢀ5 mA during initial startup or reset recovery.
TIMING SPECIFICATIONS
TC = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
Burst Read Function
Parameter
Description
Min1
5.51
ꢀ
Typ
Max1
Min
Typ
Max1
Unit
MHz
ꢂs
ns
ns
fSCLK
tSTALL
SCLK frequency
1ꢀ
6.ꢀ
2
Stall period between data
SCLK low period
SCLK high period
CS to SCLK edge
N/A3
tCLS
tCHS
tCS
31
31
32
31
31
32
ns
tDAV
tDSU
tDHD
tDR, tDF
tDSOE
tHD
tSFS
tDSHI
tNV
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
DOUT rise/fall times, ≤155 pF loading
CS assertion to DOUT active
SCLK edge to DOUT invalid
Last SCLK edge to CS deassertion
CS deassertion to DOUT high impedance
Data invalid time
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ꢂs
ꢂs
ꢂs
ꢂs
2
2
2
2
3
ꢁ
11
3
ꢁ
11
5
5
5
32
5
5
32
5
9
9
25
25
t1
t2
t3
Input sync pulse width
Input sync to data invalid
Input sync period4
ꢀ
ꢀ
356
356
222.2
222.2
1 Guaranteed by design and characterization, but not tested in production.
2 See Table 3 for exceptions to the stall time rating. Note that an insufficient stall time results in reading all 5s for the register attempting to be read.
3 N/A means not applicable.
4 This measurement represents the inverse of the maximum frequency for the input sample clock: 4ꢀ55 Hz.
Rev. D | Page 6 of 43
Data Sheet
ADIS16497
Register Specific Stall Times
Table 3.
Parameter
Description
Min1
Typ
Max
Unit
STALL TIME
FNCTIO_CTRL
FILTR_BNK_5
FILTR_BNK_1
NULL_CNFG
SYNC_SCALE
DEC_RATE
GPIO_CTRL
CONFIG
GLOB_CMD, Bit 1
GLOB_CMD, Bit 3
GLOB_CMD, Bit 6
GLOB_CMD, Bit 7
Configure the DIOx functions
Enable/select finite impulse response (FIR) filter banks
Enable/select FIR filter banks
Configure autonull bias function
Configure input clock scale factor
Configure decimation rate
Configure general-purpose input/output (I/O) lines
Configure miscellaneous functions
On demand self test
345
6ꢀ
6ꢀ
μs
μs
μs
μs
μs
μs
μs
μs
ms
ms
μs
ms
71
345
345
4ꢀ
4ꢀ
25
1125
3ꢀ5
215
Flash memory update
Clear user calibration
Software reset
1 Monitoring the data ready signal (see Table 144 for FNCTIO_CTRL configuration) for the return of regular pulsing can help minimize system wait times.
Timing Diagrams
CS
tCHS
tCLS
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
DOUT
tDSOE
tDAV
tHD
tDR
tDSHI
MSB
DB14
tDSU
DB13
DB12
DB11
DB10
DB2
DB1
tDF
LSB
LSB
tDHD
DIN
R/W
A6
A5
A4
A3
A2
D2
D1
Figure 2. SPI Timing and Sequence
tSTALL
CS
SCLK
Figure 3. Stall Time and Data Rate
t3
t2
DIO4
(SYNC CLOCK)
t1
DATA
READY
tNV
OUTPUT
REGISTERS
DATA VALID
DATA VALID
Figure 4. Input Clock Timing Diagram, FNCTIO_CTRL, Bits[7:4] = 0xFD
Rev. D | Page 7 of 43
ADIS16497
Data Sheet
CS
SCLK
DIN
7C00
DOUT
0000
1
BURST_ID
2
X_GYRO_OUT
3
CRC_UPR
19
0
Figure 5. Burst Read Function Sequence Diagram, 19 Segments
CS
SCLK
DIN
0x7C00
0000
1
BURST_ID
2
BURST_ID
3
X_GYRO_LOW
4
CRC_UPR
20
DOUT
Figure 6. Burst Read Function Sequence Diagram, 20 Segments
Rev. D | Page ꢁ of 43
Data Sheet
ADIS16497
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Pay careful attention
to PCB thermal design.
Parameter
Rating
Mechanical Shock Survivability
Any Axis, Unpowered
Any Axis, Powered
1ꢀ55 g
1ꢀ55 g
θ
JA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
JC is the junction to case thermal resistance.
VDD to GND
−5.3 V to +3.6 V
−5.3 V to VDD + 5.2 V
−5.3 V to VDD + 5.2 V
−45°C to +15ꢀ°C
−ꢀꢀ°C to +1ꢀ5°C
2 bar
Digital Input Voltage to GND
Digital Output Voltage to GND
Operating Temperature Range
Storage Temperature Range1
Barometric Pressure
θ
The ADIS16497 is a multichip module, which includes many
active components. The values in Table 5 identify the thermal
response of the hottest component inside of the ADIS16497,
with respect to the overall power dissipation of the module.
This approach enables a simple method for predicting the
temperature of the hottest junction, based on either ambient or
case temperature.
1 Extended exposure to temperatures that are lower than −45°C or higher
than +15ꢀ°C can adversely affect the accuracy of the factory calibration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
For example, when TA = 70°C, the hottest junction inside of the
ADIS16497 is 76.7°C.
TJ = θJA × VDD × IDD + 70°C
TJ = 22.8°C/W × 3.3 V × 0.089 A + 70°C
TJ = 76.7°C
Table 5. Package Characteristics
Package Type
θJA
θJC
Device Weight
ML-24-91
35.7°C/W
25.9°C/W
42 g
1 Thermal impedance simulated values come from a case with 4 M2 × 5.4 mm
machine screws (torque = 25 inch ounces). Secure the ADIS16497 to the
PCB.
ESD CAUTION
Rev. D | Page 9 of 43
ADIS16497
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADIS16497
TOP VIEW
(Not to Scale)
24 22 20 18 16 14 12 10
8
7
6
5
4
3
2
1
PIN 23
PIN 1
23 21 19 17 15 13 11
9
NOTES
1. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT
FOR THE MATING SOCKET CONNECTOR.
2. THE ACTUAL CONNECTOR PINS ARE NOT VISIBLE FROM
THE TOP VIEW.
3. MATING CONNECTOR: SAMTEC CLM-112-02 OR EQUIVALENT.
4. DNC = DO NOT CONNECT.
5. PIN 12 AND PIN 15 ARE NOT PHYSICALLY PRESENT.
PIN 1 PIN 2
Figure 7. Pin Configuration
Figure 8. Axial Orientation (Top Side Facing Up)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic Type
Description
1
2
3
4
ꢀ
6
DIO3
DIO4
SCLK
DOUT
DIN
Input/output
Input/output
Input
Output
Input
Configurable Digital Input/Output 3.
Configurable Digital Input/Output 4.
SPI Serial Clock.
SPI Data Output. Clocks output on the SCLK falling edge.
SPI Data Input. Clocks input on the SCLK rising edge.
SPI Chip Select.
CS
Input
7
ꢁ
DIO1
RST
Input/output
Input
Configurable Digital Input/Output 1.
Reset.
9
DIO2
VDD
NO PIN
GND
Input/output
Supply
Configurable Digital Input/Output 2.
Power Supply.
15, 11
12, 1ꢀ
13, 14
Not applicable No Pin. These pins are not physically present.
Supply Power Ground.
16 to 22, 24 DNC
23 DNC
Not applicable Do Not Connect. Do not connect to these pins.
Not applicable Do Not Connect. Do not connect to this pin. This pin can tolerate connection to the VDD supply.
Rev. D | Page 15 of 43
Data Sheet
ADIS16497
TYPICAL PERFORMANCE CHARACTERISTICS
1000
1000
100
10
X-AXIS
X-AXIS
Y-AXIS
Z-AXIS
Y-AXIS
Z-AXIS
100
10
1
1
0.1
0.001
0.01
0.1
1
10
100
1000 10000 100000
0.1
0.001
0.01
0.1
1
10
100
1000 10000 100000
INTEGRATION PERIOD (Seconds)
INTEGRATION PERIOD (Seconds)
Figure 9. Gyroscope Allan Deviation, ADIS16497-1
Figure 12. Accelerometer Allan Deviation
1000
0.15
0.10
0.05
0
X-AXIS
MEAN + 1σ
MEAN
MEAN – 1σ
Y-AXIS
Z-AXIS
100
10
1
–0.05
–0.10
–0.15
0.1
0.001
0.01
0.1
1
10
100
1000 10000 100000
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
INTEGRATION PERIOD (Seconds)
Figure 10. Gyroscope Allan Deviation, ADIS16497-2
Figure 13. Gyroscope Sensitivity Error vs. Temperature, Cold to Hot,
ADIS16497-2
1000
100
10
0.05
X-AXIS
Y-AXIS
Z-AXIS
0
–0.05
–0.10
–0.15
1
–0.20
MEAN + 1σ
MEAN
MEAN – 1σ
–0.25
–40
0.1
0.001
0.01
0.1
1
10
100
1000 10000 100000
–20
0
20
40
60 80
TEMPERATURE (°C)
INTEGRATION PERIOD (Seconds)
Figure 14. Gyroscope Sensitivity Error vs. Temperature, Hot to Cold,
ADIS16497-2
Figure 11. Gyroscope Allan Deviation, ADIS16497-3
Rev. D | Page 11 of 43
ADIS16497
Data Sheet
0.020
0.015
0.010
0.005
0
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
–0.18
–0.20
–0.005
–0.010
–0.015
–0.020
MEAN + 1σ
MEAN
MEAN – 1σ
MEAN + 1σ
MEAN
MEAN – 1σ
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Accelerometer Sensitivity vs. Temperature, Cold to Hot,
ADIS16497-2
Figure 18. Gyroscope Sensitivity Error vs. Temperature, Hot to Cold,
ADIS16497-3
0.020
0.015
0.010
0.005
0
0.05
MEAN + 1σ
MEAN
MEAN – 1σ
0.04
0.03
0.02
0.01
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.005
–0.010
MEAN + 1σ
MEAN
MEAN – 1σ
–0.015
–0.020
–40
–20
0
20
40
60 80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Accelerometer Sensitivity vs. Temperature, Hot to Cold,
ADIS16497-2
Figure 19. Accelerometer Sensitivity Error vs. Temperature, Cold to Hot,
ADIS16497-3
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
0.10
MEAN + 1σ
MEAN
MEAN – 1σ
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.16
MEAN + 1σ
MEAN
MEAN – 1σ
–0.18
–0.20
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Gyroscope Sensitivity Error vs. Temperature, Cold to Hot,
ADIS16497-3
Figure 20. Accelerometer Sensitivity Error vs. Temperature, Hot to Cold,
ADIS16497-3
Rev. D | Page 12 of 43
Data Sheet
ADIS16497
THEORY OF OPERATION
The ADIS16497 is an autonomous sensor system. A power-on
self test begins automatically after the voltage on the power
supply pins reaches a minimum safe level as defined by Table 1.
After the automatic power-on self test, the ADIS16497 begins
sampling, processing, and loading calibrated sensor data into
the output registers which are accessible using the SPI port.
External Clock Options
The ADIS16497 offers two modes of operation to control data
production with an external clock: sync mode and PPS mode. In
sync mode, the external clock directly controls the data sampling
and production clock (fSM in Figure 22 and Figure 23). In PPS
mode, the user can provide a lower input clock rate (1 Hz to
128 Hz) and use a scale factor (SYNC_SCALE register, see
Table 154) to establish a data collection and processing rate
that is between 3000 Hz and 4250 Hz for best performance.
INERTIAL SENSOR SIGNAL CHAIN
Figure 21 shows the basic signal chain for the inertial sensors in
the ADIS16497, which processes data at a rate of 4250 SPS
when using the internal sample clock. Using one of the external
clock options in FNCTIO_CTRL, Bits[7:4] (see Table 144) can
provide flexibility in selecting this rate.
Inertial Sensor Calibration
The calibration function for the gyroscopes and the
accelerometers has two components: factory calibration and
user calibration (see Figure 24).
OUTPUT
MEMS
SENSORS
CALIBRATION
FILTERING
DATA
FROM
SENSORS
FACTORY
CALIBRATION
USER
CALIBRATION
TO
FILTERING
REGISTERS
Figure 24. Gyroscope Calibration Processing
Figure 21. Signal Processing Diagram, Inertial Sensors
Gyroscope Factory Calibration
Gyroscope Data Sampling
Gyroscope factory calibration applies the following correction
formula to the data of each gyroscope:
The ADIS16497 produces angular rate measurements around
three orthogonal axes (x, y, and z). Figure 22 shows the basic
signal flow for the production of x-axis gyroscope data (same as
y-axis and z-axis). This signal chain contains two digital MEMS
gyroscopes (XG1 and XG2), which have their own ADC and sample
clocks (fSGX1 and fSGX2 = 4100 Hz) that produce data independently
from each other. The sensor to sensor tolerance on this sample rate
is 200 samples per second (SPS). Processing these data starts with
combining (summation and rescale) the most recent sample from
each gyroscope together by using an independent sample master
frequency (fSM) clock (fSM = 4250 Hz, see Figure 22), which drives
the rest of the digital signal processing (calibration, alignment,
and filtering) for the gyroscopes and accelerometers.
XC
X
b
m11 m12 m13
m21 m22 m23
m31 m32 m33
ω
ω
ω
ω
X
bY
bZ
YC
Y
ω ZC
ω Z
(1)
a'
g11 g12 g13
X
g 21 g 22 g 23 a'Y
g31 g32 g33
a'Z
where:
ωXC, ωYC, and ωZC are the postcalibration gyroscope data.
m11, m12, m13, m21, m22, m23, m31, m32, and m33 are the scale and
alignment correction factors.
ωX, ωY, and ωZ are the precalibration gyroscope data.
bX, bY, and bZ are the bias correction factors.
g11, g12, g13, g21, g22, g23, g31, g32, and g33 are the linear g correction
factors.
a'X, a'Y, and a'Z are the postcalibration accelerometer data.
MEMS
X-AXIS
RATE DATA
SAMPLE 1
GYROSCOPE
ADC
X
G1
X-AXIS
ANGULAR RATE
DATA PROCESSING
fSGX1 = 4100Hz
X-AXIS
RATE DATA
SAMPLE 2
MEMS
GYROSCOPE
ADC
X
G2
All the correction factors in each matrix/array are derived from
direct observation of the response of each gyroscope to a variety
of rotation rates at multiple temperatures across the calibration
temperature range (−40°C ≤ TC ≤ +85°C). These correction factors
are stored in the flash memory bank, but they are not available for
observation. Register CONFIG, Bit 7 provides an on/off control
for the linear g compensation (see Table 148). See Figure 45 for
more details on the user calibration options that are available
for the gyroscopes.
fSGX2 = 4100Hz
fSM = 4250Hz
Figure 22. Gyroscope Data Sampling
Accelerometer Data Sampling
The ADIS16497 produces linear acceleration measurements
along the same orthogonal axes (x, y, and z) as the gyroscopes,
using the same clock (fSM, see Figure 22 and Figure 23) that
triggers data acquisition and subsequent processing of the
gyroscope data.
X-AXIS
MEMS
ACCELEROMETER
X-AXIS
ACCELERATION
DATA PROCESSING
ADC
fSM = 4250SPS
Figure 23. Accelerometer Data Sampling
Rev. D | Page 13 of 43
ADIS16497
Data Sheet
The decimation filter averages multiple samples together to
Accelerometer Factory Calibration
produce each register update. In this type of filter structure, the
number of samples in the average is equal to the reduction in the
update rate for the output data registers. See the DEC_RATE
register for the user controls for this filter (see Table 150).
The accelerometer factory calibration applies the following
correction formulas to the data of each accelerometer:
b
a'
m11 m12
m
a
X
13
X
X
a'Y m21 m22 m23 aY bY
REGISTER STRUCTURE
a'Z
m31 m32 m33
aZ
bZ
All communication with the ADIS16497 involves accessing its
user registers. The register structure contains both output data
and control registers. The output data registers include the
latest sensor data, error flags, and identification data. The
control registers include sample rate, filtering, I/O, calibration,
and diagnostic configuration options. All communication
between the ADIS16497 and an external processor involves
either reading or writing to one of the user registers.
(2)
2
0
p21
p12
0
p
13
XC
p23 Y2C
2
p31 p32
0
ZC
where:
a'X, a'Y, and a'Z are the postcalibration accelerometer data.
m11, m12, m13, m21, m22, m23, m31, m32, and m33 are the scale and
alignment correction factors.
aX, aY, and aZ are the precalibration accelerometer data.
bX, bY, and bZ are the bias correction factors.
0, p12, p13, p21, p23, p31, and p32 are the point of percussion
correction factors
TRIAXIAL
OUTPUT
GYROSCOPE
ADC
DSP
REGISTERS
TRIAXIAL
ACCELEROMETER
CONTROL
REGISTERS
TEMPERATURE
SENSOR
CONTROLLER
ω2XC, ω2YC, and ω2ZC are the postcalibration gyroscope data
(squared).
All the correction factors in each matrix/array are derived from
direct observation of the response of each accelerometer to a
variety of inertial test conditions at multiple temperatures across
the calibration temperature range (−40°C ≤ TC ≤ +85°C). These
correction factors are stored in the flash memory bank, but they
are not available for observation. Register CONFIG, Bit 6 provides
an on/off control for the point of percussion alignment (see
Table 148). See Figure 46 for more details on the user calibration
options that are available for the accelerometers.
Figure 26. Basic Operation
The register structure uses a paged addressing scheme that
contains 13 pages, with each page containing 64 register
locations. Each register is 16 bits wide, with each byte having its
own unique address within the memory map of that page. The SPI
port has access to one page at a time, using the bit sequence in
Figure 27. Select the page to activate for SPI access by writing its
code to the PAGE_ID register. Read the PAGE_ID register to
determine which page is currently active. Table 7 displays the
PAGE_ID contents for each page and their basic functions. The
PAGE_ID register is located at Address 0x00 on every page.
Filtering
After calibration, the data of each inertial sensor passes through
two digital filters, both of which have user configurable
attributes: FIR and decimation (see Figure 25).
Table 7. User Register Page Assignments
Page PAGE_ID Function
TO
5
1
2
3
4
5x55
5x51
5x52
5x53
5x54
Output data, clock, identification
Reserved
Calibration
FROM
CALIBRATION
FIR
FILTER
DECIMATION
FILTER
DATA
REGISTERS
Figure 25. Inertial Sensor Filtering
Control: sample rate, filtering, I/O
The FIR filter includes four banks of coefficients that have
120 taps each. Register FILTR_BNK_0 (see Table 158) and
Register FILTR_BNK_1 (see Table 160) provide the configuration
options for the use of the FIR filters of each inertial sensor. Each
FIR filter bank includes a preconfigured filter, but the user can
design their own filters and write over these values using the
register of each coefficient. For example, Table 163 provides the
details for the FIR_COEF_A071 register, which contains
Coefficient 71 in FIR Bank A. Refer to Figure 49 for the
frequency response of the factory default filters. These filters do
not represent any specific application environment; they are
only examples.
Serial number, cyclic redundancy check (CRC)
values
ꢀ
6
7
ꢁ
5x5ꢀ
5x56
5x57
5x5ꢁ
5x59
5x5A
5x5B
5x5C
FIR Filter Bank A, Coefficient 5 to Coefficient ꢀ9
FIR Filter Bank A, Coefficient 65 to Coefficient 119
FIR Filter Bank B, Coefficient 5 to Coefficient ꢀ9
FIR Filter Bank B, Coefficient 65 to Coefficient 119
FIR Filter Bank C, Coefficient 5 to Coefficient ꢀ9
FIR Filter Bank C, Coefficient 65 to Coefficient 119
FIR Filter Bank D, Coefficient 5 to Coefficient ꢀ9
FIR Filter Bank D, Coefficient 65 to Coefficient 119
9
15
11
12
Rev. D | Page 14 of 43
Data Sheet
ADIS16497
CS
SCLK
DIN
R/W A6
A5
R/W A6
A5
A4
A3
A2
A1
D9
A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
D15 D14 D13 D12 D11 D10
D15 D14 D13
NOTES
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE
FOR OTHER DEVICES.
Figure 27. SPI Communication Bit Sequence
SERIAL PERIPHERAL INTERFACE
DATA READY
The SPI provides access to all of the user accessible registers
(see Table 8) and typically connects to a compatible port on an
embedded processor platform. See Figure 28 for a diagram that
provides the most common connections between the ADIS16497
and an embedded processor.
The factory default configuration provides the user with a data
ready (DR) signal on the DIO2 pin, which pulses low when the
output data registers are updating (see Figure 29). In this config-
uration, connect DIO2 to an interrupt service pin on the
embedded processor, which triggers data collection, when this
signal pulses high. Register FNCTIO_CTRL, Bits[3:0] (see
Table 144), provides user configuration options for this
function.
I/O LINES ARE COMPATIBLE WITH
3.3V LOGIC LEVELS
3.3V
VDD
10
11
SYSTEM
PROCESSOR
SPI MASTER
DIO2
6
3
SS
CS
ADIS16497
INACTIVE
ACTIVE
SCLK
SCLK
MOSI
Figure 29. Data Ready, when FNCTIO_CTRL, Bits[3:0] = 1101 (default)
5
4
9
DIN
During the start-up and reset recovery processes, the DR signal
can exhibit transient behavior before data production begins.
Figure 30 provides an example of the DR behavior during
startup, and Figure 31 and Figure 32 provide examples of the
DR behavior during recovery from reset commands.
MISO
IRQ
DOUT
DIO2
13
14
Figure 28. Electrical Connection Diagram
TIME THAT VDD > 3V
Table 8. Generic Master Processor Pin Names and Functions
VDD
Mnemonic
Function
PULSING INDICATES
DATA PRODUCTION
SS
Slave select
IRQ
Interrupt request
Master output, slave input
Master input, slave output
Serial clock
DR
MOSI
MISO
SCLK
START-UP TIME
Figure 30. Data Ready Response During Startup
Embedded processors typically use control registers to
configure their serial ports for communicating with SPI slave
devices such as the ADIS16497. Table 9 provides a list of settings
that describe the SPI protocol of the ADIS16497. The
initialization routine of the master processor typically
establishes these settings using firmware commands to write
them into its serial control registers.
SOFTWARE RESET COMMAND
GLOB_CMD[7] = 1
DR PULSING
RESUMES
DR
RESET RECOVERY TIME
Table 9. Generic Master Processor SPI Settings
Processor Setting Description
Figure 31. Data Ready Response During Software Reset
(Register GLOB_CMD, Bit 7 = 1) Recovery
Master
ADIS16497 operates as slave
SCLK ≤ 1ꢀ MHz
SPI Mode 3
MSB First Mode
16-Bit Mode
Maximum serial clock rate
CPOL = 1 (polarity), CPHA = 1 (phase)
Bit sequence, see Figure 27 for coding
Shift register/data length
Rev. D | Page 1ꢀ of 43
ADIS16497
Data Sheet
Burst Read Function
RST PIN
RELEASED
The burst read function (BRF) provides a method for reading a
batch of data (status, temperature, gyroscopes, accelerometers,
time stamp/data counter, and CRC code), which does not
require a stall time between each 16-bit segment and only
requires one command on the DIN line to initiate. System
processors can execute the BRF by reading the BURST_CMD
register (DIN = 0x7C00) and then reading each segment of data
RST
DR
DR PULSING
RESUMES
RESET RECOVERY TIME
in the response, while holding the
line in a low state, until
RST
CS
Figure 32. Data Ready Response During Reset (
= 0) Recovery
after reading the last 16-bit segment of data. If the
high before the completion of all data acquisition, the data from
that read request is lost.
line goes
CS
READING SENSOR DATA
Reading a single register requires two 16-bit cycles on the SPI:
one to request the contents of a register and another to receive
those contents. The 16-bit command code (see Figure 27) for a
The BRF response (on the DOUT line) contains either 19 or 20
data segments (16-bits each), after the BRF request (DIN =
0x7C00) depending on the SCLK rate. Figure 5 and Table 10
illustrate the 19-segment case, while Figure 6 and in Table 11
illustrate the 20-segment case.
R
read request on the SPI has three parts: the read bit ( /W = 0),
the 7-bit address code for either address (upper or lower) of the
register, Bits[A6:A0], and eight don’t care bits, Bits[DC7:DC0].
Figure 33 provides an example that includes two register reads
in succession. This example starts with DIN = 0x1A00, to
request the contents of the Z_GYRO_OUT register, and follows
with 0x1800, to request the contents of the Z_GYRO_LOW
register (assuming PAGE_ID already equals 0x0000). The
sequence in Figure 33 also shows full duplex mode of
operation, which means that the ADIS16497 can receive
requests on DIN while also transmitting data out on DOUT
within the same 16-bit SPI cycle.
To manage that variation, use the transition from the
BURST_ID code (0xA5A5 in Table 10 and Table 11) to the
SYS_E_FLAG register, which is not equal to 0xA5A5, as an
identifier for when the ADIS16497 BRF response is starting.
Table 10. BRF Data Format (fSCLK < 3 MHz)1
Segment DIN
DOUT
5
5x7C55 N/A
1
2
3
4
ꢀ
6
7
ꢁ
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5x5555
5xAꢀAꢀ (BURST_ID)
SYS_E_FLAG
TEMP_OUT
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
DATA_CNT (FNCTIO_CTRL, Bits[ꢁ:7] ≠ 11)
TIME_STAMP (FNCTIO_CTRL, Bits[ꢁ:7] = 11)
CRC_LWR
NEXT
DIN
0x1A00
0x1800
ADDRESS
DOUT
Z_GYRO_OUT
Z_GYRO_LOW
Figure 33. SPI Read Example
Figure 34 provides an example of the four SPI signals when
reading the PROD_ID register (see Table 92) in a repeating
pattern. This pattern can be helpful when troubleshooting the
SPI interface setup and communications.
9
15
11
12
13
14
1ꢀ
16
17
CS
SCLK
DIN
DIN = 0111 1110 0000 0000 = 0x7E00
DOUT
DOUT = 0100 0000 0111 0001 = 0x4071 = 16497 (PROD_ID)
Figure 34. SPI Read Example, Second 16-Bit Sequence
1ꢁ
19
N/A
N/A
CRC_UPR
1 N/A means not applicable.
Rev. D | Page 16 of 43
Data Sheet
ADIS16497
CS
Table 11. BRF Data Format (fSCLK > 3.6 MHz)1
Segment DIN
DOUT
SCLK
DIN
5
5x7C55
N/A
0x90DC
0x91FE
1
2
3
4
ꢀ
6
7
ꢁ
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5x5555
Figure 35. SPI Sequence for Writing 0xFEDC to XG_BIAS_LOW
5xAꢀAꢀ (BURST_ID)
5xAꢀAꢀ (BURST_ID)
SYS_E_FLAG
Dual Memory Structure
The ADIS16497 uses a dual memory structure (see Figure 36),
with static random access memory (SRAM) supporting real-
time operation and flash memory storing operational code,
calibration coefficients, and user configurable register settings. The
manual flash update command (GLOB_CMD, Bit 3, see
Table 142) provides a single-command method for storing user
configuration settings into flash memory, for automatic recall
during the next power-on or reset recovery process. This portion of
the flash memory bank has two independent banks that operate
in a ping pong manner, alternating with every flash update.
During power-on or reset recovery, the ADIS16497 performs a
CRC on the SRAM and compares it to a CRC computation from
the same memory locations in flash memory. If this memory test
fails, the ADIS16497 resets and boots up from the other flash
memory location. SYS_E_FLAG, Bit 2 (see Table 18) provides
an error flag for detecting when the backup flash memory
supported the last power-on or reset recovery. Table 12 provides a
memory map for the user registers in the ADIS16497, which
includes flash backup support (indicated by yes or no in the
flash column).
TEMP_OUT
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
9
15
11
12
13
14
1ꢀ
16
17
1ꢁ
DATA_CNT (FNCTIO_CTRL, Bits[ꢁ:7] ≠ 11)
TIME_STAMP (FNCTIO_CTRL, Bits[ꢁ:7] = 11)
CRC_LWR
19
25
N/A
N/A
CRC_UPR
1 N/A means not applicable.
DEVICE CONFIGURATION
Each register contains 16 bits (two bytes); Bits[7:0] contain the
low byte and Bits[15:8] contain the high byte. Each byte has its
own unique address in the user register map (see Table 12).
Updating the contents of a register requires writing to its low
byte first and its high byte second. There are three parts to coding
a SPI command (see Figure 27), which writes a new byte of data
MANUAL
FLASH
BACKUP
NONVOLATILE
FLASH MEMORY
VOLATILE
SRAM
SPI ACCESS
(NO SPI ACCESS)
START-UP
RESET
R
to a register: the write bit ( /W = 1), the 7-bit address code for
the byte that this command is updating, and the new data for that
location, Bits[DC7:DC0]. Figure 35 provides a coding example for
writing 0xFEDC to the XG_BIAS_LOW register (see Table 106),
assuming PAGE_ID already equals 0x0002.
Figure 36. SRAM and Flash Memory Diagram
Rev. D | Page 17 of 43
ADIS16497
Data Sheet
USER REGISTER MEMORY MAP
Table 12. User Register Memory Map1
Register Name
R/W Flash Backup PAGE_ID Address
Default Register Description
PAGE_ID
Reserved
DATA_CNT
Reserved
SYS_E_FLAG
DIAG_STS
Reserved
R/W No
N/A N/A
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x55
5x51
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x55, 5x51
5x52, 5x53
5x54, 5x5ꢀ
5x56, 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C, 5x5D
5x5E, 5x5F
5x15, 5x11
5x12, 5x13
5x14, 5x1ꢀ
5x16, 5x17
5x1ꢁ, 5x19
5x1A, 5x1B
5x1C, 5x1D
5x1E, 5x1F
5x25, 5x21
5x22, 5x23
5x24, 5x2ꢀ
5x26, 5x27
5x2ꢁ, 5x29
5x2A, 5x2B
5x2C, 5x2D
5x5555
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Page identifier
Reserved
Data counter
Reserved
Output, system error flags (5x5555 if no errors)
Output, self test error flags (5x5555 if no errors)
Reserved
R
No
N/A N/A
R
R
No
No
N/A N/A
TEMP_OUT
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Output, temperature
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TIME_STAMP
CRC_LWR
Output, x-axis gyroscope, low word
Output, x-axis gyroscope, high word
Output, y-axis gyroscope, low word
Output, y-axis gyroscope, high word
Output, z-axis gyroscope, low word
Output, z-axis gyroscope, high word
Output, x-axis accelerometer, low word
Output, x-axis accelerometer, high word
Output, y-axis accelerometer, low word
Output, y-axis accelerometer, high word
Output, z-axis accelerometer, low word
Output, z-axis accelerometer, high word
Output, time stamp
Output, CRC-32 (32 bits), lower word
Output, CRC-32, upper word
Reserved
CRC_UPR
Reserved
N/A N/A
5x2E to 5x3F N/A
X_DELTANG_LOW
X_DELTANG_OUT
Y_DELTANG_LOW
Y_DELTANG_OUT
Z_DELTANG_LOW
Z_DELTANG_OUT
X_DELTVEL_LOW
X_DELTVEL_OUT
Y_DELTVEL_LOW
Y_DELTVEL_OUT
Z_DELTVEL_LOW
Z_DELTVEL_OUT
Reserved
BURST_CMD
PROD_ID
Reserved
PAGE_ID
Reserved
X_GYRO_SCALE
Y_GYRO_SCALE
Z_GYRO_SCALE
X_ACCL_SCALE
Y_ACCL_SCALE
Z_ACCL_SCALE
XG_BIAS_LOW
XG_BIAS_HIGH
R
R
R
R
R
R
R
R
R
R
R
R
No
No
No
No
No
No
No
No
No
No
No
No
5x45, 5x41
5x42, 5x43
5x44, 5x4ꢀ
5x46, 5x47
5x4ꢁ, 5x49
5x4A, 5x4B
5x4C, 5x4D
5x4E, 5x4F
5xꢀ5, 5xꢀ1
5xꢀ2, 5xꢀ3
5xꢀ4, 5xꢀꢀ
5xꢀ6, 5xꢀ7
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Output, x-axis delta angle, low word
Output, x-axis delta angle, high word
Output, y-axis delta angle, low word
Output, y-axis delta angle, high word
Output, z-axis delta angle, low word
Output, z-axis delta angle, high word
Output, x-axis delta velocity, low word
Output, x-axis delta velocity, high word
Output, y-axis delta velocity, low word
Output, y-axis delta velocity, high word
Output, z-axis delta velocity, low word
Output, z-axis delta velocity, high word
Reserved
Burst-read command
Output, product identification (16497d)
Reserved
Page identifier
Reserved
Calibration, scale, x-axis gyroscope
Calibration, scale, y-axis gyroscope
Calibration, scale, z-axis gyroscope
Calibration, scale, x-axis accelerometer
Calibration, scale, y-axis accelerometer
Calibration, scale, z-axis accelerometer
Calibration, bias, gyroscope, x-axis, low word
Calibration, bias, gyroscope, x-axis, high word
N/A N/A
5xꢀꢁ to 5x7B N/A
5x7C, 5x7D
5x7E, 5x7F
R
R
No
Yes
N/A
5x4571
N/A N/A
R/W No
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
5x55 to 5x7F N/A
5x55, 5x51
5x52, 5x53
5x54, 5x5ꢀ
5x56, 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C, 5x5D
5x5E, 5x5F
5x15, 5x11
5x12, 5x13
5x5555
N/A
5x5555
5x5555
5x5555
5x5555
5x5555
5x5555
5x5555
5x5555
Rev. D | Page 1ꢁ of 43
Data Sheet
ADIS16497
Register Name
YG_BIAS_LOW
YG_BIAS_HIGH
ZG_BIAS_LOW
ZG_BIAS_HIGH
XA_BIAS_LOW
XA_BIAS_HIGH
YA_BIAS_LOW
YA_BIAS_HIGH
ZA_BIAS_LOW
ZA_BIAS_HIGH
Reserved
USER_SCR_1
USER_SCR_2
USER_SCR_3
USER_SCR_4
FLSHCNT_LOW
FLSHCNT_HIGH
PAGE_ID
GLOB_CMD
Reserved
FNCTIO_CTRL
GPIO_CTRL
CONFIG
DEC_RATE
NULL_CNFG
SYNC_SCALE
RANG_MDL
Reserved
FILTR_BNK_5
FILTR_BNK_1
Reserved
FIRM_REV
FIRM_DM
FIRM_Y
BOOT_REV
PAGE_ID
Reserved
CAL_SIGTR_LWR
CAL_SIGTR_UPR
CAL_DRVTN_LWR
CAL_DRVTN_UPR
CODE_SIGTR_LWR
CODE_SIGTR_UPR
CODE_DRVTN_LWR
CODE_DRVTN_UPR
Reserved
SERIAL_NUM
Reserved
PAGE_ID
Reserved
FIR_COEF_Axxx3
R/W Flash Backup PAGE_ID Address
Default Register Description
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x52
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x53
5x54
5x54
5x54
5x54
5x54
5x54
5x54
5x54
5x54
5x54
5x54
5x54
5x54
5x5ꢀ
5x5ꢀ
5x5ꢀ
5x56
5x56
5x14, 5x1ꢀ
5x16, 5x17
5x1ꢁ, 5x19
5x1A, 5x1B
5x1C, 5x1D
5x1E, 5x1F
5x25, 5x21
5x22, 5x23
5x24, 5x2ꢀ
5x26, 5x27
5x5555
5x5555
5x5555
5x5555
5x5555
5x5555
5x5555
5x5555
5x5555
5x5555
Calibration, bias, gyroscope, y-axis, low word
Calibration, bias, gyroscope, y-axis, high word
Calibration, bias, gyroscope, z-axis, low word
Calibration, bias, gyroscope, z-axis, high word
Calibration, bias, accelerometer, x-axis, low word
Calibration, bias, accelerometer, x-axis, high word
Calibration, bias, accelerometer, y-axis, low word
Calibration, bias, accelerometer, y-axis, high word
Calibration, bias, accelerometer, z-axis, low word
Calibration, bias, accelerometer, z-axis, high word
Reserved
5x2ꢁ to 5x73 5x5555
5x74, 5x7ꢀ
5x76, 5x77
5x7ꢁ, 5x79
5x7A, 5x7B
5x7C, 5x7D
5x7E, 57F
5x5555
5x5555
5x5555
5x5555
N/A
N/A
5x5555
N/A
User Scratch Register 1
User Scratch Register 2
User Scratch Register 3
User Scratch Register 4
Diagnostic, flash memory count, low word
Diagnostic, flash memory count, high word
Page identifier
R
R
Yes
Yes
R/W No
No
5x55, 5x51
5x52, 5x53
5x54, 5x5ꢀ
5x56, 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C, 5x5D
5x5E, 5x5F
5x15, 5x11
5x12, 5x13
5x14, 5x1ꢀ
5x16, 5x17
5x1ꢁ, 5x19
W
Control, global commands
N/A N/A
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
R/W Yes
N/A
Reserved
5x555D Control, I/O pins, functional definitions
5x55X52 Control, I/O pins, general-purpose
5x55C5
5x5555
Control, clock, and miscellaneous correction
Control, output sample rate decimation
5x575A Control, automatic bias correction configuration
5x159A Control, input clock scaling (PPS mode)
R
N/A
N/A
N/A
Measurement range (model-specific) Identifier
Reserved
N/A N/A
R/W Yes
R/W Yes
N/A N/A
5x5555
5x5555
Filter selection
Filter selection
5x1A to 5x77 N/A
Reserved
R
R
R
R
Yes
Yes
Yes
Yes
5x7ꢁ, 5x79
5x7A, 5x7B
5x7C, 5x7D
5x7E, 5x7F
5x55, 5x51
5x52, 5x53
5x54, 5x5ꢀ
5x56, 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C, 5x5D
5x5E, 5x5F
5x15, 5x11
5x12, 5x13
N/A
N/A
N/A
N/A
5x5555
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Firmware revision
Firmware programming date (day/month)
Firmware programming date (year)
Boot loader revision
Page identifier
Reserved
Signature CRC, calibration coefficients, low word
Signature CRC, calibration coefficients, high word
Real-time CRC, calibration coefficients, low word
Real-time CRC, calibration coefficients, high word
Signature CRC, program code, low word
Signature CRC, program code, high word
Real-time CRC, program code, low word
Real-time CRC, program code, high word
Reserved
R/W No
N/A N/A
R
R
R
R
R
R
R
R
Yes
Yes
No
No
Yes
Yes
No
No
N/A N/A
Yes
5x14 to 5x1F N/A
5x25, 5x21 N/A
5x22 to 5x7F N/A
5x55, 5x51
5x52 to 5x57 N/A
5x5ꢁ to 5x7F N/A
R
Serial number
Reserved
N/A N/A
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
5x5555
Page identifier
Reserved
FIR Filter Bank A: Coefficient 5 through Coefficient ꢀ9
Page identifier
PAGE_ID
Reserved
5x55, 5x51
5x52 to 5x57 N/A
5x5555
Reserved
Rev. D | Page 19 of 43
ADIS16497
Data Sheet
Register Name
FIR_COEF_Axxx3
PAGE_ID
Reserved
FIR_COEF_Bxxx4
PAGE_ID
Reserved
FIR_COEF_Bxxx4
PAGE_ID
Reserved
FIR_COEF_Cxxxꢀ
PAGE_ID
Reserved
FIR_COEF_Cxxxꢀ
PAGE_ID
Reserved
FIR_COEF_Dxxx6
R/W Flash Backup PAGE_ID Address
Default Register Description
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
R/W No
N/A N/A
R/W Yes
5x56
5x57
5x57
5x57
5x5ꢁ
5x5ꢁ
5x5ꢁ
5x59
5x59
5x59
5x5A
5x5A
5x5A
5x5B
5x5B
5x5B
5x5C
5x5C
5x5C
5x5ꢁ to 5x7F N/A
5x55, 5x51
5x52 to 5x57 N/A
5x5ꢁ to 5x7F N/A
5x55, 5x51
5x52 to 5x57 N/A
5x5ꢁ to 5x7F N/A
5x55, 5x51
5x52 to 5x57 N/A
5x5ꢁ to 5x7F N/A
5x55, 5x51
5x52 to 5x57 N/A
5x5ꢁ to 5x7F N/A
5x55, 5x51
5x52 to 5x57 N/A
5x5ꢁ to 5x7F N/A
5x55, 5x51
FIR Filter Bank A: Coefficient 65 through Coefficient 119
5x5555
Page identifier
Reserved
FIR Filter Bank B: Coefficient 5 through Coefficient ꢀ9
5x5555
Page identifier
Reserved
FIR Filter Bank B: Coefficient 65 through Coefficient 119
5x5555
Page identifier
Reserved
FIR Filter Bank C: Coefficient 5 through Coefficient ꢀ9
5x5555
Page identifier
Reserved
FIR Filter Bank C: Coefficient 65 through Coefficient 119
5x5555
Page identifier
Reserved
FIR Filter Bank D: Coefficient 5 through Coefficient ꢀ9
Page identifier
PAGE_ID
Reserved
FIR_COEF_Dxxx6
5x5555
5x52 to 5x57 N/A
5x5ꢁ to 5x7F N/A
Reserved
FIR Filter Bank D: Coefficient 65 through Coefficient 119
1 N/A means not applicable.
2 The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting.
3 See the FIR Filter Bank A, FIR_COEF_A555 to FIR_COEF_A119 section for additional information.
4 See the FIR Filter Bank B, FIR_COEF_B555 to FIR_COEF_B119 section for additional information.
ꢀ See the FIR Filter Bank C, FIR_COEF_C555 to FIR_COEF_C119 section for additional information.
6 See the FIR Filter Bank D, FIR_COEF_D555 to FIR_COEF_D119 section for additional information.
Rev. D | Page 25 of 43
Data Sheet
ADIS16497
USER REGISTER DEFINTIONS
PAGE NUMBER (PAGE_ID)
Table 18. SYS_E_FLAG Bit Descriptions
The contents in the PAGE_ID register (see Table 13 and Table 14)
contain the current page setting, and provide a control for selecting
another page for SPI access. For example, set DIN = 0x8002 to
select Page 2 for SPI-based user access. See Table 12 for the page
assignments associated with each user accessible register.
Bits
Description
1ꢀ
Watchdog timer flag. A 1 indicates the ADIS16497
automatically resets itself to clear an issue.
[14:9] Not used.
ꢁ
Sync error. A 1 indicates the sample timing is not scaling
correctly, when operating in PPS mode (FNCTIO_CTRL,
Bit ꢁ = 1, see Table 144). When this error occurs, verify
that the input sync frequency is correct and that
SYNC_SCALE (see Table 1ꢀ4) has the correct value.
Table 13. PAGE_ID Register Definition
Page
Addresses Default Access Flash Backup
5x55
5x55, 5x51 5x5555 R/W No
7
6
Processing overrun. A 1 indicates the occurrence of a
processing overrun. Initiate a reset to recover. Replace
the ADIS16497 if this error persists.
Table 14. PAGE_ID Bit Descriptions
Bits
Description
Flash memory update failure. A 1 indicates that the most
recent flash memory update failed (GLOB_CMD, Bit 3, see
Table 142). Repeat the test and replace the ADIS16497 if
this error persists.
[1ꢀ:5]
Page number, binary numerical format
DATA/SAMPLE COUNTER (DATA_CNT)
ꢀ
Sensor failure. A 1 indicates failure in at least one of the
inertial sensors. Read the DIAG_STS register (see Table 25)
to determine which sensor is failing. Replace the
ADIS16497 if the error persists, when it is operating in
static inertial conditions.
The DATA_CNT register (see Table 15 and Table 16) is a continu-
ous, real-time, sample counter. It starts at 0x0000, increments
every time the output data registers update, and wraps around
from 0xFFFF (65,535 decimal) to 0x0000 (0 decimal).
4
3
Not used.
Table 15. DATA_CNT Register Definition
Page Addresses Default
SPI communication error. A 1 indicates that the total
number of SCLK cycles is not equal to an integer multiple
of 16. Repeat the previous communication sequence to
recover. Persistence in this error can indicate a weakness in
the SPI service from the master processor.
Access Flash Backup
5x55 5x54, 5x5ꢀ Not applicable
R
No
Table 16. DATA_CNT Bit Descriptions
Bits Description
[1ꢀ:5] Data counter, binary format
2
SRAM error condition. A 1 indicates a failure in the CRC
(period = 25 ms) between the SRAM and flash memory.
Initiate a reset to recover. Replace the ADIS16497 if this
error persists.
1
5
Boot memory failure. A 1 indicates that the device booted
up using code from the backup memory bank. Replace the
ADIS16497 if this error occurs.
STATUS/ERROR FLAG INDICATORS (SYS_E_FLAG)
The SYS_E_FLAG register (see Table 17 and Table 18) provides
various error flags. Reading this register causes all of its bits to
return to 0, with the exception of Bit 7. If an error condition
persists, its flag (bit) automatically returns to an alarm value of 1.
Not used.
Table 17. SYS_E_FLAG Register Definition
Page
Addresses Default Access Flash Backup
5x55
5x5ꢁ, 5x59 5x5555 No
R
Rev. D | Page 21 of 43
ADIS16497
Data Sheet
SELF TEST ERROR FLAGS (DIAG_STS)
GYROSCOPE DATA
SYS_E_FLAG, Bit 5 (see Table 18) contains the pass/fail result
(0 = pass) for the on demand self test (ODST) operations,
whereas the DIAG_STS register (see Table 19 and Table 20)
contains pass/fail flags (0 = pass) for each inertial sensor.
Reading the DIAG_STS register causes all of its bits to restore to 0.
The bits in DIAG_STS return to 1 if the error conditions persists.
The gyroscopes in the ADIS16497 measure the angular rate of
rotation around three orthogonal axes (x, y, and z). Figure 38
shows the orientation of each gyroscope axis, which defines the
direction of rotation that produces a positive response in each
of the angular rate measurements.
Each gyroscope has two output data registers. Figure 37 shows how
these two registers combine to support a 32-bit, twos complement
data format for the x-axis gyroscope measurements. This format
also applies to the y-axis and z-axis as well.
Table 19. DIAG_STS Register Definition
Page
Addresses
Default Access Flash Backup
5x55
5x5A, 5x5B
5x5555 No
R
X_GYRO_OUT
X_GYRO_LOW
15
0 15
0
Table 20. DIAG_STS Bit Descriptions
Bits Description (Default = 0x0000)
[1ꢀ:6] Not used
X-AXIS GYROSCOPE DATA
Figure 37. Gyroscope Output Data Structure
ꢀ
4
3
2
1
5
Self test failure, z-axis accelerometer (1 means failure)
Self test failure, y-axis accelerometer (1 means failure)
Self test failure, x-axis accelerometer (1 means failure)
Self test failure, z-axis gyroscope (1 means failure)
Self test failure, y-axis gyroscope (1 means failure)
Self test failure, x-axis gyroscope (1 means failure)
Gyroscope Measurement Range/Scale Factor
Table 24 provides the range and scale factor (KG) for the
angular rate (gyroscope) measurements in each ADIS16497
model.
Table 24. Gyroscope Measurement Range and Scale Factors
Model
Range
Scale Factor, KG
5.5562ꢀ°/sec/LSB
5.52ꢀ°/sec/LSB
5.1°/sec/LSB
INTERNAL TEMPERATURE (TEMP_OUT)
ADIS16497-1
ADIS16497-2
ADIS16497-3
12ꢀ°/sec
4ꢀ5°/sec
2555°/sec
The TEMP_OUT register (see Table 21 and Table 22) provides
a coarse measurement of the temperature inside of the ADIS16497,
and is useful for monitoring relative changes in the thermal
environment. Table 23 provides several examples of the data
format for the TEMP_OUT register.
Gyroscope Data Formatting
Table 25 and Table 26 offer various numerical examples that
demonstrate the format of the rotation rate data in both 16-bit
and 32-bit formats. See Table 24 for the scale factor (KG)
associated with each ADIS16497 model.
Table 21. TEMP_OUT Register Definition
Page Addresses Default
Access Flash Backup
5x55 5x5E, 5x5F
Not applicable
R
No
Table 25. 16-Bit Gyroscope Data Format Examples
Rotation Rate
Table 22. TEMP_OUT Bit Definitions
Bits
Description
(°/sec)
+15555 KG
+2 KG
+KG
5°/sec
−KG
Decimal Hex
Binary
[1ꢀ:5]
Temperature data; twos complement, 1°C per ꢁ5 LSB,
2ꢀ°C = 5x5555
+15,555
5x2715
5515 5111 5551 5555
5555 5555 5555 5515
5555 5555 5555 5551
5555 5555 5555 5555
1111 1111 1111 1111
1111 1111 1111 1115
1151 1555 1111 5555
+2
+1
5
−1
−2
−15,555
5x5552
5x5551
5x5555
5xFFFF
5xFFFE
5xDꢁF5
Table 23. TEMP_OUT Data Format Examples
Temperature (°C) Decimal Hex Binary
−2 KG
−15555 KG
+ꢁꢀ
+4ꢁ55
+2
+1
5
−1
5x12C5 5551 5515 1155 5555
5x5552 5555 5555 5555 5515
5x5551 5555 5555 5555 5551
5x5555 5555 5555 5555 5555
5xFFFF 1111 1111 1111 1111
5xFFFE 1111 1111 1111 1115
5xEBB5 1115 1511 1511 5555
+2ꢀ + 2/ꢁ5
+2ꢀ + 1/ꢁ5
+2ꢀ
+2ꢀ – 1/ꢁ5
+2ꢀ – 2/ꢁ5
−45
Table 26. 32-Bit Gyroscope Data Format Examples
Rotation Rate (°/sec)
+15555 KG
+KG/21ꢀ
Decimal
Hexadecimal
5x27155555
5x55555552
5x55555551
5x5555555
5xFFFFFFFF
5xFFFFFFFE
5xDꢁF55555
−2
−ꢀ255
+6ꢀꢀ,365,555
+2
+1
5
−1
−2
+KG/216
5
−KG /216
−KG /21ꢀ
−15555 KG
−6ꢀꢀ,365,555
Rev. D | Page 22 of 43
Data Sheet
ADIS16497
Z-AXIS
ω
Z
X-AXIS
Y-AXIS
ω
X
ω
Y
PIN 23
PIN 1
Figure 38. Gyroscope Axis and Polarity Assignments
X-Axis Gyroscope (X_GYRO_LOW, X_GRYO_OUT)
Table 32. Y_GYRO_LOW Bit Descriptions
The X_GYRO_LOW (see Table 27 and Table 28) and X_GRYO_
OUT (see Table 29 and Table 30) registers contain the gyroscope
data for the x-axis.
Bits
Description
[1ꢀ:5]
Y-axis gyroscope data; low word
Table 27. X_GYRO_LOW Register Definition
Table 33. Y_GYRO_OUT Register Definition
Page Addresses Default
Access Flash Backup
Page Addresses Default
Access Flash Backup
5x55 5x15, 5x11 Not applicable
R
No
5x55 5x16, 5x17 Not applicable
R
No
Table 34. Y_GYRO_OUT Bit Descriptions
Table 28. X_GYRO_LOW Bit Descriptions
Bits
Description
Bits
Description
[1ꢀ:5]
Y-axis gyroscope data; high word; twos complement,
5°/sec = 5x5555, see Table 24 for scale factor
[1ꢀ:5]
X-axis gyroscope data; low word
Z-Axis Gyroscope (Z_GYRO_LOW, Z_GYRO_OUT)
Table 29. X_GYRO_OUT Register Definition
Page Addresses Default
Access Flash Backup
The Z_GYRO_LOW (see Table 35 and Table 36) and Z_GRYO_
OUT (see Table 37 and Table 38) registers contain the gyroscope
data for the z-axis.
5x55 5x12, 5x13 Not applicable
R
No
Table 30. X_GYRO_OUT Bit Descriptions
Table 35. Z_GYRO_LOW Register Definition
Bits
Description
Page Addresses Default
Access Flash Backup
[1ꢀ:5]
X-axis gyroscope data; high word; twos complement,
5°/sec = 5x5555, see Table 24 for scale factor
5x55 5x1ꢁ, 5x19 Not applicable
R
No
Table 36. Z_GYRO_LOW Bit Descriptions
Y-Axis Gyroscope (Y_GYRO_LOW, Y_GYRO_OUT)
Bits
Description
The Y_GYRO_LOW (see Table 31 and Table 32) and Y_GRYO_
OUT (see Table 33 and Table 34) registers contain the gyroscope
data for the y-axis.
[1ꢀ:5]
Z-axis gyroscope data; additional resolution bits
Table 37. Z_GYRO_OUT Register Definition
Table 31. Y_GYRO_LOW Register Definition
Page Addresses Default
Access Flash Backup
Page Addresses Default
Access Flash Backup
5x55 5x1A, 5x1B Not applicable
R
No
5x55 5x14, 5x1ꢀ Not applicable
R
No
Table 38. Z_GYRO_OUT Bit Descriptions
Bits
Description
[1ꢀ:5]
Z-axis gyroscope data; high word; twos complement,
5°/sec = 5x5555, see Table 24 for scale factor
Rev. D | Page 23 of 43
ADIS16497
Data Sheet
Z-AXIS
aZ
X-AXIS
Y-AXIS
aX
aY
PIN 23
PIN 1
Figure 39. Accelerometer Axis and Polarity Assignments
ACCELERATION DATA
Y-Axis Accelerometer (Y_ACCL_LOW, Y_ACCL_OUT)
The accelerometers in the ADIS16497 measure both dynamic
and static (response to gravity) acceleration along three orthogonal
axes (x, y, and z). Figure 39 shows the orientation of each
accelerometer axis, which defines the direction of linear
acceleration that produces a positive response in each of the
angular rate measurements.
The Y_ACCL_LOW (see Table 43 and Table 44) and
Y_ACCL_ OUT (see Table 45 and Table 46) registers contain
the accelerometer data for the y-axis.
Table 43. Y_ACCL_LOW Register Definition
Page Addresses Default
Access Flash Backup
5x55 5x25, 5x21 Not applicable
R
No
Each accelerometer has two output data registers. Figure 40 shows
how these two registers combine to support a 32-bit, twos comple-
ment data format for the x-axis accelerometer measurements.
This format also applies to the y-axis and z-axis.
Table 44. Y_ACCL_LOW Bit Descriptions
Bits Description
[1ꢀ:5] Y-axis accelerometer data; low word
X_ACCL_OUT
X_ACCL_LOW
15
0 15
0
Table 45. Y_ACCL_OUT Register Definition
X-AXIS ACCELEROMETER DATA
Page Addresses Default
Access Flash Backup
Figure 40. Accelerometer Output Data Structure
5x55 5x22, 5x23 Not applicable
R
No
X-Axis Accelerometer (X_ACCL_LOW, X_ACCL_OUT)
The X_ACCL_LOW (see Table 39 and Table 40) and X_ACCL_
OUT (see Table 41 and Table 42) registers contain the
accelerometer data for the x-axis.
Table 46. Y_ACCL_OUT Bit Descriptions
Bits Description
[1ꢀ:5] Y-axis accelerometer data, high word; twos complement,
45 g range; 5 g = 5x5555, 1 LSB = 1.2ꢀ mg
Table 39. X_ACCL_LOW Register Definition
Page Addresses Default
Access Flash Backup
Z-Axis Accelerometer (Z_ACCL_LOW, Z_ACCL_OUT)
5x55 5x1C, 5x1D Not applicable
R
No
The Z_ACCL_LOW (see Table 47 and Table 48) and Z_ACCL_
OUT (see Table 49 and Table 50) registers contain the
accelerometer data for the z-axis.
Table 40. X_ACCL_LOW Bit Descriptions
Bits Description
Table 47. Z_ACCL_LOW Register Definition
[1ꢀ:5] X-axis accelerometer data; low word
Page Addresses Default
Access Flash Backup
5x55 5x24, 5x2ꢀ Not applicable
R
No
Table 41. X_ACCL_OUT Register Definition
Page Addresses Default
Access Flash Backup
Table 48. Z_ACCL_LOW Bit Descriptions
Bits Description
[1ꢀ:5] Z-axis accelerometer data; low word
5x55 5x1E, 5x1F Not applicable
R
No
Table 42. X_ACCL_OUT Descriptions
Bits Description
[1ꢀ:5] X-axis accelerometer data, high word; twos complement,
45 g range; 5 g = 5x5555, 1 LSB = 1.2ꢀ mg
Rev. D | Page 24 of 43
Data Sheet
ADIS16497
When using the decimation filter (DEC_RATE > 0x0000) the
value in the TIME_STAMP register represents the time of the
first sample (taken at the rate of fSM, per Figure 22 and Figure 23).
For example, when DEC_RATE = 0x0003, the decimation filter
reduces the update by a factor of four and the TIME_STAMP
register updates to 1 (decimal) during the first data update,
then to 5 on the second update, 9 on the third update, for
example; until the next clock signal pulse.
Table 49. Z_ACCL_OUT Register Definition
Page Addresses Default
Access Flash Backup
5x55 5x26, 5x27 Not applicable
R
No
Table 50. Z_ACCL_OUT Bit Descriptions
Bits Description
[1ꢀ:5] Z-axis accelerometer data, high word; twos complement,
45 g range; 5 g = 5x5555, 1 LSB = 1.2ꢀ mg
CYCLICAL REDUNDANCY CHECK (CRC-32)
The ADIS16497 performs a CRC-32 computation, using the
data registers that are shown in Table 55.
Accelerometer Resolution
Table 51 and Table 52 offer various numerical examples that
demonstrate the format of the linear acceleration data in both
16-bit and 32-bit formats.
Table 55. CRC-32 Source Data and Example Values
Register
Example Value
5x5555
5x5ꢁ3A
5x5555
5xFFF7
SYS_E_FLAG
TEMP_OUT
Table 51. 16-Bit Accelerometer Data Format Examples
Acceleration
Decimal
+32,555
+2
+1
5
Hex
Binary
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TIME_STAMP
+45 g
5x7D55 5111 1151 5555 5555
+2.ꢀ mg
+1.2ꢀ mg
5 mg
5x5552
5x5551
5x5555
5xFFFF
5xFFFE
5xꢁ355
5555 5555 5555 5515
5555 5555 5555 5551
5555 5555 5555 5555
1111 1111 1111 1111
1111 1111 1111 1115
1555 5511 5555 5555
5x5555
5xFFFE
5x5555
5x5551
5xꢀ551
5x5553
5xE55A
5x551ꢀ
5xC559
5x5325
5xꢁAꢀ4
−1.2ꢀ mg
−2.ꢀ mg
−45 g
−1
−2
−32,555
Table 52. 32-Bit Accelerometer Data Format Examples
Acceleration
Decimal
Hexadecimal
5x7D555555
5x55555552
5x55555551
5x55555555
5xFFFFFFFF
5xFFFFFFFE
5xꢁ3555555
+45 g
+2,597,1ꢀ2,555
+1.2ꢀ/21ꢀ mg
+1.2ꢀ/216 mg
5 mg
+2
+1
5
The CRC_LWR (see Table 56 and Table 57) and CRC_UPR (see
Table 58 and Table 59) registers contain the result of the CRC-32
computation. For the example, the register values from
Table 55 are,
−1.2ꢀ/216 mg
−1.2ꢀ/21ꢀ mg
−45 g
−1
−2
−2,597,1ꢀ2,555
CRC_LWR = 0x15B4
CRC_UPR = 0xB6C8
TIME STAMP
When using PPS mode (FNCTIO_CTRL, Bits[8:7] = 11 (binary),
see Table 144), the TIME_STAMP register (see Table 53 and
Table 54) provides the time between the most recent pulse on
the input clock signal and the most recent data update.
Table 56. CRC_LWR Register Definition
Page Addresses Default
Access Flash Backup
5x55 5x2A, 5x2B Not applicable
R
No
Table 53. TIME_STAMP Register Definition
Table 57. CRC_LWR Bit Descriptions
Page Addresses Default
Access Flash Backup
Bits
Description
5x55 5x2ꢁ, 5x29 Not applicable
R
No
[1ꢀ:5] CRC-32 code from most recent BRF, lower word
Table 54. TIME_STAMP Bit Descriptions
Bits Description
[1ꢀ:5] Time stamp, binary format.
Table 58. CRC_UPR Register Definition
Page Addresses Default
Access Flash Backup
5x55 5x2C, 5x2D Not applicable
R
No
1 LSB = 1/fSM (see Figure 22, Figure 23, and Table 1ꢀ4).
The leading edge of the input clock pulse resets the
value in this register to 5x5555.
Table 59. CRC_UPR Bit Descriptions
Bits Description
[1ꢀ:5] CRC-32 code from most recent BRF, upper word
Rev. D | Page 2ꢀ of 43
ADIS16497
Data Sheet
Z-AXIS
Δθ
Z
X-AXIS
Y-AXIS
Δθ
X
Δθ
Y
PIN 23
PIN 1
Figure 41. Delta Angle Axis and Polarity Assignments
Delta Angle Measurement Range
DELTA ANGLES
Table 60 offers the measurement range and scale factor for each
ADIS16497 model.
In addition to the angular rate of rotation (gyroscope) measure-
ments around each axis (x, y, and z), the ADIS16497 also provides
delta angle measurements that represent a computation of
angular displacement between each sample update. Figure 41
shows the orientation of each delta angle output, which defines
the direction of rotation that produces a positive response in
each of the angular displacement (delta angle) measurements.
Table 60. Delta Angle Measurement Range and Scale Factor
Model
Measurement Range, ±±θMAX
ADIS16497-1
ADIS16497-2
ADIS16497-3
365°
725°
2165°
The delta angle outputs represent an integration of the gyro-
scope measurements and use the following formula for all three
axes (x-axis displayed):
X-Axis Delta Angle (X_DELTANG_LOW, X_DELTANG_OUT)
The X_DELTANG_LOW (see Table 61 and Table 62) and
X_DELTANG_OUT (see Table 63 and Table 64) registers
contain the delta angle data for the x-axis.
D 1
1
x,n D
x,n D d 1
x,n D d
2 fS
d 0
where:
Table 61. X_DELTANG_LOW Register Definitions
ΔθX is the delta angle measurement for the x-axis
D is the decimation rate = DEC_RATE + 1 (see Table 150).
fS is the sample rate.
Page Addresses Default
Access Flash Backup
5x55 5x45, 5x41 Not applicable
R
No
d is the incremental variable in the summation formula.
ωx is the x-axis rate of rotation (gyroscope).
n is the sample time, prior to the decimation filter.
Table 62. X_DELTANG_LOW Bit Descriptions
Bits
Description
[1ꢀ:5]
X-axis delta angle data; low word
When using the internal sample clock, fS is equal to 4250 SPS.
When using the external clock option, fS is equal to the frequency
of the external clock. The range in the delta angle registers
accommodates the maximum rate of rotation (100°/sec), the
nominal sample rate (4250 SPS), and an update rate of 1 Hz
(DEC_RATE = 0x1099; divide by 4249 plus 1, see Table 150),
all at the same time. When using an external clock that is
higher than 4250 SPS, reduce the DEC_RATE setting to
avoid over-ranging the delta angle registers.
Table 63. X_DELTANG_OUT Register Definitions
Page Addresses Default
Access Flash Backup
5x55 5x42, 5x43 Not applicable
R
No
Table 64. X_DELTANG_OUT Bit Descriptions
Bits Description
[1ꢀ:5] X-axis delta angle data; twos complement, 5° = 5x5555,
1 LSB = ΔθMAX/21ꢀ (see Table 65 for ΔθMAX
)
Each axis of the delta angle measurements has two output data
registers. Figure 42 shows how these two registers combine to
support a 32-bit, twos complement data format for the x-axis
delta angle measurements. This format also applies to the y-axis
and z-axis.
Y-Axis Delta Angle (Y_DELTANG_LOW, Y_DELTANG_OUT)
The Y_DELTANG_LOW (see Table 65 and Table 66) and
Y_DELTANG_OUT (see Table 67 and Table 68) registers
contain the delta angle data for the y-axis.
X_DELTANG_OUT
X_DELTANG_LOW
Table 65. Y_DELTANG_LOW Register Definitions
15
0 15
0
Page Addresses Default
Access Flash Backup
X-AXIS DELTA ANGLE DATA
5x55 5x44, 5x4ꢀ Not applicable
R
No
Figure 42. Delta Angle Output Data Structure
Rev. D | Page 26 of 43
Data Sheet
ADIS16497
Table 66. Y_DELTANG_LOW Bit Descriptions
Table 74. 32-Bit Delta Angle Data Format Examples
Bits
Description
Delta Angle (°)
+ΔθMAX × (231 − 1)/231
+ΔθMAX/235
+ΔθMAX2555/231
5
−ΔθMAX/231
−ΔθMAX/235
−ΔθMAX
Decimal
Hexadecimal
[1ꢀ:5]
Y-axis delta angle data; low word
+2,147,4ꢁ3,647 5x7FFFFFFF
+2
+1
5
−1
−2
5x55555552
5x55555551
5x55555555
5xFFFFFFFF
5xFFFFFFFE
Table 67. Y_DELTANG_OUT Register Definitions
Page Addresses Default
Access Flash Backup
5x55 5x46, 5x47 Not applicable
R
No
−2,147,4ꢁ3,64ꢁ 5xꢁ5555555
Table 68. Y_DELTANG_OUT Bit Descriptions
Bits Description
[1ꢀ:5] Y-axis delta angle data; twos complement, 5° = 5x5555,
1 LSB = ΔθMAX/21ꢀ (see Table 65 for ΔθMAX
DELTA VELOCITY
)
In addition to the linear acceleration measurements along each
axis (x, y, and z), the ADIS16497 also provides delta velocity
measurements that represent a computation of linear velocity
change between each sample update. Figure 44 shows the
orientation of each delta-velocity measurement, which defines
the direction of linear velocity increase that produces a positive
response in each of the delta velocity rate measurements.
Z-Axis Delta Angle (Z_DELTANG_LOW, Z_DELTANG_OUT)
The Z_DELTANG_LOW (see Table 69 and Table 70) and
Z_DELTANG_OUT (see Table 71 and Table 72) registers
contain the delta angle data for the z-axis.
Table 69. Z_DELTANG_LOW Register Definitions
The delta velocity outputs represent an integration of the accelera-
tion measurements and use the following formula for all three
axes (x-axis displayed):
Page Addresses Default
Access Flash Backup
5x55 5x4ꢁ, 5x49 Not applicable
R
No
D1
1
2 fS
Table 70. Z_DELTANG_LOW Bit Descriptions
a
Vx,nD
ax,nDd1
x,nDd
Bits
Description
d0
[1ꢀ:5]
Z-axis delta angle data; low word
where:
ΔVX is the delta velocity measurement for the x-axis.
D is the decimation rate = DEC_RATE + 1 (see Table 150).
fS is the sample rate.
Table 71. Z_DELTANG_OUT Register Definitions
Page Addresses Default
Access Flash Backup
d is the incremental variable in the summation formula.
ax is the x-axis rate of acceleration (accelerometer).
n is the sample time, prior to the decimation filter.
5x55 5x4A, 5x4B Not applicable
R
No
Table 72. Z_DELTANG_OUT Bit Descriptions
Bits Description
[1ꢀ:5] Z-axis delta angle data; twos complement, 5° = 5x5555,
1 LSB = ΔθMAX/21ꢀ (see Table 65 for ΔθMAX
When using the internal sample clock, fS is equal to 4250 SPS.
When using the external clock option, fS is equal to the frequency
of the external clock. The range in the delta velocity registers
accommodates the maximum linear acceleration (8 g), the nominal
sample rate (4250 SPS), and an update rate of 1 Hz (DEC_RATE =
0x1099; divide by 4249 plus 1, see Table 150), all at the same
time. When using an external clock that is higher than 4250 SPS,
reduce the DEC_RATE setting to avoid overranging the delta
velocity registers.
)
Delta Angle Resolution
Table 73 and Table 74 show various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
Table 73. 16-Bit Delta Angle Data Format Examples
Each axis of the delta velocity measurements has two output
data registers. Figure 43 shows how these two registers combine
to support 32-bit, twos complement data format for the delta
velocity measurements along the x-axis. This format also
applies to the y-axis and x-axis.
Delta Angle (°)
ΔθMAX × (21ꢀ−1)/21ꢀ +32,767
Decimal Hex
Binary
5x7FFF 5111 1111 1115 1111
5x5552 5555 5555 5555 5515
5x5551 5555 5555 5555 5551
5x5555 5555 5555 5555 5555
5xFFFF 1111 1111 1111 1111
5xFFFE 1111 1111 1111 1115
5xꢁ555 1555 5555 5555 5555
+ΔθMAX/214
+ΔθMAX/21ꢀ
5
+2
+1
5
X_DELTVEL_OUT
X_DELTVEL_LOW
−ΔθMAX/21ꢀ
−ΔθMAX/214
−ΔθMAX
−1
−2
−32,76ꢁ
15
0 15
0
X-AXIS DELTA ANGLE DATA
Figure 43. Delta Angle Output Data Structure
Rev. D | Page 27 of 43
Data Sheet
ADIS16497
Z-AXIS
ΔV
Z
X-AXIS
Y-AXIS
ΔV
X
ΔV
Y
PIN 23
PIN 1
Figure 44. Delta Velocity Axis and Polarity Assignments
X-Axis Delta Velocity (X_DELTVEL_LOW, X_DELTVEL_OUT)
Table 81. Y_DELTVEL_OUT Register Definitions
The X_DELTVEL_LOW (see Table 75 and Table 76) and
X_DELTVEL_OUT (see Table 77 and Table 78) registers
contain the delta velocity data for the x-axis.
Page Addresses Default
Access Flash Backup
5x55 5xꢀ2, 5xꢀ3 Not applicable
R
No
Table 75. X_DELTVEL_LOW Register Definitions
Table 82. Y_DELTVEL_OUT Bit Descriptions
Bits Description
Page Addresses Default
Access Flash Backup
5x55 5x4C, 5x4D Not applicable
R
No
[1ꢀ:5] Y-axis delta velocity data; high word; twos complement,
455 m/sec range, 5 m/sec = 5x5555;
1 LSB = 455 m/sec ÷ 21ꢀ = ~12.25ꢁ mm/sec
Table 76. X_DELTVEL_LOW Bit Descriptions
Bits
Description
Z-Axis Delta Velocity (Z_DELTVEL_LOW, Z_DELTVEL_OUT)
[1ꢀ:5]
X-axis delta angle data; low word
The Z_DELTVEL_LOW (see Table 83 and Table 84) and
Z_DELTVEL_OUT (see Table 85 and Table 86) registers
contain the delta velocity data for the z-axis.
Table 77. X_DELTVEL_OUT Register Definitions
Page Addresses Default Access Flash Backup
5x55 5x4E, 5x4F Not applicable No
Table 83. Z_DELTVEL_LOW Register Definitions
R
Page Addresses Default
Access Flash Backup
5x55 5xꢀ4, 5xꢀꢀ Not applicable
R
No
Table 78. X_DELTVEL_OUT Bit Descriptions
Bits Description
Table 84. Z_DELTVEL_LOW Bit Descriptions
[1ꢀ:5] X-axis delta velocity data; high word; twos complement,
455 m/sec range, 5 m/sec = 5x5555;
Bits
Description
1 LSB = 455 m/sec ÷ 21ꢀ = ~12.25ꢁ mm/sec
[1ꢀ:5]
Z-axis delta angle data; low word
Y-Axis Delta Velocity (Y_DELTVEL_LOW, Y_DELTVEL_OUT)
Table 85. Z_DELTVEL_OUT Register Definitions
The Y_DELTVEL_LOW (see Table 79 and Table 80) and
Y_DELTVEL_OUT (see Table 81 and Table 82) registers contain
the delta velocity data for the y-axis.
Page Addresses Default
Access Flash Backup
5x55 5xꢀ6, 5xꢀ7 Not applicable
R
No
Table 79. Y_DELTVEL_LOW Register Definitions
Table 86. Z_DELTVEL_OUT Bit Descriptions
Bits Description
Page Addresses Default
Access Flash Backup
5x55 5xꢀ5, 5xꢀ1 Not applicable
R
No
[1ꢀ:5] Z-axis delta velocity data; high word; twos complement,
455 m/sec range, 5 m/sec = 5x5555;
1 LSB = 455 m/sec ÷ 21ꢀ = ~12.25ꢁ mm/sec
Table 80. Y_DELTVEL_LOW Bit Descriptions
Bits
Description
[1ꢀ:5]
Y-axis delta angle data; low word
Rev. D | Page 2ꢁ of 43
Data Sheet
ADIS16497
USER BIAS/SCALE ADJUSTMENT
Delta Velocity Resolution
The signal chain of each inertial sensor (accelerometers, gyro-
scopes) includes application of unique correction formulas that
come from extensive characterization of bias, sensitivity, align-
ment, and response to linear acceleration (gyroscopes) over a
temperature range of −40°C to +85°C for the ADIS16497. These
correction formulas are not accessible, but the user does have the
opportunity to adjust the bias and the scale factor, for each sensor
individually, through user accessible registers. These correction
factors follow immediately after the factory derived correction
formulas in the signal chain, which processes at a rate of 4250 Hz
when using the internal sample clock (see fSM in Figure 22 and
Figure 23).
Table 87 and Table 88 show various numerical examples that
demonstrate the format of the delta angle data in both 16-bit
and 32-bit formats.
Table 87. 16-Bit Delta Velocity Data Format Examples
Velocity (m/sec)
Decimal Hex
Binary
+455 × (21ꢀ − 1)/21ꢀ +32,767
5x7FFF 5111 1111 1115 1111
5x5552 5555 5555 5555 5515
5x5551 5555 5555 5555 5551
5x5555 5555 5555 5555 5555
5xFFFF 1111 1111 1111 1111
5xFFFE 1111 1111 1111 1115
5xꢁ555 1555 5555 5555 5555
+455/214
+455/21ꢀ
5
−455/21ꢀ
−455/214
−455
+2
+1
5
−1
−2
−32,76ꢁ
Gyroscope Scale Adjustment, X_GYRO_SCALE
The X_GYRO_SCALE register (see Table 93 and Table 94)
provides the user with the opportunity to adjust the scale factor
for the x-axis gyroscopes. See Figure 45 for an illustration of
how this scale factor influences the x-axis gyroscope data.
Table 88. 32-Bit Delta Angle Data Format Examples
Velocity (m/sec)
+455 × (231 − 1)/231
+455/235
+455/231
5
Decimal
Hex
+2,147,4ꢁ3,647
+2
+1
5
5x7FFFFFFF
5x55555552
5x55555551
5x55555555
5xFFFFFFFF
5xFFFFFFFE
5xꢁ5555555
Table 93. X_GYRO_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
5x52
5x54, 5x5ꢀ
5x5555 R/W Yes
−455/231
−455/235
−455
−1
−2
−2,147,4ꢁ3,64ꢁ
Table 94. X_GYRO_SCALE Bit Descriptions
Bits Description
Burst Read Command, BURST_CMD
[1ꢀ:5] X-axis gyroscope scale correction; twos complement,
5x5555 = unity gain, 1 LSB = 1 ÷ 21ꢀ = ~5.5535ꢀ2%
Reading the BURST_CMD register (see Table 89 and Table 90)
starts the BRF. See Table 10, Table 11, Figure 5, and Figure 6
for more information on the BRF function.
1 + X_GYRO_SCALE
FACTORY
X-AXIS
GYRO
CALIBRATION
AND
FILTERING
Table 89. BURST_CMD Register Definitions
X_GYRO_OUT X_GYRO_LOW
Page Addresses Default
Access Flash Backup
5x55 5x7C, 5x7D Not Applicable
R
No
XG_BIAS_HIGH XG_BIAS_LOW
Figure 45. User Bias/Scale Adjustment Registers in Gyroscope Signal Path
Table 90. BURST_CMD Bit Descriptions
Bits
Description
Gyroscope Scale Adjustment, Y_GYRO_SCALE
[1ꢀ:5]
Burst read command register
The Y_GYRO_SCALE register (see Table 95 and Table 96) allows
the user to adjust the scale factor for the y-axis gyroscopes. This
register influences the y-axis gyroscope measurements in the
same manner that X_GYRO_SCALE influences the x-axis
gyroscope measurements (see Figure 45).
Product Identification, PROD_ID
The PROD_ID register (see Table 91 and Table 92) contains
the numerical portion of the device number (16,497). See
Figure 34 for an example of how to use a looping read of this
register to validate the integrity of the communication.
Table 95. Y_GYRO_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
Table 91. PROD_ID Register Definitions
5x52
5x56, 5x57
5x5555 R/W Yes
Page
Addresses
Default Access Flash Backup
5x55
5x7E, 5x7F
5x4571 Yes
R
Table 96. Y_GYRO_SCALE Bit Descriptions
Bits Description
Table 92. PROD_ID Bit Descriptions
[1ꢀ:5] Y-axis gyroscope scale correction; twos complement,
5x5555 = unity gain, 1 LSB = 1 ÷ 21ꢀ = ~5.5535ꢀ2%
Bits
Description
[1ꢀ:5]
Product identification = 5x4571
Rev. D | Page 29 of 43
ADIS16497
Data Sheet
Gyroscope Scale Adjustment, Z_GYRO_SCALE
Table 102. Y_ACCL_SCALE Bit Descriptions
Bits Description
[1ꢀ:5] Y-axis accelerometer scale correction; twos complement,
5x5555 = unity gain, 1 LSB = 1 ÷ 21ꢀ = ~5.5535ꢀ2%
The Z_GYRO_SCALE register (see Table 97 and Table 98)
allows the user to adjust the scale factor for the z-axis gyroscopes.
This register influences the z-axis gyroscope measurements in the
same manner that X_GYRO_SCALE influences the x-axis
gyroscope measurements (see Figure 45).
Accelerometer Scale Adjustment, Z_ACCL_SCALE
The Z_ACCL_SCALE register (see Table 103 and Table 104)
allows the user to adjust the scale factor for the z-axis
accelerometers. This register influences the z-axis
accelerometer measurements in the same manner that
X_ACCL_SCALE influences the x-axis accelerometer
measurements (see Figure 46).
Table 97. Z_GYRO_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
5x52
5x5ꢁ, 5x59
5x5555 R/W Yes
Table 98. Z_GYRO_SCALE Bit Descriptions
Bits Description
Table 103. Z_ACCL_SCALE Register Definitions
[1ꢀ:5] Z-axis gyroscope scale correction; twos complement,
5x5555 = unity gain, 1 LSB = 1 ÷ 21ꢀ = ~5.5535ꢀ2%
Page
Addresses
Default Access Flash Backup
5x52
5x5E, 5x5F
5x5555 R/W Yes
Accelerometer Scale Adjustment, X_ACCL_SCALE
The X_ACCL_SCALE register (see Table 99 and Table 100)
allows the user to adjust the scale factor for the x-axis
accelerometers. See Figure 46 for an illustration of how this
scale factor influences the x-axis accelerometer data.
Table 104. Z_ACCL_SCALE Bit Descriptions
Bits Description
[1ꢀ:5] Z-axis accelerometer scale correction; twos complement,
5x5555 = unity gain, 1 LSB = 1 ÷ 21ꢀ = ~5.5535ꢀ2%
Table 99. X_ACCL_SCALE Register Definitions
Page
Addresses
Default Access Flash Backup
Gyroscope Bias Adjustment, XG_BIAS_LOW,
XG_BIAS_HIGH
5x52
5x5A, 5x5B
5x5555 R/W Yes
The XG_BIAS_LOW (see Table 105 and Table 106) and XG_
BIAS_HIGH (see Table 107 and Table 108) registers combine
to allow the user to adjust the bias of the x-axis gyroscopes. The
digital format examples in Table 25 also apply to the XG_BIAS_
HIGH register, and the digital format examples in Table 26 apply
to the number that comes from combining the XG_BIAS_LOW
and XG_BIAS_HIGH registers. See Figure 45 for an illustration
of how these two registers combine and influence the x-axis
gyroscope measurements.
Table 100. X_ACCL_SCALE Bit Descriptions
Bits Description
[1ꢀ:5] X-axis accelerometer scale correction; twos complement,
5x5555 = unity gain, 1 LSB = 1 ÷ 21ꢀ = ~5.5535ꢀ2%
1 + X_ACCL_SCALE
FACTORY
X-AXIS
ACCL
CALIBRATION
AND
X_ACCL_OUT X_ACCL_LOW
FILTERING
Table 105. XG_BIAS_LOW Register Definitions
XA_BIAS_HIGH
XA_BIAS_LOW
Page
Addresses
Default Access Flash Backup
Figure 46. User Bias/Scale Adjustment Registers in Accelerometer Signal Path
5x52
5x15, 5x11
5x5555 R/W Yes
Accelerometer Scale Adjustment, Y_ACCL_SCALE
Table 106. XG_BIAS_LOW Bit Descriptions
The Y_ACCL_SCALE register (see Table 101 and Table 102)
allows the user to adjust the scale factor for the y-axis
Bits
Description
accelerometers. This register influences the y-axis accelerometer
measurements in the same manner that X_ACCL_SCALE
influences the x-axis accelerometer measurements (see Figure 46).
[1ꢀ:5]
X-axis gyroscope offset correction, low word;
twos complement, 5°/sec = 5x5555, 1 LSB = KG ÷ 216
(see Table 24)
Table 101. Y_ACCL_SCALE Register Definitions
Table 107. XG_BIAS_HIGH Register Definitions
Page
Addresses
Default Access Flash Backup
Page
Addresses
Default Access Flash Backup
5x52
5x5C, 5x5D
5x5555 R/W Yes
5x52
5x12, 5x13
5x5555 R/W Yes
Table 108. XG_BIAS_HIGH Bit Descriptions
Bits Description
[1ꢀ:5] X-axis gyroscope offset correction, high word twos
complement, 5°/sec = 5x5555, 1 LSB = KG (see Table 24)
Rev. D | Page 35 of 43
Data Sheet
ADIS16497
Table 115. ZG_BIAS_HIGH Register Definitions
Gyroscope Bias Adjustment, YG_BIAS_LOW,
YG_BIAS_HIGH
Page
Addresses
Default Access Flash Backup
5x52
5x1A, 5x1B
5x5555 R/W Yes
The YG_BIAS_LOW (see Table 109 and Table 110) and YG_
BIAS_HIGH (see Table 111 and Table 112) registers combine
to allow the user to adjust the bias of the y-axis gyroscopes. The
digital format examples in Table 25 also apply to the YG_BIAS_
HIGH register, and the digital format examples in Table 26 apply
to the number that comes from combining the YG_BIAS_LOW
and YG_BIAS_HIGH registers. These registers influences the
y-axis gyroscope measurements in the same manner that the
XG_BIAS_LOW and XG_BIAS_HIGH registers influence the
x-axis gyroscope measurements (see Figure 45).
Table 116. ZG_BIAS_HIGH Bit Definitions
Bits Description
[1ꢀ:5] Z-axis gyroscope offset correction, high word twos
complement, 5°/sec = 5x5555, 1 LSB = 5.55ꢀ°/sec
Accelerometer Bias Adjustment, XA_BIAS_LOW,
XA_BIAS_HIGH
The XA_BIAS_LOW (see Table 117 and Table 118) and XA_
BIAS_HIGH (see Table 119 and Table 120) registers combine
to allow the user to adjust the bias of the x-axis accelerometers.
The digital format examples in Table 51 also apply to the
XA_BIAS_HIGH register and the digital format examples in
Table 52 apply to the number that comes from combining the
XA_BIAS_LOW and XA_BIAS_HIGH registers. See Figure 46
for an illustration of how these two registers combine and
influence the x-axis accelerometer measurements.
Table 109. YG_BIAS_LOW Register Definitions
Page
Addresses
Default Access Flash Backup
5x52
5x14, 5x1ꢀ
5x5555 R/W Yes
Table 110. YG_BIAS_LOW Bit Descriptions
Bits Description
[1ꢀ:5] Y-axis gyroscope offset correction, low word; twos
complement, 5°/sec = 5x5555, 1 LSB = 5.55ꢀ°/sec ÷ 216
Table 117. XA_BIAS_LOW Register Definitions
Table 111. YG_BIAS_HIGH Register Definitions
Page
Addresses
Default Access Flash Backup
Page
Addresses
Default Access Flash Backup
5x52
5x1C, 5x1D
5x5555 R/W Yes
5x52
5x16, 5x17
5x5555 R/W Yes
Table 118. XA_BIAS_LOW Bit Descriptions
Table 112. YG_BIAS_HIGH Bit Descriptions
Bits Description
Bits
Description
[1ꢀ:5]
X-axis accelerometer offset correction, low word, twos
complement, 5 g = 5x5555, 1 LSB = 1.2ꢀ mg ÷ 216
[1ꢀ:5] Y-axis gyroscope offset correction, high word; twos
complement, 5°/sec = 5x5555, 1 LSB = 5.55ꢀ°/sec
Table 119. XA_BIAS_HIGH Register Definitions
Gyroscope Bias Adjustment, ZG_BIAS_LOW,
ZG_BIAS_HIGH
Page
Addresses
Default Access Flash Backup
5x52
5x1E, 5x1F
5x5555 R/W Yes
The ZG_BIAS_LOW (see Table 113 and Table 114) and ZG_
BIAS_HIGH (see Table 115 and Table 116) registers combine
to allow the user to adjust the bias of the z-axis gyroscopes. The
digital format examples in Table 25 also apply to the ZG_BIAS_
HIGH register, and the digital format examples in Table 26 apply
to the number that comes from combining the ZG_BIAS_LOW
and ZG_BIAS_HIGH registers. These registers influence the
z-axis gyroscope measurements in the same manner that the
XG_BIAS_LOW and XG_BIAS_HIGH registers influence the x-
axis gyroscope measurements (see Figure 45).
Table 120. XA_BIAS_HIGH Bit Descriptions
Bits Description
[1ꢀ:5] X-axis accelerometer offset correction, high word,
twos complement, 5 g = 5x5555, 1 LSB = 1.2ꢀ mg
Accelerometer Bias Adjustment, YA_BIAS_LOW,
YA_BIAS_HIGH
The YA_BIAS_LOW (see Table 121 and Table 122) and YA_
BIAS_HIGH (see Table 123 and Table 124) registers combine
to allow the user to adjust the bias of the y-axis accelerometers.
The digital format examples in Table 51 also apply to the
YA_BIAS_HIGH register, and the digital format examples in
Table 52 apply to the number that comes from combining the
YA_BIAS_LOW and YA_BIAS_HIGH registers. These registers
influence the y-axis accelerometer measurements in the same
manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers
influence the x-axis accelerometer measurements (see Figure 46).
Table 113. ZG_BIAS_LOW Register Definitions
Page
Addresses
Default Access Flash Backup
5x52
5x1ꢁ, 5x19
5x5555 R/W Yes
Table 114. ZG_BIAS_LOW Bit Descriptions
Bits Description
[1ꢀ:5] Z-axis gyroscope offset correction, low word; twos
complement, 5°/sec = 5x5555, 1 LSB = 5.55ꢀ°/sec ÷ 216
Rev. D | Page 31 of 43
ADIS16497
Data Sheet
Table 121. YA_BIAS_LOW Register Definitions
SCRATCH REGISTERS, USER_SCR_X
Page
Addresses
Default Access Flash Backup
The USER_SCR_1 (see Table 129 and Table 130),
USER_SCR_2 (see Table 131 and Table 132), USER_SCR_3
(see Table 133 and Table 134), and the USER_SCR_4 (see Table
135 and Table 136) registers provide four locations for the user
to store information.
5x52
5x25, 5x21
5x5555 R/W Yes
Table 122. YA_BIAS_LOW Bit Descriptions
Bits
Description
[1ꢀ:5]
Y-axis accelerometer offset correction, low word, twos
complement, 5 g = 5x5555, 1 LSB = 1.2ꢀ mg ÷ 216
Table 129. USER_SCR_1 Register Definitions
Page
Addresses
Default Access Flash Backup
5x52
5x74, 5x7ꢀ
5x5555 R/W Yes
Table 123. YA_BIAS_HIGH Register Definitions
Page
Addresses
Default Access Flash Backup
Table 130. USER_SCR_1 Bit Descriptions
Bits Description
[1ꢀ:5] User defined
5x52
5x22, 5x23
5x5555 R/W Yes
Table 124. YA_BIAS_HIGH Bit Descriptions
Bits Description
Table 131. USER_SCR_2 Register Definitions
[1ꢀ:5] Y-axis accelerometer offset correction, high word,
twos complement, 5 g = 5x5555, 1 LSB = 1.2ꢀ mg
Page
Addresses
Default Access Flash Backup
5x52
5x76, 5x77
5x5555 R/W Yes
Accelerometer Bias Adjustment, ZA_BIAS_LOW,
ZA_BIAS_HIGH
The ZA_BIAS_LOW (see Table 125 and Table 126) and ZA_
BIAS_HIGH (see Table 127 and Table 128) registers combine
to allow the user to adjust the bias of the z-axis accelerometers. The
digital format examples in Table 51 also apply to the ZA_BIAS_
HIGH register and the digital format examples in Table 52 apply
to the number that comes from combining the ZA_BIAS_LOW
and ZA_BIAS_HIGH registers. These registers influence the z-
axis accelerometer measurements in the same manner that the
XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-
axis accelerometer measurements (see Figure 46).
Table 132. USER_SCR_2 Bit Descriptions
Bits Description
[1ꢀ:5] User defined
Table 133. USER_SCR_3 Register Definitions
Page
Addresses
Default Access Flash Backup
5x52
5x7ꢁ, 5x79
5x5555 R/W Yes
Table 134. USER_SCR_3 Bit Descriptions
Bits Description
[1ꢀ:5] User defined
Table 125. ZA_BIAS_LOW Register Definitions
Page
Addresses
Default Access Flash Backup
5x52
5x24, 5x2ꢀ
5x5555 R/W Yes
Table 135. USER_SCR_4 Register Definitions
Page
Addresses
Default Access Flash Backup
5x52
5x7A, 5x7B
5x5555 R/W Yes
Table 126. ZA_BIAS_LOW Bit Descriptions
Bits Description
[1ꢀ:5] Z-axis accelerometer offset correction, low word,
Table 136. USER_SCR_4 Bit Descriptions
Bits Description
[1ꢀ:5] User defined
twos complement, 5 g = 5x5555, 1 LSB = 1.2ꢀ mg ÷ 216
Table 127. ZA_BIAS_HIGH Register Definitions
FLASH MEMORY ENDURANCE COUNTER,
FLSHCNT_LOW, FLSHCNT_HIGH
Page
Addresses
Default Access Flash Backup
5x52
5x26, 5x27
5x5555 R/W Yes
The FLSHCNT_LOW (see Table 137 and Table 138) and
FLSHCNT_HIGH (see Table 139 and Table 140) registers
combine to provide a 32-bit, binary counter that tracks the
number of flash memory write cycles. In addition to the number of
write cycles, the flash memory has a finite service lifetime, which
depends on the junction temperature. Figure 47 provides guidance
for estimating the retention life for the flash memory at specific
junction temperatures. The junction temperature is approximately
7°C above the case temperature.
Table 128. ZA_BIAS_HIGH Bit Descriptions
Bits Description
[1ꢀ:5] Z-axis accelerometer offset correction, high word,
twos complement, 5 g = 5x5555, 1 LSB = 1.2ꢀ mg
Rev. D | Page 32 of 43
Data Sheet
ADIS16497
Table 137. FLSHCNT_LOW Register Definitions
Software Reset
Page Addresses Default
Access Flash Backup
Select Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 7 = 1
(DIN = 0x8280, then DIN = 0x8300) to initiate a reset in the
operation of the ADIS16497. This reset removes all data,
initializes all registers from their flash settings, and restarts data
sampling and processing. This function provides a firmware
5x52 5x7C, 5x7D Not applicable
R
Yes
Table 138. FLSHCNT_LOW Bit Descriptions
Bits Description
[1ꢀ:5] Flash memory write counter, low word
RST
alternative to providing a low pulse on the
Pin 8).
pin (see Table 6,
Clear User Calibration
Table 139. FLSHCNT_HIGH Register Definitions
Page Addresses Default Access Flash Backup
5x52 5x7E, 5x7F Not applicable
Select Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 6 = 1
(DIN = 0x8240, then DIN = 0x8300) to clear all user bias/scale
adjustments for each accelerometer and gyroscope. This command
writes 0x0000 to the following registers: X_GYRO_SCALE,
Y_GYRO_SCALE, Z_GYRO_SCALE, X_ACCL_SCALE, Y_
ACCL_ SCALE, Z_ACCL_SCALE, XG_BIAS_LOW,
XG_BIAS_HIGH, YG_BIAS_LOW, YG_BIAS_HIGH,
ZG_BIAS_LOW, ZG_BIAS_HIGH, XA_BIAS_LOW,
XA_BIAS_HIGH, YA_BIAS_LOW, YA_BIAS_ HIGH,
ZA_BIAS_LOW, and ZA_BIAS_HIGH.
R
Yes
Table 140. FLSHCNT_HIGH Bit Descriptions
Bits Description
[1ꢀ:5] Flash memory write counter, high word
600
450
300
Flash Memory Update
Select Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 3 = 1
(DIN = 0x8208, DIN = 0x8300) to initiate a manual flash update.
SYS_E_FLAG, Bit 6 (see Table 18) identifies success (0) or
failure (1) in completing this process.
Note that the user must not poll the status registers while
waiting for the update to complete because the serial port is
disabled during the update. Rather, the user must either wait
the prescribed amount of time found in Table 3 or wait for the
data ready indicator pin to begin toggling.
150
0
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (°C)
On Demand Self Test (ODST)
Figure 47. Flash Memory Retention
Select Page 3 (DIN = 0x8003) and then set GLOB_CMD, Bit 1 = 1
(DIN = 0x8202, then DIN = 0x8300) to run the ODST routine,
which executes the following steps:
GLOBAL COMMANDS, GLOB_CMD
The GLOB_CMD register (see Table 141 and Table 142) provides
trigger bits for several operations. Write a 1 to the appropriate bit
in GLOB_CMD to start a particular function.
1. Measure the output on each sensor.
2. Activate an internal force on the mechanical elements of
each sensor, which simulates the force associated with
actual inertial motion.
3. Measure the output response on each sensor.
4. Deactivate the internal force on each sensor.
5. Calculate the difference between the force on and normal
operating conditions (force off).
6. Compare the difference with internal pass/fail criteria.
7. Report the pass/fail results for each sensor in DIAG_STS
(see Table 20) and the overall pass/fail flag in SYS_E_FLAG,
Bit 5 (see Table 18).
Table 141. GLOB_CMD Register Definitions
Page Addresses Default
Access Flash Backup
5x53 5x52, 5x53 Not applicable
W
No
Table 142. GLOB_CMD Bit Descriptions
Bits
Description
[1ꢀ:ꢁ]
Not used
7
6
[ꢀ:4]
3
2
Software reset
Clear user calibration
Not used
Flash memory update
Not used
False positive results are possible when the executing the ODST
while the device is in motion. Note that the user must not poll
the status registers while waiting for the test to complete. Rather,
the user must either wait the prescribed amount of time found
in Table 3 or wait for the data ready indicator pin to begin
toggling.
1
Self test
5
Bias correction update
Rev. D | Page 33 of 43
ADIS16497
Data Sheet
Bias Correction Update
Data Ready Indicator
Select Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 0 = 1
(DIN = 0x8201, then DIN = 0x8300) to update the user offset
registers with the correction factors of the continuous bias
estimation (CBE) (see Table 152). Ensure that the inertial
platform is stable during the entire average time for optimal bias
estimates.
The FNCTIO_CTRL, Bits[3:0] provide three configuration
options for the data ready function: on/off, polarity, and DIOx line.
The primary purpose this signal is to drive the interrupt control
line of an embedded processor, which can synchronize data
collection and minimize latency. The data ready indicator is
useful to determine if the controller inside the ADIS16497 is busy
with a task (for example, a flash memory update) because data
ready stops togging while these tasks are performed and resumes
on completion. The factory default assigns DIO2 as a positive
polarity, data ready signal, which means the data in the output
registers is valid when the DIO2 line is high (see Figure 29). This
configuration works well when DIO2 drives an interrupt
service pin that activates on a low to high pulse. Use the
following sequence to change this assignment to DIO3 with
negative polarity:
AUXILIARY I/O LINE CONFIGURATION,
FNCTIO_CTRL
The FNCTIO_CTRL register (see Table 143 and Table 144)
provides configuration control for each I/O pin (DIO1, DIO2,
DIO3, and DIO4). Each DIOx pin supports only one function at
a time. When a single pin has two assignments, the enable bit for
the lower priority function automatically resets to zero (disabling
the lower priority function). The order of priority is as follows,
from highest priority to lowest priority: data ready, sync clock
input, and general-purpose. The ADIS16497 can take up to 20 ms
to execute a write command to the FNCTIO_CTRL register.
During this time, the operational state and the contents of the
register remain unchanged, but the SPI interface supports
normal communication (for accessing other registers).
1. Select Page 3 (DIN = 0x8003).
2. Set FNCTIO_CTRL, Bits[3:0] = 1000 (DIN = 0x860A, then
DIN = 0x8700).
The timing jitter on the data ready signal is typically within
1.4 ꢀs. When using DIO1 to support the data ready function,
this signal can experience premature data ready pulses during
the ADIS16497 start-up, However, these pulses do not indicate
that data production has started. If it is necessary to use DIO1
for this function, use it in conjunction with a delay or other
control mechanism to prevent premature data acquisition
activity during the start-up process.
Table 143. FNCTIO_CTRL Register Definitions
Page
Addresses
Default Access Flash Backup
5x53
5x56, 5x57
5x555D R/W Yes
Table 144. FNCTIO_CTRL Bit Descriptions
Bits
[1ꢀ:9]
ꢁ
Description
Not used
Input Sync/Clock Control
Sync clock mode
1 = PPS
The FNCTIO_CTRL, Bits[8:4] provide several configuration
options for using one of the DIOx lines as an external clock
signal and for controlling inertial sensor data collection and
processing. For example, use the following sequence to establish
DIO4 as a positive polarity, input clock pin that operates in sync
mode and preserves the factory default setting for the data ready
function:
5 = sync
7
Sync clock input enable
1 = enabled
5 = disabled
6
Sync clock input polarity
1 = rising edge
5 = falling edge
Sync clock input line selection
55 = DIO1
1. Select Page 3 (DIN = 0x8003).
2. Set FNCTIO_CTRL, Bits[7:0] = 0xFD (DIN = 0x86FD).
3. Set FNCTIO_CTRL, Bits[15:8] = 0x00 (DIN = 0x8700).
[ꢀ:4]
51 = DIO2
In sync mode, the ADIS16497 disables its internal sample clock,
and the frequency of the external clock signal establishes the rate of
data collection and processing (fSM in Figure 22 and Figure 23).
When using the PPS mode (FNCTIO_CTRL, Bit 8 = 1) the rate
of data collection and production (fSM) is equal to the product
of the external clock frequency and scale factor (KECSF) in the
SYNC_SCALE register (see Table 154).
15 = DIO3
11 = DIO4
3
Data ready enable:
1 = enabled
5 = disabled
2
Data ready polarity:
1 = positive
5 = negative
[1:5]
Data ready line selection
55 = DIO1
51 = DIO2
15 = DIO3
11 = DIO4
Rev. D | Page 34 of 43
Data Sheet
ADIS16497
Point of Percussion
GENERAL-PURPOSE I/O CONTROL, GPIO_CTRL
CONFIG, Bit 6 offers a point of percussion alignment function
that maps the accelerometer sensors to the corner of the
package identified in Figure 48. To activate this feature, select
Page 3 (DIN = 0x8003), then set CONFIG, Bit 6 = 1 (DIN =
0x8A40, then DIN = 0x8B00).
When FNCTIO_CTRL does not configure a DIOx pin, the
GPIO_CTRL register (see Table 145 and Table 146) provides
user controls for general-purpose use of the DIOx pins.
GPIO_CTRL, Bits[3:0], provide I/O assignment controls for
each line. When the DIOx lines are inputs, monitor their level
by reading GPIO_CTRL, Bits[7:4]. When the DIOx lines are
used as outputs, set their level by writing to GPIO_CTRL, Bits[7:4].
For example, use the following sequence to set DIO1 and DIO3
as high and low output lines, respectively, and set DIO2 and DIO4
as input lines. Select Page 3 (DIN = 0x8003) and set GPIO_
CTRL, Bits[7:0] = 0x15 (DIN = 0x8815, then DIN = 0x8900).
PIN 23
PIN 1
Table 145. GPIO_CTRL Register Definitions1
POINT OF PERCUSSION
ALIGNMENT REFERENCE POINT.
SEE CONFIG[6].
Page
Addresses
Default Access Flash Backup
Figure 48. Point of Percussion Reference Point
5x53
5x5ꢁ, 5x59
5x55X5 R/W Yes
1 The GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx lines and do not
have a default setting.
LINEAR ACCELERATION ON EFFECT ON
GYROSCOPE BIAS
Table 146. GPIO_CTRL Bit Descriptions 1
The ADIS16497 includes first-order compensation for the linear g
effect in the gyroscopes, which uses the following model:
Bits
Description
[1ꢀ:ꢁ]
Don’t care
XC
XPC
LG11 LG12 LG
A
ω
ω
ω
ω
ω
ω
13
X
7
6
ꢀ
4
3
General-Purpose I/O Line 4 (DIO4) data level
General-Purpose I/O Line 3 (DIO3) data level
General-Purpose I/O Line 2 (DIO2) data level
General-Purpose I/O Line 1 (DIO1) data level
General-Purpose I/O Line 4 (DIO4) direction control
(1 = output, 5 = input)
General-Purpose I/O Line 3 (DIO3) direction control
(1 = output, 5 = input)
General-Purpose I/O Line 2 (DIO2) direction control
(1 = output, 5 = input)
LG
LG22 LG23 AY
21
YC
YPC
LG31 LG32 LG33
AZ
ZC
ZPC
The linear g correction factors, LGXY, apply correction for linear
acceleration in all three directions to the data path of each gyro-
scope (ωXPC, ωYPC, and ωZPC) at the rate of the data samples
(4250 SPS when using the internal clock). CONFIG, Bit 7, provides
an on/off control for this compensation. The factory default
value for this bit activates this compensation.
2
1
5
General-Purpose I/O Line 1 (DIO1) direction control
(1 = output, 5 = input)
To turn it off, select Page 3 (DIN = 0x8003) and set CONFIG,
Bit 7 = 0 (DIN = 0x8A40, then DIN = 0x8B00). This command
sequence also preserves the default setting for the point of
percussion alignment function (on).
1 The GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx lines and do not
have a default setting.
DECIMATION FILTER, DEC_RATE
MISCELLANEOUS CONFIGURATION, CONFIG
The DEC_RATE register (see Table 149 and Table 150)
provides user control for the final filter stage (see Figure 25),
which averages and decimates the accelerometers and
gyroscopes data, and extends the time that the delta angle and
delta velocity track between each update. The output sample
rate is equal to 4250/(DEC_RATE + 1). For example, select Page
3 (DIN = 0x8003), and set DEC_RATE = 0x2A (DIN = 0x8C2A,
then DIN = 0x8D00) to reduce the output sample rate to ~98.8 SPS
(4250 ÷ 43).
The CONFIG register (see Table 147 and Table 148) provides
configuration options for the linear g compensation in the
gyroscopes (on/off) and the point of percussion alignment for
the accelerometers (on/off).
Table 147. CONFIG Register Definitions
Page
Addresses
Default Access Flash Backup
5x53
5x5A, 5x5B
5x55C5 R/W Yes
Table 148. CONFIG Bit Descriptions
Bits Description
[1ꢀ:ꢁ] Not used
Table 149. DEC_RATE Register Definitions
Page
Addresses
Default Access Flash Backup
5x53
5x5C, 5x5D
5x5555 R/W Yes
7
Linear g compensation for gyroscopes (1 = enabled)
Point of percussion alignment (1 = enabled)
Not used
6
[ꢀ:5]
Rev. D | Page 3ꢀ of 43
ADIS16497
Data Sheet
SCALING THE INPUT CLOCK (PPS MODE),
SYNC_SCALE
Table 150. DEC_RATE Bit Descriptions
Bits
Description
The PPS mode (FNCTIO_CTRL, Bit 8 = 1, see Table 144)
supports the use of an input sync frequency that is slower than
the data sample rates of the inertial sensors. This mode
supports a frequency range of 1 Hz to 128 Hz for the input sync
mode. In this mode, the data sample rate is equal to the product
of the value in the SYNC_SCALE register (see Table 153 and
Table 154) and the input sync frequency. For example, the
following command sequence sets the data collection and
processing rate (fSM in Figure 22 and Figure 23) to 4000 Hz
(SYNC_SCALE = 0x0FA0) when using a 1 Hz signal on the
DIO3 line as the external clock input, and preserves the factory
default configuration for the data ready signal:
[1ꢀ:11]
[15:5]
Don’t care
Decimation rate, binary format, maximum = 4249
CONTINUOUS BIAS ESTIMATION (CBE),
NULL_CNFG
The NULL_CNFG register (see Table 151 and Table 152) provides
the configuration controls for the CBE, which associates with the
bias correction update command in GLOB_CMD, Bit 0 (see
Table 142). NULL_CNFG, Bits[3:0], establishes the total
average time (tA) for the bias estimates and NULL_CNFG,
Bits[13:8], provide on/off controls for each sensor. The factory
default configuration for NULL_CNFG enables the bias null
command for the gyroscopes, disables the bias null command for
the accelerometers, and sets the average time to ~15.42 seconds.
1. Select Page 3 (DIN = 0x8003).
2. Set SYNC_SCALE, Bits[7:0] = 0xA0 (DIN = 0x90A0).
3. Set SYNC_SCALE, Bits[15:8] = 0x0F (DIN = 0x910F).
4. Set FNCTIO_CTRL, Bits[7:0] = 0xFD (DIN = 0x86ED).
5. Set FNCTIO_CTRL, Bits[15:8] = 0x00 (DIN = 0x8701).
tB = 2TBC/4250 = 210/4250 = ~0.241 seconds
tA = 64 × tB = 64 × 0.241 = 15.42 seconds
where:
tB is the time base.
tA is the averaging time.
Note that the data ready indicator pin does not begin to toggle
until at least two external clock edges (with valid time period
between them) are detected by the ADIS16497.
When a sensor bit in NULL_CNFG is active (equal to 1), setting
GLOB_CMD, Bit 0 = 1 (DIN sequence: 0x8003, 0x8201, 0x8300)
causes its bias correction register to automatically update with a
value that corrects for its present bias error (from the CBE). For
example, setting NULL_CNFG, Bit 8 equal to 1 causes an update in
the XG_BIAS_LOW (see Table 106) and XG_BIAS_HIGH (see
Table 108) registers.
Table 153. SYNC_SCALE Register Definitions
Page
Addresses
Default
Access
Flash Backup
5x53
5x15, 5x11
5x159A
R/W
Yes
Table 154. SYNC_SCALE Bit Descriptions
Bits
Description
[1ꢀ:5]
External clock scale factor (KECSF), binary format
Table 151. NULL_CNFG Register Definitions
Page
Addresses
Default Access Flash Backup
Measurement Range Identifier, RANG_MDL
5x53
5x5E, 5x5F
5x575A R/W Yes
The RANG_MDL register (see Table 155 and Table 156)
provides a convenient method for identifying the model (and
gyroscope measurement range) of the ADIS16497.
Table 152. NULL_CNFG Bit Descriptions
Bits Description
[1ꢀ:14] Not used
Table 155. RANG_MDL Register Definitions1
Page
Addresses
Default
Access
Flash Backup
13
12
11
15
9
ꢁ
[7:4]
[3:5]
Z-axis acceleration bias correction enable (1 = enabled)
Y-axis acceleration bias correction enable (1 = enabled)
X-axis acceleration bias correction enable (1 = enabled)
Z-axis gyroscope bias correction enable (1 = enabled)
Y-axis gyroscope bias correction enable (1 = enabled)
X-axis gyroscope bias correction enable (1 = enabled)
Not used
5x53
5x12, 5x13
N/A
R
N/A
1 N/A means not applicable.
Table 156. RANG_MDL Bit Descriptions
Bits
Description
[1ꢀ:3]
[3:5]
Not used
5511 = ADIS16497-1 ( 12ꢀ°/sec)
5111 = ADIS16497-2 ( 4ꢀ5°/sec)
1111 = ADIS16497-3 ( 2555°/sec)
Time base control (TBC), range: 5 to 13 (default = 15);
tB = 2TBC/42ꢀ5, time base; tA = 64 × tB, average time
Rev. D | Page 36 of 43
Data Sheet
ADIS16497
Table 160. FILTR_BNK_1 Bit Descriptions
FIR FILTERS
FIR Filters Control, FILTR_BNK_0, FILTR_BNK_1
Bits
[1ꢀ:3]
2
Description
Don’t care
The FILTR_BNK_0 (see Table 157 and Table 158) and FILTR_
BNK_1 (see Table 159 and Table 160) registers provide the
configuration controls for the FIR filter bank in the signal chain
of each sensor (see Figure 25). These registers provide on/off
control for the FIR bank for each inertial sensor, along with the
FIR bank (A, B, C, or D) that each sensor uses.
Z-axis accelerometer filter enable (1 = enabled)
[1:5]
Z-axis accelerometer filter bank selection:
55 = Bank A
51 = Bank B
15 = Bank C
11 = Bank D
Table 157. FILTR_BNK_0 Register Definitions
FIR Filter Bank Memory Maps
Page
Addresses
Default Access Flash Backup
The ADIS16497 provides four FIR filter banks to configure and
select for each individual inertial sensor using the FILTR_BNK_0
(see Table 158) and FILTR_BNK_1 (see Table 160) registers.
Each FIR filter bank (A, B, C, and D) has 120 taps that consume
two pages of memory. The coefficient associated with each tap,
in each filter bank, has its own dedicated register that uses a 16-bit,
twos complement format. The FIR filter has unity gain when the
sum of all of the coefficients is equal to 32,768. For filter designs
that require less than 120 taps, write 0x0000 to all unused registers
to eliminate the latency associated with that particular tap.
5x53
5x16, 5x17
5x5555 R/W Yes
Table 158. FILTR_BNK_0 Bit Descriptions
Bits
Description (Default = 0x0000)
1ꢀ
Don’t care
14
Y-axis accelerometer filter enable (1 = enabled)
[13:12]
Y-axis accelerometer filter bank selection
55 = Bank A
51 = Bank B
15 = Bank C
FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119
11 = Bank D
11
X-axis accelerometer filter enable (1 = enabled)
X-axis accelerometer filter bank selection
55 = Bank A
51 = Bank B
15 = Bank C
Table 161. FIR Filter Bank A Memory Map
[15:9]
Page PAGE_ID Addresses
Register
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5x5ꢀ
5x5ꢀ
5x5ꢀ
5x5ꢀ
5x5ꢀ
5x55, 5x51
5x52 to 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C to 5x7D
PAGE_ID
Not used
FIR_COEF_A555
FIR_COEF_A551
FIR_COEF_A552 to
FIR_COEF_A5ꢀꢁ
11 = Bank D
ꢁ
Z-axis gyroscope filter enable (1 = enabled)
Z-axis gyroscope filter bank selection
55 = Bank A
51 = Bank B
15 = Bank C
[7:6]
ꢀ
6
6
6
6
6
5x5ꢀ
5x56
5x56
5x56
5x56
5x56
5x7E, 5x57F
5x55, 5x51
5x52 to 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C to 5x7D
FIR_COEF_A5ꢀ9
PAGE_ID
Not used
FIR_COEF_A565
FIR_COEF_A561
FIR_COEF_A562 to
FIR_COEF_A11ꢁ
11 = Bank D
ꢀ
Y-axis gyroscope filter enable (1 = enabled)
Y-axis gyroscope filter bank selection
55 = Bank A
[4:3]
6
5x56
5x7E, 5x7F
FIR_COEF_A119
51 = Bank B
15 = Bank C
Table 162 and Table 163 provide detailed register and bit
definitions for one of the FIR coefficient registers in Bank A,
FIR_COEF_ A071. Table 164 provides a configuration
example, which sets this register to a decimal value of −169
(0xFF57).
11 = Bank D
2
X-axis gyroscope filter enable (1 = enabled)
X-axis gyroscope filter bank selection
55 = Bank A
[1:5]
51 = Bank B
15 = Bank C
11 = Bank D
Table 162. FIR_COEF_A071 Register Definitions
Page Addresses Default
Access Flash Backup
5x56 5x1E, 5x1F
Not applicable R/W
Yes
Table 159. FILTR_BNK_1 Register Definitions
Table 163. FIR_COEF_A071 Bit Descriptions
Page
Addresses
Default Access Flash Backup
Bits
Description
5x53
5x1ꢁ, 5x19
5x5555 R/W Yes
[1ꢀ:5]
FIR Bank A, Coefficient 71, twos complement
Rev. D | Page 37 of 43
ADIS16497
Data Sheet
Table 164. Configuration Example, FIR Coefficient
FIR Filter Bank D, FIR_COEF_D000 to FIR_COEF_D119
Table 167. Filter Bank D Memory Map
DIN Command
Description
5xꢁ556
Select Page 6
Page PAGE_ID Addresses
Register
5x9Eꢀ7
5x9FFF
FIR_COEF_A571, Bits[7:5] = 5xꢀ7
FIR_COEF_A571, Bits[1ꢀ:ꢁ] = 5xFF
11
11
11
11
11
5x5B
5x5B
5x5B
5x5B
5x5B
5x55, 5x51
5x52 to 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C to 5x7D FIR_COEF_D552 to
FIR_COEF_D5ꢀꢁ
PAGE_ID
Not used
FIR_COEF_D555
FIR_COEF_D551
FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119
Table 165. Filter Bank B Memory Map
Page PAGE_ID Addresses
Register
11
12
12
12
12
12
5x5B
5x5C
5x5C
5x5C
5x5C
5x5C
5x7E, 5x57F
5x55, 5x51
5x52 to 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C to 5x7D FIR_COEF_D562 to
FIR_COEF_D11ꢁ
5x7E, 5x7F
FIR_COEF_D5ꢀ9
PAGE_ID
Not used
FIR_COEF_D565
FIR_COEF_D561
7
7
7
7
7
5x57
5x57
5x57
5x57
5x57
5x55, 5x51
5x52 to 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C to 5x7D FIR_COEF_B552 to
FIR_COEF_B5ꢀꢁ
5x7E, 5x57F
5x55, 5x51
5x52 to 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
PAGE_ID
Not used
FIR_COEF_B555
FIR_COEF_B551
7
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
5x57
5x5ꢁ
5x5ꢁ
5x5ꢁ
5x5ꢁ
5x5ꢁ
FIR_COEF_B5ꢀ9
PAGE_ID
Not used
FIR_COEF_B565
FIR_COEF_B561
12
5x5C
FIR_COEF_D119
Default Filter Performance
The FIR filter banks have factory programmed filter designs that
are all low-pass filters that have unity dc gain. Table 168 provides a
summary of each filter design, and Figure 49 shows the frequency
response characteristics. The phase delay is equal to ½ of the total
number of taps.
5x5C to 5x7D FIR_COEF_B562 to
FIR_COEF_B11ꢁ
5x7E, 5x7F
ꢁ
5x5ꢁ
FIR_COEF_B119
FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119
Table 166. Filter Bank C Memory Map
Table 168. FIR Filter Descriptions, Default Configuration
FIR Filter Bank
Taps
125
125
32
−3 dB Frequency (Hz)
Page PAGE_ID Addresses
Register
A
B
C
D
355
155
355
155
9
9
9
9
9
5x59
5x59
5x59
5x59
5x59
5x55, 5x51
5x52 to 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C to 5x7D FIR_COEF_C552 to
FIR_COEF_C5ꢀꢁ
PAGE_ID
Not used
FIR_COEF_C555
FIR_COEF_C551
32
0
–10
9
5x59
5x5A
5x5A
5x5A
5x5A
5x5A
5x7E, 5x57F
5x55, 5x51
5x52 to 5x57
5x5ꢁ, 5x59
5x5A, 5x5B
5x5C to 5x7D FIR_COEF_C562 to
FIR_COEF_C11ꢁ
5x7E, 5x7F
FIR_COEF_C5ꢀ9
PAGE_ID
Not used
FIR_COEF_C565
FIR_COEF_C561
NO FIR
FILTERING
–20
B
15
15
15
15
15
D
A
C
–30
–40
–50
–60
–70
–80
–90
15
5x5A
FIR_COEF_C119
–100
0
200
400
600
800
1000
1200
FREQUENCY (Hz)
Figure 49. FIR Filter Frequency Response Curves
Rev. D | Page 3ꢁ of 43
Data Sheet
ADIS16497
FIRMWARE REVISION, FIRM_REV
Table 174. FIRM_Y Bit Descriptions
The FIRM_DM register (see Table 171 and Table 172) contains
the month and day of the factory configuration date. Register
FIRM_DM, Bits[15:12] and Register FIRM_DM, Bits[11:8]
contain digits that represent the month of the factory configuration
in a binary coded decimal (BCD) format. For example,
November is the 11th month in a year and is represented by
Register FIRM_DM, Bits[15:8] = 0x11. Register FIRM_DM,
Bits[7:4] and Register FIRM_DM, Bits[3:0], contain digits that
represent the day of factory configuration in a BCD format. For
example, the 27th day of the month is represented by FIRM_DM,
Bits[7:0] = 0x27.
Bits
Description
[1ꢀ:12]
Factory configuration year BCD code, thousands digit,
numerical format = 4-bit binary, range = 5 to 9
Factory configuration year BCD code, hundreds digit,
numerical format = 4-bit binary, range = 5 to 9
Factory configuration year BCD code, tens digit,
numerical format = 4-bit binary, range = 5 to 3
Factory configuration year BCD code, ones digit,
numerical format = 4-bit binary, range = 5 to 9
[11:ꢁ]
[7:4]
[3:5]
BOOT REVISION NUMBER, BOOT_REV
Table 175. BOOT_REV Register Definitions
Table 169. FIRM_REV Register Definitions
Page Addresses Default
Access Flash Backup
Page Addresses Default
Access Flash Backup
5x53 5x7E, 5x7F Not applicable
R
Yes
5x53 5x7ꢁ, 5x79 Not applicable
R
Yes
Table 176. BOOT_REV Bit Definitions
Table 170. FIRM_REV Bit Descriptions
Bits Description
Bits
Description
[1ꢀ:ꢁ]
[7:5]
Binary, major revision number
Binary, minor revision number
[1ꢀ:12] Firmware revision BCD code, tens digit, numerical
format = 4-bit binary, range = 5 to 9
[11:ꢁ]
[7:4]
[3:5]
Firmware revision BCD code, ones digit, numerical
format = 4-bit binary, range = 5 to 9
Firmware revision BCD code, tenths digit, numerical
format = 4-bit binary, range = 5 to 9
Firmware revision BCD code, hundredths digit,
numerical format = 4-bit binary, range = 5 to 9
CONTINUOUS SRAM TESTING
This device employs a CRC function on the SRAM memory
blocks that contain the program code (CODE_SIGTR_xxx) and
the calibration coefficients (CAL_DRVTN_xxx). This process
operates in the background and generates real-time, 32-bit
CRC values for the program code and calibration coefficients,
respectively. At the conclusion of each cycle, the processor
writes these calculated values in the CAL_DRVTN_xxx and
CODE_DRVTN_xxx registers (see Table 183, Table 184, Table
190, and Table 192) and compares them with the signature
values, which reflect the state of these memory locations at the
time of factory configuration. When the calculation results do
not match the signature values, Register SYS_E_FLAG, Bit 2
increases to a 1. The respective signature values are available for
user access through the CAL_SIGTR_xxx and CODE_SIGTR_xxx
registers (see Table 177, Table 178, Table 179, Table 180, Table 186,
and Table 188). The following conditions must be met for
Register SYS_E_FLAG, Bit 2 to remain at the zero level:
Table 171. FIRM_DM Register Definitions
Page Addresses Default
Access Flash Backup
5x53 5x7A, 5x7B Not applicable
R Yes
Table 172. FIRM_DM Bit Descriptions
Bits
Description
[1ꢀ:12]
Factory configuration month BCD code, tens digit,
numerical format = 4-bit binary, range = 5 to 2
Factory configuration month BCD code, ones digit,
numerical format = 4-bit binary, range = 5 to 9
Factory configuration day BCD code, tens digit,
numerical format = 4-bit binary, range = 5 to 3
Factory configuration day BCD code, ones digit,
numerical format = 4-bit binary, range = 5 to 9
[11:ꢁ]
[7:4]
[3:5]
CAL_SIGTR_LWR = CAL_DRVTN_LWR
CAL_SIGTR_UPR = CAL_DRVTN_UPR
CODE_SIGTR_LWR = CODE_DRVTN_LWR
CODE_SIGTR_UPR = CODE_DRVTN_UPR
FIRMWARE REVISION YEAR, FIRM_Y
The FIRM_Y register (see Table 173 and Table 174) contains
the year of the factory configuration date. For example, the year
2013 is represented by FIRM_Y = 0x2013.
Table 173. FIRM_Y Register Definitions
Page Addresses Default
Access Flash Backup
5x53 5x7C, 5x7D Not applicable
R
Yes
Rev. D | Page 39 of 43
ADIS16497
Data Sheet
Signature CRC, Calibration Values, CAL_SIGTR_LWR
Signature CRC, Program Code, CODE_SIGTR_UPR
Table 187. CODE_SIGTR_UPR Register Definitions
Page Addresses Default Access Flash Backup
5x54 5x5E, 5x5F Not applicable Yes
Table 177. CAL_SIGTR_LWR Register Definitions
Page Addresses Default
Access Flash Backup
5x54 5x54, 5x5ꢀ Not applicable
R
Yes
R
Table 178. CAL_SIGTR_LWR Bit Descriptions
Bits Description
[1ꢀ:5] Factory programmed CRC value for the program code,
low word
Table 188. CODE_SIGTR_UPR Bit Descriptions
Bits Description
[1ꢀ:5] Factory programmed CRC value for the calibration
coefficients, high word
Signature CRC, Calibration Values, CAL_SIGTR_UPR
Derived CRC, Program Code, CODE_DRVTN_LWR
Table 179. CAL_SIGTR_UPR Register Definitions
Table 189. CODE_DRVTN_LWR Register Definitions
Page Addresses Default
Access Flash Backup
Page Addresses Default
Access Flash Backup
5x54 5x56, 5x57 Not applicable
R
Yes
5x54 5x15, 5x11 Not applicable
R
No
Table 180. CAL_SIGTR_UPR Bit Descriptions
Bits Description
[1ꢀ:5] Factory programmed CRC value for the program code,
high word
Table 190. CODE_DRVTN_LWR Bit Descriptions
Bits Description
[1ꢀ:5] Calculated CRC value for the calibration coefficients, low
word
Derived CRC, Calibration Values, CAL_DRVTN_LWR
Derived CRC, Program Code, CODE_DRVTN_UPR
Table 181. CAL_DRVTN_LWR Register Definitions
Page Addresses Default
Access Flash Backup
Table 191. CODE_DRVTN_LWR Register Definitions
5x54 5x5ꢁ, 5x59 Not applicable
R
No
Page Addresses Default
Access Flash Backup
5x54 5x12, 5x13 Not applicable
R
No
Table 182. CAL_DRVTN_LWR Bit Descriptions
Bits Description
Table 192. CODE_DRVTN_UPR Bit Descriptions
Bits Description
[1ꢀ:5] Calculated CRC value for the program code, low word
[1ꢀ:5] Calculated CRC value for the calibration coefficients,
high word
Derived CRC, Calibration Values, CAL_DRVTN_UPR
Table 183. CAL_DRVTN_UPR Register Definitions
Lot Specific Serial Number, SERIAL_NUM
Page Addresses Default
Access Flash Backup
Table 193. SERIAL_NUM Register Definitions
5x54 5x5A, 5x5B Not applicable
R No
Page Addresses Default
Access Flash Backup
5x54 5x25, 5x21 Not applicable
R
Yes
Table 184. CAL_DRVTN_UPR Bit Descriptions
Bits Description
Table 194. SERIAL_NUM Bit Descriptions
[1ꢀ:5] Calculated CRC value for the program code, high word
Bits
Description
[1ꢀ:5]
Lot specific serial number
Signature CRC, Program Code, CODE_SIGTR_LWR
Table 185. CODE_SIGTR_LWR Register Definitions
Page Addresses Default
Access Flash Backup
5x54 5x5C, 5x5D Not applicable
R
Yes
Table 186. CODE_SIGTR_LWR Bit Descriptions
Bits Description
[1ꢀ:5] Factory programmed CRC value for the calibration
coefficients, low word
Rev. D | Page 45 of 43
Data Sheet
ADIS16497
APPLICATIONS INFORMATION
MOUNTING BEST PRACTICES
PREVENTING MISINSERTION
For the best performance, follow these guidelines when
installing the ADIS16497 into a system:
The ADIS16497 connector uses the same pattern as the
ADIS16485, but with Pin 12 and Pin 15 missing. This pin
configuration enables a mating connector to plug these holes,
which helps prevent misconnection with the ADIS16497. Samtec
has a custom part number that provides this type of mating
socket: ASP-193371-04.
Eliminate opportunity for translational force (x- and y-axis
direction, per Figure 39) application on the electrical
connector.
Use uniform mounting forces on all four corners. The
suggested torque setting is 40 inch ounces (0.285 Nm).
When the ADIS16497 rests on the PCB, which contains
the mating connector (see Figure 50), use a diameter of at
least 2.85 mm for the passthrough holes.
EVALUATION TOOLS
Breakout Board, ADIS16IMU1/PCBZ
The ADIS16IMU1/PCBZ (sold separately) provides a breakout
board function for the ADIS16497, which means that it provides
access to the ADIS16497 through larger connectors that support
standard 1 mm ribbon cabling. It also provides four mounting
holes for attachment of the ADIS16497 to the breakout board.
These guidelines help prevent irregular force profiles, which
can warp the package and introduce bias errors in the sensors.
Figure 50 and Figure 51 provide details for mounting hole and
connector alignment pin drill locations.
PC-Based Evaluation, EVAL-ADIS2
39.600 BSC
Use the EVAL-ADIS2 and ADIS16IMU1/PCBZ to evaluate the
ADIS16497 on a PC-based platform.
19.800 BSC
PASSTHROUGH HOLE
FOR MOUNTING SCREWS
POWER SUPPLY CONSIDERATIONS
DIAMETER OF THE HOLE
MUST ACCOMODATE
DIMENSIONAL TOLERANCE
BETWEEN THE CONNECTOR
AND HOLES
The VDD power supply must charge 46 ꢀF of capacitance (inside
of the ADIS16497, across the VDD and GND pins) during its
initial ramp and settling process. When VDD reaches 2.85 V,
the ADIS16497 begins its internal start-up process, which gener-
ates additional transient current demand. See Figure 52 for a
typical current profile during the start-up process. The first
peak in Figure 52 relates to charging the 46 ꢀF capacitor bank,
whereas the other transient activity relates to numerous
functions turning on during the initialization process of the
ADIS16497.
DEVICE
OUTLINE
0.560 BSC 2×
ALIGNMENT HOLES
FOR MATING SOCKET
5 BSC
5 BSC
a
b
T
a
b
1.608ms
159.8ms
Δ158.2ms Δ60.00mA
92.00mA
152.0mA
NOTES
1. ALL DIMENSIONS IN UNITS OF MILLIMETERS (mm).
2. IN THIS CONFIGURATION, THE CONNECTOR IS FACING DOWN AND
ITS PINSARE NOT VISIBLE.
Figure 50. Suggested PCB Layout Pattern, Connector Down
0.4334 [11.0]
0.019685
[0.5000]
(TYP)
VDD
0.0240 [0.610]
3
0.054 [1.37]
DR
2
4
0.1800
[4.57]
0.0394 [1.00]
0.0394 [1.00]
CURRENT
B
0.022±
DIA (TYP)
CH2 2.0V
M40.0ms
20.10%
A
CH3
3.00V
W
B
B
CH3 2.0V
CH4 100mA
T
12.5MS/s 5M pts
NONPLATED
THROUGH HOLE 2×
0.022 DIA THROUGH HOLE (TYP)
NONPLATED THROUGH HOLE
W
W
Figure 52. Transient Current Demand, Startup
Figure 51. Suggested Layout and Mechanical Design When Using Samtec
CLM-112-02-G-D-A for the Mating Connector
Rev. D | Page 41 of 43
ADIS16497
Data Sheet
unsigned long crc32_block( unsigned long crc,
const unsigned short data[], int n )
CRC32 CODING EXAMPLE
This section contains sample code and values for computing
the cyclic redundancy check (CRC) for the ADIS16497 register
readback values.
{
unsigned long long_c;
int i;
In this coding example, the 32-bit CRC is first initialized with
0xFFFFFFFF. Next, each 16-bit word passes through the CRC
computation in ascending order. Finally, the CRC is Xor’ed
with 0xFFFFFFFF.
/* cycle through memory */
for ( i=0; i<n; i++ )
{
/* Get lower byte */
long_c = 0x000000ff &
(unsigned long)data[i];
/* Process with CRC */
crc = ((crc>>8) & 0x00ffffff) ^
crc_tab32[(crc^long_c)&0xff];
/* Get upper byte */
long_c = (0x000000ff &
((unsigned long)data[i]>>8);
/* Process with CRC */
crc = ((crc>>8) & 0x00ffffff) ^
crc_tab32[(crc^long_c)&0xff];
}
The ADIS16497 updates the CRC value for each data ready
cycle. The registers listed in Table 195 are used as inputs for
computing the CRC32 checksum. The registers can either be
read individually in normal SPI mode or in burst mode,
provided that all registers are all read during the same data
ready cycle.
1
Table 195. Sample Input Data for CRC Computation
Register Number
Register
Input Value
5x5555
5x5ꢁ3A
5x5555
5xFFF7
5x5555
5xFFFE
5x5555
5x5551
5xꢀ551
5x5553
5xE55A
5x551ꢀ
5xC559
5x5325
5xꢁAꢀ4
1
2
3
4
ꢀ
6
7
ꢁ
STATUS
TEMP_OUT
return crc;
}
X_GYRO_LOW
X_GYRO_OUT
Y_GYRO_LOW
Y_GYRO_OUT
Z_GYRO_LOW
Z_GYRO_OUT
X_ACCL_LOW
X_ACCL_OUT
Y_ACCL_LOW
Y_ACCL_OUT
Z_ACCL_LOW
Z_ACCL_OUT
TIME_STAMP
The CRC table (crc_tab32) is computed with the following
function:
void init_crc32_table( void )
{
9
unsigned long P_32;
int i, j;
unsigned long crc;
15
11
12
13
14
1ꢀ
/* CRC32 polynomial defined by IEEE-802.3 */
P_32 = 0xEDB88320
/* 8 bits require 256 entries in Table */
for (i=0; i<256; i++)
1 This information is contained in the array data in the coding example.
{
1
Table 196. Output Results for CRC Sample Computation
/* start with table entry number */
crc = (unsigned long) i;
Register Number
Register
CRC_LWR
CRC_UPR
Output Value
1
2
5x1ꢀB4
5xB6Cꢁ
/* cycle through all bits in entry number */
for (j=0; j<8; j++)
{
1 Based on the input shown in Table 19ꢀ.
The following is the CRC initialization code:
/* LSBit set? */
if ((crc&(unsigned
long)0x00000001)!=(unsigned long)0)
/* Initialize CRC */
crc = 0xFFFFFFFFU;
{
/* process for bit set */
/* Compute CRC in the order of bytes low-high
crc = (crc>>1) ^ P_32;
starting at 0-14, BurstID, STATUS - TIME_STAMP */
crc = crc32_block(crc, DATA, 15);
/* Final operation per IEEE-802.3 */
crc ^= 0xFFFFFFFFU;
}
else
{
/* process for bit clear */
crc = (crc>>1);
}
The crc32_block function accepts an array of 16-bit numbers
and computes the CRC byte-by-byte:
}
/* Store calculated value into table */
crc_tab32[i] = crc;
}
}
Rev. D | Page 42 of 43
Data Sheet
ADIS16497
OUTLINE DIMENSIONS
44.254
44.000
43.746
39.800
34.600
34.575
34.550
39.600
39.400
7.350
7.225
7.100
20.00
19.80
19.60
2.20 BSC
2.20 BSC
2.065
Ø 2.040
2.015
2.325
2.200
2.075
1.142 BSC
42.800
42.600
42.400
37.598
37.573
37.548
47.254
47.000
46.746
3.70
3.50
3.30
Ø 2.40
BSC
2.065
2.040
2.015
BOTTOM VIEW
TOP VIEW
°
47.479
47.379
47.279
DETAIL A
13.750 REF
0.250 BSC
DETAIL A
FRONT VIEW
14.200
14.000
13.800
2.84 BSC
3.454
3.200
2.946
0.250 BSC
5.50
BSC
5.50
BSC
1.00 BSC
PITCH
0.30 SQ BSC
Figure 53. 24-Lead Module with Connector Interface [MODULE]
(ML-24-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−45°C to +15ꢀ°C
−45°C to +15ꢀ°C
−45°C to +15ꢀ°C
Description
Package Option
ML-24-9
ML-24-9
ADIS16497-1BMLZ
ADIS16497-2BMLZ
ADIS16497-3BMLZ
24-Lead Module with Connector Interface [MODULE]
24-Lead Module with Connector Interface [MODULE]
24-Lead Module with Connector Interface [MODULE]
ML-24-9
1 Z = RoHS Compliant Part.
©2017-2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D1ꢀ061-7/20(D)
Rev. D | Page 43 of 43
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