ADL5310-EVALZ_技术文档

120 dB Range (3 nA to 3 mA)

Dual Logarithmic Converter

Data Sheet

ADL5310

FEATURES

FUNCTIONAL BLOCK DIAGRAM

2 independent channels optimized for photodiode interfacing

6-decade input dynamic range

Law conformance 0.3 dB from 3 nA to 3 mA

Temperature-stable logarithmic outputs

665kΩ

VREF

VRDZ

OUT1

VSUM

IRF1

V

OUT1

COMM

Nominal slope 10 mV/dB (200 mV/dec), externally scalable

Intercepts may be independently set by external resistors

User-configurable output buffer amplifiers

Single-supply or dual-supply operation

SCL1

BIN1

V

BIAS

6.69kΩ

I

LOG

TEMPERATURE

COMPENSATION

VNEG

LOG1

451Ω

14.2kΩ

Space efficient, 24-lead 4 mm × 4 mm LFCSP

Low power: <10 mA quiescent current

I

INP1

IRF2

PD1

OUT2

REFERENCE

GENERATOR

0.5V

2.5V

V

OUT2

APPLICATIONS

20kΩ

COMM

80kΩ

Gain and absorbance measurements

Multichannel power monitoring

General-purpose baseband log compression

SCL2

BIN2

V

BIAS

14.2kΩ

I

LOG

TEMPERATURE

VNEG

COMPENSATION

LOG2

451Ω

6.69kΩ

I

INP2

PD2

COMM

VSUM

665kΩ

VREF

Figure 1.

GENERAL DESCRIPTION

The ADL5310¹low cost, dual logarithmic amplifier converts input

current over a wide dynamic range to a linear-in-dB output

voltage. It is optimized to determine the optical power in wide-

ranging optical communication system applications, including

control circuitry for lasers, optical switches, atten-uators, and

amplifiers, as well as system monitoring. The device is equivalent

to a dual AD8305 with enhanced dynamic range (120 dB). While

the ADL5310 contains two independent signal channels with

individually configurable transfer function constants (slope and

intercept), internal bias circuitry is shared between channels for

improved power consumption and channel matching. Dual

converters in a single, compact LFCSP package yield space-

efficient solutions for measuring gain or attenuation across

optical elements. Only a single supply is required; optional

dual-supply operation offers added flexibility.

VSUM potential. The VSUM potential is internally set to 500 mV

but may be externally grounded for dual-supply operation, and

for additional applications requiring voltage inputs.

The logarithmic slope is set to 10 mV/dB (200 mV/decade)

nominal and can be modified using external resistors and the

independent buffer amplifiers. The logarithmic intercepts for

each channel are defined by the individual reference currents,

which are set to 3 μA nominal for maximum input range by

connecting 665 kΩ resistors between the 2.5 V VREF pins and

the IRF1 and IRF2 inputs. Tying VRDZ to VREF effectively sets

the x-intercept four decades below the reference current, which

is typically 300 pA for a 3 µA reference.

The use of individually optimized reference currents may be

valuable when using the ADL5310 for gain or absorbance measure-

ments where each channel input has a different current range

requirement. The reference current inputs are also fully functional

dynamic inputs, allowing log ratio operation with the reference

input current as the denominator. The ADL5310 is specified for

operation from –40°C to +85°C.

The ADL5310 employs an optimized translinear structure that

use the accurate logarithmic relationship between a bipolar

transistor’s base emitter voltage and collector current, with

appropriate scaling by precision currents to compensate for the

inherent temperature dependence. Input and reference current

pins sink current ranging from 3 nA to 3 mA (limited to 60 dB

between input and reference) into a fixed voltage defined by the

¹Protected by US Patents 4,604,532, and 5,519,308. Other patents pending.

Rev. B

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

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ADL5310

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory.......................................................................................... 11

Managing Intercept and Slope.................................................. 12

Response Time and Noise Considerations ............................. 12

Applications Information.............................................................. 13

Calibration................................................................................... 14

Minimizing Crosstalk ................................................................ 14

Relative and Absolute Power Measurements.......................... 15

Characterization Methods ........................................................ 16

Evaluation Board ............................................................................ 17

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Typical Performance Characteristics ............................................. 6

General Structure ........................................................................... 11

REVISION HISTORY

4/2018—Rev. A to Rev. B

Changes to Figure 2 and Table 3..................................................... 5

Changes to Figure 40...................................................................... 18

Updated Outline Dimensions ....................................................... 20

Changes to Ordering Guide .......................................................... 20

9/2004—Rev. 0 to Rev. A

Changes to Ordering Guide .......................................................... 20

11/2003—Revision 0: Initial Version

Rev. B | Page 2 of 20

Data Sheet

ADL5310

SPECIFICATIONS

VP = 5 V, V N = 0 V, T _A= 25°C, R_REF= 665 kΩ, and VRDZ connected to VREF, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Pin 1 to Pin 6: INP1 and INP2, IRF1 and IRF2, VSUM

Flows toward INP1 pin or INP2 pin

Flows toward IRF1 pin or IRF2 pin

Internally preset; user alterable

–40°C < T_A< +85°C

Min

Typ

Max

Unit

INPUT INTERFACE

Specified Current Range, I_PD

Input Current Min/Max Limits

Reference Current, I_REF, Range

Summing Node Voltage

Temperature Drift

3 n

3 m

10 m

3 m

A

V

3 n

0.46

0.5

0.030

0.54

mV/°C

mV

Input Offset Voltage

+20

V_IN− V_SUM, V_IREF− V_SUM

−20

LOGARITHMIC OUTPUTS

Logarithmic Slope

Pin 15 and Pin 16: LOG1 and LOG2

190

185

165

40

200

300

210

215

535

1940 pA

0.4

0.6

mV/dec

pA

–40°C < T_A< +85°C

Logarithmic Intercept¹

Law Conformance Error

–40°C < T_A< +85°C

10 nA < I_PD< 1 mA

3 nA < I_PD< 3 mA

I_PD> 3 µA; output referred

I_PD= 3 µA

0.1

0.3

0.5

1.5

1.7

0.10

5

dB

µV/√Hz

MHz

V

Wideband Noise²

Small Signal Bandwidth²

Maximum Output Voltage

Minimum Output Voltage

Output Resistance

Limited by V_N= 0 V

V

4.375

5.625 kΩ

REFERENCE OUTPUT

Voltage wrt Ground

Pin 7 and Pin 24 (internally shorted): VREF

2.45

2.42

2.5

2.55

2.58

V

–40°C < T_A< +85°C

Maximum Output Current

Incremental Output Resistance

OUTPUT BUFFERS

Sourcing (grounded load)

Load current < 10 mA

20

4

mA

Ω

Pins 12 to 14 and 17 to 19: OUT2, SCL2, BIN2, BIN1, SCL1,

and OUT1

Input Offset Voltage

Input Bias Current

Incremental Input Resistance

Incremental Output Resistance

Output High Voltage

Output Low Voltage

Peak Source/Sink Current

Small-Signal Bandwidth

Slew Rate

−20

+20

mV

µA

MΩ

Ω

Flowing out of Pins 13, 14, 17, and 18

0.4

35

0.5

Load current < 10 mA; gain = 1

R_L= 1 kΩ to ground

V

V_P− 0.1

0.10

30

15

R_L= 1 kΩ to ground

V

mA

MHz

V/µs

Gain = 1

0.2 V to 4.8 V output swing

Pins 8 and 9: VPOS; Pins 10, 11, and 20: VNEG

(V_P– V_N) ≤ 12 V

Input currents < 10 µA

(V_P– V_N) ≤ 12 V

POWER SUPPLY

Positive Supply Voltage

Quiescent Current

3

5

9.5

0

12

11.5

V

mA

V

Negative Supply Voltage (Optional)

−5.5

¹Other values of logarithmic intercept can be achieved by adjustment of R_REF

²Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1.

.

Rev. B | Page 3 of 20

ADL5310

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Parameter

Rating

12 V

Supply Voltage V_P− V_N

Input Current

Internal Power Dissipation

θ_JA

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

Lead Temperature Range (Soldering 60 sec)

20 mA

500 mW

35°C/W¹

125°C

–40°C to +85°C

−65°C to +150°C

300°C

ESD CAUTION

¹With paddle soldered down.

Rev. B | Page 4 of 20

Data Sheet

ADL5310

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

18 SCL1

BIN1

VSUM

INP1 2

17

ADL5310

16 LOG1

15 LOG2

3

4

5

6

IRF1

IRF2

DUAL LOG AMP

TOP VIEW

(Not to Scale)

INP2

14

BIN2

VSUM

CL2

13 S

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST

BE CONNECTED TO ANALOG GROUND

VIA A LOW IMPEDANCE PATH.

Figure 2. 24-Lead LFCSP Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic Function

1, 6

VSUM

Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input

summing node potentials. Pin 1 and Pin 6 are internally shorted.

2

INP1

Channel 1 Numerator Input. Accepts (sinks) photodiode current I_PD1. Usually connected to photodiode anode

such that photocurrent flows into INP1.

3

4

5

IRF1

IRF2

INP2

Channel 1 Denominator Input. Accepts (sinks) reference current, I_RF1

Channel 2 Denominator Input. Accepts (sinks) reference current, I_RF2

Channel 2 Numerator Input. Accepts (sinks) photodiode current I_PD2. Usually connected to photodiode anode

such that photocurrent flows into INP2.

.

7, 24

8, 9

10, 11, 20

VREF

VPOS

VNEG

Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted.

Positive Supply, (V_P– V_N) ≤ 12 V. Both pins must be connected externally.

Optional Negative Supply, V_N. These pins are usually grounded. For more details, see the General Structure and

Applications Information sections. All VNEG pins must be connected externally.

12

13

14

15

16

17

18

19

OUT2

SCL2

BIN2

LOG2

LOG1

BIN1

SCL1

OUT1

COMM

VRDZ

Buffer Output for Channel 2.

Buffer Amplifier Inverting Input for Channel 2.

Buffer Amplifier Noninverting Input for Channel 2.

Output of the Logarithmic Front End for Channel 2.

Output of the Logarithmic Front End for Channel 1.

Buffer Amplifier Noninverting Input for Channel 1.

Buffer Amplifier Inverting Input for Channel 1.

Buffer Output for Channel 1.

21, 22

23

Analog Ground. Pin 21 and Pin 22 are internally shorted.

Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the intercept.

Normally connected to VREF; may also be connected to ground when bipolar outputs are to be provided.

EPAD

Exposed Pad. The exposed pad must be connected to analog ground via a low impedance path.

Rev. B | Page 5 of 20

ADL5310

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

V_P= 5 V, V _N= 0 V, R _REF= 665 kΩ, T_A= 25°C, unless otherwise noted.

1.6

2.0

1.5

T

V

= –40°C, 0°C, +25°C, +70°C, +85°C

= 0V

A

IN

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.0

+85°C

+70°C

+25°C

0.5

0

–0.5

–1.0

–1.5

–2.0

0°C

–40°C

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

I

INP

Figure 3. V_LOGvs. I_INPfor Multiple Temperatures

Figure 6. Law Conformance Error vs. I_INPfor Multiple Temperatures,

Normalized to 25°C

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.0

1.5

1.0

T

V

= –40°C, 0°C, +25°C, +70°C, +85°C

= 0V

A

IN

+85°C

+70°C

0.5

0

+25°C

–0.5

–1.0

–1.5

–2.0

–40°C

0°C

1m

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

1n

10n

100n

1µ

10µ

(A)

100µ

10m

I

REF

Figure 4. V_LOGvs. I_REFfor Multiple Temperatures (I_INP= 3 µA)

Figure 7. Law Conformance Error vs. I_REFfor Multiple Temperatures,

Normalized to 25°C (I_INP= 3 µA)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.0

0.8

3mA

300µA

0.6

0.4

3µA

30µA

300nA

3µA

30nA

3nA

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

300nA

3mA

300µA

30µA

3nA

30nA

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

I

INP

Figure 8. Law Conformance Error vs. I_INPfor Multiple Values of I_REF

Decade Steps from 3 nA to 3 mA

,

Figure 5. V_LOGvs. I_INPfor Multiple Values of I_REF

Decade Steps from 3 nA to 3 mA

,

Rev. B | Page 6 of 20

Data Sheet

ADL5310

1.8

1.6

1.4

1.2

1.0

0.8

3nA

30nA

0.6

300nA

30µA

0.4

3µA

300µA

0.2

3µA

3mA

0

0.8

3mA

–0.2

–0.4

–0.6

–0.8

–1.0

3nA

0.6

3mA

30nA

300µA

300nA

0.4

0.2

0

3µA

30µA

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

I

REF

Figure 9. V_LOGvs. I_REFfor Multiple Values of I_INP

,

Figure 12. Law Conformance Error vs. I_REFfor Multiple Values of I_INP

Decade Steps from 3 nA to 3 mA

,

Decade Steps from 3 nA to 3 mA

1.0

0.8

2.0

T

= 25°C

A

1.5

1.0

+5V, 0V

+12V, 0V

0.6

+12V, 0V

0.4

+9V, 0V

+3V, 0V

0.5

MEAN + 3σ

MEAN – 3σ

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

+5V, –5V

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

I

INP

PD

Figure 10. Law Conformance Error vs. I_INPfor Various Supply Conditions

Figure 13. Law Conformance Error Distribution (3σ to Either Side of Mean)

2.0

4

T

= 0°C, 70°C

T

= –40°C, 85°C

A

1.5

1.0

3

2

MEAN + 3σ AT –40°C

MEAN + 3σ AT 70°C

0.5

1

MEAN + 3σ AT +85°C

0

MEAN ± 3σ AT 0°C

0

–0.5

–1.0

–1.5

–2.0

–1

–2

–3

–4

MEAN – 3σ AT 70°C

MEAN – 3σ AT –40°C

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

I

PD

Figure 11. Law Conformance Error Distribution (3σ to Either Side of Mean)

Figure 14. Law Conformance Error Distribution (3σ to Either Side of Mean)

Rev. B | Page 7 of 20

ADL5310

Data Sheet

15

10

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

30nA

300nA

5

3nA

T-RISE < 1µs T-FALL < 1µs

300µA TO 3mA

30µA

0

–5

30µA TO 300µA

3µA TO 30µA

–10

–15

–20

–25

–30

–35

–40

–45

300µA

T-RISE < 1µs T-FALL < 5µs

T-RISE < 5µs T-FALL < 10µs

T-RISE < 10µs T-FALL < 40µs

300nA TO 3µA

30nA TO 300nA

3mA

3µA

T-RISE < 30µs T-FALL < 80µs

3nA TO 30nA

–50

100

0

20

40

60

80

100 120 140 160 180 200

TIME (µs)

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 15. Small Signal AC Response, I_INPto V_OUT(A_V= 1)

(5% Sine Modulation, Decade Steps from 3 nA to 3 mA)

Figure 18. Pulse Response—I_INPto V_OUT(A_V= 1)

in Consecutive 1-Decade Steps

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

15

10

30nA

300nA

3mA

5

T-RISE < 80µs T-FALL < 30µs

T-RISE < 40µs T-FALL < 10µs

3nA TO 30nA

0

–5

30nA TO 300nA

300µA

3nA

–10

–15

–20

–25

–30

–35

–40

–45

–50

T-RISE < 10µs T-FALL < 5µs

T-RISE < 1µs T-FALL < 1µs

300nA TO 3µA

3µA TO 30µA

30µA TO 300µA

3µA

30µA

T-RISE < 1µs T-FALL < 1µs

300µA TO 3mA

0

20

40

60

80

100 120 140 160 180 200

TIME (µs)

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 16. Small Signal AC Response, I_REFto V_OUT(A_V= 1)

(5% Sine Modulation, Decade Steps from 3 nA to 3 mA)

Figure 19. Pulse Response—I_REFto V_OUT(A_V= 1)

in Consecutive 1-Decade Steps

5.0

4.0

3.0

2.0

1.0

0

100

10

3nA

30nA

1

3µA

300nA

0.1

30µA

3mA

300µA

0.01

100

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

1k

10k

100k

1M

10M

FREQUENCY (Hz)

I

INP

Figure 17. Spot Noise Spectral Density at V_OUTvs. Frequency (A_V= 1)

for I_INPin Decade Steps from 3 nA to 3 mA

Figure 20. Total Wideband Noise Voltage at V_OUTvs. I_INP(A_V= 1)

Rev. B | Page 8 of 20

Data Sheet

ADL5310

25

20

5

4

3

15

2

10

MEAN + 3σ

1

MEAN + 3σ

5

0

–1

–2

–3

–4

–5

–6

MEAN – 3σ

–5

–10

–15

–20

MEAN – 3σ

–25

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

Figure 21. V_REFDrift vs. Temperature (3σ to Either Side of Mean)

Normalized to 25°C

Figure 24. V_INPTDrift vs. Temperature (3σ to Either Side of Mean)

Normalized to 25°C

6

5

4

3

7

6

5

4

3

2

1

MEAN + 3σ

2

1

MEAN + 3σ

0

–1

–2

–3

–4

–5

–6

–1

–2

–3

–4

–5

–6

MEAN – 3σ

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

Figure 22. Slope Drift vs. Temperature (3σ to Either Side of Mean)

Normalized to 25°C

Figure 25. Slope Mismatch Drift vs. Temperature

(V_Y1– V_Y2, 3σ to Either Side of Mean) Normalized to 25°C

200

150

100

50

150

100

50

MEAN + 3σ

0

–50

–100

–150

–200

MEAN – 3σ

–50

–100

–150

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

Figure 26. Intercept Mismatch Drift vs. Temperature

(I_Z1– I_Z2, 3σ to Either Side of Mean) Normalized to 25°C

Figure 23. Intercept Drift vs. Temperature

(3σ to Either Side of Mean) Normalized to 25°C

Rev. B | Page 9 of 20

ADL5310

Data Sheet

450

400

350

300

250

200

150

100

50

700

600

500

400

300

200

100

0

190

–9

–6

–3

0

3

6

9

195

200

205

210

SLOPE MISMATCH (mV/dec)

SLOPE (mV/dec)

Figure 27. Distribution of Logarithmic Slope

Figure 30. Distribution of Channel-to-Channel Slope Mismatch (V_Y1– V_Y2)

600

500

400

300

200

100

500

400

300

200

100

0

–300

–200

–100

0

100

200

300

100

200

300

400

500

INTERCEPT MISMATCH (pA)

INTERCEPT (pA)

Figure 28. Distribution of Logarithmic Intercept

Figure 31. Distribution of Channel-to-Channel Intercept Mismatch (I_Z1– I_Z2)

500

700

600

500

400

300

200

100

0

400

300

200

100

0

–9

–6

–3

0

3

6

9

2.46

2.48

2.50

2.52

2.54

V

– V VOLTAGE (mV)

SUM

VREF VOLTAGE (V)

INPT

Figure 29. Distribution of V_REF(R_L= 100 kΩ)

Figure 32. Distribution of Offset Voltage (V_INPT– V_SUM)

Rev. B | Page 10 of 20

Data Sheet

ADL5310

GENERAL STRUCTURE

The ADL5310 addresses a wide variety of interfacing conditions

to meet the needs of fiber optic supervisory systems and is useful

in many nonoptical applications. These notes explain the structure

of this unique style of translinear log amp. Figure 33 shows the

key elements of one of the two identical on-board log amps.

THEORY

The base-emitter voltage of a bipolar junction transistor (BJT)

can be expressed by Equation 1, which immediately shows its

basic logarithmic nature:

V

_BE= kT/q ln(I_C/I_S)

(1)

BIAS

GENERATOR

where:

I_Cis the collector current.

IREF

PHOTODIODE

INPUT

V

BE1

TEMPERATURE

COMPENSATION

(SUBTRACT AND

DIVIDE BY T°K)

I_Sis a scaling current, typically only 10^–17A.

kT/q is the thermal voltage, proportional to absolute

temperature (PTAT), and is 25.85 mV at 300 K.

2.5V

VREF

CURRENT

I

REF

BE2

80kΩ

0.5V

20kΩ

COMM

I

PD

I_Sis never precisely defined and exhibits an even stronger temper-

ature dependence, varying by a factor of roughly a billion between

−35°C and +85°C. Thus, to make use of the BJT as an accurate

logarithmic element, both of these temperature dependencies

must be eliminated.

VSUM

44µA/dec

INP1

(INP2)

0.5V

14.2kΩ 451Ω

VRDZ

VLOG

0.5V

Q1

V

Q2

BE2

6.69kΩ

BE1

The difference between the base-emitter voltages of a matched

pair of BJTs, one operating at the photodiode current I_PDand

the other operating at a reference current I_REF, can be written as

COMM

VNEG (NORMALLY GROUNDED)

Figure 33. Simplified Schematic of Single Log Amp

V

_BE1– V_BE2= kT/q ln(I_PD/I_S) – kT/q ln(I_REF/I_S)

The photodiode current I_PDis received at either Pin INP1 or

Pin INP2. The voltages at these nodes are approximately equal

to the voltage on the adjacent guard pins, V_SUM, as well as reference

inputs IRF1 and IRF2, due to the low offset voltage of the JFET

operational amplifiers. Transistor Q1 converts I_PDto a corre-

sponding logarithmic voltage, as shown in Equation 1. A finite

positive value of V_SUMis needed to bias the collector of Q1 for

the usual case of a single-supply voltage. This is internally set to

0.5 V, one-fifth of the 2.5 V reference voltage that appears on

Pin VREF. Both VREF pins are internally shorted, as are both

VSUM pins. The resistance at the VSUM pin is nominally 16 kΩ;

this voltage is not intended as a general bias source.

= ln(10) kT/q log₁₀(I_PD/I_REF

= 59.5 mV log₁₀(I_PD/I_REF) (T = 300 K)

)

(2)

The uncertain, temperature-dependent saturation current, I_S,

that appears in Equation 1 has therefore been eliminated. To

eliminate the temperature variation of kT/q, this difference

voltage is processed by what is essentially an analog divider.

Effectively, it puts a variable under Equation 2. The output of

this process, which also involves a conversion from voltage

mode to current mode, is an intermediate, temperature-

corrected current:

I

_LOG= I_Ylog₁₀(I_PD/I_REF

)

(3)

The ADL5310 also supports the use of an optional negative supply

voltage, V_N, at Pin VNEG. When V_Nis 0.5 V or more negative,

VSUM may be connected to ground; thus, INP1, INP2, IRF1,

and IRF2 assume this potential. This allows operation as a voltage-

input logarithmic converter by the inclusion of a series resistor

at either or both inputs. Note that the resistor setting I_REFfor

each channel needs to be adjusted to maintain the intercept value.

Also, note that the collector-emitter voltages of Q1 and Q2 are

the full V_Nand effects due to self-heating cause errors at large

input currents.

where I_Yis an accurate, temperature-stable scaling current that

determines the slope of the function (change in current per

decade).

For the ADL5310, I_Yis 44 µA, resulting in a temperature-

independent slope of 44 µA/decade for all values of I_PDand I_REF

This current is subsequently converted back to a voltage-mode

output, V_LOG, scaled 200 mV/decade.

.

It is apparent that this output is 0 for I_PD= I_REFand must swing

negative for smaller values of input current. To avoid this, I_REF

would need to be as small as the smallest value of I_PD. Accordingly,

an offset voltage is added to V_LOGto shift it upward by 0.8 V when

VRDZ is directly connected to VREF. This moves the intercept

to the left by four decades (at 200 mV/decade), from 3 μA to

300 pA:

The input-dependent V_BE1of Q1 is compared with the reference

V_BE2of a second transistor, Q2, operating at I_REF. I_REFis generated

externally to a recommended value of 3 µA. However, other

values over a several-decade range can be used with a slight

degradation in law conformance.

I

_LOG= I_Ylog₁₀(I_PD/I_INTC

)

(4)

where I_INTCis the operational value of the intercept current.

Rev. B | Page 11 of 20

ADL5310

Data Sheet

Because values of I_PD< I_INTCresult in a negative V_LOG, a negative

supply of sufficient value is required to accommodate this

situation.

Thus, the effective intercept current I_INTCis only one ten-

thousandth of I_REF, corresponding to 300 pA when using the

recommended value of I_REF= 3 μA.

The voltage V_LOGis generated by applying I_LOGto an internal

resistance of 4.55 kΩ, formed by the parallel combination of a

6.69 kΩ resistor to ground and a 14.2 kΩ resistor to Pin VRDZ

(typically tied to the 2.5 V reference, VREF). At the LOG1

(LOG2) pin, the output current I_LOGgenerates a voltage of

The slope can be reduced by attaching a resistor between the log

amp output pin, LOG1 or LOG2, and ground. This is strongly

discouraged given that the on-chip resistors do not ratio

correctly to the added resistance. In addition, it is rare that one

would wish to lower the basic slope of 10 mV/dB; if this is

needed, it should be effected at the low impedance output of the

buffer amps, which are provided to avoid such miscalibration

and to allow higher slopes to be used.

V

_LOG= I_LOG× 4.55 kΩ

= 44 μA × 4.55 kΩ × log₁₀(I_PD/I_INTC

= V_Ylog₁₀(I_PD/I_INTC

)

(5)

)

Each buffer of the ADL5310 is essentially an uncommitted

operational amplifier with rail-to-rail output swing, good load

driving capabilities, and a typical unity-gain bandwidth of 15 MHz.

In addition to allowing the introduction of gain, using standard

feedback networks and thereby increasing the slope voltage V_Y,

the buffer can be used to implement multipole, low-pass filters,

threshold detectors, and a variety of other functions. Further

details on these applications can be found in the AD8304 data

sheet.

where V_Y= 200 mV/decade or 10 mV/dB.

Note that any resistive loading on LOG1 (LOG2) lowers this

slope and results in an overall scaling uncertainty. This is due to

the variability of the on-chip resistors compared to the off-chip

load. As a consequence, this practice is not recommended.

V_LOGmay also swing below ground when dual supplies (V_Pand

V_N) are used. When V_N= −0.5 V or larger, the input Pins INP1

(INP2) and IRF1 (INP2) may be positioned at ground level

simply by grounding VSUM. Care must be taken to limit the

power consumed by the input BJT devices when using a larger

negative supply, because self heating degrades the accuracy at

higher currents.

RESPONSE TIME AND NOISE CONSIDERATIONS

The response time and output noise of the ADL5310 are funda-

mentally a function of the signal current, I_PD. For small currents,

the bandwidth is proportional to I_PD, as shown in Figure 15. The

output low frequency voltage-noise spectral-density is a function

of I_PD(see Figure 17) and increases for small values of I_REF. Details

of the noise and bandwidth performance of translinear log amps

can be found in the AD8304 data sheet.

MANAGING INTERCEPT AND SLOPE

When using a single supply, VRDZ should be directly connected

to VREF to allow operation over the entire 6-decade input current

range. As noted in the Theory section, this introduces an accurate

offset voltage of 0.8 V at the LOG1 and LOG2 pins, equivalent

to four decades, resulting in a logarithmic transfer function that

can be written as

V

_LOG= V_Ylog₁₀(10⁴× I_PD/I_REF) = V_Ylog₁₀(I_PD/I_INTC

where I_INTC= I_REF/10⁴.

)

(6)

Rev. B | Page 12 of 20

Data Sheet

ADL5310

APPLICATIONS INFORMATION

5V

VPOS

COMM

665kΩ

0.5log (^I

)

PD1

1nA

VREF

VRDZ

OUT1

SCL1

VSUM

10

V

OUT1

I

RF1

12kΩ

IRF1

8kΩ

2kΩ

4.7nF

BIAS

6.69kΩ

BIN1

I

V

LOG

LOG1

TEMPERATURE

COMPENSATION

VNEG

C

451Ω

FLT1

10 nF

14.2kΩ

I

PD1

INP1

0.5log (^I

)

1kΩ

PD2

1nA

OUT2

SCL2

10

1nF

REFERENCE

GENERATOR

0.5V

2.5V

V

OUT2

20kΩ

80kΩ

12kΩ

COMM

IRF2

8kΩ

2kΩ

14.2kΩ

BIN2

4.7nF

BIAS

I

V

LOG

LOG2

TEMPERATURE

COMPENSATION

VNEG

C

451Ω

FLT2

10 nF

I

RF2

6.69kΩ

COMM

I

PD2

INP2

1kΩ

VSUM

VREF

VNEG

COMM

1nF

665kΩ

Figure 34. Basic Connections for Fixed Intercept Use

The ADL5310 is easy to use in optical supervisory systems and in

similar situations where a wide-ranging current is to be converted

to its logarithmic equivalent, that is, represented in decibel terms.

Basic connections for measuring a single current at each input

are shown in Figure 34, which also includes various nonessential

components, as explained next.

In addition, each input and reference pin (INP1, INP2, IRF1,

and IRF2) has a compensation network made up of a series

resistor and capacitor. The junction capacitance of the photo-

diode along with the network capacitance of the board artwork

around the input system creates a pole that varies widely with

input current. The RC network stabilizes the system by simul-

taneously reducing this pole frequency and inserting a zero to

compensate an additional pole inherent in the input system. In

general, the 1 nF, 1 kΩ network handles almost any photodiode

interface. In situations where larger active area photodiodes are

used, or when long input traces are used, the capacitor value may

need to be increased to ensure stability. Although the signal and

reference input systems are similar, additional care is required

to ensure stable operation of the reference inputs at temperature

extremes across the full current range of I_RF1(I_RF2). It is recom-

mended that filter components of 4.7 nF and 2 kΩ should be

used from Pin IRF1 (IRF2) to ground. Temperature-stable compo-

nents should always be used in critical locations, such as the

compensation networks. Y5V-type chip capacitors are to be

avoided due to their poor temperature stability.

The 2 V difference in voltage between the VREF and Input Pins

INP1 and INP2, in conjunction with the external 665 kΩ resistors

R_RF1and R_RF2, provides 3 µA reference currents I_RF1and I_RF2into

Pins IRF1 and IRF2. Connecting VRDZ to VREF raises the

voltage at LOG1 and LOG2 by 0.8 V, effectively lowering each

intercept current I_INTCby a factor of 10⁴to position it at 300 pA.

A wide range of other values for I_REF, from 3 nA to 3 mA, may

be used. The effect of such changes is shown in Figure 5 and

Figure 8.

Any temperature variation in R_RF1(R_RF2) must be taken into account

when estimating the stability of the intercept. Also, the overall

noise increases when using very low values of I_RF1(I_RF2). In fixed

intercept applications, there is little benefit in using a large reference

current, because doing so only compresses the low current end

of the dynamic range when operated from a single supply. The

capacitor between VSUM and ground is strongly recommended

to minimize the noise on this node, to reduce channel-to-channel

crosstalk, and to help provide clean reference currents.

The optional capacitor from LOG1 (LOG2) to ground forms a

single-pole, low-pass filter in combination with the 5 kΩ resis-

tance at this pin. For example, when using a C_FLTof 10 nF, the

3 dB corner frequency is 3.2 kHz. Such filtering is useful in

Rev. B | Page 13 of 20

ADL5310

Data Sheet

minimizing the output noise, particularly when I_PDis small.

Multipole filters are more effective in reducing the total noise;

examples are provided in the AD8304 data sheet.

Figure 35 shows the improvement in accuracy when using a

2-point calibration method. To perform this calibration, apply

two known currents, I₁and I₂, in the linear operating range

between 10 nA and 1 mA. Measure the resulting output, V₁and

V₂, respectively, and calculate the slope m and the intercept b:

Because the basic scaling at LOG1 (LOG2) is 0.2 V/decade, and

a 4 V swing at the buffer output would correspond to 20 decades,

it is often useful to raise the slope to make better use of the rail-

to-rail voltage range. For illustrative purposes, both channels in

Figure 34 provide a 0.5 V/decade overall slope (25 mV/dB).

Thus, using I_REF= 3 μA, V_LOGruns from 0.2 V at I_PD= 3 nA to

1.4 V at I_PD= 3 mA; the buffer output runs from 0.5 V to 3.5 V,

corresponding to a dynamic range of 120 dB (electrical, that is,

60 dB optical power).

m = (V₁– V₂)/[log₁₀(I₁) – log₁₀(I₂)]

b = V₁– m × log₁₀(I₁)

(7)

(8)

The same calibration can be performed with two known optical

powers, P₁and P₂. This allows for calibration of the entire

measurement system while providing a simplified relationship

between the incident optical power and V_LOGvoltage:

m = (V₁– V₂)/(P₁– P₂)

b = V₁– m × P₁

(9)

(10)

Further information on adjusting the slope and intercept, using

a negative supply, and additional operations can be found in the

AD8305 data sheet.

The uncalibrated error line in Figure 35 was generated assuming

that the slope of the measured output was 200 mV/decade when

in fact it was actually 194 mV/decade. Correcting for this discre-

pancy decreased measurement error up to 3 dB.

CALIBRATION

Each channel of the ADL5310 has a nominal slope and intercept

at LOG1 (LOG2) of 200 mV/decade and 300 pA, respectively,

when configured as shown in Figure 34. These values are

untrimmed and the slope alone may vary by as much as 7.5%

over temperature. For this reason, it is recommended that a

simple calibration be done to achieve increased accuracy. While

the ADL5310 offers improved slope and intercept matching

compared to a randomly selected pair of AD8305 log amps, the

specified accuracy can only be achieved by calibrating each

channel individually.

MINIMIZING CROSSTALK

Combining two high-dynamic-range logarithmic converters in

one IC carries potential pitfalls concerning channel-to-channel

isolation. Special care must be taken in several areas to ensure

acceptable crosstalk performance, particularly when one or

both channels may operate at very low input currents. Fastidious

supply bypassing, which is also necessary for overall stability,

and careful board layout are important first steps for

minimizing crosstalk.

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

4

While the shared bias circuitry improves channel-to-channel

matching and reduces power consumption, it is also a source of

crosstalk that must be mitigated. The VSUM pins, which are inter-

nally shorted, should be bypassed with at least 1 nF to ground,

and 20 nF is recommended for operation at the lowest currents

(<30 nA). VSUM is of particular importance because it acts as a

reference voltage input for each input system, but without the

bandwidth limitation at low currents that the primary inputs incur.

Disturbances at the VSUM pin that are well within the bandwidth

of the input are tracked by the loop and do not generate distur-

bances at the output (aside from the generally minor perturbation

in reference currents caused by voltage variations at IRF1 and

IRF2).

UNCALIBRATED ERROR

3

2

MEASURED OUTPUT

1

0

CALIBRATED ERROR

–1

–2

–3

IDEAL OUTPUT

1n

10n

100n

1µ

10µ

(A)

100µ

1m

10m

I

PD

Figure 35. Using 2-Point Calibration to Increase Measurement Accuracy

For this reason, the pole frequency at VSUM, which has a 16 kΩ

typical source resistance, should be set below the minimum input

system bandwidth for the lowest input current to be encountered.

Because the low frequency noise at VSUM is also tracked by the

loop within its available bandwidth, this is also a criterion for

reducing the noise contribution at the output from the thermal

noise of the 16 kΩ source resistance at VSUM.

Rev. B | Page 14 of 20

Data Sheet

ADL5310

A 10 nF capacitor on each VSUM pin (20 nF parallel equivalent)

combined with the 16 kΩ source resistance yields a 500 Hz pole,

which is sufficiently below the bandwidth for the minimum

input current of 3 nA.

voltage, followed by differencing of the two signal levels in the

digital domain for a relative gain or absorbance measurement.

A more straightforward analog implementation includes the use

of a current mirror, as shown in Figure 37. The current mirror

is used to feed an opposite polarity replica of the cathode photo-

current of PD2 into Channel 2 of the ADL5310. This allows one

channel to be used as an absolute power meter for the optical

signal incident on PD2, while the opposite channel is used to

directly compute the log ratio of the two input signals.

Residual crosstalk disturbance is particularly problematic at the

lowest currents for two reasons. First, the loop is unable to reject

summing node disturbances beyond the limited bandwidth.

Second, the settling response at the lowest currents to any residual

disturbance is significantly slower than that for input currents

even one or two decades higher (see Figure 18).

5V

VPOS

COMM

5V

0.1µF

Φ *

OUT2

2

VSUM

12

1.2

1.0

0.8

0.6

0.4

0.2

0

ACTIVE CHANNEL OUTPUT PULSE, 1-DECADE STEP

3µA TO 30µA

ADL5310

1nF

9

I

IN2

*Φ (V) ≅ 0.2log

(

)

2

10

100pA

I

=I

6

IN2 PD2

SCL2

log

INP2

I

– 3nA

I

INP

1kΩ

BIN2

3

– 10nA

I

– 100nA

INP

4.7nF

INP

I

LOG2

TEMPERATURE

COMPENSATION

1nF

0

I

– 30nA

IRF2

INP

2MΩ

–3

–6

INACTIVE CHANNEL RESPONSE

α

**

21

OUT1

SCL1

VRDZ

VREF

1kΩ

BIAS

GENERATOR

4.7nF

0

0.5

1.0

1.5

2.0

2.5

TIME (ms)

I

IN1

**α (V) ≅ 0.2log

(

)

21

10

I

PD2

Figure 36. Crosstalk Pulse Response for Various Input Current Values

I

PD2

IRF1

log

PD2

InGaAs PIN

Figure 36 shows the measured response of an inactive channel

(dc input) to a 1-decade current step on the input of the active

channel for several inactive channel dc current values. Additional

system considerations may be necessary to ensure adequate

settling time following a known transient when one or both

channels are operating at very low input currents.

BIN1

1kΩ

4.7nF

I

LOG1

TEMPERATURE

COMPENSATION

1nF

5V

PD1

InGaAs PIN

I

IN1

INP1

1kΩ

COMM

0.1µF

4.7nF

VSUM

VNEG

RELATIVE AND ABSOLUTE POWER

MEASUREMENTS

1nF

Figure 37. Absolute and Relative Power Measurement Application

Using Modified Wilson Current Mirror

When properly calibrated, the ADL5310 provides two independent

channels capable of accurate absolute optical power measurements.

Often, it is desirable to measure the relative gain or absorbance

across an optical network element, such as an optical amplifier

or variable attenuator. If each channel has identical logarithmic

slopes and intercepts, this can easily be done by differencing the

output signals of each channel. In reality, channel mismatch can

result in significant errors over a wide range of input levels if

left uncompensated. Postprocessing of the signal can be used to

account for individual channel characteristics. This requires a

simple calculation of the expected input level for a measured log

The presented current mirror is a modified Wilson mirror. Other

current mirror implementations would also work, though the

modified Wilson mirror provides fairly constant performance

over temperature. It is essential to use matched pair transistors

when designing the current mirror to minimize the effects of

temperature gradients and beta mismatch.

Rev. B | Page 15 of 20

ADL5310

Data Sheet

The solution in Figure 37 is no longer subject to potential channel

mismatch issues. Individual channel slope and intercept charac-

teristics can be calibrated independently. The accuracy was verified

using a pair of calibrated current sources. The performance of

the circuit depicted in Figure 37 is shown in Figure 38 and

Figure 39. Multiple transfer functions and error plots are provided

for various power levels. The accuracy is better than 0.1 dB over

a 5-decade range. The dynamic range is slightly reduced for strong

I_INinput currents. This is due to the limited available swing of

the VLOG pin and can be recovered through careful selection

of input and output optical tap coupling ratios.

CHARACTERIZATION METHODS

During the characterization of the ADL5310, the device was

treated as a precision current-input logarithmic converter, because

it is impractical to generate accurate photocurrents by illumin-

ating a photodiode. The test currents were generated by using

either a well calibrated current source, such as the Keithley 236,

or a high value resistor from a voltage source to the input pin.

Great care is needed when using very small input currents. For

example, the triax output connection from the current generator

was used with the guard tied to VSUM. The input trace on the

PC board was guarded by connecting adjacent traces to VSUM.

1.8

These measures are needed to minimize the risk of leakage current

paths. With 0.5 V as the nominal bias on the INP1 (INP2) pin, a

leakage-path resistance of 1 GΩ to ground would subtract 0.5 nA

from the input, which amounts to a −1.6 dB error for a 3 nA source

current. Additionally, the very high sensitivity at the input pins

and the long cables commonly needed during characterization

allow 60 Hz and RF emissions to introduce substantial measure-

ment errors. Careful guarding techniques are essential to reducing

the pickup of these spurious signals.

1.6

φ

WHEN I = 100µA

PD1

2

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

α

FOR MULTIPLE VALUES OF I

PD1

21

Additional information, including test setups, can be found in

the AD8305 and ADL5306 data sheets.

–20

–10

0

10

LOG [I

20

/I

30

40

50

60

] (dB)

10 PD1 PD2

Figure 38. Absorbance and Absolute Power Transfer Functions for

Wilson Mirror ADL5310 Combination

0.5

0.4

0.3

I

= 1µA

PD1

0.2

0.1

0

I

= 10µA

–0.1 PD1

–0.2

–0.3

I

= 100µA

PD1

0

–0.4

–0.5

–40

–30 –20 –10

10

20

30

40

50

60

LOG [I

/I

] (dB)

10 PD1 PD2

Figure 39. Log Conformance for Wilson Mirror ADL5310 Combination,

Normalized to 10 mA Channel 1 Input Current, I_IN1

Rev. B | Page 16 of 20

Data Sheet

ADL5310

EVALUATION BOARD

An evaluation board is available for the ADL5310 (Figure 40 shows the schematic). It can be configured for a wide variety of experiments.

The gain of each buffer amp is factory-set to unity, providing a slope of 200 mV/dec, and the intercept is set to 300 pA. Table 4 describes

the various configuration options.

Table 4. Evaluation Board Configuration Options

Component

Function

Default Condition

P1

Supply Interface. Provides access to the Supply Pins VNEG, COMM, and

VPOS.

P1 = installed

P2, R1, R3, R8, R9,

Monitor Interface. By adding 0 Ω resistors to R1, R3, R8, R9, R17, R22, and

P2 = not installed

R17, R22, R25, R30 R25, the VRDZ, VREF, VSUM, BIN1, BIN2, OUT1, and OUT2 pin voltages

can be monitored using a high impedance probe. VBIAS allows for the

external bias voltages to be applied to J1 and J2. If R30 = 0 Ω,

VBIAS = VREF.

R1 = R3 = R8 = open (size 0402)

R9 = R17 = open (size 0402)

R22 = R25 = R30 = open (size 0402)

R5, R6, R7, R16,

R18, R19, R20,

R21, R31, R32, C4,

C14, C15, C16,

C19, C20

Buffer Amplifier/Output Interface. The logarithmic slopes of the ADL5310

can be altered using each buffer’s gain-setting resistors, R5 and R6, and

R18 and R19. R7, R16, R31, R32, C19, and C20 allow for variation in the

buffer loading. R20, R21, C4, C14, C15, and C16 are provided for a variety

of filtering applications.

R5 = R19 = 0 Ω (size 0402)

R7 = R16 = 0 Ω (size 0402)

R20 = R21 = 0 Ω (size 0402)

R6 = R18 = open (size 0402)

R31 = R32 = open (size 0402)

C4 = C14 = open (size 0402)

C19 = C20 = open (size 0402)

C15 = C16 = open (size 0402)

LOG1 = OUT1 = installed

LOG2 = OUT2 = installed

R2, R28, R29

Intercept Adjustment. The voltage dropped across Resistors R28 and R29

determines the intercept reference current for each log amp, nominally

set to 3 µA using a 665 kΩ 1% resistor. R2 can be used to adjust the output

offset voltage at the LOG1 and LOG2 outputs.

R28 = R29 = 665 kΩ (size 0402)

R2 = 0 Ω (size 0402)

R4, R10, R11, C2,

C3, C5, C6, C8, C9

Supply Decoupling.

C2 = C5 = C9 = 100 pF (size 0402)

C3 = C6 = C8 = 0.01 µF (size 0402)

R4 = R10 = R11 = 0 Ω (size 0402)

C1, C7

Filtering VSUM.

C1 = C7 = 0.01 µF (size 0402)

R12, R13, R14,

R15, C10, C11,

C12, C13

Input Compensation. Provides essential HF compensation at the Input

Pins INP1, INP2, IRF1, and IRF2.

R12 = R15 = 1 kΩ (size 0402)

R13 = R14 = 2 kΩ (size 0402)

C10 = C13 = 1 nF (size 0402)

C11 = C12 = 4.7 nF (size 0402)

IREF, INPT

J1, J2

Input Interface. The test board is configured to accept current through the IREF = INPT = installed

SMA connectors labeled INP1 and INP2. Through-holes are provided to

connect photodiodes in place of the INP1 and INP2 SMAs for optical

interfacing. By removing R28 (R29 for INP2), a second current can be

applied to the IRF1 (IRF2 for INP2) input (also SMA) for evaluating the

ADL5310 in log ratio applications.

SC-Style Photodiode. Provides for the direct mounting of SC-style

photodiodes.

J1 = J2 = open

Rev. B | Page 17 of 20

ADL5310

Data Sheet

VRDZ

VNEG

C3 0.01µF

R7 0Ω

OUT1

R32

OPEN

C20

OPEN

R3

OPEN

R2

3

R4

0Ω

C2

2

1

J2

PHOTODIODE

0Ω

VBIAS

R29

R8 OPEN

C4 OPEN

100pF

21

R5 0Ω

C1 0.01µF

R28

C16

OPEN

24

23

22

20

19

665kΩ 665kΩ

R20

R24

LOG1

0Ω

R1

R6

VSUM

INP1

1

2

3

4

5

6

18

17

16

15

14

13

VSUM

INP1

IRF1

SCL1

BIN1

OPEN

R26 0Ω

R27 0Ω

R25

BIN1

LOG2

BIN2

LOG1

LOG2

BIN2

ADL5310

OPEN

IRF1

IRF2

INP2

IRF2

R21

R22

INP2

VSUM

0Ω

OPEN

R23

R18

C14

OPEN

C15

SCL2

OPEN

LOG2

0Ω

R19

0Ω

7

8

9

10

11

12

R15 R14 R13 R12

1kΩ 2kΩ 2kΩ 1kΩ

R9

OPEN

1

2

3

4

5

6

OUT1

VREF

C5 100pF

C9 100pF

R17

OPEN

C13 C12 C11 C10

1nF 4.7nF 4.7nF 1nF

BIN1

LOG1

LOG2

BIN2

R11

0Ω

C8 0.01µF

R10

0Ω

C6 0.01µF

OUT2

R16 0Ω

3

R31

OPEN

C19

OPEN

2

1

J1

VBIAS

PHOTODIODE

AGND

2

OUT2

VPOS

1

3

VNEG

7

8

VREF

C7 0.01µF

R30 OPEN

P1

VBIAS

P2

Figure 40. Evaluation Board Schematic

Rev. B | Page 18 of 20

Data Sheet

ADL5310

Figure 41. Component-Side Layout

Figure 42. Component-Side Silkscreen

Rev. B | Page 19 of 20

ADL5310

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

4.10

4.00 SQ

3.90

0.30

0.25

0.20

PIN 1

INDICATOR

PIN 1

24

19

18

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

1

0.50

BSC

2.20

2.10 SQ

2.00

EXPOSED

PAD

13

12

6

7

0.50

0.40

0.30

0.20 MIN

TOP VIEW

SIDE VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.

Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-24-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADL5310ACPZ-REEL7

ADL5310-EVALZ

–40°C to +85°C

24-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

CP-24-10

registered trademarks are the property of their respective owners.

D04415-0-4/18(B)

Rev. B | Page 20 of 20


型号：	ADL5310-EVALZ
厂家：	ADI
描述：	Dual Logarithmic Converter
文件：	总20页 (文件大小：570K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADL5310-EVALZ [ADI]

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