ADL5353XCPZ-R7 [ADI]
IC,RF MIXER,BICMOS,LLCC,20PIN,PLASTIC;
| 型号： | ADL5353XCPZ-R7 |
| 厂家： | 
ADI |
| 描述： | IC,RF MIXER,BICMOS,LLCC,20PIN,PLASTIC 信息通信管理 |
| 文件： | 总16页 (文件大小：1262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2300 MHz to 2900 MHz Balanced Mixer,
LO Buffer, IF Amplifier, and RF Balun
ADL5353
Preliminary Technical Datasheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
IFGM
20
IFOP
19
IFON
18
PWDN
17
LEXT
16
RF frequency range of 2300 MHz to 2900 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.5 dB
ADL5353
1
2
3
4
5
15
14
13
12
11
VPIF
RFIN
LOI2
SSB noise figure of 9.9 dB
SSB noise figure with 5 dBm blocker of 21 dB
Input IP3 of 25 dBm
Input P1dB of 10.6 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle 5 mm × 5 mm, 20-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
VPSW
VGS1
VGS0
LOI1
RFCT
COMM
COMM
BIAS
GENERATOR
APPLICATIONS
6
7
LGM3
8
9
10
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
VLO3
VLO2
LOSW
NC
NC = NO CONNECT
Figure 1.
The ADL5353 provides two switched LO paths that can be used
in TDD applications where it is desirable to rapidly switch
between two local oscillators. LO current can be externally set
using a resistor to minimize dc current commensurate with the
desired level of performance. For low voltage applications, the
ADL5353 is capable of operation at voltages down to 3.3 V with
substantially reduced current. Under low voltage operation, an
additional logic pin is provided to power down (<200 μA) the
circuit when desired.
GENERAL DESCRIPTION
The ADL5353 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and LO balancing circuitry
to allow for single-ended operation. The ADL5353 incorporates
an RF balun, allowing for optimal performance over a 2300 MHz
to 2900 MHz The balanced passive mixer arrangement provides
good LO-to-RF leakage, typically better than −39 dBm, and
excellent intermodulation performance. The balanced mixer
core also provides extremely high input linearity, allowing the
device to be used in demanding cellular applications where in-
band blocking signals may otherwise result in the degradation
of dynamic performance. A high linearity IF buffer amplifier
follows the passive mixer core to yield a typical power conversion
gain of 8.4 dB and can be used with a wide range of output
impedances.
The ADL5353 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
Single
Mixer
Single Mixer
and IF Amp
Dual Mixer
and IF Amp
500 to 1700
1200 to 2500
2300 to 2900
ADL5367
ADL5365
ADL5357
ADL5355
ADL5353
ADL5358
ADL5356
ADL5854
PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks are theproperty of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADL5353
Preliminary Technical Datasheet
TABLE OF CONTENTS
Features .............................................................................................. 1
RF Subsystem.................................................................................8
LO Subsystem ................................................................................8
Applications Information.............................................................. 10
Basic Connections...................................................................... 10
IF Port .......................................................................................... 10
Bias Resistor Selection............................................................... 10
Mixer VGS Control DAC .......................................................... 10
Evaluation Board ............................................................................ 12
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
5 V Performance........................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance........................................................................... 7
Circuit Description........................................................................... 8
Rev. PrA | Page 2 of 16
Preliminary Technical Datasheet
ADL5353
SPECIFICATIONS
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2600 MHz, fLO = 2803 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB over a limited bandwidth
TBD
50
dB
Ω
MHz
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage1
LO INTERFACE
2300
2900
Differential impedance, f = 200 MHz
Externally generated
230||0.75
5.0
Ω||pF
MHz
V
30
3.3
450
5.5
LO Power
Return Loss
−6
0
TBD
50
+10
TBD
0.4
dBm
dB
Ω
Input Impedance
LO Frequency Range
POWER-DOWN (PWDN) INTERFACE 2
PWDN Threshold
Logic 0 Level
TBD
MHz
1.0
V
V
Logic 1 Level
1.4
V
PWDN Response Time
Device enabled, IF output to 90% of its final level
Device disabled, supply current < 5 mA
Device enabled
160
220
0.0
70
ns
ns
μA
μA
PWDN Input Bias Current
Device disabled
1 Apply the supply voltage from the external circuit through the choke inductors.
2 PWDN function is intended for use with VS ≤ 3.6 V only.
Rev. PrA | Page 3 of 16
ADL5353
Preliminary Technical Datasheet
5 V PERFORMANCE
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2600 MHz, fLO = 2803 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
8.5
14.5
9.9
dB
dB
dB
dB
SSB Noise Figure Under Blocking
5 dBm blocker present 10 MHz from wanted RF input,
LO source filtered
TBD
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
fRF1 = 2599.5 MHz, fRF2 = 2600.5 MHz, fLO = 2803 MHz,
each RF tone at −10 dBm
fRF1 = 2600 MHz, fRF2 = 2650 MHz, fLO = 2803 MHz,
each RF tone at −10 dBm
25
48
dBm
dBm
Input 1 dB Compression Point (IP1dB)
LO-to-IF Leakage
LO-to-RF Leakage
RF-to-IF Isolation
IF/2 Spurious
IF/3 Spurious
10.6
−15
−36
−28
−63
−73
dBm
dBm
dBm
dBc
dBc
dBc
Unfiltered IF output
−10 dBm input power
−10 dBm input power
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
4.5
5
5.5
V
LO supply, resistor programmable
IF supply, resistor programmable
VS = 5 V
TBD
TBD
186
mA
mA
mA
Total Quiescent Current
Rev. PrA | Page 4 of 16
Preliminary Technical Datasheet
ADL5353
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Supply Voltage, VS
RF Input Level
Rating
5.5 V
20 dBm
13 dBm
6.0 V
LO Input Level
IFOP, IFON Bias Voltage
VGS0, VGS1, LOSW, PWDN
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering, 60 sec)
5.5 V
1.2 W
25°C/W
150°C
−40°C to +85°C
−65°C to +150°C
260°C
ESD CAUTION
Rev. PrA | Page 5 of 16
ADL5353
Preliminary Technical Datasheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
VPIF 1
RFIN 2
15 LOI2
14 VPSW
13 VGS1
12 VGS0
11 LOI1
ADL5353
TOP VIEW
(Not to Scale)
RFCT
COMM
COMM
3
4
5
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. MUST BE SOLDERED
TO GROUND.
Figure 2. Pin Conꢀguration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
VPIF
RFIN
Positive Supply Voltage for IF Ampliꢀer.
RF Input. Must be ac-coupled.
3
RFCT
COMM
RF Balun Center Tap (AC Ground).
Device Common (DC Ground).
4, 5
6, 8
7
9
10
VLO3, VLO2 Positive Supply Voltages for LO Ampliꢀer.
LGM3
LOSW
NC
LO Ampliꢀer Bias Control.
LO Switch. LOI1 selected for 0 V, and LOI2 selected for 3 V.
No Connect.
11, 15
12, 13
14
LOI1, LOI2
LO Inputs. Must be ac-coupled.
VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
VPSW
Positive Supply Voltage for LO Switch.
16
LEXT
IF Return. This pin must be grounded.
17
18, 19
20
PWDN
IFON, IFOP
IFGM
Power Down. Connect this pin to ground for normal operation and connect this pin to 3.0 V for disable mode.
Diꢁerential IF Outputs (Open Collectors). Each requires an external dc bias.
IF Ampliꢀer Bias Control.
EPAD (EP)
Exposed pad. Must be soldered to ground.
Rev. PrA | Page 6 of 16
Preliminary Technical Datasheet
ADL5353
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2600 MHz, fLO = 2803 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
Figure 3. Supply Current vs. RF Frequency
Figure 6. Input IP2 vs. RF Frequency
Figure 4. Power Conversion Gain vs. RF Frequency
Figure 7. Input P1dB vs. RF Frequency
Figure 5 .Input IP3 vs. RF Frequency
Figure 8. SSB Noise Figure vs. RF Frequency
Rev. PrA | Page 7 of 16
ADL5353
Preliminary Technical Datasheet
CIRCUIT DESCRIPTION
The ADL5353 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated
into a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
As the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input
of the IF amplifier, where high peak signal levels can compromise
the compression and intermodulation performance of the system.
This termination is accomplished by the addition of a sum
network between the IF amplifier and the mixer and also in
the feedback elements in the IF amplifier.
The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network, and IF
amplifier.
The LO subsystem consists of an SPDT-terminated FET switch
and a three-stage limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input.
The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance that is
required to achieve the overall performance. The balanced open-
collector output of the IF amplifier, with impedance modified
by the feedback within the amplifier, permits the output to be
connected directly to a high impedance filter, differential amplifier,
or an analog-to-digital input while providing optimum second-
order intermodulation suppression. The differential output
impedance of the IF amplifier is approximately 200 Ω. If operation
in a 50 Ω system is desired, the output can be transformed to
50 Ω by using a 4:1 transformer.
A block diagram of the device is shown in Figure 9.
IFGM
IFOP
IFON
PWDN
LEXT
20
19
18
17
16
ADL5353
1
2
3
4
5
15
14
13
12
11
VPIF
RFIN
LOI2
VPSW
VGS1
VGS0
LOI1
RFCT
COMM
COMM
BIAS
GENERATOR
The intermodulation performance of the design is generally
limited by the IF amplifier. The IP3 performance can be optimized
by adjusting the IF current with an external resistor.
Additionally, dc current can be saved by increasing either or
both resistors. It is permissible to reduce the dc supply voltage
to as low as 3.3 V, further reducing the dissipated power of the
part. (Note that no performance enhancement is obtained by
reducing the value of these resistors and excessive dc power
dissipation may result.)
6
7
LGM3
8
9
10
VLO3
VLO2
LOSW
NC
NC = NO CONNECT
Figure 9. Simplified Schematic
LO SUBSYSTEM
RF SUBSYSTEM
The ADL5353 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can be
dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range
of 2300 MHz to 2900 MHz.
Rev. PrA | Page 8 of 16
Preliminary Technical Datasheet
ADL5353
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
can operate with a supply voltage as low as 3.3 V, resulting in
substantial dc power savings.
In addition, when operating with supply voltages below 3.6 V,
the ADL5353 has a power-down mode that permits the dc
current to drop to <200 μA.
All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.
The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the
LO amplifier by raising the value of the external bias control
resistor. For dc current critical applications, the LO chain
All pins, including the RF pins, are ESD protected and have
been tested up to a level of 1500 V HBM and 500 V CDM.
Rev. PrA | Page 9 of 16
ADL5353
Preliminary Technical Datasheet
APPLICATIONS INFORMATION
BASIC CONNECTIONS
impedance is needed, use a 4:1 impedance transformer, as
shown in Figure 10.
The ADL5353 mixer is designed to downconvert radio
frequencies (RF) primarily between 2300 MHz and 2900 MHz
to lower intermediate frequencies (IF) between 30 MHz and
450 MHz. Figure 10 depicts the basic connections of the mixer.
It is recommended to ac-couple RF and LO input ports to
prevent non-zero dc voltages from damaging the RF balun or LO
input circuit. The RFIN capacitor value of 3 pF is recommended
to provide the optimized RF input return loss for the desired
frequency band.
BIAS RESISTOR SELECTION
Two external resistors, RBIAS IF and RBIAS LO, are used to adjust the
bias current of the integrated amplifiers at the IF and LO terminals.
It is necessary to have a sufficient amount of current to bias both
the internal IF and LO amplifiers to optimize dc current vs.
optimum IIP3 performance.
MIXER VGS CONTROL DAC
The ADL5353 features two logic control pins, VGS0 (Pin 12) and
VGS1 (Pin 13), that allow programmability for internal gate-to-
source voltages for optimizing mixer performance over desired
frequency bands. The evaluation board defaults both VGS0 and
VGS1 to ground.
IF PORT
The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.
The real part of the output impedance is approximately
200 Ω, which matches many commonly used SAW filters
without the need for a transformer. This results in a voltage
conversion gain that is approximately 6 dB higher than the
power conversion gain, as shown in Table 3. When a 50 Ω output
Rev. PrA | Page 10 of 16
Preliminary Technical Datasheet
ADL5353
+5V
100pF
150pF
470nH
470nH
4:1
IF OUT
R
10kΩ
BIAS IF
+5V
20
19
18
17
16
10pF
4.7µF
22pF
ADL5353
+5V
1
2
3
4
5
15
14
13
12
11
LO2 IN
+5V
3pF
RF IN
10pF
10pF
0.1µF
BIAS
GENERATOR
22pF
LO1 IN
6
7
8
9
10
R
BIAS LO
10kΩ
+5V
10pF
10pF
Figure 10. Typical Application Circuit
Rev. PrA | Page 11 of 16
ADL5353
Preliminary Technical Datasheet
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. ꢀe standard evaluation board schematic is shown in
Figure 11. ꢀe evaluation board is fabricated using Rogers®
RO3003 material. Table 6 describes the various conꢁguration
options of the evaluation board. Evaluation board layout is shown
in Figure 12 to Figure 15.
L5
470nH
T1
IF1-OUT
VPOS
C18
100pF
C19
100pF
L4
470nH
R1
0Ω
C17
150pF
R24
0Ω
R25
0Ω
PWR_UP
R21
10kΩ
R14
910Ω
L3
0Ω
C12
22pF
LO2_IN
VPOS
VPOS
VPIF
LOI2
VPSW
VGS1
VGS0
LOI1
C2
C21
C20
R22
10kΩ
10µF
10pF
10pF
RFIN
RF-IN
C22
1nF
C1
3pF
R23
15kΩ
ADL5353
RFCT
COMM
COMM
C5
0.01µF
C4
10pF
VGS1
VGS0
LO1_IN
C10
22nF
LOSEL
VPOS
R9
1.1kΩ
C6
10pF
R4
10kΩ
VPOS
C8
10pF
Figure 11. Evaluation Board Schematic
Rev. PrA | Page 12 of 16
Preliminary Technical Datasheet
ADL5353
Table 6. Evaluation Board Configuration
Components
Description
Default Conditions
C2, C6, C8, C18, C19, Power Supply Decoupling. Nominal supply decoupling consists of
C2 = 10 μF (size 0603),
C20, C21
a 10 μF capacitor to ground in parallel with a 10 pF capacitor to
ground positioned as close to the device as possible.
C6, C8, C20, C21 = 10 pF (size 0402),
C18, C19 = 100 pF (size 0402)
C1, C4, C5
RF Input Interface. The input channels are ac-coupled through C1.
C4 and C5 provide bypassing for the center taps of the RF input baluns.
C1 = 3 pF (size 0402), C4 = 10 pF (size 0402),
C5 = 0.01 μF (size 0402)
T1, C17, L4, L5,
R1, R24, R25
IF Output Interface. The open-collector IF output interfaces are
biased through pull-up choke inductors L4 and L5. T1is a 4:1
impedance transformer used to provide a single-ended IF output
interface, with C17 providing center-tap bypassing. Remove R1 for
balanced output operation.
T1 = TC4-1W+ (Mini-Circuits),
C17 = 150 pF (size 0402),
L4, L5 = 470 nH (size 1008),
R1, R24, R25 = 0 Ω (size 0402)
C10, C12, R4
LO Interface. C10 and C12 provide ac coupling for the LO1_IN and
LO2_IN local oscillator inputs. LOSEL selects the appropriate LO
input for both mixer cores. R4 provides a pull-down to ensure that
LO1_IN is enabled when the LOSEL test point is logic low.
LO2_IN is enabled when LOSEL is pulled to logic high.
C10, C12 = 22 pF (size 0402),
R4 = 10 kΩ (size 0402)
R21
PWDN Interface. R21 pulls the PWDN logic low and enables the
device. The PWR_UP test point allows the PWDN interface to be
exercised using the external logic generator. Grounding the
PWDN pin for nominal operation is allowed. Using the PWDN pin
when supply voltages exceed 3.3 V is not allowed.
R21 = 10 kΩ (size 0402)
C22, L3, R9, R14, R22, Bias Control. R22 and R23 form a voltage divider to provide 3 V
C22 = 1 nF (size 0402), L3 = 0 Ω (size 0603),
R9 = 1.1 kΩ (size 0402), R14 = 910 Ω (size 0402),
R22 = 10 kΩ (size 0402), R23 = 15 kΩ (size 0402),
VGS0 = VGS1 = 3-pin shunt
R23, VGS0, VGS1
for logic control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins. It is
recommended to pull these two pins to ground for nominal
operation. R9 sets the bias point for the internal LO buffers.
R14 sets the bias point for the internal IF amplifier.
Rev. PrA | Page 13 of 16
ADL5353
Preliminary Technical Datasheet
Figure 12. Evaluation Board Top Layer
Figure 14. Evaluation Board Power Plane, Internal Layer 2
Figure 13. Evaluation Board Ground Plane, Internal Layer 1
Figure 15. Evaluation Board Bottom Layer
Rev. PrA | Page 14 of 16
Preliminary Technical Datasheet
OUTLINE DIMENSIONS
ADL5353
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.65
BSC
PIN 1
INDICATOR
4.75
BSC SQ
3.20
3.10 SQ
3.00
EXPOSED
PAD
(BOTTOM VIEW)
10
11
6
0.75
0.60
0.50
TOP VIEW
2.60 BSC
0.70
0.65
0.60
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.01 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.05
0.35
0.28
0.23
SEATING
PLANE
0.20 REF
COMPLIANT TOJEDEC STANDARDS MO-220-VHHC
Figure 16. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad (CP-20-5)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Ordering
Quantity
Model
Package Description
ADL5353XCPZ-R71
ADL5353XCPZ-WP1
ADL5353-EVALZ1
−40°C to +85°C
−40°C to +85°C
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-20-5
CP-20-5
1,500, 7”Tape and Reel
36, Waꢀe Pack
1
1 Z = RoHS Compliant Part.
Rev. PrA | Page 15 of 16
ADL5353
NOTES
Preliminary Technical Datasheet
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR09117-0-4/10(PrA)
Rev. PrA | Page 16 of 16
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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