ADL5354ACPZ-R7 [ADI]
2200 MHz TO 2700 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun;
| 型号： | ADL5354ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | 2200 MHz TO 2700 MHz, Dual-Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun 电信 信息通信管理 电信集成电路 |
| 文件： | 总24页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2200 MHz to 2700 MHz, Dual-Balanced
Mixer, LO Buffer, IF Amplifier, and RF Balun
ADL5354
FUNCTIONAL BLOCK DIAGRAM
FEATURES
RF frequency range of 2200 MHz to 2700 MHz
IF frequency range of 30 MHz to 450 MHz
Power conversion gain: 8.6 dB
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
MNIN
MNCT
COMM
VPOS
COMM
VPOS
COMM
DVCT
DVIN
LOI2
SSB noise figure of 10.6 dB
Input IP3 of 26.1 dBm
Input P1dB of 10.6 dBm
Typical LO power of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed paddle, 6 mm × 6 mm, 36-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
VGS2
VGS1
VGS0
LOSW
PWDN
VPOS
COMM
LOI1
APPLICATIONS
ADL5354
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
Figure 1.
commensurate with the desired level of performance. For low
voltage applications, the ADL5354 is capable of operation at
voltages as low as 3.3 V with substantially reduced current. For
low voltage operation, an additional logic pin is provided to
power down (~300 μA) the circuit when desired.
GENERAL DESCRIPTION
The ADL5354 uses a highly linear, doubly balanced, passive mixer
core along with integrated RF and local oscillator (LO) balancing
circuitry to allow single-ended operation. The ADL5354 incor-
porates the RF baluns, allowing for optimal performance over a
2200 MHz to 2700 MHz RF input frequency range. The balanced
passive mixer arrangement provides good LO-to-RF leakage,
typically better than −37 dBm, and excellent intermodulation
performance. The balanced mixer core also provides extremely
high input linearity, allowing the device to be used in demanding
cellular applications where in-band blocking signals may other-
wise result in the degradation of dynamic performance. A high
linearity IF buffer amplifier follows the passive mixer core to yield
a typical power conversion gain of 8 dB and can be used with a
wide range of output impedances.
The ADL5354 is fabricated using a BiCMOS high performance
IC process. The device is available in a 6 mm × 6 mm, 36-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency
(MHz)
Single
Mixer
Single Mixer
and IF Amp
Dual Mixer
and IF Amp
500 to 1700
1200 to 2500
2200 to 2700
ADL5367
ADL5365
ADL5357
ADL5355
ADL5353
ADL5358
ADL5356
ADL5354
The ADL5354 provides two switched LO paths that can be used
in time division duplex (TDD) applications where it is desirable
to ping-pong between two local oscillators. LO current can be
externally set using a resistor to minimize dc current
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADL5354
TABLE OF CONTENTS
Features .............................................................................................. 1
Spur Tables ...................................................................................... 15
5 V Performance......................................................................... 15
3.3 V Performance...................................................................... 15
Circuit Description......................................................................... 16
RF Subsystem.............................................................................. 16
LO Subsystem ............................................................................. 16
Applications Information.............................................................. 18
Basic Connections...................................................................... 18
IF Port .......................................................................................... 18
Bias Resistor Selection ............................................................... 18
Mixer VGS Control DAC.......................................................... 18
Evaluation Board ............................................................................ 20
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Performance........................................................................... 4
3.3 V Performance........................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance........................................................................... 7
3.3 V Performance...................................................................... 14
REVISION HISTORY
2/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5354
SPECIFICATIONS
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 =
R5 = 1 kΩ, ZO = 50 ꢀ, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB over a limited bandwidth
20
50
dB
Ω
MHz
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage1
LO INTERFACE
2200
2700
Differential impedance, f = 200 MHz
Externally generated
230||0.75
5.0
Ω||pF
MHz
V
30
3.3
450
5.5
LO Power
−6
0
+10
2670
0.4
dBm
dB
Ω
Return Loss
13
50
Input Impedance
LO Frequency Range
POWER-DOWN (PWDN) INTERFACE2
PWDN Threshold
Logic 0 Level
1750
MHz
1.0
V
V
Logic 1 Level
1.4
V
PWDN Response Time
Device enabled, IF output to 90% of its final level
Device disabled, supply current < 5 mA
Device enabled
160
230
0
ns
ns
μA
μA
PWDN Input Bias Current
Device disabled
70
1 Apply supply voltage from external circuit through choke inductors.
2 PWDN function is intended for use with VS ≤ 3.6 V only.
Rev. 0 | Page 3 of 24
ADL5354
5 V PERFORMANCE
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kΩ, R2 = R5 = 1 kΩ,
VGS0 = VGS1 = VGS2 = 0 V, and ZO = 50 ꢀ, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
8.6
dB
dB
dB
dBm
14.6
10.6
26.1
Input Third-Order Intercept (IIP3)
fRF1 = 2534.5 MHz, fRF2 = 2535.5 MHz, fLO = 2332 MHz,
each RF tone at −10 dBm
Input Second-Order Intercept (IIP2)
fRF1 = 2535 MHz, fRF2 = 2585 MHz, fLO = 2332 MHz,
each RF tone at −10 dBm
50
dBm
Input 1 dB Compression Point (IP1dB)
LO-to-IF Leakage
LO-to-RF Leakage
RF-to-IF Isolation
IF/2 Spurious
IF/3 Spurious
IF Channel-to-Channel Isolation
POWER SUPPLY
10.6
−20.7
−37
−34
−73
−71
52
dBm
dBm
dBm
dBc
dBc
dBc
dB
Unfiltered IF output
−10 dBm input power
−10 dBm input power
Positive Supply Voltage
Quiescent Current
4.75
5
5.25
V
LO supply
IF supply
VS = 5 V
170
180
350
mA
mA
mA
Total Quiescent Current
3.3 V PERFORMANCE
VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
8
14
9.9
17.5
dB
dB
dB
dBm
Input Third-Order Intercept (IIP3)
fRF1 = 2534.5 MHz, fRF2 = 2535.5 MHz, fLO = 2332 MHz, each
RF tone at −10 dBm
Input Second-Order Intercept (IIP2)
fRF1 = 2535 MHz, fRF2 = 2585 MHz, fLO = 2332 MHz, each RF
tone at −10 dBm
49
7
dBm
dBm
Input 1 dB Compression Point (IP1dB)
POWER INTERFACE
Supply Voltage
3.0
3.3
3.6
V
Quiescent Current
Power-Down Current
Resistor programmable
Device disabled
200
300
mA
ꢀA
Rev. 0 | Page 4 of 24
ADL5354
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Supply Voltage, VS
RF Input Level
LO Input Level
MNOP, MNON, DVOP, DVON Bias
VGS2,VGS1,VGS0, LOSW, PWDN
Internal Power Dissipation
Thermal Characteristic θJA
Maximum Junction Temperature
Temperature Range
Operating
5.5 V
20 dBm
13 dBm
6.0 V
5.5 V
2.2 W
22°C/W
150°C
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
260°C
Storage
Lead Temperature (Soldering, 60 sec)
Rev. 0 | Page 5 of 24
ADL5354
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
27 LOI2
VGS2
MNIN
MNCT
COMM
VPOS
COMM
VPOS
COMM
DVCT
DVIN
26
25 VGS1
VGS0
ADL5354
TOP VIEW
(Not to Scale)
24
23 LOSW
22 PWDN
21 VPOS
20
19
COMM
LOI1
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
MNIN
MNCT
COMM
VPOS
RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled.
Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor.
Device Common (DC Ground).
3, 5, 7, 12, 20, 34
4, 6, 10, 16, 21, 30, 36
Positive Supply Voltage.
8
9
11
DVCT
DVIN
DVGM
Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.
RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled.
Diversity Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.
13, 14
DVOP, DVON
Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled up to
VCC using external inductors, see Figure 53 for details.
15
17
18, 28
19
DVLE
DVLG
NC
Diversity Channel IF Return. This pin must be grounded.
Diversity Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.
No Connect. Do not connect to this pin.
LOI1
Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled.
22
PWDN
Power Down. Connect this pin to ground for normal operation. Connect pin to 3 V for disable
mode when using VPOS ≤ 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.
23
LOSW
Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.
24, 25, 26
VGS0, VGS1,
VGS2
Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to a low logic
level.
27
29
31
LOI2
MNLG
MNLE
Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled.
Main Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.
Main Channel IF Return. This pin must be grounded.
32, 33
MNOP, MNON
Main Channel Differential Open-Collector Outputs. Pull up MNOP and MNON to VCC by using
external inductors, see Figure 53 for details.
35
MNGM
EPAD
Main Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.
Exposed Paddle. Exposed pad must be connected to ground.
Rev. 0 | Page 6 of 24
ADL5354
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kꢀ, R2 = R5 = 1 kꢀ,
ZO = 50 ꢀ, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
400
390
380
370
360
350
340
330
320
310
300
60
58
56
54
52
50
48
46
44
42
40
T
= –40°C
A
T
T
= –40°C
= +85°C
A
T
T
= +25°C
= +85°C
A
A
A
T
= +25°C
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 3. Supply Current vs. RF Frequency
Figure 6. Input IP2 vs. RF Frequency
12
18
11
10
9
16
14
12
10
8
T
= –40°C
A
T
= +85°C
A
T
T
= +25°C
= +85°C
A
8
A
T
= –40°C
A
T
= +25°C
A
7
6
6
5
4
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 4. Power Conversion Gain vs. RF Frequency
Figure 7. Input P1dB vs. RF Frequency
14
35
13
12
11
10
9
30
25
20
15
10
5
T
T
= –40°C
= +85°C
A
T
= +85°C
A
T
= +25°C
A
T
T
= +25°C
= –40°C
A
A
A
8
7
6
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 8. SSB Noise Figure vs. RF Frequency
Figure 5. Input IP3 vs. RF Frequency
Rev. 0 | Page 7 of 24
ADL5354
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kꢀ, R2 = R5 = 1 kꢀ,
ZO = 50 ꢀ, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
400
390
380
370
360
350
340
330
320
310
300
53
52
51
50
49
48
47
46
V
= 5.25V
S
V
= 5.25V
S
V
V
= 5.00V
= 4.75V
S
S
V
V
= 5.00V
= 4.75V
S
S
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 9. Supply Current vs. Temperature
Figure 12. Input IP2 vs. Temperature
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
7.8
15
14
13
12
11
10
9
V
V
= 5.25V
= 4.75V
S
S
V
= 5.00V
S
V
= 5.25V
S
8
7
V
= 4.75V
S
6
V
= 5.00V
S
5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 10. Power Conversion Gain vs. Temperature
Figure 13. Input P1dB vs. Temperature
12.0
11.5
11.0
10.5
10.0
9.5
29
28
27
26
25
24
23
22
21
V
= 5.25V
S
V
V
= 5.25V
= 4.75V
S
S
V
= 5.00V
= 4.75V
S
V
= 5.00V
S
V
S
9.0
8.5
8.0
7.5
7.0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 14. SSB Noise Figure vs. Temperature
Figure 11. Input IP3 vs. Temperature
Rev. 0 | Page 8 of 24
ADL5354
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kꢀ,
R2 = R5 = 1 kꢀ, ZO = 50 ꢀ, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
400
390
380
60
58
56
54
52
50
48
46
44
42
40
T
= –40°C
A
370
360
350
340
330
320
310
300
T
= –40°C
A
T
= +25°C
A
T
T
= +25°C
= +85°C
A
T
= +85°C
A
A
30
80
130
180
230
280
330
380
430
430
430
30
80
130
180
230
280
330
380
430
430
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 15. Supply Current vs. IF Frequency
Figure 18. Input IP2 vs. IF Frequency
12
11
10
9
12
11
10
9
T
= +85°C
= +25°C
A
T
T
= –40°C
= +85°C
A
T
= –40°C
A
T
A
8
T
= +25°C
A
A
7
8
6
7
5
4
30
6
30
80
130
180
230
280
330
380
80
130
180
230
280
330
380
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 16. Power Conversion Gain vs. IF Frequency
Figure 19. Input P1dB vs. IF Frequency
40
35
30
25
20
15
10
14
13
12
11
10
9
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
8
7
30
30
80
130
180
230
280
330
380
80
130
180
230
280
330
380
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 17. Input IP3 vs. IF Frequency
Figure 20. SSB Noise Figure vs. IF Frequency
Rev. 0 | Page 9 of 24
ADL5354
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kꢀ, R2 = R5 = 1 kꢀ,
ZO = 50 ꢀ, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
12
11
10
9
12.0
11.6
11.2
10.8
10.4
10.0
9.6
T
= +85°C
A
T
= –40°C
A
T
= +25°C
A
T
T
= +25°C
= +85°C
A
T
= –40°C
A
8
A
9.2
7
8.8
6
8.4
5
–6
8.0
–6
–4
–2
0
2
4
6
8
10
10
10
–4
–2
0
2
4
6
8
10
LO POWER (dBm)
LO POWER (dBm)
Figure 21. Power Conversion Gain vs. LO Power
Figure 24. Input P1dB vs. LO Power
32
30
28
26
24
22
20
18
16
–66
–68
–70
–72
–74
–76
–78
–80
T
= –40°C
A
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
T
= +85°C
A
T
= +25°C
A
–6
–4
–2
0
2
4
6
8
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
LO POWER (dBm)
RF FREQUENCY (GHz)
Figure 22. Input IP3 vs. LO Power
Figure 25. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm
58
56
54
52
50
48
46
44
42
40
–60
–62
–64
–66
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
T
= +85°C
A
–68
–70
–72
–74
T
= +25°C
A
T
= –40°C
A
–6
–4
–2
0
2
4
6
8
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
LO POWER (dBm)
RF FREQUENCY (GHz)
Figure 23. Input IP2 vs. LO Power
Figure 26. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm
Rev. 0 | Page 10 of 24
ADL5354
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kꢀ, R2 = R5 = 1 kꢀ,
ZO = 50 ꢀ, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
500
400
300
200
100
0
10
100
80
60
40
20
0
MEAN = 8.6
SD = 0.28%
8
6
RESISTANCE
4
2
CAPACITANCE
0
8.3
8.4
8.5
8.6
8.7
30
80
130
180
230
280
330
380
430
CONVERSION GAIN (dB)
IF FREQUENCY (MHz)
Figure 27. Conversion Gain Distribution
Figure 30. IF Output Impedance (R Parallel, C Equivalent)
0
100
80
60
40
20
0
MEAN = 26.1
SD = 0.5%
–3
–6
–9
–12
–15
–18
–21
–24
–27
23
24
25
26
27
28
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
INPUT IP3 (dBm)
RF FREQUENCY (GHz)
Figure 28. Input IP3 Distribution
Figure 31. RF Return Loss, Fixed IF
0
–5
100
80
60
40
20
0
MEAN = 10.6
SD = 0.36%
–10
–15
–20
–25
–30
–35
SELECTED
UNSELECTED
2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
10.0
10.3
10.6
10.9
11.2
LO FREQUENCY (GHz)
INPUT P1dB (dBm)
Figure 32. LO Return Loss, Selected and Unselected
Figure 29. Input P1dB Distribution
Rev. 0 | Page 11 of 24
ADL5354
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kꢀ,
R2 = R5 = 1 kꢀ, ZO = 50 ꢀ, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
60
55
50
45
40
35
30
–30
–32
–34
–36
–38
–40
–42
–44
–46
–48
T
= –40°C
A
T
= –40°C
A
T
T
= +25°C
= +85°C
A
A
T
= +85°C
A
T
= +25°C
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
RF FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 33. LO Switch Isolation vs. RF Frequency
Figure 36. LO-to-RF Leakages vs. LO Frequency
–30
0
–31
–32
–33
–34
–35
–36
–37
–38
–39
–40
–5
T
= +85°C
A
–10
–15
–20
–25
–30
–35
–40
–45
–50
2 × LO-TO-RF
2 × LO-TO-IF
T
T
= +25°C
= –40°C
A
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
RF FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 34 RF-to-IF Isolation vs. RF Frequency
Figure 37. 2 × LO Leakage vs. LO Frequency
–30
0
–35
–40
–45
–50
–55
–60
–65
–70
–5
–10
–15
–20
–25
–30
–35
–40
T
= +25°C
3 × LO-TO-RF
T
T
= –40°C
= +85°C
A
A
A
3 × LO-TO-IF
2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
LO FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 38. 3 × LO Leakage vs. LO Frequency
Figure 35. LO-to-IF Leakage vs. LO Frequency
Rev. 0 | Page 12 of 24
ADL5354
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.3 kꢀ, R2 = R5 = 1 kꢀ,
ZO = 50 ꢀ, VGS0 = VGS1 = VGS2 = 0 V, unless otherwise noted.
0.30
0.25
0.20
0.15
0.10
0.05
0
10
18
16
14
12
10
8
IF BIAS SUPPLY CURRENT
9
8
7
LO BIAS SUPPLY CURRENT
6
VGS = 000
VGS = 011
VGS = 100
VGS = 110
5
4
6
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
RF FREQUENCY (GHz)
BIAS RESISTOR VALUE (kΩ)
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency for
Various VGS Settings
Figure 42. LO and IF Supply Current vs. IF and LO Bias Resistor Value
20
18
16
14
12
10
8
32
29
26
23
20
17
16
15
14
13
12
11
10
9
30
27
24
21
18
15
12
9
INPUT IP3
SSB NOISE FIGURE
CONVERSION GAIN
8
6
VGS = 000
VGS = 011 14
VGS = 100
7
3
VGS = 110
6
11
6
0
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
RF FREQUENCY (GHz)
IF BIAS RESISTOR VALUE (kΩ)
Figure 40. Input P1dB and Input IP3 vs. RF Frequency for Various VGS Settings
Figure 43. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias
Resistor Value
62
14
13
12
11
10
9
32
29
26
23
20
17
14
11
8
T
= –40°C
A
60
58
56
54
52
50
INPUT IP3
T
= +25°C
A
SSB NOISE FIGURE
T
= +85°C
A
CONVERSION GAIN
8
7
6
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
LO BIAS RESISTOR VALUE (kΩ)
RF FREQUENCY (GHz)
Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. LO Bias
Resistor Value
Figure 44. IF Channel-to-Channel Isolation vs. RF Frequency
Rev. 0 | Page 13 of 24
ADL5354
3.3 V PERFORMANCE
VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2332 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
208
206
204
202
200
198
196
194
192
190
188
60
50
40
30
20
10
0
T
= +25°C
A
T
= –40°C
= +25°C
A
T
= +85°C
A
T
A
T
= –40°C
A
T
= +85°C
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 45. Supply Current vs. RF Frequency at 3.3 V
Figure 48. Input IP2 vs. RF Frequency at 3.3 V
15
8
6
4
13
11
9
T
T
= –40°C
= +85°C
A
T
= +25°C
T
= +85°C
A
A
2
0
7
T
= +25°C
A
A
5
–2
–4
–6
–8
–10
3
1
–1
–3
–5
T
= –40°C
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 46. Power Conversion Gain vs. RF Frequency at 3.3 V
Figure 49. Input P1dB vs. RF Frequency at 3.3 V
25
22
20
18
16
14
12
10
8
20
T
T
= –40°C
= +85°C
A
15
10
5
T
= +25°C
A
A
T
T
= +85°C
= +25°C
A
A
T
= –40°C
A
0
6
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 47. Input IP3 vs. RF Frequency at 3.3 V
Figure 50. SSB Noise Figure vs. RF Frequency at 3.3 V
Rev. 0 | Page 14 of 24
ADL5354
SPUR TABLES
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement
system = −100 dBm.
5 V PERFORMANCE
VS = 5 V, IS = 350 mA, TA = 25°C, fRF = 2500 MHz, fLO = 2297 MHz, LO power = 0 dBm, RF power = −10 dBm, VGS0 = VGS1 = VGS2 = 0 V,
and ZO = 50 ꢀ, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−19.7
0.00
−95.3
−28.9
−65.2
−73.6
1
−41.5
−92.6
−51.9
−90.2
2
−84.3
3
<−100 <−100 −77.6
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100
4
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
<−100
3.3 V PERFORMANCE
VS = 3.3 V, IS = 200 mA, TA = 25°C, fRF = 2500 MHz, fLO = 2297 MHz, LO power = 0 dBm, RF power = −10 dBm, R1 = R4 = 1.2 kꢀ, R2 =
R5 = 400 ꢀ, VGS0 = VGS1 = VG2 = 0 V, and ZO = 50 ꢀ, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−26.5
0.00
−36.3
−58.8
−64.2
<−100
<−100
1
−40.6
−87.8
−55.5
−79.1
−70.2
<−100
<−100
2
−77.7
<−100
−84.3
3
<−100
<−100
<−100
<−100
<−100
<−100
<−100
<−100
4
<−100
<−100
<−100
<−100
<−100
5
<−100 <−100 <−100
<−100 <−100 <−100 <−100
6
7
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
N
8
9
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
<−100
Rev. 0 | Page 15 of 24
ADL5354
CIRCUIT DESCRIPTION
The ADL5354 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated into
a single die using mature packaging and interconnection tech-
nologies to provide a high performance, low cost design with
excellent electrical, mechanical, and thermal properties. In
addition, the need for external components is minimized,
optimizing cost and size.
contribution from the mixer is due to the resistive loss of the
switches, which is in the order of a few ohms.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the input
of the IF amplifier, where high peak signal levels can compromise
the compression and intermodulation performance of the system.
This termination is accomplished by the addition of a sum network
between the IF amplifier and the mixer and in the feedback
elements in the IF amplifier.
The RF subsystem consists of integrated, low loss RF baluns,
passive MOSFET mixers, sum termination networks, and IF
amplifiers. The LO subsystem consists of an SPDT-terminated FET
switch and two multistage limiting LO amplifiers. The purpose of
the LO subsystem is to provide a large, fixed amplitude, balanced
signal to drive the mixer independent of the level of the LO input.
A block diagram of the device is shown in Figure 51.
The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance that is
required to achieve the overall performance. The balanced open-
collector output of the IF amplifier, with impedance modified by
the feedback within the amplifier, permits the output to be con-
nected directly to a high impedance filter, differential amplifier, or
an analog-to-digital input while providing optimum second-order
intermodulation suppression. The differential output impedance of
the IF amplifier is approximately 200 Ω. If operation in a 50 Ω
system is desired, the output can be transformed to 50 Ω by using
a 4:1 transformer.
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
MNIN
MNCT
COMM
VPOS
COMM
VPOS
COMM
DVCT
DVIN
LOI2
VGS2
VGS1
VGS0
LOSW
PWDN
VPOS
COMM
LOI1
The intermodulation performance of the design is generally limited
by the IF amplifier. The IP3 performance can be optimized by
adjusting the IF current with an external resistor. Additionally,
dc current can be saved by increasing either or both resistors. It
is permissible to reduce the dc supply voltage to as low as 3.3 V,
further reducing the dissipated power of the part. (No performance
enhancement is obtained by reducing the value of these resistors,
and excessive dc power dissipation may result.)
ADL5354
LO SUBSYSTEM
The ADL5354 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
Figure 51. Simplified Schematic
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can be
dc connected, it is recommended that a blocking capacitor be used
to avoid running excessive dc current through the part. The RF
balun can easily support an RF input frequency range of 2200 MHz
to 2700 MHz.
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier. This
results in consistent performance over a range of LO input power.
Optimum performance is achieved from −6 dBm to +10 dBm,
but the circuit continues to function at considerably lower levels
of LO input power.
The resulting balanced RF signal is applied to a passive mixer that
commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimal noise to the frequency translation. The only noise
The performance of this amplifier is critical in achieving a high
intercept passive mixer without degrading the noise floor of the
Rev. 0 | Page 16 of 24
ADL5354
system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the LO
amplifier by raising the value of the external bias control resistor.
For dc current critical applications, the LO chain can operate
with a supply voltage as low as 3.3 V, resulting in substantial
dc power savings.
In addition, when operating with supply voltages below 3.6 V, the
ADL5354 has a power-down mode that permits the dc current
to drop to ~300 μA.
The logic inputs are designed to work with any logic family that
provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.
All pins, including the RF pins, are ESD protected and have
been tested to a level of 1500 V HBM and 500 V FICDM.
Rev. 0 | Page 17 of 24
ADL5354
APPLICATIONS INFORMATION
need for a transformer. This results in a voltage conversion gain
that is approximately 6 dB higher than the power conversion gain,
as shown in Table 3. When a 50 ꢀ output impedance is needed,
use a 4:1 impedance transformer, as shown in Figure 52.
BASIC CONNECTIONS
The ADL5354 mixer is designed to downconvert radio frequencies
(RF) primarily between 2200 MHz and 2700 MHz to lower inter-
mediate frequencies (IF) between 30 MHz and 450 MHz. Figure 52
depicts the basic connections of the mixer. It is recommended to
ac couple the RF and LO input ports to prevent nonzero dc
voltages from damaging the RF balun or LO input circuit. The
RFIN matching network consists of a series 1.5 pF capacitor and
a shunt 4.3 nH inductor to provide the optimized RF input return
loss for the desired frequency band.
BIAS RESISTOR SELECTION
The IF bias resistors (R1 and R4) and LO bias resistors (R2 and R5)
are used to adjust the bias current of the integrated amplifiers at the
IF and LO terminals. It is necessary to have a sufficient amount
of current to bias both the internal IF and LO amplifiers to optimize
dc current vs. optimum IIP3 performance.
IF PORT
MIXER VGS CONTROL DAC
The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.
The ADL5354 features three logic control pins, VGS0 (Pin 24),
VGS1 (Pin 25), and VGS2 (Pin26), that allow programmability for
internal gate-to-source voltages for optimizing mixer performance
over desired frequency bands. The evaluation board defaults
VGS0, VGS1, and VGS2 to ground.
The real part of the output impedance is approximately 200 ꢀ,
which matches many commonly used SAW filters without the
Rev. 0 | Page 18 of 24
ADL5354
R10
MAIN_OUTN
MAIN_OUTP
C33
C32
T1
C19
C17
C27
C8
C21
L2
L1
R3
VCC
C25
C18
R1
C22
VCC
L6
R2
28
VCC
36
35
34
33
32
31
30
29
C9
C16
1
2
27
26
25
24
23
22
21
20
19
MAIN_IN
LO2
VCC
Z1
Z2
R12
R7
R16
C34
C3
C2
R13
R8
3
4
5
6
7
8
9
R14
R11
R17
R15
VCC
R19
VCC
C26
C15
C6
C7
ADL5354
C11
LO1
DIV_IN
C14
Z3
Z4
10
11
12
13
14
15
L3
C24
16
17
18
VCC
+
VCC
R5
VCC
C23
R4
C10
VCC
R6
C13
GND
L5
L4
C1
C12
C28
C20
C29
T2
DIV_OUTP
DIV_OUTN
C30
C31
R9
Figure 52. Typical Application Circuit
Rev. 0 | Page 19 of 24
ADL5354
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 53. The evaluation board is fabricated using Rogers®
RO3003 material. Table 7 describes the various configuration
options of the evaluation board. Evaluation board layout is shown
in Figure 54 and Figure 55.
R10
MAIN_OUTN
C33
MAIN_OUTP
C32
T1
C19
C17
C27
C8
C21
L2
L1
R3
VCC
C25
C18
R1
C22
VCC
R2
L6
VCC
C9
C16
LOI2
MNIN
MAIN_IN
LO2
R12
R7
R16
C34
Z1
Z2
C3
VGS2
VGS1
VGS0
LOSW
PWDN
VPOS
COMM
LOI1
VCC
MNCT
COMM
VPOS
COMM
VPOS
COMM
DVCT
DVIN
C2
R13
R8
R14
R11
R17
ADL5354
TOP VIEW
(Not to Scale)
VCC
R15
C6
C7
R19
VCC
C11
C26
C15
DIV_IN
Z3
Z4
LO1
C14
VCC
VCC
L3
R5
+
C10
C23
R4
VCC
VCC
GND
C24
C13
R6
L4
L5
C1
C12
C28
C20
C29
T2
DIV_OUTP
DIV_OUTN
C30
C31
R9
Figure 53. Evaluation Board Schematic
Rev. 0 | Page 20 of 24
ADL5354
Table 7. Evaluation Board Configuration
Components
Description
Default Conditions
C1, C8, C10, C12,
C13, C15, C18,
C21, C22, C23,
C24, C25, C26
Power supply decoupling. Nominal supply decoupling consists of
a 0.01 μF capacitor to ground in parallel with 10 pF capacitors to
ground positioned as close to the device as possible.
C10 = 4.7 μF (Size 3216),
C1, C8, C12, C21 = 150 pF (Size 0402),
C22, C23, C24, C25, C26 = 10 pF (Size 0402),
C13, C15, C18 = 0.1 μF (Size 0402)
Z1 to Z4, C2, C3,
C6, C7, C9, C11
RF main and diversity input interface. Main and diversity input
channels are ac-coupled through C9 and C11. Z1 to Z4 provide
additional component placement for external matching/filter
C2, C7 = 10 pF (Size 0402),
C3, C6 = 0.01 μF (Size 0402),
C9, C11 = 1.5 pF (Size 0402),
networks. C2, C3, C6, and C7 provide bypassing for the center taps of Z2, Z4 = 4.3 nH (Size 0402),
the main and diversity on-chip input baluns. Z1, Z3 = open (Size 0402)
IF main and diversity output interface. The open-collector IF output C17, C19, C20, C29 to C33 = 0.001 μF (Size 0402),
T1, T2, C17, C19,
C20, C27 to C33,
L1, L2, L4, L5,
interfaces are biased through the pull-up choke inductors (L1, L2,
L4, and L5), leaving R3 and R6 available for additional supply
bypassing. T1 and T2 are 4:1 impedance transformers that are used
to provide a single-ended IF output interface, and C27 and C28
provide the center tap bypassing. C17, C19, C20, C29, C30, C31, C32,
and C33 ensure an ac-coupled output interface. Remove R9 and
R10 for balanced output operation.
C27, C28 = 150 pF (Size 0402),
T1, T2 = TC4-1T+ (Mini-Circuits),
L1, L2, L4, L5 = 330 nH (Size 0805),
R3, R6, R9, R10 = 0 Ω (Size 0402)
R3, R6, R9, R10
C14, C16,
R15, LOSEL
LO interface. C14 and C16 provide ac coupling for the LOI1 and LOI2 C14, C16 = 10 pF (Size 0402),
local oscillator inputs. LOSEL selects the appropriate LO input for
both mixer cores. R15 provides a pull-down to ensure LOI2 is enabled
when the LOSEL jumper is removed. The jumper can be removed to
allow the LOSEL interface to be exercised by using an external logic
generator.
R15 = 10 kΩ (Size 0402),
LOSEL = 2-pin shunt
R19, PWDN
PWDN interface. When the PWDN 2-pin shunt is inserted, the
ADL5354 is powered down. When R19 is open, it pulls the PWDN
logic low and enables the device. The jumper can be removed to
allow PWDN interface to be exercised using an external logic
generator. Grounding the PWDN pin is allowed during nominal
operation but is not permitted when supply voltages exceed 3.3 V.
R19 = 10 kΩ (Size 0402),
PWDN = 2-pin shunt
R1, R2, R4, R5, L3,
L6, R7, R8, R11 to
Bias control. R16 and R17 form a voltage divider to provide a 3 V for
logic control, bypassed to ground through C34. Resistors R7, R8, R11,
R1, R4 = 1.3 kΩ (Size 0402),
R2, R5 = 1 kΩ (Size 0402),
L3, L6 = 0 Ω (Size 0603),
R12, R13, R14 = open (Size 0402),
R7, R8, R11 = 0 Ω (Size 0402),
R16 = 10 kΩ (Size 0402),
R17 = 15 kΩ (Size 0402),
C34 = 1 nF (Size 0402)
R14, R16, R17, C34 R12, R13, and R14 provide resistor programmability of VGS0, VGS1,
and VGS2. Typically, these nodes can be hardwired for nominal
operation. Grounding these pins is allowed for nominal operation.
R2 and R5 set the bias point for the internal LO buffers. R1 and R4 set
the bias point for the internal IF amplifiers. L3 and L6 are external
inductors used to improve isolation and common-mode rejection.
Figure 54. Evaluation Board Top Layer
Figure 55. Evaluation Board Bottom Layer
Rev. 0 | Page 21 of 24
ADL5354
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
36
28
1
9
27
0.50
BSC
PIN 1
INDICATOR
3.85
3.70 SQ
3.55
TOP
VIEW
5.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
0.75
0.60
0.50
19
18
10
0.20 MIN
4.00
REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.35
0.28
0.23
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-1
Figure 56. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad (CP-36-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADL5354ACPZ-R2
ADL5354ACPZ-R7
ADL5354-EVALZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-36-1
CP-36-1
36-Lead LFCSP_VQ
36-Lead LFCSP_VQ
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 22 of 24
ADL5354
NOTES
Rev. 0 | Page 23 of 24
ADL5354
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09118-0-2/11(0)
Rev. 0 | Page 24 of 24
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