ADL5354 [ADI]
2300 MHz to 2900 MHz Balanced Mixer; 2300 MHz至2900 MHz的平衡混频器
| 型号： | ADL5354 |
| 厂家： | 
ADI |
| 描述： | 2300 MHz to 2900 MHz Balanced Mixer |
| 文件： | 总24页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2300 MHz to 2900 MHz Balanced Mixer,
LO Buffer and RF Balun
ADL5363
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VCMI
20
IFOP
19
IFON
18
PWDN
17
COMM
16
RF frequency range of 2300 MHz to 2900 MHz
IF frequency range of dc to 450 MHz
Power conversion loss: 7.7 dB
SSB noise figure of 7.6 dB
Input IP3 of 31 dBm
ADL5363
1
2
3
4
5
15
14
13
12
11
VPMX
RFIN
LOI2
Typical LO drive of 0 dBm
VPSW
VGS1
VGS0
LOI1
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed pad, 5 mm × 5 mm 20-lead LFCSP
1500 V HBM/1250 V FICDM ESD performance
RFCT
COMM
COMM
BIAS
GENERATOR
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
6
7
LGM3
8
9
10
GENERAL DESCRIPTION
VLO3
VLO2
LOSW
NC
The ADL5363 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and local oscillator (LO)
balancing circuitry to allow for single-ended operation. The
ADL5363 incorporates an RF balun to provide optimal
performance over a 2300 MHz to 2900 MHz input frequency
range. The balanced passive mixer arrangement provides good
LO-to-RF leakage, typically better than −30 dBm, and excellent
intermodulation performance. The balanced mixer core also
provides extremely high input linearity, allowing the device to
be used in demanding cellular applications where in-band
blocking signals might otherwise result in the degradation of
dynamic performance.
NC = NO CONNECT
Figure 1.
The ADL5363 provides two switched LO paths that can be used
in TDD applications where it is desirable to rapidly switch between
two local oscillators. LO current can be externally set using a
resistor to minimize dc current commensurate with the desired
level of performance. For low voltage applications, the ADL5363 is
capable of operation at voltages down to 3.3 V with substantially
reduced current. For low voltage operation, an additional logic
pin is provided to power down (<200 μA) the circuit when desired.
The ADL5363 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
Single
Single Mixer Dual Mixer
RF Frequency (MHz) Mixer
and IF Amp
and IF Amp
ADL5358
ADL5356
ADL5354
500 to 1700
1200 to 2500
2300 to 2900
ADL5367 ADL5357
ADL5365 ADL5355
ADL5363 ADL5353
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADL5363
TABLE OF CONTENTS
Features .............................................................................................. 1
Upconversion.............................................................................. 15
Spurious Performance ............................................................... 16
Circuit Description......................................................................... 17
RF Subsystem.............................................................................. 17
LO Subsystem ............................................................................. 18
Applications Information.............................................................. 19
Basic Connections...................................................................... 19
IF Port .......................................................................................... 19
Bias Resistor Selection ............................................................... 19
Mixer VGS Control DAC.......................................................... 19
Evaluation Board ............................................................................ 20
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Performance........................................................................... 4
3.3 V Performance........................................................................ 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance........................................................................... 7
3.3 V Performance...................................................................... 14
REVISION HISTORY
7/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5363
SPECIFICATIONS
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB over a limited bandwidth
16
50
dB
Ω
MHz
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage1
LO INTERFACE
2300
2900
Differential impedance, f = 200 MHz
Externally generated
33||-0.3
5.0
Ω||pF
MHz
V
dc
3.3
450
5.5
LO Power
−6
0
+10
3350
0.4
dBm
dB
Ω
Return Loss
15
50
Input Impedance
LO Frequency Range
POWER-DOWN (PWDN) INTERFACE2
PWDN Threshold
Logic 0 Level
2330
MHz
1.0
V
V
Logic 1 Level
1.4
V
PWDN Response Time
Device enabled, IF output to 90% of its final level
Device disabled, supply current <5 mA
Device enabled
160
220
0.0
70
ns
ns
μA
μA
PWDN Input Bias Current
Device disabled
1 Apply the supply voltage from the external circuit through the choke inductors.
2 The PWDN function is intended for use with VS ≤ 3.6 V only.
Rev. 0 | Page 3 of 24
ADL5363
5 V PERFORMANCE
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Loss
SSB Noise Figure
Including 1:1 IF port transformer and PCB loss
7.7
7.6
31
dB
dB
dBm
Input Third-Order Intercept (IIP3)
fRF1 = 2534.5 MHz, fRF2 = 2535.5 MHz, fLO = 2738 MHz,
each RF tone at 0 dBm
Input Second-Order Intercept (IIP2)
fRF1 = 2535 MHz, fRF2 = 2585 MHz, fLO = 2738 MHz,
each RF tone at 0 dBm
62
dBm
Input 1 dB Compression Point (IP1dB)1 Exceeding 20 dBm RF power results in damage to the device
25
dBm
dBm
dBm
dBc
dBc
dBc
LO-to-IF Leakage
LO-to-RF Leakage
RF-to-IF Isolation
IF/2 Spurious
Unfiltered IF output
−22
−32
−44
−61
−70
−10 dBm input power
−10 dBm input power
IF/3 Spurious
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
4.5
5
100
5.5
V
mA
VS = 5 V
1 Exceeding 20 dBm RF power results in damage to the device.
3.3 V PERFORMANCE
VS = 3.3 V, IS = 60 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω,
unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Loss
SSB Noise Figure
Including 1:1 IF port transformer and PCB loss
7.4
6.8
26
dB
dB
dBm
Input Third-Order Intercept (IIP3)
fRF1 = 2534.5 MHz, fRF2 = 2535.5 MHz, fLO = 2738 MHz,
each RF tone at 0 dBm
Input Second-Order Intercept (IIP2)
fRF1 = 2535 MHz, fRF2 = 2585 MHz, fLO = 2738 MHz,
each RF tone at 0 dBm
56
dBm
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
3.3
60
V
mA
VS = 5 V
Rev. 0 | Page 4 of 24
ADL5363
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5.5 V
20 dBm
13 dBm
6.0 V
5.5 V
0.5 W
25°C/W
Supply Voltage, VS
RF Input Level
LO Input Level
IFOP, IFON Bias Voltage
VGS0, VGS1, LOSW, PWDN
Internal Power Dissipation
Thermal Resistance, θJA
Temperature
ESD CAUTION
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
150°C
−40°C to +85°C
−65°C to +150°C
260°C
Rev. 0 | Page 5 of 24
ADL5363
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
VPMX 1
RFIN 2
RFCT 3
COMM 4
COMM 5
15 LOI2
14 VPSW
13 VGS1
12 VGS0
11 LOI1
ADL5363
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. EXPOSED PAD. MUST BE SOLDERED
TO GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic
Description
1
2
3
VPMX
RFIN
RFCT
COMM
Positive Supply Voltage.
RF Input. Must be ac-coupled.
RF Balun Center Tap (AC Ground).
Device Common (DC Ground).
4, 5,16
6, 8
7
9
10
VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
LGM3
LOSW
NC
LO Amplifier Bias Control.
LO Switch. LOI1 selected for 0 V, and LOI2 selected for 3 V.
No Connect.
11, 15
12, 13
14
LOI1, LOI2
LO Inputs. Must be ac-coupled.
VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
VPSW
Positive Supply Voltage for LO Switch.
17
18, 19
20
PWDN
IFON, IFOP
VCMI
Power Down. Connect this pin to ground for normal operation and connect this pin to 3.0 V for disable mode.
Differential IF Outputs.
No Connect. This pin can be grounded.
EPAD (EP)
Exposed pad. Must be soldered to ground.
Rev. 0 | Page 6 of 24
ADL5363
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
105
104
103
90
85
80
75
70
65
60
55
50
45
40
T
T
= –40°C
= +25°C
A
102
T
= +85°C
A
A
101
100
T
= +25°C
A
T
= +85°C
A
99
98
97
96
95
T
= –40°C
A
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 3. Supply Current vs. RF Frequency
Figure 6. Input IP2 vs. RF Frequency
11
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
10
9
T
= +25°C
A
T
= +85°C
T = +85°C
A
A
8
T
= –40°C
A
7
T
= +25°C
T
= –40°C
A
A
6
5
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 7. SSB Noise Figure vs. RF Frequency
Figure 4. Power Conversion Loss vs. RF Frequency
40
38
36
34
32
30
28
26
24
22
20
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
RF FREQUENCY (GHz)
Figure 5. Input IP3 vs. RF Frequency
Rev. 0 | Page 7 of 24
ADL5363
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
140
130
120
110
100
90
74
71
68
65
62
59
56
53
50
5.25V
5.00V
4.75V
5.25V
4.75V
5.00V
80
70
60
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 8. Supply Current vs. Temperature
Figure 11. Input IP2 vs. Temperature
9.1
8.8
8.5
8.2
7.9
7.6
7.3
7.0
6.7
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.75V
5.00V
5.25V
4.75V
5.00V
5.25V
6.4
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. SSB Noise Figure vs. Temperature
Figure 9. Power Conversion Loss vs. Temperature
39
37
4.75V
5.00V
5.25V
35
33
31
29
27
25
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 10. Input IP3 vs. Temperature
Rev. 0 | Page 8 of 24
ADL5363
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
120
100
90
80
70
60
50
40
115
110
105
100
95
T
= +85°C
A
T
= –40°C
A
T
= +85°C
T
= +25°C
A
A
T
= +25°C
A
90
T
= –40°C
330
A
85
80
30
80
130
180
230
280
330
380
430
430
430
30
80
130
180
230
280
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 13. Supply Current vs. IF Frequency
Figure 16. Input IP2 vs. IF Frequency
8.4
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
8.2
8.0
7.8
7.6
7.4
7.2
T
= +85°C
A
T
= +25°C
A
T
= –40°C
A
7.0
30
6.0
30
80
130
180
230
280
330
380
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 14. Power Conversion Loss vs. IF Frequency
Figure 17. SSB Noise Figure vs. IF Frequency
41
38
35
32
29
T
= –40°C
A
T
= +25°C
T = +85°C
A
A
26
23
20
30
80
130
180
230
280
330
380
IF FREQUENCY (MHz)
Figure 15. Input IP3 vs. IF Frequency
Rev. 0 | Page 9 of 24
ADL5363
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
12
11
10
9
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
T
= +85°C
A
8
T
= +85°C
A
7
T
= +25°C
T
= –40°C
A
A
6
T
= +25°C
A
T
= –40°C
A
5
4
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
–6
–4
–2
0
2
4
6
8
10
10
10
RF FREQUENCY (GHz)
LO POWER (dBm)
Figure 21. IF/2 Spurious vs. RF Frequency
Figure 18. Power Conversion Loss vs. LO Power
–20
36
34
32
30
28
26
24
22
20
–30
–40
–50
–60
–70
–80
–90
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
T
= +85°C
= +25°C
A
T
= –40°C
A
T
A
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
–6
–4
–2
0
2
4
6
8
RF FREQUENCY (GHz)
LO POWER (dBm)
Figure 22. IF/3 Spurious vs. RF Frequency
Figure 19. Input IP3 vs. LO Power
80
70
T
= +85°C
= +25°C
A
60
50
40
30
20
10
0
T
= –40°C
A
T
A
–6
–4
–2
0
2
4
6
8
LO POWER (dBm)
Figure 20. Input IP2 vs. LO Power
Rev. 0 | Page 10 of 24
ADL5363
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
100
50
45
50
4
3
80
60
40
20
40
35
30
25
20
15
10
5
RESISTANCE (Ω)
2
1
0
–1
–2
–3
–4
0
CAPACITANCE (pF)
MEAN: 101.06
SD: 0.0008%
0
80
0
30
90
100
110
120
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
I
(mA)
SUPPLY
Figure 23. Supply Current Distribution
Figure 26. IF Output Impedance (R Parallel, C Equivalent)
100
80
0
–2
–4
–6
–8
60
–10
–12
–14
–16
–18
–20
40
20
MEAN: 7.7
SD: 0.104%
0
8.2
8.0
7.8
7.6
7.4
7.2
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
CONVERSION LOSS DISTRIBUTION (dB)
RF FREQUENCY (GHz)
Figure 27. RF Port Return Loss, Fixed IF
Figure 24.Conversion Loss Distribution
0
100
80
60
40
20
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
SELECTED
UNSELECTED
MEAN: 31.13
SD: 0.286%
0
21
24
27
30
33
36 39
2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10
LO FREQUENCY (GHz)
INPUT IP3 (dBm)
Figure 25. Input IP3 Distribution
Figure 28. LO Return Loss, Selected and Unselected
Rev. 0 | Page 11 of 24
ADL5363
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
60
57
54
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
T
= +85°C
A
51
T
= –40°C
A
48
45
T
= –40°C
A
42
39
36
33
30
T = +25°C
A
T
= +85°C
A
T
= +25°C
A
2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
LO FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 29. LO Switch Isolation vs. RF Frequency
Figure 32. LO-to-RF Leakage vs. LO Frequency
–30
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–35
–40
–45
–50
–55
2xLO TO RF
2xLO TO IF
T
= –40°C
A
T
= +25°C
= +85°C
A
T
A
–60
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10
RF FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 30. RF-to-IF Isolation vs. RF Frequency
Figure 33. 2LO Leakage vs. LO Frequency
–5
–52
–55
–58
–61
–64
–67
–70
–73
–76
–10
–15
–20
–25
–30
–35
–40
T
= –40°C
A
T
= +25°C
3xLO TO RF
3xLO TO IF
A
T
= +85°C
A
2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10
2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10
LO FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 31. LO-to-IF Leakage vs. LO Frequency
Figure 34. 3LO Leakage vs. LO Frequency
Rev. 0 | Page 12 of 24
ADL5363
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
12
23
21
11.0
10.5
10.0
9.5
32
31
30
29
28
27
26
VGS = 0, 0
INPUT IP3 (dBm)
VGS = 0, 1
VGS = 1, 0
VGS = 1, 1
11
10
9
GAIN
19
17
15
13
11
9
8
7
9.0
6
8.5
NOISE FIGURE
5
8.0
CONVERSION LOSS (dB)
NOISE FIGURE (dB)
4
7
7.5
7.0
25
24
3
5
2
3
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800
RF FREQUENCY (GHz)
BIAS RESISTOR VALUE (Ω)
Figure 35. Power Conversion Loss and SSB Noise Figure vs. RF Frequency
Figure 37. Power Conversion Loss, SSB Noise Figure, and
Input IP3 vs. IF Bias Resistor Value
40
140
130
VGS = 0, 0
VGS = 0, 1
VGS = 1, 0
38
VGS = 1, 1
36
120
110
100
90
34
32
30
28
26
24
22
80
70
20
60
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800
RF FREQUENCY (GHz)
BIAS RESISTOR VALUE (Ω)
Figure 36. Input IP3 vs. RF Frequency
Figure 38. Supply Current vs. Bias Resistor Value
Rev. 0 | Page 13 of 24
ADL5363
3.3 V PERFORMANCE
VS = 3.3 V, IS = 60 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
67
65
63
61
59
57
100
90
80
70
60
50
40
30
20
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
T = +85°C
A
T
= +25°C
A
T
= –40°C
A
56
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 39. Supply Current vs. RF Frequency at 3.3 V
Figure 42. Input IP2 vs. RF Frequency at 3.3 V
9.0
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
T
= +85°C
A
T
= +85°C
A
T
= +25°C
A
T
= –40°C
T
= –40°C
A
A
T
= +25°C
A
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
RF FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 40. Power Conversion Loss vs. RF Frequency at 3.3 V
Figure 43. SSB Noise Figure vs. RF Frequency at 3.3 V
34
31
28
25
22
19
16
13
10
T
= –40°C
= +85°C
A
T
= +25°C
A
T
A
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
RF FREQUENCY (GHz)
Figure 41. Input IP3 vs. RF Frequency at 3.3 V
Rev. 0 | Page 14 of 24
ADL5363
UPCONVERSION
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
13
12
11
10
9
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
T
= +85°C
= +25°C
A
T
A
T
= –40°C
A
8
T
= –40°C
A
7
T
= +85°C
A
6
T
= +25°C
A
5
4
3
4.0
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 44. Power Conversion Loss vs. RF Frequency, VS = 5 V, Upconversion
Figure 46. Power Conversion Loss vs. RF Frequency at 3.3 V, Upconversion
30
29
28
35
33
31
T
= +85°C
A
27
26
25
24
23
22
21
20
29
27
25
23
21
19
17
15
T
= –40°C
A
T
= +25°C
A
T
= +25°C
A
T
= –40°C
A
T
= +85°C
A
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 45. Input IP3 vs. RF Frequency, VS = 5 V, Upconversion
Figure 47. Input IP3 vs. RF Frequency at 3.3 V, Upconversion
Rev. 0 | Page 15 of 24
ADL5363
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc
from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system
= −100 dBm.
5 V Performance
VS = 5 V, IS = 100 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, RF power = 0 dBm, VGS0 = VGS1 = 0 V, and
ZO = 50 ꢀ, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
−10.9
0.0
−28.3
−49.3
−64.6
−44.5
−31.2
−78.4
1
−42.2
−75.8
−49.8
−78.5
−90.9
2
−76.5
−94.7
−89.8
3
<−100 −83.0
<−100 −73.5
<−100
4
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
3.3 V Performance
VS = 3.3 V, IS = 56 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, RF power = 0 dBm, R9 = 226 Ω, VGS0 = VGS1 =
0 V, and ZO = 50 Ω, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
−16.9
0.0
−35.1
−49.1
−62.7
−61.4
−30.4
−68.5
1
−41.9
−72.3
−94.6
−52.6
−71.9
−92.7
2
−80.3
−71.6
<−100
−75.1
3
<−100 −61.2
<−100
4
<−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
5
6
7
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100
Rev. 0 | Page 16 of 24
ADL5363
CIRCUIT DESCRIPTION
The ADL5363 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated
into a single die, using mature packaging and interconnection
technologies to provide a high performance, low cost design
with excellent electrical, mechanical, and thermal properties.
In addition, the need for external components is minimized,
optimizing cost and size.
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range
of 2300 MHz to 2900 MHz.
The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
The LO subsystem consists of an SPDT-terminated FET switch
and a three-stage limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input.
A block diagram of the device is shown in Figure 48.
As the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation
products and reduces the level of unwanted signals at the IF
output. This termination is accomplished by the addition of a
sum network between the IF output and the mixer.
VCMI
IFOP
19
IFON
18
PWDN
17
COMM
16
20
ADL5363
1
2
3
4
5
15
14
13
12
11
VPMX
RFIN
LOI2
VPSW
VGS1
VGS0
LOI1
The IP3 performance can be optimized by adjusting the supply
current with an external resistor. Figure 37 and 38 illustrate how
the bias resistor affects the performance with a 5 V supply.
Additionally, dc current can be saved by increasing either or
both resistors. It is permissible to reduce the dc supply voltage
to as low as 3.3 V, further reducing the dissipated power of the
part. (Note that no performance enhancement is obtained by
reducing the value of these resistors and excessive dc power
dissipation may result.)
RFCT
COMM
COMM
BIAS
GENERATOR
6
7
LGM3
8
9
10
VLO3
VLO2
LOSW
NC
NC = NO CONNECT
Figure 48. Simplified Schematic
Rev. 0 | Page 17 of 24
ADL5363
interferers can limit mixer performance. The bandwidth of the
intermodulation performance is somewhat influenced by the
current in the LO amplifier chain. For dc current sensitive
applications, it is permissible to reduce the current in the
LO amplifier by raising the value of the external bias control
resistor. For dc current critical applications, the LO chain
can operate with a supply voltage as low as 3.3 V, resulting in
substantial dc power savings.
LO SUBSYSTEM
The ADL5363 has two LO inputs permitting multiple synthesizers
to be rapidly switched with extremely short switching times
(<40 ns) for frequency agile applications. The two inputs are
applied to a high isolation SPDT switch that provides a constant
input impedance, regardless of whether the port is selected, to
avoid pulling the LO sources. This multiple section switch also
ensures high isolation to the off input, minimizing any leakage
from the unwanted LO input that may result in undesired IF
responses.
In addition, when operating with supply voltages below 3.6 V,
the ADL5363 has a power-down mode that permits the dc
current to drop to <200 μA.
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation up to 5.5 V, although a small bias
current is drawn.
The performance of this amplifier is critical in achieving a
high intercept passive mixer without degrading the noise floor
of the system. This is a critical requirement in an interferer rich
environment, such as cellular infrastructure, where blocking
All pins, including the RF pins, are ESD protected and have
been tested up to a level of 1500 V HBM and 1250 V CDM.
Rev. 0 | Page 18 of 24
ADL5363
APPLICATIONS INFORMATION
BASIC CONNECTIONS
BIAS RESISTOR SELECTION
An external resistor, RBIAS LO, is used to adjust the bias current
of the integrated amplifiers at the LO terminals. It is necessary
to have a sufficient amount of current to bias the internal LO
amplifier to optimize dc current vs. optimum IIP3 performance.
Figure 37 and Figure 38 provide the reference for the bias
resistor selection when lower power consumption is considered
at the expense of conversion gain and IP3 performance.
The ADL5363 mixer is designed to downconvert radio frequen-
cies (RF) primarily between 2300 MHz and 2900 MHz to lower
intermediate frequencies (IF) between 30 MHz and 450 MHz.
Figure 49 depicts the basic connections of the mixer. To prevent
nonzero dc voltages from damaging the RF balun or LO input
circuit, ac-couple the RF and LO input ports. The RFIN
matching network consists of a series 1.5 pF capacitor and a
shunt 12 nH inductor to provide the optimized RF input return
loss for the desired frequency band.
MIXER VGS CONTROL DAC
The ADL5363 features two logic control pins, VGS0 (Pin 12) and
VGS1 (Pin 13), that allow programmability for internal gate-to-
source voltages for optimizing mixer performance over desired
frequency bands. The evaluation board defaults both VGS0 and
VGS1 to ground.
IF PORT
The real part of the output impedance is approximately 50 ꢀ, as
seen in Figure 26, which matches many commonly used SAW
filters without the need for a transformer. This results in a
voltage conversion loss that is approximately the same as the
power conversion loss, as shown in Table 3.
IF1_OUT
R1
0Ω
T1
C25
560pF
C24
560pF
10kΩ
+5V
20
19
18
17
16
10pF
4.7µF
22pF
ADL5363
+5V
1
2
3
4
5
15
14
13
12
11
LO2_IN
+5V
10µH
1.5pF
12nH
RF-IN
10pF
0.01µF
10pF
BIAS
GENERATOR
22pF
LO1_IN
6
7
8
9
10
R
BIAS LO
10kΩ
+5V
10pF
10pF
Figure 49. Typical Application Circuit
Rev. 0 | Page 19 of 24
ADL5363
EVALUATION BOARD
An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 50.
The evaluation board is fabricated using Rogers® RO3003 material. Table 7 describes the various configuration options of the evaluation
board. Evaluation board layout is shown in Figure 51 to Figure 54.
IF1_OUT
R1
0Ω
T1
C25
560pF
C24
560pF
PWR_UP
R21
10kΩ
R14
0Ω
L3
0Ω
C12
22pF
LO2_IN
VPOS
VPOS
VPMX
RFIN
LOI2
VPSW
VGS1
VGS0
LOI1
C2
C21
C20
R22
10kΩ
10µF
10pF
10pF
RF-IN
Z1
12nH
C22
1nF
C1
1.5pF
R23
15kΩ
RFCT
COMM
COMM
ADL5363
C5
0.01µF
C4
10pF
VGS1
VGS0
LO1_IN
C10
22pF
LOSEL
VPOS
R9
1.1kΩ
C6
10pF
R4
10kΩ
VPOS
C8
10pF
Figure 50. Evaluation Board Schematic
Rev. 0 | Page 20 of 24
ADL5363
Table 7. Evaluation Board Configuration
Components
Function
Description
Default Conditions
C2, C6, C8,
C20, C21
Power supply
decoupling
Power Supply Decoupling. Nominal supply decoupling
consists of a 10 μF capacitor to ground in parallel with a
10 pF capacitor to ground positioned as close to the device
as possible.
C2 = 10 μF (size 0603),
C6, C8, C20, C21 = 10 pF (size 0402)
C1, C4, C5, Z1
T1, R1, C24, C25
C10, C12, R4
RF input interface
RF Input Interface. The input channels are ac-coupled
through C1. C4 and C5 provide bypassing for the center taps
of the RF input baluns.
C1 = 1.5 pF (size 0402),
C4 = 10 pF (size 0402),
C5 = 0.01 μF (size 0402)
Z1= 12 nH (size 0402)
IF output interface IF Output Interface. T1 is a 1:1 impedance transformer used T1 = TC1-1-13M+ (Mini-Circuits),
to provide a single-ended IF output interface. Remove R1
for balanced output operation. C24 and C25 are used to
block the dc bias at the IF ports.
R1 = 0 Ω (size 0402),
C24, C25 = 560 pF (size 0402)
LO interface
PWDN interface
Bias control
LO Interface. C10 and C12 provide ac coupling for the
LO1_IN and LO2_IN local oscillator inputs. LOSEL selects
the appropriate LO input for both mixer cores. R4 provides
a pull-down to ensure that LO1_IN is enabled when the
LOSEL test point is logic low. LO2_IN is enabled when
LOSEL is pulled to logic high.
C10, C12 = 22 pF (size 0402),
R4 = 10 kΩ (size 0402)
R21
PWDN Interface. R21 pulls the PWDN logic low and enables R21 = 10 kΩ (size 0402)
the device. The PWR_UP test point allows the PWDN
interface to be exercised using the an external logic
generator. Grounding the PWDN pin for nominal operation
is allowed. Using the PWDN pin when supply voltages
exceed 3.3 V is not allowed.
C22, L3, R9, R14,
R22, R23, VGS0,
VGS1
Bias Control. R22 and R23 form a voltage divider to provide
3 V for logic control, bypassed to ground through C22.
VGS0 and VGS1 jumpers provide programmability at the
VGS0 and VGS1 pins. It is recommended to pull these two
pins to ground for nominal operation. R9 sets the bias
point for the internal LO buffers.
C22 = 1 nF (size 0402),
L3 = 0 Ω (size 0603),
R9 = 1.1 kΩ (size 0402),
R14 = 0 Ω (size 0402),
R22 = 10 kΩ (size 0402),
R23 = 15 kΩ (size 0402),
VGS0 = VGS1 = 3-pin shunt
Rev. 0 | Page 21 of 24
ADL5363
Figure 51. Evaluation Board Top Layer
Figure 53. Evaluation Board Power Plane, Internal Layer 2
Figure 54. Evaluation Board Bottom Layer
Figure 52. Evaluation Board Ground Plane, Internal Layer 1
Rev. 0 | Page 22 of 24
ADL5363
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.65
BSC
PIN 1
INDICATOR
4.75
BSC SQ
3.20
3.10 SQ
3.00
EXPOSED
PAD
(BOTTOM VIEW)
10
11
6
0.75
0.60
0.50
TOP VIEW
2.60 BSC
0.70
0.65
0.60
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.01 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.05
0.35
0.28
0.23
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHC
Figure 55. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-20-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option Ordering Quantity
ADL5363ACPZ-R7 −40°C to +85°C
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-5
1,500
7”Tape and Reel
ADL5363-EVALZ
Evaluation Board
1
1 Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
ADL5363
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09914-0-7/11(0)
Rev. 0 | Page 24 of 24
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